drivers/gpu/drm/stm/ltdc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics SA 2017
   4  *
   5  * Authors: Philippe Cornu <[email protected]>
   6  *          Yannick Fertre <[email protected]>
   7  *          Fabien Dessenne <[email protected]>
   8  *          Mickael Reulier <[email protected]>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/component.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/media-bus-format.h>
  16 #include <linux/module.h>
  17 #include <linux/of_graph.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/regmap.h>
  22 #include <linux/reset.h>
  23
  24 #include <drm/drm_atomic.h>
  25 #include <drm/drm_atomic_helper.h>
  26 #include <drm/drm_blend.h>
  27 #include <drm/drm_bridge.h>
  28 #include <drm/drm_device.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/drm_fb_dma_helper.h>
  31 #include <drm/drm_fourcc.h>
  32 #include <drm/drm_framebuffer.h>
  33 #include <drm/drm_gem_atomic_helper.h>
  34 #include <drm/drm_gem_dma_helper.h>
  35 #include <drm/drm_of.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_vblank.h>
  39 #include <drm/drm_managed.h>
  40
  41 #include <video/videomode.h>
  42
  43 #include "ltdc.h"
  44
  45 #define NB_CRTC 1
  46 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
  47
  48 #define MAX_IRQ 4
  49
  50 #define HWVER_10200 0x010200
  51 #define HWVER_10300 0x010300
  52 #define HWVER_20101 0x020101
  53 #define HWVER_40100 0x040100
  54
  55 /*
  56  * The address of some registers depends on the HW version: such registers have
  57  * an extra offset specified with layer_ofs.
  58  */
  59 #define LAY_OFS_0       0x80
  60 #define LAY_OFS_1       0x100
  61 #define LAY_OFS (ldev->caps.layer_ofs)
  62
  63 /* Global register offsets */
  64 #define LTDC_IDR        0x0000          /* IDentification */
  65 #define LTDC_LCR        0x0004          /* Layer Count */
  66 #define LTDC_SSCR       0x0008          /* Synchronization Size Configuration */
  67 #define LTDC_BPCR       0x000C          /* Back Porch Configuration */
  68 #define LTDC_AWCR       0x0010          /* Active Width Configuration */
  69 #define LTDC_TWCR       0x0014          /* Total Width Configuration */
  70 #define LTDC_GCR        0x0018          /* Global Control */
  71 #define LTDC_GC1R       0x001C          /* Global Configuration 1 */
  72 #define LTDC_GC2R       0x0020          /* Global Configuration 2 */
  73 #define LTDC_SRCR       0x0024          /* Shadow Reload Configuration */
  74 #define LTDC_GACR       0x0028          /* GAmma Correction */
  75 #define LTDC_BCCR       0x002C          /* Background Color Configuration */
  76 #define LTDC_IER        0x0034          /* Interrupt Enable */
  77 #define LTDC_ISR        0x0038          /* Interrupt Status */
  78 #define LTDC_ICR        0x003C          /* Interrupt Clear */
  79 #define LTDC_LIPCR      0x0040          /* Line Interrupt Position Conf. */
  80 #define LTDC_CPSR       0x0044          /* Current Position Status */
  81 #define LTDC_CDSR       0x0048          /* Current Display Status */
  82 #define LTDC_EDCR       0x0060          /* External Display Control */
  83 #define LTDC_CCRCR      0x007C          /* Computed CRC value */
  84 #define LTDC_FUT        0x0090          /* Fifo underrun Threshold */
  85
  86 /* Layer register offsets */
  87 #define LTDC_L1C0R      (ldev->caps.layer_regs[0])      /* L1 configuration 0 */
  88 #define LTDC_L1C1R      (ldev->caps.layer_regs[1])      /* L1 configuration 1 */
  89 #define LTDC_L1RCR      (ldev->caps.layer_regs[2])      /* L1 reload control */
  90 #define LTDC_L1CR       (ldev->caps.layer_regs[3])      /* L1 control register */
  91 #define LTDC_L1WHPCR    (ldev->caps.layer_regs[4])      /* L1 window horizontal position configuration */
  92 #define LTDC_L1WVPCR    (ldev->caps.layer_regs[5])      /* L1 window vertical position configuration */
  93 #define LTDC_L1CKCR     (ldev->caps.layer_regs[6])      /* L1 color keying configuration */
  94 #define LTDC_L1PFCR     (ldev->caps.layer_regs[7])      /* L1 pixel format configuration */
  95 #define LTDC_L1CACR     (ldev->caps.layer_regs[8])      /* L1 constant alpha configuration */
  96 #define LTDC_L1DCCR     (ldev->caps.layer_regs[9])      /* L1 default color configuration */
  97 #define LTDC_L1BFCR     (ldev->caps.layer_regs[10])     /* L1 blending factors configuration */
  98 #define LTDC_L1BLCR     (ldev->caps.layer_regs[11])     /* L1 burst length configuration */
  99 #define LTDC_L1PCR      (ldev->caps.layer_regs[12])     /* L1 planar configuration */
 100 #define LTDC_L1CFBAR    (ldev->caps.layer_regs[13])     /* L1 color frame buffer address */
 101 #define LTDC_L1CFBLR    (ldev->caps.layer_regs[14])     /* L1 color frame buffer length */
 102 #define LTDC_L1CFBLNR   (ldev->caps.layer_regs[15])     /* L1 color frame buffer line number */
 103 #define LTDC_L1AFBA0R   (ldev->caps.layer_regs[16])     /* L1 auxiliary frame buffer address 0 */
 104 #define LTDC_L1AFBA1R   (ldev->caps.layer_regs[17])     /* L1 auxiliary frame buffer address 1 */
 105 #define LTDC_L1AFBLR    (ldev->caps.layer_regs[18])     /* L1 auxiliary frame buffer length */
 106 #define LTDC_L1AFBLNR   (ldev->caps.layer_regs[19])     /* L1 auxiliary frame buffer line number */
 107 #define LTDC_L1CLUTWR   (ldev->caps.layer_regs[20])     /* L1 CLUT write */
 108 #define LTDC_L1CYR0R    (ldev->caps.layer_regs[21])     /* L1 Conversion YCbCr RGB 0 */
 109 #define LTDC_L1CYR1R    (ldev->caps.layer_regs[22])     /* L1 Conversion YCbCr RGB 1 */
 110 #define LTDC_L1FPF0R    (ldev->caps.layer_regs[23])     /* L1 Flexible Pixel Format 0 */
 111 #define LTDC_L1FPF1R    (ldev->caps.layer_regs[24])     /* L1 Flexible Pixel Format 1 */
 112
 113 /* Bit definitions */
 114 #define SSCR_VSH        GENMASK(10, 0)  /* Vertical Synchronization Height */
 115 #define SSCR_HSW        GENMASK(27, 16) /* Horizontal Synchronization Width */
 116
 117 #define BPCR_AVBP       GENMASK(10, 0)  /* Accumulated Vertical Back Porch */
 118 #define BPCR_AHBP       GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
 119
 120 #define AWCR_AAH        GENMASK(10, 0)  /* Accumulated Active Height */
 121 #define AWCR_AAW        GENMASK(27, 16) /* Accumulated Active Width */
 122
 123 #define TWCR_TOTALH     GENMASK(10, 0)  /* TOTAL Height */
 124 #define TWCR_TOTALW     GENMASK(27, 16) /* TOTAL Width */
 125
 126 #define GCR_LTDCEN      BIT(0)          /* LTDC ENable */
 127 #define GCR_DEN         BIT(16)         /* Dither ENable */
 128 #define GCR_CRCEN       BIT(19)         /* CRC ENable */
 129 #define GCR_PCPOL       BIT(28)         /* Pixel Clock POLarity-Inverted */
 130 #define GCR_DEPOL       BIT(29)         /* Data Enable POLarity-High */
 131 #define GCR_VSPOL       BIT(30)         /* Vertical Synchro POLarity-High */
 132 #define GCR_HSPOL       BIT(31)         /* Horizontal Synchro POLarity-High */
 133
 134 #define GC1R_WBCH       GENMASK(3, 0)   /* Width of Blue CHannel output */
 135 #define GC1R_WGCH       GENMASK(7, 4)   /* Width of Green Channel output */
 136 #define GC1R_WRCH       GENMASK(11, 8)  /* Width of Red Channel output */
 137 #define GC1R_PBEN       BIT(12)         /* Precise Blending ENable */
 138 #define GC1R_DT         GENMASK(15, 14) /* Dithering Technique */
 139 #define GC1R_GCT        GENMASK(19, 17) /* Gamma Correction Technique */
 140 #define GC1R_SHREN      BIT(21)         /* SHadow Registers ENabled */
 141 #define GC1R_BCP        BIT(22)         /* Background Colour Programmable */
 142 #define GC1R_BBEN       BIT(23)         /* Background Blending ENabled */
 143 #define GC1R_LNIP       BIT(24)         /* Line Number IRQ Position */
 144 #define GC1R_TP         BIT(25)         /* Timing Programmable */
 145 #define GC1R_IPP        BIT(26)         /* IRQ Polarity Programmable */
 146 #define GC1R_SPP        BIT(27)         /* Sync Polarity Programmable */
 147 #define GC1R_DWP        BIT(28)         /* Dither Width Programmable */
 148 #define GC1R_STREN      BIT(29)         /* STatus Registers ENabled */
 149 #define GC1R_BMEN       BIT(31)         /* Blind Mode ENabled */
 150
 151 #define GC2R_EDCA       BIT(0)          /* External Display Control Ability  */
 152 #define GC2R_STSAEN     BIT(1)          /* Slave Timing Sync Ability ENabled */
 153 #define GC2R_DVAEN      BIT(2)          /* Dual-View Ability ENabled */
 154 #define GC2R_DPAEN      BIT(3)          /* Dual-Port Ability ENabled */
 155 #define GC2R_BW         GENMASK(6, 4)   /* Bus Width (log2 of nb of bytes) */
 156 #define GC2R_EDCEN      BIT(7)          /* External Display Control ENabled */
 157
 158 #define SRCR_IMR        BIT(0)          /* IMmediate Reload */
 159 #define SRCR_VBR        BIT(1)          /* Vertical Blanking Reload */
 160
 161 #define BCCR_BCBLACK    0x00            /* Background Color BLACK */
 162 #define BCCR_BCBLUE     GENMASK(7, 0)   /* Background Color BLUE */
 163 #define BCCR_BCGREEN    GENMASK(15, 8)  /* Background Color GREEN */
 164 #define BCCR_BCRED      GENMASK(23, 16) /* Background Color RED */
 165 #define BCCR_BCWHITE    GENMASK(23, 0)  /* Background Color WHITE */
 166
 167 #define IER_LIE         BIT(0)          /* Line Interrupt Enable */
 168 #define IER_FUWIE       BIT(1)          /* Fifo Underrun Warning Interrupt Enable */
 169 #define IER_TERRIE      BIT(2)          /* Transfer ERRor Interrupt Enable */
 170 #define IER_RRIE        BIT(3)          /* Register Reload Interrupt Enable */
 171 #define IER_FUEIE       BIT(6)          /* Fifo Underrun Error Interrupt Enable */
 172 #define IER_CRCIE       BIT(7)          /* CRC Error Interrupt Enable */
 173 #define IER_MASK (IER_LIE | IER_FUWIE | IER_TERRIE | IER_RRIE | IER_FUEIE | IER_CRCIE)
 174
 175 #define CPSR_CYPOS      GENMASK(15, 0)  /* Current Y position */
 176
 177 #define ISR_LIF         BIT(0)          /* Line Interrupt Flag */
 178 #define ISR_FUWIF       BIT(1)          /* Fifo Underrun Warning Interrupt Flag */
 179 #define ISR_TERRIF      BIT(2)          /* Transfer ERRor Interrupt Flag */
 180 #define ISR_RRIF        BIT(3)          /* Register Reload Interrupt Flag */
 181 #define ISR_FUEIF       BIT(6)          /* Fifo Underrun Error Interrupt Flag */
 182 #define ISR_CRCIF       BIT(7)          /* CRC Error Interrupt Flag */
 183
 184 #define EDCR_OCYEN      BIT(25)         /* Output Conversion to YCbCr 422: ENable */
 185 #define EDCR_OCYSEL     BIT(26)         /* Output Conversion to YCbCr 422: SELection of the CCIR */
 186 #define EDCR_OCYCO      BIT(27)         /* Output Conversion to YCbCr 422: Chrominance Order */
 187
 188 #define LXCR_LEN        BIT(0)          /* Layer ENable */
 189 #define LXCR_COLKEN     BIT(1)          /* Color Keying Enable */
 190 #define LXCR_CLUTEN     BIT(4)          /* Color Look-Up Table ENable */
 191 #define LXCR_HMEN       BIT(8)          /* Horizontal Mirroring ENable */
 192 #define LXCR_MASK (LXCR_LEN | LXCR_COLKEN | LXCR_CLUTEN | LXCR_HMEN)
 193
 194 #define LXWHPCR_WHSTPOS GENMASK(11, 0)  /* Window Horizontal StarT POSition */
 195 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
 196
 197 #define LXWVPCR_WVSTPOS GENMASK(10, 0)  /* Window Vertical StarT POSition */
 198 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
 199
 200 #define LXPFCR_PF       GENMASK(2, 0)   /* Pixel Format */
 201 #define PF_FLEXIBLE     0x7             /* Flexible Pixel Format selected */
 202
 203 #define LXCACR_CONSTA   GENMASK(7, 0)   /* CONSTant Alpha */
 204
 205 #define LXBFCR_BF2      GENMASK(2, 0)   /* Blending Factor 2 */
 206 #define LXBFCR_BF1      GENMASK(10, 8)  /* Blending Factor 1 */
 207 #define LXBFCR_BOR      GENMASK(18, 16) /* Blending ORder */
 208
 209 #define LXCFBLR_CFBLL   GENMASK(12, 0)  /* Color Frame Buffer Line Length */
 210 #define LXCFBLR_CFBP    GENMASK(31, 16) /* Color Frame Buffer Pitch in bytes */
 211
 212 #define LXCFBLNR_CFBLN  GENMASK(10, 0)  /* Color Frame Buffer Line Number */
 213
 214 #define LXCR_C1R_YIA    BIT(0)          /* Ycbcr 422 Interleaved Ability */
 215 #define LXCR_C1R_YSPA   BIT(1)          /* Ycbcr 420 Semi-Planar Ability */
 216 #define LXCR_C1R_YFPA   BIT(2)          /* Ycbcr 420 Full-Planar Ability */
 217 #define LXCR_C1R_SCA    BIT(31)         /* SCaling Ability*/
 218
 219 #define LxPCR_YREN      BIT(9)          /* Y Rescale Enable for the color dynamic range */
 220 #define LxPCR_OF        BIT(8)          /* Odd pixel First */
 221 #define LxPCR_CBF       BIT(7)          /* CB component First */
 222 #define LxPCR_YF        BIT(6)          /* Y component First */
 223 #define LxPCR_YCM       GENMASK(5, 4)   /* Ycbcr Conversion Mode */
 224 #define YCM_I           0x0             /* Interleaved 422 */
 225 #define YCM_SP          0x1             /* Semi-Planar 420 */
 226 #define YCM_FP          0x2             /* Full-Planar 420 */
 227 #define LxPCR_YCEN      BIT(3)          /* YCbCr-to-RGB Conversion Enable */
 228
 229 #define LXRCR_IMR       BIT(0)          /* IMmediate Reload */
 230 #define LXRCR_VBR       BIT(1)          /* Vertical Blanking Reload */
 231 #define LXRCR_GRMSK     BIT(2)          /* Global (centralized) Reload MaSKed */
 232
 233 #define CLUT_SIZE       256
 234
 235 #define CONSTA_MAX      0xFF            /* CONSTant Alpha MAX= 1.0 */
 236 #define BF1_PAXCA       0x600           /* Pixel Alpha x Constant Alpha */
 237 #define BF1_CA          0x400           /* Constant Alpha */
 238 #define BF2_1PAXCA      0x007           /* 1 - (Pixel Alpha x Constant Alpha) */
 239 #define BF2_1CA         0x005           /* 1 - Constant Alpha */
 240
 241 #define NB_PF           8               /* Max nb of HW pixel format */
 242
 243 #define FUT_DFT         128             /* Default value of fifo underrun threshold */
 244
 245 /*
 246  * Skip the first value and the second in case CRC was enabled during
 247  * the thread irq. This is to be sure CRC value is relevant for the
 248  * frame.
 249  */
 250 #define CRC_SKIP_FRAMES 2
 251
 252 enum ltdc_pix_fmt {
 253         PF_NONE,
 254         /* RGB formats */
 255         PF_ARGB8888,            /* ARGB [32 bits] */
 256         PF_RGBA8888,            /* RGBA [32 bits] */
 257         PF_ABGR8888,            /* ABGR [32 bits] */
 258         PF_BGRA8888,            /* BGRA [32 bits] */
 259         PF_RGB888,              /* RGB [24 bits] */
 260         PF_BGR888,              /* BGR [24 bits] */
 261         PF_RGB565,              /* RGB [16 bits] */
 262         PF_BGR565,              /* BGR [16 bits] */
 263         PF_ARGB1555,            /* ARGB A:1 bit RGB:15 bits [16 bits] */
 264         PF_ARGB4444,            /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
 265         /* Indexed formats */
 266         PF_L8,                  /* Indexed 8 bits [8 bits] */
 267         PF_AL44,                /* Alpha:4 bits + indexed 4 bits [8 bits] */
 268         PF_AL88                 /* Alpha:8 bits + indexed 8 bits [16 bits] */
 269 };
 270
 271 /* The index gives the encoding of the pixel format for an HW version */
 272 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
 273         PF_ARGB8888,            /* 0x00 */
 274         PF_RGB888,              /* 0x01 */
 275         PF_RGB565,              /* 0x02 */
 276         PF_ARGB1555,            /* 0x03 */
 277         PF_ARGB4444,            /* 0x04 */
 278         PF_L8,                  /* 0x05 */
 279         PF_AL44,                /* 0x06 */
 280         PF_AL88                 /* 0x07 */
 281 };
 282
 283 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
 284         PF_ARGB8888,            /* 0x00 */
 285         PF_RGB888,              /* 0x01 */
 286         PF_RGB565,              /* 0x02 */
 287         PF_RGBA8888,            /* 0x03 */
 288         PF_AL44,                /* 0x04 */
 289         PF_L8,                  /* 0x05 */
 290         PF_ARGB1555,            /* 0x06 */
 291         PF_ARGB4444             /* 0x07 */
 292 };
 293
 294 static const enum ltdc_pix_fmt ltdc_pix_fmt_a2[NB_PF] = {
 295         PF_ARGB8888,            /* 0x00 */
 296         PF_ABGR8888,            /* 0x01 */
 297         PF_RGBA8888,            /* 0x02 */
 298         PF_BGRA8888,            /* 0x03 */
 299         PF_RGB565,              /* 0x04 */
 300         PF_BGR565,              /* 0x05 */
 301         PF_RGB888,              /* 0x06 */
 302         PF_NONE                 /* 0x07 */
 303 };
 304
 305 static const u32 ltdc_drm_fmt_a0[] = {
 306         DRM_FORMAT_ARGB8888,
 307         DRM_FORMAT_XRGB8888,
 308         DRM_FORMAT_RGB888,
 309         DRM_FORMAT_RGB565,
 310         DRM_FORMAT_ARGB1555,
 311         DRM_FORMAT_XRGB1555,
 312         DRM_FORMAT_ARGB4444,
 313         DRM_FORMAT_XRGB4444,
 314         DRM_FORMAT_C8
 315 };
 316
 317 static const u32 ltdc_drm_fmt_a1[] = {
 318         DRM_FORMAT_ARGB8888,
 319         DRM_FORMAT_XRGB8888,
 320         DRM_FORMAT_RGB888,
 321         DRM_FORMAT_RGB565,
 322         DRM_FORMAT_RGBA8888,
 323         DRM_FORMAT_RGBX8888,
 324         DRM_FORMAT_ARGB1555,
 325         DRM_FORMAT_XRGB1555,
 326         DRM_FORMAT_ARGB4444,
 327         DRM_FORMAT_XRGB4444,
 328         DRM_FORMAT_C8
 329 };
 330
 331 static const u32 ltdc_drm_fmt_a2[] = {
 332         DRM_FORMAT_ARGB8888,
 333         DRM_FORMAT_XRGB8888,
 334         DRM_FORMAT_ABGR8888,
 335         DRM_FORMAT_XBGR8888,
 336         DRM_FORMAT_RGBA8888,
 337         DRM_FORMAT_RGBX8888,
 338         DRM_FORMAT_BGRA8888,
 339         DRM_FORMAT_BGRX8888,
 340         DRM_FORMAT_RGB565,
 341         DRM_FORMAT_BGR565,
 342         DRM_FORMAT_RGB888,
 343         DRM_FORMAT_BGR888,
 344         DRM_FORMAT_ARGB1555,
 345         DRM_FORMAT_XRGB1555,
 346         DRM_FORMAT_ARGB4444,
 347         DRM_FORMAT_XRGB4444,
 348         DRM_FORMAT_C8
 349 };
 350
 351 static const u32 ltdc_drm_fmt_ycbcr_cp[] = {
 352         DRM_FORMAT_YUYV,
 353         DRM_FORMAT_YVYU,
 354         DRM_FORMAT_UYVY,
 355         DRM_FORMAT_VYUY
 356 };
 357
 358 static const u32 ltdc_drm_fmt_ycbcr_sp[] = {
 359         DRM_FORMAT_NV12,
 360         DRM_FORMAT_NV21
 361 };
 362
 363 static const u32 ltdc_drm_fmt_ycbcr_fp[] = {
 364         DRM_FORMAT_YUV420,
 365         DRM_FORMAT_YVU420
 366 };
 367
 368 /* Layer register offsets */
 369 static const u32 ltdc_layer_regs_a0[] = {
 370         0x80,   /* L1 configuration 0 */
 371         0x00,   /* not available */
 372         0x00,   /* not available */
 373         0x84,   /* L1 control register */
 374         0x88,   /* L1 window horizontal position configuration */
 375         0x8c,   /* L1 window vertical position configuration */
 376         0x90,   /* L1 color keying configuration */
 377         0x94,   /* L1 pixel format configuration */
 378         0x98,   /* L1 constant alpha configuration */
 379         0x9c,   /* L1 default color configuration */
 380         0xa0,   /* L1 blending factors configuration */
 381         0x00,   /* not available */
 382         0x00,   /* not available */
 383         0xac,   /* L1 color frame buffer address */
 384         0xb0,   /* L1 color frame buffer length */
 385         0xb4,   /* L1 color frame buffer line number */
 386         0x00,   /* not available */
 387         0x00,   /* not available */
 388         0x00,   /* not available */
 389         0x00,   /* not available */
 390         0xc4,   /* L1 CLUT write */
 391         0x00,   /* not available */
 392         0x00,   /* not available */
 393         0x00,   /* not available */
 394         0x00    /* not available */
 395 };
 396
 397 static const u32 ltdc_layer_regs_a1[] = {
 398         0x80,   /* L1 configuration 0 */
 399         0x84,   /* L1 configuration 1 */
 400         0x00,   /* L1 reload control */
 401         0x88,   /* L1 control register */
 402         0x8c,   /* L1 window horizontal position configuration */
 403         0x90,   /* L1 window vertical position configuration */
 404         0x94,   /* L1 color keying configuration */
 405         0x98,   /* L1 pixel format configuration */
 406         0x9c,   /* L1 constant alpha configuration */
 407         0xa0,   /* L1 default color configuration */
 408         0xa4,   /* L1 blending factors configuration */
 409         0xa8,   /* L1 burst length configuration */
 410         0x00,   /* not available */
 411         0xac,   /* L1 color frame buffer address */
 412         0xb0,   /* L1 color frame buffer length */
 413         0xb4,   /* L1 color frame buffer line number */
 414         0xb8,   /* L1 auxiliary frame buffer address 0 */
 415         0xbc,   /* L1 auxiliary frame buffer address 1 */
 416         0xc0,   /* L1 auxiliary frame buffer length */
 417         0xc4,   /* L1 auxiliary frame buffer line number */
 418         0xc8,   /* L1 CLUT write */
 419         0x00,   /* not available */
 420         0x00,   /* not available */
 421         0x00,   /* not available */
 422         0x00    /* not available */
 423 };
 424
 425 static const u32 ltdc_layer_regs_a2[] = {
 426         0x100,  /* L1 configuration 0 */
 427         0x104,  /* L1 configuration 1 */
 428         0x108,  /* L1 reload control */
 429         0x10c,  /* L1 control register */
 430         0x110,  /* L1 window horizontal position configuration */
 431         0x114,  /* L1 window vertical position configuration */
 432         0x118,  /* L1 color keying configuration */
 433         0x11c,  /* L1 pixel format configuration */
 434         0x120,  /* L1 constant alpha configuration */
 435         0x124,  /* L1 default color configuration */
 436         0x128,  /* L1 blending factors configuration */
 437         0x12c,  /* L1 burst length configuration */
 438         0x130,  /* L1 planar configuration */
 439         0x134,  /* L1 color frame buffer address */
 440         0x138,  /* L1 color frame buffer length */
 441         0x13c,  /* L1 color frame buffer line number */
 442         0x140,  /* L1 auxiliary frame buffer address 0 */
 443         0x144,  /* L1 auxiliary frame buffer address 1 */
 444         0x148,  /* L1 auxiliary frame buffer length */
 445         0x14c,  /* L1 auxiliary frame buffer line number */
 446         0x150,  /* L1 CLUT write */
 447         0x16c,  /* L1 Conversion YCbCr RGB 0 */
 448         0x170,  /* L1 Conversion YCbCr RGB 1 */
 449         0x174,  /* L1 Flexible Pixel Format 0 */
 450         0x178   /* L1 Flexible Pixel Format 1 */
 451 };
 452
 453 static const u64 ltdc_format_modifiers[] = {
 454         DRM_FORMAT_MOD_LINEAR,
 455         DRM_FORMAT_MOD_INVALID
 456 };
 457
 458 static const struct regmap_config stm32_ltdc_regmap_cfg = {
 459         .reg_bits = 32,
 460         .val_bits = 32,
 461         .reg_stride = sizeof(u32),
 462         .max_register = 0x400,
 463         .use_relaxed_mmio = true,
 464         .cache_type = REGCACHE_NONE,
 465 };
 466
 467 static const u32 ltdc_ycbcr2rgb_coeffs[DRM_COLOR_ENCODING_MAX][DRM_COLOR_RANGE_MAX][2] = {
 468         [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 469                 0x02040199,     /* (b_cb = 516 / r_cr = 409) */
 470                 0x006400D0      /* (g_cb = 100 / g_cr = 208) */
 471         },
 472         [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = {
 473                 0x01C60167,     /* (b_cb = 454 / r_cr = 359) */
 474                 0x005800B7      /* (g_cb = 88 / g_cr = 183) */
 475         },
 476         [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 477                 0x021D01CB,     /* (b_cb = 541 / r_cr = 459) */
 478                 0x00370089      /* (g_cb = 55 / g_cr = 137) */
 479         },
 480         [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = {
 481                 0x01DB0193,     /* (b_cb = 475 / r_cr = 403) */
 482                 0x00300078      /* (g_cb = 48 / g_cr = 120) */
 483         }
 484         /* BT2020 not supported */
 485 };
 486
 487 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
 488 {
 489         return (struct ltdc_device *)crtc->dev->dev_private;
 490 }
 491
 492 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
 493 {
 494         return (struct ltdc_device *)plane->dev->dev_private;
 495 }
 496
 497 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
 498 {
 499         enum ltdc_pix_fmt pf;
 500
 501         switch (drm_fmt) {
 502         case DRM_FORMAT_ARGB8888:
 503         case DRM_FORMAT_XRGB8888:
 504                 pf = PF_ARGB8888;
 505                 break;
 506         case DRM_FORMAT_ABGR8888:
 507         case DRM_FORMAT_XBGR8888:
 508                 pf = PF_ABGR8888;
 509                 break;
 510         case DRM_FORMAT_RGBA8888:
 511         case DRM_FORMAT_RGBX8888:
 512                 pf = PF_RGBA8888;
 513                 break;
 514         case DRM_FORMAT_BGRA8888:
 515         case DRM_FORMAT_BGRX8888:
 516                 pf = PF_BGRA8888;
 517                 break;
 518         case DRM_FORMAT_RGB888:
 519                 pf = PF_RGB888;
 520                 break;
 521         case DRM_FORMAT_BGR888:
 522                 pf = PF_BGR888;
 523                 break;
 524         case DRM_FORMAT_RGB565:
 525                 pf = PF_RGB565;
 526                 break;
 527         case DRM_FORMAT_BGR565:
 528                 pf = PF_BGR565;
 529                 break;
 530         case DRM_FORMAT_ARGB1555:
 531         case DRM_FORMAT_XRGB1555:
 532                 pf = PF_ARGB1555;
 533                 break;
 534         case DRM_FORMAT_ARGB4444:
 535         case DRM_FORMAT_XRGB4444:
 536                 pf = PF_ARGB4444;
 537                 break;
 538         case DRM_FORMAT_C8:
 539                 pf = PF_L8;
 540                 break;
 541         default:
 542                 pf = PF_NONE;
 543                 break;
 544                 /* Note: There are no DRM_FORMAT for AL44 and AL88 */
 545         }
 546
 547         return pf;
 548 }
 549
 550 static inline u32 ltdc_set_flexible_pixel_format(struct drm_plane *plane, enum ltdc_pix_fmt pix_fmt)
 551 {
 552         struct ltdc_device *ldev = plane_to_ltdc(plane);
 553         u32 lofs = plane->index * LAY_OFS, ret = PF_FLEXIBLE;
 554         int psize, alen, apos, rlen, rpos, glen, gpos, blen, bpos;
 555
 556         switch (pix_fmt) {
 557         case PF_BGR888:
 558                 psize = 3;
 559                 alen = 0; apos = 0; rlen = 8; rpos = 0;
 560                 glen = 8; gpos = 8; blen = 8; bpos = 16;
 561         break;
 562         case PF_ARGB1555:
 563                 psize = 2;
 564                 alen = 1; apos = 15; rlen = 5; rpos = 10;
 565                 glen = 5; gpos = 5;  blen = 5; bpos = 0;
 566         break;
 567         case PF_ARGB4444:
 568                 psize = 2;
 569                 alen = 4; apos = 12; rlen = 4; rpos = 8;
 570                 glen = 4; gpos = 4; blen = 4; bpos = 0;
 571         break;
 572         case PF_L8:
 573                 psize = 1;
 574                 alen = 0; apos = 0; rlen = 8; rpos = 0;
 575                 glen = 8; gpos = 0; blen = 8; bpos = 0;
 576         break;
 577         case PF_AL44:
 578                 psize = 1;
 579                 alen = 4; apos = 4; rlen = 4; rpos = 0;
 580                 glen = 4; gpos = 0; blen = 4; bpos = 0;
 581         break;
 582         case PF_AL88:
 583                 psize = 2;
 584                 alen = 8; apos = 8; rlen = 8; rpos = 0;
 585                 glen = 8; gpos = 0; blen = 8; bpos = 0;
 586         break;
 587         default:
 588                 ret = NB_PF; /* error case, trace msg is handled by the caller */
 589         break;
 590         }
 591
 592         if (ret == PF_FLEXIBLE) {
 593                 regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs,
 594                              (rlen << 14)  + (rpos << 9) + (alen << 5) + apos);
 595
 596                 regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs,
 597                              (psize << 18) + (blen << 14)  + (bpos << 9) + (glen << 5) + gpos);
 598         }
 599
 600         return ret;
 601 }
 602
 603 /*
 604  * All non-alpha color formats derived from native alpha color formats are
 605  * either characterized by a FourCC format code
 606  */
 607 static inline u32 is_xrgb(u32 drm)
 608 {
 609         return ((drm & 0xFF) == 'X' || ((drm >> 8) & 0xFF) == 'X');
 610 }
 611
 612 static inline void ltdc_set_ycbcr_config(struct drm_plane *plane, u32 drm_pix_fmt)
 613 {
 614         struct ltdc_device *ldev = plane_to_ltdc(plane);
 615         struct drm_plane_state *state = plane->state;
 616         u32 lofs = plane->index * LAY_OFS;
 617         u32 val;
 618
 619         switch (drm_pix_fmt) {
 620         case DRM_FORMAT_YUYV:
 621                 val = (YCM_I << 4) | LxPCR_YF | LxPCR_CBF;
 622                 break;
 623         case DRM_FORMAT_YVYU:
 624                 val = (YCM_I << 4) | LxPCR_YF;
 625                 break;
 626         case DRM_FORMAT_UYVY:
 627                 val = (YCM_I << 4) | LxPCR_CBF;
 628                 break;
 629         case DRM_FORMAT_VYUY:
 630                 val = (YCM_I << 4);
 631                 break;
 632         case DRM_FORMAT_NV12:
 633                 val = (YCM_SP << 4) | LxPCR_CBF;
 634                 break;
 635         case DRM_FORMAT_NV21:
 636                 val = (YCM_SP << 4);
 637                 break;
 638         case DRM_FORMAT_YUV420:
 639         case DRM_FORMAT_YVU420:
 640                 val = (YCM_FP << 4);
 641                 break;
 642         default:
 643                 /* RGB or not a YCbCr supported format */
 644                 DRM_ERROR("Unsupported pixel format: %u\n", drm_pix_fmt);
 645                 return;
 646         }
 647
 648         /* Enable limited range */
 649         if (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE)
 650                 val |= LxPCR_YREN;
 651
 652         /* enable ycbcr conversion */
 653         val |= LxPCR_YCEN;
 654
 655         regmap_write(ldev->regmap, LTDC_L1PCR + lofs, val);
 656 }
 657
 658 static inline void ltdc_set_ycbcr_coeffs(struct drm_plane *plane)
 659 {
 660         struct ltdc_device *ldev = plane_to_ltdc(plane);
 661         struct drm_plane_state *state = plane->state;
 662         enum drm_color_encoding enc = state->color_encoding;
 663         enum drm_color_range ran = state->color_range;
 664         u32 lofs = plane->index * LAY_OFS;
 665
 666         if (enc != DRM_COLOR_YCBCR_BT601 && enc != DRM_COLOR_YCBCR_BT709) {
 667                 DRM_ERROR("color encoding %d not supported, use bt601 by default\n", enc);
 668                 /* set by default color encoding to DRM_COLOR_YCBCR_BT601 */
 669                 enc = DRM_COLOR_YCBCR_BT601;
 670         }
 671
 672         if (ran != DRM_COLOR_YCBCR_LIMITED_RANGE && ran != DRM_COLOR_YCBCR_FULL_RANGE) {
 673                 DRM_ERROR("color range %d not supported, use limited range by default\n", ran);
 674                 /* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */
 675                 ran = DRM_COLOR_YCBCR_LIMITED_RANGE;
 676         }
 677
 678         DRM_DEBUG_DRIVER("Color encoding=%d, range=%d\n", enc, ran);
 679         regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs,
 680                      ltdc_ycbcr2rgb_coeffs[enc][ran][0]);
 681         regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs,
 682                      ltdc_ycbcr2rgb_coeffs[enc][ran][1]);
 683 }
 684
 685 static inline void ltdc_irq_crc_handle(struct ltdc_device *ldev,
 686                                        struct drm_crtc *crtc)
 687 {
 688         u32 crc;
 689         int ret;
 690
 691         if (ldev->crc_skip_count < CRC_SKIP_FRAMES) {
 692                 ldev->crc_skip_count++;
 693                 return;
 694         }
 695
 696         /* Get the CRC of the frame */
 697         ret = regmap_read(ldev->regmap, LTDC_CCRCR, &crc);
 698         if (ret)
 699                 return;
 700
 701         /* Report to DRM the CRC (hw dependent feature) */
 702         drm_crtc_add_crc_entry(crtc, true, drm_crtc_accurate_vblank_count(crtc), &crc);
 703 }
 704
 705 static irqreturn_t ltdc_irq_thread(int irq, void *arg)
 706 {
 707         struct drm_device *ddev = arg;
 708         struct ltdc_device *ldev = ddev->dev_private;
 709         struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
 710
 711         /* Line IRQ : trigger the vblank event */
 712         if (ldev->irq_status & ISR_LIF) {
 713                 drm_crtc_handle_vblank(crtc);
 714
 715                 /* Early return if CRC is not active */
 716                 if (ldev->crc_active)
 717                         ltdc_irq_crc_handle(ldev, crtc);
 718         }
 719
 720         mutex_lock(&ldev->err_lock);
 721         if (ldev->irq_status & ISR_TERRIF)
 722                 ldev->transfer_err++;
 723         if (ldev->irq_status & ISR_FUEIF)
 724                 ldev->fifo_err++;
 725         if (ldev->irq_status & ISR_FUWIF)
 726                 ldev->fifo_warn++;
 727         mutex_unlock(&ldev->err_lock);
 728
 729         return IRQ_HANDLED;
 730 }
 731
 732 static irqreturn_t ltdc_irq(int irq, void *arg)
 733 {
 734         struct drm_device *ddev = arg;
 735         struct ltdc_device *ldev = ddev->dev_private;
 736
 737         /*
 738          *  Read & Clear the interrupt status
 739          *  In order to write / read registers in this critical section
 740          *  very quickly, the regmap functions are not used.
 741          */
 742         ldev->irq_status = readl_relaxed(ldev->regs + LTDC_ISR);
 743         writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR);
 744
 745         return IRQ_WAKE_THREAD;
 746 }
 747
 748 /*
 749  * DRM_CRTC
 750  */
 751
 752 static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
 753 {
 754         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 755         struct drm_color_lut *lut;
 756         u32 val;
 757         int i;
 758
 759         if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
 760                 return;
 761
 762         lut = (struct drm_color_lut *)crtc->state->gamma_lut->data;
 763
 764         for (i = 0; i < CLUT_SIZE; i++, lut++) {
 765                 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) |
 766                         (lut->blue >> 8) | (i << 24);
 767                 regmap_write(ldev->regmap, LTDC_L1CLUTWR, val);
 768         }
 769 }
 770
 771 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
 772                                     struct drm_atomic_state *state)
 773 {
 774         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 775         struct drm_device *ddev = crtc->dev;
 776
 777         DRM_DEBUG_DRIVER("\n");
 778
 779         pm_runtime_get_sync(ddev->dev);
 780
 781         /* Sets the background color value */
 782         regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK);
 783
 784         /* Enable IRQ */
 785         regmap_set_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_TERRIE);
 786
 787         /* Commit shadow registers = update planes at next vblank */
 788         if (!ldev->caps.plane_reg_shadow)
 789                 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
 790
 791         drm_crtc_vblank_on(crtc);
 792 }
 793
 794 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
 795                                      struct drm_atomic_state *state)
 796 {
 797         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 798         struct drm_device *ddev = crtc->dev;
 799         int layer_index = 0;
 800
 801         DRM_DEBUG_DRIVER("\n");
 802
 803         drm_crtc_vblank_off(crtc);
 804
 805         /* Disable all layers */
 806         for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++)
 807                 regmap_write_bits(ldev->regmap, LTDC_L1CR + layer_index * LAY_OFS, LXCR_MASK, 0);
 808
 809         /* Disable IRQ */
 810         regmap_clear_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_TERRIE);
 811
 812         /* immediately commit disable of layers before switching off LTDC */
 813         if (!ldev->caps.plane_reg_shadow)
 814                 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR);
 815
 816         pm_runtime_put_sync(ddev->dev);
 817
 818         /*  clear interrupt error counters */
 819         mutex_lock(&ldev->err_lock);
 820         ldev->transfer_err = 0;
 821         ldev->fifo_err = 0;
 822         ldev->fifo_warn = 0;
 823         mutex_unlock(&ldev->err_lock);
 824 }
 825
 826 #define CLK_TOLERANCE_HZ 50
 827
 828 static enum drm_mode_status
 829 ltdc_crtc_mode_valid(struct drm_crtc *crtc,
 830                      const struct drm_display_mode *mode)
 831 {
 832         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 833         int target = mode->clock * 1000;
 834         int target_min = target - CLK_TOLERANCE_HZ;
 835         int target_max = target + CLK_TOLERANCE_HZ;
 836         int result;
 837
 838         result = clk_round_rate(ldev->pixel_clk, target);
 839
 840         DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
 841
 842         /* Filter modes according to the max frequency supported by the pads */
 843         if (result > ldev->caps.pad_max_freq_hz)
 844                 return MODE_CLOCK_HIGH;
 845
 846         /*
 847          * Accept all "preferred" modes:
 848          * - this is important for panels because panel clock tolerances are
 849          *   bigger than hdmi ones and there is no reason to not accept them
 850          *   (the fps may vary a little but it is not a problem).
 851          * - the hdmi preferred mode will be accepted too, but userland will
 852          *   be able to use others hdmi "valid" modes if necessary.
 853          */
 854         if (mode->type & DRM_MODE_TYPE_PREFERRED)
 855                 return MODE_OK;
 856
 857         /*
 858          * Filter modes according to the clock value, particularly useful for
 859          * hdmi modes that require precise pixel clocks.
 860          */
 861         if (result < target_min || result > target_max)
 862                 return MODE_CLOCK_RANGE;
 863
 864         return MODE_OK;
 865 }
 866
 867 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
 868                                  const struct drm_display_mode *mode,
 869                                  struct drm_display_mode *adjusted_mode)
 870 {
 871         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 872         int rate = mode->clock * 1000;
 873
 874         if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
 875                 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
 876                 return false;
 877         }
 878
 879         adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
 880
 881         DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n",
 882                          mode->clock, adjusted_mode->clock);
 883
 884         return true;
 885 }
 886
 887 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
 888 {
 889         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 890         struct drm_device *ddev = crtc->dev;
 891         struct drm_connector_list_iter iter;
 892         struct drm_connector *connector = NULL;
 893         struct drm_encoder *encoder = NULL, *en_iter;
 894         struct drm_bridge *bridge = NULL, *br_iter;
 895         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 896         u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
 897         u32 total_width, total_height;
 898         u32 bus_formats = MEDIA_BUS_FMT_RGB888_1X24;
 899         u32 bus_flags = 0;
 900         u32 val;
 901         int ret;
 902
 903         /* get encoder from crtc */
 904         drm_for_each_encoder(en_iter, ddev)
 905                 if (en_iter->crtc == crtc) {
 906                         encoder = en_iter;
 907                         break;
 908                 }
 909
 910         if (encoder) {
 911                 /* get bridge from encoder */
 912                 list_for_each_entry(br_iter, &encoder->bridge_chain, chain_node)
 913                         if (br_iter->encoder == encoder) {
 914                                 bridge = br_iter;
 915                                 break;
 916                         }
 917
 918                 /* Get the connector from encoder */
 919                 drm_connector_list_iter_begin(ddev, &iter);
 920                 drm_for_each_connector_iter(connector, &iter)
 921                         if (connector->encoder == encoder)
 922                                 break;
 923                 drm_connector_list_iter_end(&iter);
 924         }
 925
 926         if (bridge && bridge->timings) {
 927                 bus_flags = bridge->timings->input_bus_flags;
 928         } else if (connector) {
 929                 bus_flags = connector->display_info.bus_flags;
 930                 if (connector->display_info.num_bus_formats)
 931                         bus_formats = connector->display_info.bus_formats[0];
 932         }
 933
 934         if (!pm_runtime_active(ddev->dev)) {
 935                 ret = pm_runtime_get_sync(ddev->dev);
 936                 if (ret) {
 937                         DRM_ERROR("Failed to set mode, cannot get sync\n");
 938                         return;
 939                 }
 940         }
 941
 942         DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
 943         DRM_DEBUG_DRIVER("Video mode: %dx%d", mode->hdisplay, mode->vdisplay);
 944         DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
 945                          mode->hsync_start - mode->hdisplay,
 946                          mode->htotal - mode->hsync_end,
 947                          mode->hsync_end - mode->hsync_start,
 948                          mode->vsync_start - mode->vdisplay,
 949                          mode->vtotal - mode->vsync_end,
 950                          mode->vsync_end - mode->vsync_start);
 951
 952         /* Convert video timings to ltdc timings */
 953         hsync = mode->hsync_end - mode->hsync_start - 1;
 954         vsync = mode->vsync_end - mode->vsync_start - 1;
 955         accum_hbp = mode->htotal - mode->hsync_start - 1;
 956         accum_vbp = mode->vtotal - mode->vsync_start - 1;
 957         accum_act_w = accum_hbp + mode->hdisplay;
 958         accum_act_h = accum_vbp + mode->vdisplay;
 959         total_width = mode->htotal - 1;
 960         total_height = mode->vtotal - 1;
 961
 962         /* Configures the HS, VS, DE and PC polarities. Default Active Low */
 963         val = 0;
 964
 965         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 966                 val |= GCR_HSPOL;
 967
 968         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 969                 val |= GCR_VSPOL;
 970
 971         if (bus_flags & DRM_BUS_FLAG_DE_LOW)
 972                 val |= GCR_DEPOL;
 973
 974         if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
 975                 val |= GCR_PCPOL;
 976
 977         regmap_update_bits(ldev->regmap, LTDC_GCR,
 978                            GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
 979
 980         /* Set Synchronization size */
 981         val = (hsync << 16) | vsync;
 982         regmap_update_bits(ldev->regmap, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
 983
 984         /* Set Accumulated Back porch */
 985         val = (accum_hbp << 16) | accum_vbp;
 986         regmap_update_bits(ldev->regmap, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
 987
 988         /* Set Accumulated Active Width */
 989         val = (accum_act_w << 16) | accum_act_h;
 990         regmap_update_bits(ldev->regmap, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
 991
 992         /* Set total width & height */
 993         val = (total_width << 16) | total_height;
 994         regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
 995
 996         regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1));
 997
 998         /* Configure the output format (hw version dependent) */
 999         if (ldev->caps.ycbcr_output) {
1000                 /* Input video dynamic_range & colorimetry */
1001                 int vic = drm_match_cea_mode(mode);
1002                 u32 val;
1003
1004                 if (vic == 6 || vic == 7 || vic == 21 || vic == 22 ||
1005                     vic == 2 || vic == 3 || vic == 17 || vic == 18)
1006                         /* ITU-R BT.601 */
1007                         val = 0;
1008                 else
1009                         /* ITU-R BT.709 */
1010                         val = EDCR_OCYSEL;
1011
1012                 switch (bus_formats) {
1013                 case MEDIA_BUS_FMT_YUYV8_1X16:
1014                         /* enable ycbcr output converter */
1015                         regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | val);
1016                         break;
1017                 case MEDIA_BUS_FMT_YVYU8_1X16:
1018                         /* enable ycbcr output converter & invert chrominance order */
1019                         regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | EDCR_OCYCO | val);
1020                         break;
1021                 default:
1022                         /* disable ycbcr output converter */
1023                         regmap_write(ldev->regmap, LTDC_EDCR, 0);
1024                         break;
1025                 }
1026         }
1027 }
1028
1029 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
1030                                    struct drm_atomic_state *state)
1031 {
1032         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1033         struct drm_device *ddev = crtc->dev;
1034         struct drm_pending_vblank_event *event = crtc->state->event;
1035
1036         DRM_DEBUG_ATOMIC("\n");
1037
1038         ltdc_crtc_update_clut(crtc);
1039
1040         /* Commit shadow registers = update planes at next vblank */
1041         if (!ldev->caps.plane_reg_shadow)
1042                 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
1043
1044         if (event) {
1045                 crtc->state->event = NULL;
1046
1047                 spin_lock_irq(&ddev->event_lock);
1048                 if (drm_crtc_vblank_get(crtc) == 0)
1049                         drm_crtc_arm_vblank_event(crtc, event);
1050                 else
1051                         drm_crtc_send_vblank_event(crtc, event);
1052                 spin_unlock_irq(&ddev->event_lock);
1053         }
1054 }
1055
1056 static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc,
1057                                            bool in_vblank_irq,
1058                                            int *vpos, int *hpos,
1059                                            ktime_t *stime, ktime_t *etime,
1060                                            const struct drm_display_mode *mode)
1061 {
1062         struct drm_device *ddev = crtc->dev;
1063         struct ltdc_device *ldev = ddev->dev_private;
1064         int line, vactive_start, vactive_end, vtotal;
1065
1066         if (stime)
1067                 *stime = ktime_get();
1068
1069         /* The active area starts after vsync + front porch and ends
1070          * at vsync + front porc + display size.
1071          * The total height also include back porch.
1072          * We have 3 possible cases to handle:
1073          * - line < vactive_start: vpos = line - vactive_start and will be
1074          * negative
1075          * - vactive_start < line < vactive_end: vpos = line - vactive_start
1076          * and will be positive
1077          * - line > vactive_end: vpos = line - vtotal - vactive_start
1078          * and will negative
1079          *
1080          * Computation for the two first cases are identical so we can
1081          * simplify the code and only test if line > vactive_end
1082          */
1083         if (pm_runtime_active(ddev->dev)) {
1084                 regmap_read(ldev->regmap, LTDC_CPSR, &line);
1085                 line &= CPSR_CYPOS;
1086                 regmap_read(ldev->regmap, LTDC_BPCR, &vactive_start);
1087                 vactive_start &= BPCR_AVBP;
1088                 regmap_read(ldev->regmap, LTDC_AWCR, &vactive_end);
1089                 vactive_end &= AWCR_AAH;
1090                 regmap_read(ldev->regmap, LTDC_TWCR, &vtotal);
1091                 vtotal &= TWCR_TOTALH;
1092
1093                 if (line > vactive_end)
1094                         *vpos = line - vtotal - vactive_start;
1095                 else
1096                         *vpos = line - vactive_start;
1097         } else {
1098                 *vpos = 0;
1099         }
1100
1101         *hpos = 0;
1102
1103         if (etime)
1104                 *etime = ktime_get();
1105
1106         return true;
1107 }
1108
1109 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
1110         .mode_valid = ltdc_crtc_mode_valid,
1111         .mode_fixup = ltdc_crtc_mode_fixup,
1112         .mode_set_nofb = ltdc_crtc_mode_set_nofb,
1113         .atomic_flush = ltdc_crtc_atomic_flush,
1114         .atomic_enable = ltdc_crtc_atomic_enable,
1115         .atomic_disable = ltdc_crtc_atomic_disable,
1116         .get_scanout_position = ltdc_crtc_get_scanout_position,
1117 };
1118
1119 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc)
1120 {
1121         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1122         struct drm_crtc_state *state = crtc->state;
1123
1124         DRM_DEBUG_DRIVER("\n");
1125
1126         if (state->enable)
1127                 regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE);
1128         else
1129                 return -EPERM;
1130
1131         return 0;
1132 }
1133
1134 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc)
1135 {
1136         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1137
1138         DRM_DEBUG_DRIVER("\n");
1139         regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE);
1140 }
1141
1142 static int ltdc_crtc_set_crc_source(struct drm_crtc *crtc, const char *source)
1143 {
1144         struct ltdc_device *ldev;
1145         int ret;
1146
1147         DRM_DEBUG_DRIVER("\n");
1148
1149         if (!crtc)
1150                 return -ENODEV;
1151
1152         ldev = crtc_to_ltdc(crtc);
1153
1154         if (source && strcmp(source, "auto") == 0) {
1155                 ldev->crc_active = true;
1156                 ret = regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN);
1157         } else if (!source) {
1158                 ldev->crc_active = false;
1159                 ret = regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN);
1160         } else {
1161                 ret = -EINVAL;
1162         }
1163
1164         ldev->crc_skip_count = 0;
1165         return ret;
1166 }
1167
1168 static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc,
1169                                        const char *source, size_t *values_cnt)
1170 {
1171         DRM_DEBUG_DRIVER("\n");
1172
1173         if (!crtc)
1174                 return -ENODEV;
1175
1176         if (source && strcmp(source, "auto") != 0) {
1177                 DRM_DEBUG_DRIVER("Unknown CRC source %s for %s\n",
1178                                  source, crtc->name);
1179                 return -EINVAL;
1180         }
1181
1182         *values_cnt = 1;
1183         return 0;
1184 }
1185
1186 static void ltdc_crtc_atomic_print_state(struct drm_printer *p,
1187                                          const struct drm_crtc_state *state)
1188 {
1189         struct drm_crtc *crtc = state->crtc;
1190         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1191
1192         drm_printf(p, "\ttransfer_error=%d\n", ldev->transfer_err);
1193         drm_printf(p, "\tfifo_underrun_error=%d\n", ldev->fifo_err);
1194         drm_printf(p, "\tfifo_underrun_warning=%d\n", ldev->fifo_warn);
1195         drm_printf(p, "\tfifo_underrun_threshold=%d\n", ldev->fifo_threshold);
1196 }
1197
1198 static const struct drm_crtc_funcs ltdc_crtc_funcs = {
1199         .set_config = drm_atomic_helper_set_config,
1200         .page_flip = drm_atomic_helper_page_flip,
1201         .reset = drm_atomic_helper_crtc_reset,
1202         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1203         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1204         .enable_vblank = ltdc_crtc_enable_vblank,
1205         .disable_vblank = ltdc_crtc_disable_vblank,
1206         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1207         .atomic_print_state = ltdc_crtc_atomic_print_state,
1208 };
1209
1210 static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = {
1211         .set_config = drm_atomic_helper_set_config,
1212         .page_flip = drm_atomic_helper_page_flip,
1213         .reset = drm_atomic_helper_crtc_reset,
1214         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1215         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1216         .enable_vblank = ltdc_crtc_enable_vblank,
1217         .disable_vblank = ltdc_crtc_disable_vblank,
1218         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1219         .set_crc_source = ltdc_crtc_set_crc_source,
1220         .verify_crc_source = ltdc_crtc_verify_crc_source,
1221         .atomic_print_state = ltdc_crtc_atomic_print_state,
1222 };
1223
1224 /*
1225  * DRM_PLANE
1226  */
1227
1228 static int ltdc_plane_atomic_check(struct drm_plane *plane,
1229                                    struct drm_atomic_state *state)
1230 {
1231         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1232                                                                                  plane);
1233         struct drm_framebuffer *fb = new_plane_state->fb;
1234         u32 src_w, src_h;
1235
1236         DRM_DEBUG_DRIVER("\n");
1237
1238         if (!fb)
1239                 return 0;
1240
1241         /* convert src_ from 16:16 format */
1242         src_w = new_plane_state->src_w >> 16;
1243         src_h = new_plane_state->src_h >> 16;
1244
1245         /* Reject scaling */
1246         if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) {
1247                 DRM_DEBUG_DRIVER("Scaling is not supported");
1248
1249                 return -EINVAL;
1250         }
1251
1252         return 0;
1253 }
1254
1255 static void ltdc_plane_atomic_update(struct drm_plane *plane,
1256                                      struct drm_atomic_state *state)
1257 {
1258         struct ltdc_device *ldev = plane_to_ltdc(plane);
1259         struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state,
1260                                                                           plane);
1261         struct drm_framebuffer *fb = newstate->fb;
1262         u32 lofs = plane->index * LAY_OFS;
1263         u32 x0 = newstate->crtc_x;
1264         u32 x1 = newstate->crtc_x + newstate->crtc_w - 1;
1265         u32 y0 = newstate->crtc_y;
1266         u32 y1 = newstate->crtc_y + newstate->crtc_h - 1;
1267         u32 src_x, src_y, src_w, src_h;
1268         u32 val, pitch_in_bytes, line_length, line_number, ahbp, avbp, bpcr;
1269         u32 paddr, paddr1, paddr2;
1270         enum ltdc_pix_fmt pf;
1271
1272         if (!newstate->crtc || !fb) {
1273                 DRM_DEBUG_DRIVER("fb or crtc NULL");
1274                 return;
1275         }
1276
1277         /* convert src_ from 16:16 format */
1278         src_x = newstate->src_x >> 16;
1279         src_y = newstate->src_y >> 16;
1280         src_w = newstate->src_w >> 16;
1281         src_h = newstate->src_h >> 16;
1282
1283         DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
1284                          plane->base.id, fb->base.id,
1285                          src_w, src_h, src_x, src_y,
1286                          newstate->crtc_w, newstate->crtc_h,
1287                          newstate->crtc_x, newstate->crtc_y);
1288
1289         regmap_read(ldev->regmap, LTDC_BPCR, &bpcr);
1290
1291         ahbp = (bpcr & BPCR_AHBP) >> 16;
1292         avbp = bpcr & BPCR_AVBP;
1293
1294         /* Configures the horizontal start and stop position */
1295         val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
1296         regmap_write_bits(ldev->regmap, LTDC_L1WHPCR + lofs,
1297                           LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
1298
1299         /* Configures the vertical start and stop position */
1300         val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
1301         regmap_write_bits(ldev->regmap, LTDC_L1WVPCR + lofs,
1302                           LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
1303
1304         /* Specifies the pixel format */
1305         pf = to_ltdc_pixelformat(fb->format->format);
1306         for (val = 0; val < NB_PF; val++)
1307                 if (ldev->caps.pix_fmt_hw[val] == pf)
1308                         break;
1309
1310         /* Use the flexible color format feature if necessary and available */
1311         if (ldev->caps.pix_fmt_flex && val == NB_PF)
1312                 val = ltdc_set_flexible_pixel_format(plane, pf);
1313
1314         if (val == NB_PF) {
1315                 DRM_ERROR("Pixel format %.4s not supported\n",
1316                           (char *)&fb->format->format);
1317                 val = 0;        /* set by default ARGB 32 bits */
1318         }
1319         regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
1320
1321         /* Specifies the constant alpha value */
1322         val = newstate->alpha >> 8;
1323         regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
1324
1325         /* Specifies the blending factors */
1326         val = BF1_PAXCA | BF2_1PAXCA;
1327         if (!fb->format->has_alpha)
1328                 val = BF1_CA | BF2_1CA;
1329
1330         /* Manage hw-specific capabilities */
1331         if (ldev->caps.non_alpha_only_l1 &&
1332             plane->type != DRM_PLANE_TYPE_PRIMARY)
1333                 val = BF1_PAXCA | BF2_1PAXCA;
1334
1335         if (ldev->caps.dynamic_zorder) {
1336                 val |= (newstate->normalized_zpos << 16);
1337                 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs,
1338                                   LXBFCR_BF2 | LXBFCR_BF1 | LXBFCR_BOR, val);
1339         } else {
1340                 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs,
1341                                   LXBFCR_BF2 | LXBFCR_BF1, val);
1342         }
1343
1344         /* Sets the FB address */
1345         paddr = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 0);
1346
1347         if (newstate->rotation & DRM_MODE_REFLECT_X)
1348                 paddr += (fb->format->cpp[0] * (x1 - x0 + 1)) - 1;
1349
1350         if (newstate->rotation & DRM_MODE_REFLECT_Y)
1351                 paddr += (fb->pitches[0] * (y1 - y0));
1352
1353         DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
1354         regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr);
1355
1356         /* Configures the color frame buffer pitch in bytes & line length */
1357         line_length = fb->format->cpp[0] *
1358                       (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
1359
1360         if (newstate->rotation & DRM_MODE_REFLECT_Y)
1361                 /* Compute negative value (signed on 16 bits) for the picth */
1362                 pitch_in_bytes = 0x10000 - fb->pitches[0];
1363         else
1364                 pitch_in_bytes = fb->pitches[0];
1365
1366         val = (pitch_in_bytes << 16) | line_length;
1367         regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
1368
1369         /* Configures the frame buffer line number */
1370         line_number = y1 - y0 + 1;
1371         regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number);
1372
1373         if (ldev->caps.ycbcr_input) {
1374                 if (fb->format->is_yuv) {
1375                         switch (fb->format->format) {
1376                         case DRM_FORMAT_NV12:
1377                         case DRM_FORMAT_NV21:
1378                         /* Configure the auxiliary frame buffer address 0 */
1379                         paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1);
1380
1381                         if (newstate->rotation & DRM_MODE_REFLECT_X)
1382                                 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1;
1383
1384                         if (newstate->rotation & DRM_MODE_REFLECT_Y)
1385                                 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1;
1386
1387                         regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1);
1388                         break;
1389                         case DRM_FORMAT_YUV420:
1390                         /* Configure the auxiliary frame buffer address 0 & 1 */
1391                         paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1);
1392                         paddr2 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 2);
1393
1394                         if (newstate->rotation & DRM_MODE_REFLECT_X) {
1395                                 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1;
1396                                 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1;
1397                         }
1398
1399                         if (newstate->rotation & DRM_MODE_REFLECT_Y) {
1400                                 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1;
1401                                 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1;
1402                         }
1403
1404                         regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1);
1405                         regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2);
1406                         break;
1407                         case DRM_FORMAT_YVU420:
1408                         /* Configure the auxiliary frame buffer address 0 & 1 */
1409                         paddr1 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 2);
1410                         paddr2 = (u32)drm_fb_dma_get_gem_addr(fb, newstate, 1);
1411
1412                         if (newstate->rotation & DRM_MODE_REFLECT_X) {
1413                                 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1;
1414                                 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1;
1415                         }
1416
1417                         if (newstate->rotation & DRM_MODE_REFLECT_Y) {
1418                                 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1;
1419                                 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1;
1420                         }
1421
1422                         regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1);
1423                         regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2);
1424                         break;
1425                         }
1426
1427                         /*
1428                          * Set the length and the number of lines of the auxiliary
1429                          * buffers if the framebuffer contains more than one plane.
1430                          */
1431                         if (fb->format->num_planes > 1) {
1432                                 if (newstate->rotation & DRM_MODE_REFLECT_Y)
1433                                         /*
1434                                          * Compute negative value (signed on 16 bits)
1435                                          * for the picth
1436                                          */
1437                                         pitch_in_bytes = 0x10000 - fb->pitches[1];
1438                                 else
1439                                         pitch_in_bytes = fb->pitches[1];
1440
1441                                 line_length = ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) +
1442                                               (ldev->caps.bus_width >> 3) - 1;
1443
1444                                 /* Configure the auxiliary buffer length */
1445                                 val = (pitch_in_bytes << 16) | line_length;
1446                                 regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val);
1447
1448                                 /* Configure the auxiliary frame buffer line number */
1449                                 val = line_number >> 1;
1450                                 regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val);
1451                         }
1452
1453                         /* Configure YCbC conversion coefficient */
1454                         ltdc_set_ycbcr_coeffs(plane);
1455
1456                         /* Configure YCbCr format and enable/disable conversion */
1457                         ltdc_set_ycbcr_config(plane, fb->format->format);
1458                 } else {
1459                         /* disable ycbcr conversion */
1460                         regmap_write(ldev->regmap, LTDC_L1PCR + lofs, 0);
1461                 }
1462         }
1463
1464         /* Enable layer and CLUT if needed */
1465         val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
1466         val |= LXCR_LEN;
1467
1468         /* Enable horizontal mirroring if requested */
1469         if (newstate->rotation & DRM_MODE_REFLECT_X)
1470                 val |= LXCR_HMEN;
1471
1472         regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_MASK, val);
1473
1474         /* Commit shadow registers = update plane at next vblank */
1475         if (ldev->caps.plane_reg_shadow)
1476                 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
1477                                   LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR);
1478
1479         ldev->plane_fpsi[plane->index].counter++;
1480
1481         mutex_lock(&ldev->err_lock);
1482         if (ldev->transfer_err) {
1483                 DRM_WARN("ltdc transfer error: %d\n", ldev->transfer_err);
1484                 ldev->transfer_err = 0;
1485         }
1486
1487         if (ldev->caps.fifo_threshold) {
1488                 if (ldev->fifo_err) {
1489                         DRM_WARN("ltdc fifo underrun: please verify display mode\n");
1490                         ldev->fifo_err = 0;
1491                 }
1492         } else {
1493                 if (ldev->fifo_warn >= ldev->fifo_threshold) {
1494                         DRM_WARN("ltdc fifo underrun: please verify display mode\n");
1495                         ldev->fifo_warn = 0;
1496                 }
1497         }
1498         mutex_unlock(&ldev->err_lock);
1499 }
1500
1501 static void ltdc_plane_atomic_disable(struct drm_plane *plane,
1502                                       struct drm_atomic_state *state)
1503 {
1504         struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
1505                                                                           plane);
1506         struct ltdc_device *ldev = plane_to_ltdc(plane);
1507         u32 lofs = plane->index * LAY_OFS;
1508
1509         /* Disable layer */
1510         regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_MASK, 0);
1511
1512         /* Reset the layer transparency to hide any related background color */
1513         regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, 0x00);
1514
1515         /* Commit shadow registers = update plane at next vblank */
1516         if (ldev->caps.plane_reg_shadow)
1517                 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
1518                                   LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR);
1519
1520         DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
1521                          oldstate->crtc->base.id, plane->base.id);
1522 }
1523
1524 static void ltdc_plane_atomic_print_state(struct drm_printer *p,
1525                                           const struct drm_plane_state *state)
1526 {
1527         struct drm_plane *plane = state->plane;
1528         struct ltdc_device *ldev = plane_to_ltdc(plane);
1529         struct fps_info *fpsi = &ldev->plane_fpsi[plane->index];
1530         int ms_since_last;
1531         ktime_t now;
1532
1533         now = ktime_get();
1534         ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp));
1535
1536         drm_printf(p, "\tuser_updates=%dfps\n",
1537                    DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last));
1538
1539         fpsi->last_timestamp = now;
1540         fpsi->counter = 0;
1541 }
1542
1543 static const struct drm_plane_funcs ltdc_plane_funcs = {
1544         .update_plane = drm_atomic_helper_update_plane,
1545         .disable_plane = drm_atomic_helper_disable_plane,
1546         .reset = drm_atomic_helper_plane_reset,
1547         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1548         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1549         .atomic_print_state = ltdc_plane_atomic_print_state,
1550 };
1551
1552 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
1553         .atomic_check = ltdc_plane_atomic_check,
1554         .atomic_update = ltdc_plane_atomic_update,
1555         .atomic_disable = ltdc_plane_atomic_disable,
1556 };
1557
1558 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
1559                                            enum drm_plane_type type,
1560                                            int index)
1561 {
1562         unsigned long possible_crtcs = CRTC_MASK;
1563         struct ltdc_device *ldev = ddev->dev_private;
1564         struct device *dev = ddev->dev;
1565         struct drm_plane *plane;
1566         unsigned int i, nb_fmt = 0;
1567         u32 *formats;
1568         u32 drm_fmt;
1569         const u64 *modifiers = ltdc_format_modifiers;
1570         u32 lofs = index * LAY_OFS;
1571         u32 val;
1572
1573         /* Allocate the biggest size according to supported color formats */
1574         formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb +
1575                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) +
1576                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) +
1577                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp)) *
1578                                sizeof(*formats), GFP_KERNEL);
1579         if (!formats)
1580                 return NULL;
1581
1582         for (i = 0; i < ldev->caps.pix_fmt_nb; i++) {
1583                 drm_fmt = ldev->caps.pix_fmt_drm[i];
1584
1585                 /* Manage hw-specific capabilities */
1586                 if (ldev->caps.non_alpha_only_l1)
1587                         /* XR24 & RX24 like formats supported only on primary layer */
1588                         if (type != DRM_PLANE_TYPE_PRIMARY && is_xrgb(drm_fmt))
1589                                 continue;
1590
1591                 formats[nb_fmt++] = drm_fmt;
1592         }
1593
1594         /* Add YCbCr supported pixel formats */
1595         if (ldev->caps.ycbcr_input) {
1596                 regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val);
1597                 if (val & LXCR_C1R_YIA) {
1598                         memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_cp,
1599                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) * sizeof(*formats));
1600                         nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp);
1601                 }
1602                 if (val & LXCR_C1R_YSPA) {
1603                         memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_sp,
1604                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) * sizeof(*formats));
1605                         nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp);
1606                 }
1607                 if (val & LXCR_C1R_YFPA) {
1608                         memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_fp,
1609                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp) * sizeof(*formats));
1610                         nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp);
1611                 }
1612         }
1613
1614         plane = drmm_universal_plane_alloc(ddev, struct drm_plane, dev,
1615                                            possible_crtcs, &ltdc_plane_funcs, formats,
1616                                            nb_fmt, modifiers, type, NULL);
1617         if (IS_ERR(plane))
1618                 return NULL;
1619
1620         if (ldev->caps.ycbcr_input) {
1621                 if (val & (LXCR_C1R_YIA | LXCR_C1R_YSPA | LXCR_C1R_YFPA))
1622                         drm_plane_create_color_properties(plane,
1623                                                           BIT(DRM_COLOR_YCBCR_BT601) |
1624                                                           BIT(DRM_COLOR_YCBCR_BT709),
1625                                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1626                                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1627                                                           DRM_COLOR_YCBCR_BT601,
1628                                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
1629         }
1630
1631         drm_plane_helper_add(plane, &ltdc_plane_helper_funcs);
1632
1633         drm_plane_create_alpha_property(plane);
1634
1635         DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
1636
1637         return plane;
1638 }
1639
1640 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
1641 {
1642         struct ltdc_device *ldev = ddev->dev_private;
1643         struct drm_plane *primary, *overlay;
1644         int supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
1645         unsigned int i;
1646         int ret;
1647
1648         primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0);
1649         if (!primary) {
1650                 DRM_ERROR("Can not create primary plane\n");
1651                 return -EINVAL;
1652         }
1653
1654         if (ldev->caps.dynamic_zorder)
1655                 drm_plane_create_zpos_property(primary, 0, 0, ldev->caps.nb_layers - 1);
1656         else
1657                 drm_plane_create_zpos_immutable_property(primary, 0);
1658
1659         if (ldev->caps.plane_rotation)
1660                 drm_plane_create_rotation_property(primary, DRM_MODE_ROTATE_0,
1661                                                    supported_rotations);
1662
1663         /* Init CRTC according to its hardware features */
1664         if (ldev->caps.crc)
1665                 ret = drmm_crtc_init_with_planes(ddev, crtc, primary, NULL,
1666                                                  &ltdc_crtc_with_crc_support_funcs, NULL);
1667         else
1668                 ret = drmm_crtc_init_with_planes(ddev, crtc, primary, NULL,
1669                                                  &ltdc_crtc_funcs, NULL);
1670         if (ret) {
1671                 DRM_ERROR("Can not initialize CRTC\n");
1672                 return ret;
1673         }
1674
1675         drm_crtc_helper_add(crtc, &ltdc_crtc_helper_funcs);
1676
1677         drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE);
1678         drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE);
1679
1680         DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
1681
1682         /* Add planes. Note : the first layer is used by primary plane */
1683         for (i = 1; i < ldev->caps.nb_layers; i++) {
1684                 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY, i);
1685                 if (!overlay) {
1686                         DRM_ERROR("Can not create overlay plane %d\n", i);
1687                         return -ENOMEM;
1688                 }
1689                 if (ldev->caps.dynamic_zorder)
1690                         drm_plane_create_zpos_property(overlay, i, 0, ldev->caps.nb_layers - 1);
1691                 else
1692                         drm_plane_create_zpos_immutable_property(overlay, i);
1693
1694                 if (ldev->caps.plane_rotation)
1695                         drm_plane_create_rotation_property(overlay, DRM_MODE_ROTATE_0,
1696                                                            supported_rotations);
1697         }
1698
1699         return 0;
1700 }
1701
1702 static void ltdc_encoder_disable(struct drm_encoder *encoder)
1703 {
1704         struct drm_device *ddev = encoder->dev;
1705         struct ltdc_device *ldev = ddev->dev_private;
1706
1707         DRM_DEBUG_DRIVER("\n");
1708
1709         /* Disable LTDC */
1710         regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);
1711
1712         /* Set to sleep state the pinctrl whatever type of encoder */
1713         pinctrl_pm_select_sleep_state(ddev->dev);
1714 }
1715
1716 static void ltdc_encoder_enable(struct drm_encoder *encoder)
1717 {
1718         struct drm_device *ddev = encoder->dev;
1719         struct ltdc_device *ldev = ddev->dev_private;
1720
1721         DRM_DEBUG_DRIVER("\n");
1722
1723         /* set fifo underrun threshold register */
1724         if (ldev->caps.fifo_threshold)
1725                 regmap_write(ldev->regmap, LTDC_FUT, ldev->fifo_threshold);
1726
1727         /* Enable LTDC */
1728         regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);
1729 }
1730
1731 static void ltdc_encoder_mode_set(struct drm_encoder *encoder,
1732                                   struct drm_display_mode *mode,
1733                                   struct drm_display_mode *adjusted_mode)
1734 {
1735         struct drm_device *ddev = encoder->dev;
1736
1737         DRM_DEBUG_DRIVER("\n");
1738
1739         /*
1740          * Set to default state the pinctrl only with DPI type.
1741          * Others types like DSI, don't need pinctrl due to
1742          * internal bridge (the signals do not come out of the chipset).
1743          */
1744         if (encoder->encoder_type == DRM_MODE_ENCODER_DPI)
1745                 pinctrl_pm_select_default_state(ddev->dev);
1746 }
1747
1748 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = {
1749         .disable = ltdc_encoder_disable,
1750         .enable = ltdc_encoder_enable,
1751         .mode_set = ltdc_encoder_mode_set,
1752 };
1753
1754 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge)
1755 {
1756         struct drm_encoder *encoder;
1757         int ret;
1758
1759         encoder = drmm_simple_encoder_alloc(ddev, struct drm_encoder, dev,
1760                                             DRM_MODE_ENCODER_DPI);
1761         if (IS_ERR(encoder))
1762                 return PTR_ERR(encoder);
1763
1764         encoder->possible_crtcs = CRTC_MASK;
1765         encoder->possible_clones = 0;   /* No cloning support */
1766
1767         drm_encoder_helper_add(encoder, &ltdc_encoder_helper_funcs);
1768
1769         ret = drm_bridge_attach(encoder, bridge, NULL, 0);
1770         if (ret)
1771                 return ret;
1772
1773         DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id);
1774
1775         return 0;
1776 }
1777
1778 static int ltdc_get_caps(struct drm_device *ddev)
1779 {
1780         struct ltdc_device *ldev = ddev->dev_private;
1781         u32 bus_width_log2, lcr, gc2r;
1782
1783         /*
1784          * at least 1 layer must be managed & the number of layers
1785          * must not exceed LTDC_MAX_LAYER
1786          */
1787         regmap_read(ldev->regmap, LTDC_LCR, &lcr);
1788
1789         ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER);
1790
1791         /* set data bus width */
1792         regmap_read(ldev->regmap, LTDC_GC2R, &gc2r);
1793         bus_width_log2 = (gc2r & GC2R_BW) >> 4;
1794         ldev->caps.bus_width = 8 << bus_width_log2;
1795         regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version);
1796
1797         switch (ldev->caps.hw_version) {
1798         case HWVER_10200:
1799         case HWVER_10300:
1800                 ldev->caps.layer_ofs = LAY_OFS_0;
1801                 ldev->caps.layer_regs = ltdc_layer_regs_a0;
1802                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
1803                 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a0;
1804                 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a0);
1805                 ldev->caps.pix_fmt_flex = false;
1806                 /*
1807                  * Hw older versions support non-alpha color formats derived
1808                  * from native alpha color formats only on the primary layer.
1809                  * For instance, RG16 native format without alpha works fine
1810                  * on 2nd layer but XR24 (derived color format from AR24)
1811                  * does not work on 2nd layer.
1812                  */
1813                 ldev->caps.non_alpha_only_l1 = true;
1814                 ldev->caps.pad_max_freq_hz = 90000000;
1815                 if (ldev->caps.hw_version == HWVER_10200)
1816                         ldev->caps.pad_max_freq_hz = 65000000;
1817                 ldev->caps.nb_irq = 2;
1818                 ldev->caps.ycbcr_input = false;
1819                 ldev->caps.ycbcr_output = false;
1820                 ldev->caps.plane_reg_shadow = false;
1821                 ldev->caps.crc = false;
1822                 ldev->caps.dynamic_zorder = false;
1823                 ldev->caps.plane_rotation = false;
1824                 ldev->caps.fifo_threshold = false;
1825                 break;
1826         case HWVER_20101:
1827                 ldev->caps.layer_ofs = LAY_OFS_0;
1828                 ldev->caps.layer_regs = ltdc_layer_regs_a1;
1829                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
1830                 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a1;
1831                 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a1);
1832                 ldev->caps.pix_fmt_flex = false;
1833                 ldev->caps.non_alpha_only_l1 = false;
1834                 ldev->caps.pad_max_freq_hz = 150000000;
1835                 ldev->caps.nb_irq = 4;
1836                 ldev->caps.ycbcr_input = false;
1837                 ldev->caps.ycbcr_output = false;
1838                 ldev->caps.plane_reg_shadow = false;
1839                 ldev->caps.crc = false;
1840                 ldev->caps.dynamic_zorder = false;
1841                 ldev->caps.plane_rotation = false;
1842                 ldev->caps.fifo_threshold = false;
1843                 break;
1844         case HWVER_40100:
1845                 ldev->caps.layer_ofs = LAY_OFS_1;
1846                 ldev->caps.layer_regs = ltdc_layer_regs_a2;
1847                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2;
1848                 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a2;
1849                 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2);
1850                 ldev->caps.pix_fmt_flex = true;
1851                 ldev->caps.non_alpha_only_l1 = false;
1852                 ldev->caps.pad_max_freq_hz = 90000000;
1853                 ldev->caps.nb_irq = 2;
1854                 ldev->caps.ycbcr_input = true;
1855                 ldev->caps.ycbcr_output = true;
1856                 ldev->caps.plane_reg_shadow = true;
1857                 ldev->caps.crc = true;
1858                 ldev->caps.dynamic_zorder = true;
1859                 ldev->caps.plane_rotation = true;
1860                 ldev->caps.fifo_threshold = true;
1861                 break;
1862         default:
1863                 return -ENODEV;
1864         }
1865
1866         return 0;
1867 }
1868
1869 void ltdc_suspend(struct drm_device *ddev)
1870 {
1871         struct ltdc_device *ldev = ddev->dev_private;
1872
1873         DRM_DEBUG_DRIVER("\n");
1874         clk_disable_unprepare(ldev->pixel_clk);
1875 }
1876
1877 int ltdc_resume(struct drm_device *ddev)
1878 {
1879         struct ltdc_device *ldev = ddev->dev_private;
1880         int ret;
1881
1882         DRM_DEBUG_DRIVER("\n");
1883
1884         ret = clk_prepare_enable(ldev->pixel_clk);
1885         if (ret) {
1886                 DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
1887                 return ret;
1888         }
1889
1890         return 0;
1891 }
1892
1893 int ltdc_load(struct drm_device *ddev)
1894 {
1895         struct platform_device *pdev = to_platform_device(ddev->dev);
1896         struct ltdc_device *ldev = ddev->dev_private;
1897         struct device *dev = ddev->dev;
1898         struct device_node *np = dev->of_node;
1899         struct drm_bridge *bridge;
1900         struct drm_panel *panel;
1901         struct drm_crtc *crtc;
1902         struct reset_control *rstc;
1903         struct resource *res;
1904         int irq, i, nb_endpoints;
1905         int ret = -ENODEV;
1906
1907         DRM_DEBUG_DRIVER("\n");
1908
1909         /* Get number of endpoints */
1910         nb_endpoints = of_graph_get_endpoint_count(np);
1911         if (!nb_endpoints)
1912                 return -ENODEV;
1913
1914         ldev->pixel_clk = devm_clk_get(dev, "lcd");
1915         if (IS_ERR(ldev->pixel_clk)) {
1916                 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER)
1917                         DRM_ERROR("Unable to get lcd clock\n");
1918                 return PTR_ERR(ldev->pixel_clk);
1919         }
1920
1921         if (clk_prepare_enable(ldev->pixel_clk)) {
1922                 DRM_ERROR("Unable to prepare pixel clock\n");
1923                 return -ENODEV;
1924         }
1925
1926         /* Get endpoints if any */
1927         for (i = 0; i < nb_endpoints; i++) {
1928                 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge);
1929
1930                 /*
1931                  * If at least one endpoint is -ENODEV, continue probing,
1932                  * else if at least one endpoint returned an error
1933                  * (ie -EPROBE_DEFER) then stop probing.
1934                  */
1935                 if (ret == -ENODEV)
1936                         continue;
1937                 else if (ret)
1938                         goto err;
1939
1940                 if (panel) {
1941                         bridge = drmm_panel_bridge_add(ddev, panel);
1942                         if (IS_ERR(bridge)) {
1943                                 DRM_ERROR("panel-bridge endpoint %d\n", i);
1944                                 ret = PTR_ERR(bridge);
1945                                 goto err;
1946                         }
1947                 }
1948
1949                 if (bridge) {
1950                         ret = ltdc_encoder_init(ddev, bridge);
1951                         if (ret) {
1952                                 if (ret != -EPROBE_DEFER)
1953                                         DRM_ERROR("init encoder endpoint %d\n", i);
1954                                 goto err;
1955                         }
1956                 }
1957         }
1958
1959         rstc = devm_reset_control_get_exclusive(dev, NULL);
1960
1961         mutex_init(&ldev->err_lock);
1962
1963         if (!IS_ERR(rstc)) {
1964                 reset_control_assert(rstc);
1965                 usleep_range(10, 20);
1966                 reset_control_deassert(rstc);
1967         }
1968
1969         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1970         ldev->regs = devm_ioremap_resource(dev, res);
1971         if (IS_ERR(ldev->regs)) {
1972                 DRM_ERROR("Unable to get ltdc registers\n");
1973                 ret = PTR_ERR(ldev->regs);
1974                 goto err;
1975         }
1976
1977         ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg);
1978         if (IS_ERR(ldev->regmap)) {
1979                 DRM_ERROR("Unable to regmap ltdc registers\n");
1980                 ret = PTR_ERR(ldev->regmap);
1981                 goto err;
1982         }
1983
1984         ret = ltdc_get_caps(ddev);
1985         if (ret) {
1986                 DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
1987                           ldev->caps.hw_version);
1988                 goto err;
1989         }
1990
1991         /* Disable all interrupts */
1992         regmap_clear_bits(ldev->regmap, LTDC_IER, IER_MASK);
1993
1994         DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version);
1995
1996         /* initialize default value for fifo underrun threshold & clear interrupt error counters */
1997         ldev->transfer_err = 0;
1998         ldev->fifo_err = 0;
1999         ldev->fifo_warn = 0;
2000         ldev->fifo_threshold = FUT_DFT;
2001
2002         for (i = 0; i < ldev->caps.nb_irq; i++) {
2003                 irq = platform_get_irq(pdev, i);
2004                 if (irq < 0) {
2005                         ret = irq;
2006                         goto err;
2007                 }
2008
2009                 ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
2010                                                 ltdc_irq_thread, IRQF_ONESHOT,
2011                                                 dev_name(dev), ddev);
2012                 if (ret) {
2013                         DRM_ERROR("Failed to register LTDC interrupt\n");
2014                         goto err;
2015                 }
2016         }
2017
2018         crtc = drmm_kzalloc(ddev, sizeof(*crtc), GFP_KERNEL);
2019         if (!crtc) {
2020                 DRM_ERROR("Failed to allocate crtc\n");
2021                 ret = -ENOMEM;
2022                 goto err;
2023         }
2024
2025         ret = ltdc_crtc_init(ddev, crtc);
2026         if (ret) {
2027                 DRM_ERROR("Failed to init crtc\n");
2028                 goto err;
2029         }
2030
2031         ret = drm_vblank_init(ddev, NB_CRTC);
2032         if (ret) {
2033                 DRM_ERROR("Failed calling drm_vblank_init()\n");
2034                 goto err;
2035         }
2036
2037         clk_disable_unprepare(ldev->pixel_clk);
2038
2039         pinctrl_pm_select_sleep_state(ddev->dev);
2040
2041         pm_runtime_enable(ddev->dev);
2042
2043         return 0;
2044 err:
2045         clk_disable_unprepare(ldev->pixel_clk);
2046
2047         return ret;
2048 }
2049
2050 void ltdc_unload(struct drm_device *ddev)
2051 {
2052         DRM_DEBUG_DRIVER("\n");
2053
2054         pm_runtime_disable(ddev->dev);
2055 }
2056
2057 MODULE_AUTHOR("Philippe Cornu <[email protected]>");
2058 MODULE_AUTHOR("Yannick Fertre <[email protected]>");
2059 MODULE_AUTHOR("Fabien Dessenne <[email protected]>");
2060 MODULE_AUTHOR("Mickael Reulier <[email protected]>");
2061 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
2062 MODULE_LICENSE("GPL v2");