drivers/gpu/drm/i915/display/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <[email protected]>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <[email protected]>
  26  *      Dave Airlie <[email protected]>
  27  *      Jesse Barnes <[email protected]>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/acpi.h>
  32 #include <linux/dmi.h>
  33 #include <linux/i2c.h>
  34 #include <linux/slab.h>
  35 #include <linux/vga_switcheroo.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_edid.h>
  40
  41 #include "i915_drv.h"
  42 #include "i915_reg.h"
  43 #include "intel_atomic.h"
  44 #include "intel_backlight.h"
  45 #include "intel_connector.h"
  46 #include "intel_de.h"
  47 #include "intel_display_types.h"
  48 #include "intel_dpll.h"
  49 #include "intel_fdi.h"
  50 #include "intel_gmbus.h"
  51 #include "intel_lvds.h"
  52 #include "intel_lvds_regs.h"
  53 #include "intel_panel.h"
  54 #include "intel_pps_regs.h"
  55
  56 /* Private structure for the integrated LVDS support */
  57 struct intel_lvds_pps {
  58         /* 100us units */
  59         int t1_t2;
  60         int t3;
  61         int t4;
  62         int t5;
  63         int tx;
  64
  65         int divider;
  66
  67         int port;
  68         bool powerdown_on_reset;
  69 };
  70
  71 struct intel_lvds_encoder {
  72         struct intel_encoder base;
  73
  74         bool is_dual_link;
  75         i915_reg_t reg;
  76         u32 a3_power;
  77
  78         struct intel_lvds_pps init_pps;
  79         u32 init_lvds_val;
  80
  81         struct intel_connector *attached_connector;
  82 };
  83
  84 static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder)
  85 {
  86         return container_of(encoder, struct intel_lvds_encoder, base);
  87 }
  88
  89 bool intel_lvds_port_enabled(struct drm_i915_private *i915,
  90                              i915_reg_t lvds_reg, enum pipe *pipe)
  91 {
  92         u32 val;
  93
  94         val = intel_de_read(i915, lvds_reg);
  95
  96         /* asserts want to know the pipe even if the port is disabled */
  97         if (HAS_PCH_CPT(i915))
  98                 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val);
  99         else
 100                 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val);
 101
 102         return val & LVDS_PORT_EN;
 103 }
 104
 105 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
 106                                     enum pipe *pipe)
 107 {
 108         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 109         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 110         intel_wakeref_t wakeref;
 111         bool ret;
 112
 113         wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain);
 114         if (!wakeref)
 115                 return false;
 116
 117         ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe);
 118
 119         intel_display_power_put(i915, encoder->power_domain, wakeref);
 120
 121         return ret;
 122 }
 123
 124 static void intel_lvds_get_config(struct intel_encoder *encoder,
 125                                   struct intel_crtc_state *crtc_state)
 126 {
 127         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 128         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 129         u32 tmp, flags = 0;
 130
 131         crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS);
 132
 133         tmp = intel_de_read(dev_priv, lvds_encoder->reg);
 134         if (tmp & LVDS_HSYNC_POLARITY)
 135                 flags |= DRM_MODE_FLAG_NHSYNC;
 136         else
 137                 flags |= DRM_MODE_FLAG_PHSYNC;
 138         if (tmp & LVDS_VSYNC_POLARITY)
 139                 flags |= DRM_MODE_FLAG_NVSYNC;
 140         else
 141                 flags |= DRM_MODE_FLAG_PVSYNC;
 142
 143         crtc_state->hw.adjusted_mode.flags |= flags;
 144
 145         if (DISPLAY_VER(dev_priv) < 5)
 146                 crtc_state->gmch_pfit.lvds_border_bits =
 147                         tmp & LVDS_BORDER_ENABLE;
 148
 149         /* gen2/3 store dither state in pfit control, needs to match */
 150         if (DISPLAY_VER(dev_priv) < 4) {
 151                 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
 152
 153                 crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
 154         }
 155
 156         crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
 157 }
 158
 159 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 160                                         struct intel_lvds_pps *pps)
 161 {
 162         u32 val;
 163
 164         pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET;
 165
 166         val = intel_de_read(dev_priv, PP_ON_DELAYS(0));
 167         pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
 168         pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
 169         pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
 170
 171         val = intel_de_read(dev_priv, PP_OFF_DELAYS(0));
 172         pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
 173         pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
 174
 175         val = intel_de_read(dev_priv, PP_DIVISOR(0));
 176         pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
 177         val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
 178         /*
 179          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 180          * too short power-cycle delay due to the asynchronous programming of
 181          * the register.
 182          */
 183         if (val)
 184                 val--;
 185         /* Convert from 100ms to 100us units */
 186         pps->t4 = val * 1000;
 187
 188         if (DISPLAY_VER(dev_priv) < 5 &&
 189             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 190                 drm_dbg_kms(&dev_priv->drm,
 191                             "Panel power timings uninitialized, "
 192                             "setting defaults\n");
 193                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 194                 pps->t1_t2 = 40 * 10;
 195                 pps->t5 = 200 * 10;
 196                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 197                 pps->t3 = 35 * 10;
 198                 pps->tx = 200 * 10;
 199         }
 200
 201         drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 202                 "divider %d port %d powerdown_on_reset %d\n",
 203                 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 204                 pps->divider, pps->port, pps->powerdown_on_reset);
 205 }
 206
 207 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 208                                    struct intel_lvds_pps *pps)
 209 {
 210         u32 val;
 211
 212         val = intel_de_read(dev_priv, PP_CONTROL(0));
 213         drm_WARN_ON(&dev_priv->drm,
 214                     (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 215         if (pps->powerdown_on_reset)
 216                 val |= PANEL_POWER_RESET;
 217         intel_de_write(dev_priv, PP_CONTROL(0), val);
 218
 219         intel_de_write(dev_priv, PP_ON_DELAYS(0),
 220                        REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |
 221                        REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) |
 222                        REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5));
 223
 224         intel_de_write(dev_priv, PP_OFF_DELAYS(0),
 225                        REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) |
 226                        REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx));
 227
 228         intel_de_write(dev_priv, PP_DIVISOR(0),
 229                        REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
 230                        REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1));
 231 }
 232
 233 static void intel_pre_enable_lvds(struct intel_atomic_state *state,
 234                                   struct intel_encoder *encoder,
 235                                   const struct intel_crtc_state *crtc_state,
 236                                   const struct drm_connector_state *conn_state)
 237 {
 238         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 239         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 240         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 241         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 242         enum pipe pipe = crtc->pipe;
 243         u32 temp;
 244
 245         if (HAS_PCH_SPLIT(i915)) {
 246                 assert_fdi_rx_pll_disabled(i915, pipe);
 247                 assert_shared_dpll_disabled(i915, crtc_state->shared_dpll);
 248         } else {
 249                 assert_pll_disabled(i915, pipe);
 250         }
 251
 252         intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps);
 253
 254         temp = lvds_encoder->init_lvds_val;
 255         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 256
 257         if (HAS_PCH_CPT(i915)) {
 258                 temp &= ~LVDS_PIPE_SEL_MASK_CPT;
 259                 temp |= LVDS_PIPE_SEL_CPT(pipe);
 260         } else {
 261                 temp &= ~LVDS_PIPE_SEL_MASK;
 262                 temp |= LVDS_PIPE_SEL(pipe);
 263         }
 264
 265         /* set the corresponsding LVDS_BORDER bit */
 266         temp &= ~LVDS_BORDER_ENABLE;
 267         temp |= crtc_state->gmch_pfit.lvds_border_bits;
 268
 269         /*
 270          * Set the B0-B3 data pairs corresponding to whether we're going to
 271          * set the DPLLs for dual-channel mode or not.
 272          */
 273         if (lvds_encoder->is_dual_link)
 274                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 275         else
 276                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 277
 278         /*
 279          * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 280          * appropriately here, but we need to look more thoroughly into how
 281          * panels behave in the two modes. For now, let's just maintain the
 282          * value we got from the BIOS.
 283          */
 284         temp &= ~LVDS_A3_POWER_MASK;
 285         temp |= lvds_encoder->a3_power;
 286
 287         /*
 288          * Set the dithering flag on LVDS as needed, note that there is no
 289          * special lvds dither control bit on pch-split platforms, dithering is
 290          * only controlled through the TRANSCONF reg.
 291          */
 292         if (DISPLAY_VER(i915) == 4) {
 293                 /*
 294                  * Bspec wording suggests that LVDS port dithering only exists
 295                  * for 18bpp panels.
 296                  */
 297                 if (crtc_state->dither && crtc_state->pipe_bpp == 18)
 298                         temp |= LVDS_ENABLE_DITHER;
 299                 else
 300                         temp &= ~LVDS_ENABLE_DITHER;
 301         }
 302         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 303         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 304                 temp |= LVDS_HSYNC_POLARITY;
 305         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 306                 temp |= LVDS_VSYNC_POLARITY;
 307
 308         intel_de_write(i915, lvds_encoder->reg, temp);
 309 }
 310
 311 /*
 312  * Sets the power state for the panel.
 313  */
 314 static void intel_enable_lvds(struct intel_atomic_state *state,
 315                               struct intel_encoder *encoder,
 316                               const struct intel_crtc_state *crtc_state,
 317                               const struct drm_connector_state *conn_state)
 318 {
 319         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 320         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 321
 322         intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN);
 323
 324         intel_de_rmw(dev_priv, PP_CONTROL(0), 0, PANEL_POWER_ON);
 325         intel_de_posting_read(dev_priv, lvds_encoder->reg);
 326
 327         if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000))
 328                 drm_err(&dev_priv->drm,
 329                         "timed out waiting for panel to power on\n");
 330
 331         intel_backlight_enable(crtc_state, conn_state);
 332 }
 333
 334 static void intel_disable_lvds(struct intel_atomic_state *state,
 335                                struct intel_encoder *encoder,
 336                                const struct intel_crtc_state *old_crtc_state,
 337                                const struct drm_connector_state *old_conn_state)
 338 {
 339         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 340         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 341
 342         intel_de_rmw(dev_priv, PP_CONTROL(0), PANEL_POWER_ON, 0);
 343         if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000))
 344                 drm_err(&dev_priv->drm,
 345                         "timed out waiting for panel to power off\n");
 346
 347         intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0);
 348         intel_de_posting_read(dev_priv, lvds_encoder->reg);
 349 }
 350
 351 static void gmch_disable_lvds(struct intel_atomic_state *state,
 352                               struct intel_encoder *encoder,
 353                               const struct intel_crtc_state *old_crtc_state,
 354                               const struct drm_connector_state *old_conn_state)
 355
 356 {
 357         intel_backlight_disable(old_conn_state);
 358
 359         intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
 360 }
 361
 362 static void pch_disable_lvds(struct intel_atomic_state *state,
 363                              struct intel_encoder *encoder,
 364                              const struct intel_crtc_state *old_crtc_state,
 365                              const struct drm_connector_state *old_conn_state)
 366 {
 367         intel_backlight_disable(old_conn_state);
 368 }
 369
 370 static void pch_post_disable_lvds(struct intel_atomic_state *state,
 371                                   struct intel_encoder *encoder,
 372                                   const struct intel_crtc_state *old_crtc_state,
 373                                   const struct drm_connector_state *old_conn_state)
 374 {
 375         intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
 376 }
 377
 378 static void intel_lvds_shutdown(struct intel_encoder *encoder)
 379 {
 380         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 381
 382         if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000))
 383                 drm_err(&dev_priv->drm,
 384                         "timed out waiting for panel power cycle delay\n");
 385 }
 386
 387 static enum drm_mode_status
 388 intel_lvds_mode_valid(struct drm_connector *_connector,
 389                       struct drm_display_mode *mode)
 390 {
 391         struct intel_connector *connector = to_intel_connector(_connector);
 392         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 393         const struct drm_display_mode *fixed_mode =
 394                 intel_panel_fixed_mode(connector, mode);
 395         int max_pixclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq;
 396         enum drm_mode_status status;
 397
 398         status = intel_cpu_transcoder_mode_valid(i915, mode);
 399         if (status != MODE_OK)
 400                 return status;
 401
 402         status = intel_panel_mode_valid(connector, mode);
 403         if (status != MODE_OK)
 404                 return status;
 405
 406         if (fixed_mode->clock > max_pixclk)
 407                 return MODE_CLOCK_HIGH;
 408
 409         return MODE_OK;
 410 }
 411
 412 static int intel_lvds_compute_config(struct intel_encoder *encoder,
 413                                      struct intel_crtc_state *crtc_state,
 414                                      struct drm_connector_state *conn_state)
 415 {
 416         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 417         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 418         struct intel_connector *connector = lvds_encoder->attached_connector;
 419         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 420         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 421         unsigned int lvds_bpp;
 422         int ret;
 423
 424         /* Should never happen!! */
 425         if (DISPLAY_VER(i915) < 4 && crtc->pipe == 0) {
 426                 drm_err(&i915->drm, "Can't support LVDS on pipe A\n");
 427                 return -EINVAL;
 428         }
 429
 430         if (HAS_PCH_SPLIT(i915)) {
 431                 crtc_state->has_pch_encoder = true;
 432                 if (!intel_fdi_compute_pipe_bpp(crtc_state))
 433                         return -EINVAL;
 434         }
 435
 436         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 437                 lvds_bpp = 8*3;
 438         else
 439                 lvds_bpp = 6*3;
 440
 441         /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
 442         if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) {
 443                 drm_dbg_kms(&i915->drm,
 444                             "forcing display bpp (was %d) to LVDS (%d)\n",
 445                             crtc_state->pipe_bpp, lvds_bpp);
 446                 crtc_state->pipe_bpp = lvds_bpp;
 447         }
 448
 449         crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
 450         crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
 451
 452         /*
 453          * We have timings from the BIOS for the panel, put them in
 454          * to the adjusted mode.  The CRTC will be set up for this mode,
 455          * with the panel scaling set up to source from the H/VDisplay
 456          * of the original mode.
 457          */
 458         ret = intel_panel_compute_config(connector, adjusted_mode);
 459         if (ret)
 460                 return ret;
 461
 462         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 463                 return -EINVAL;
 464
 465         ret = intel_panel_fitting(crtc_state, conn_state);
 466         if (ret)
 467                 return ret;
 468
 469         /*
 470          * XXX: It would be nice to support lower refresh rates on the
 471          * panels to reduce power consumption, and perhaps match the
 472          * user's requested refresh rate.
 473          */
 474
 475         return 0;
 476 }
 477
 478 /*
 479  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 480  */
 481 static int intel_lvds_get_modes(struct drm_connector *_connector)
 482 {
 483         struct intel_connector *connector = to_intel_connector(_connector);
 484         const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
 485
 486         /* Use panel fixed edid if we have one */
 487         if (!IS_ERR_OR_NULL(fixed_edid)) {
 488                 drm_edid_connector_update(&connector->base, fixed_edid);
 489
 490                 return drm_edid_connector_add_modes(&connector->base);
 491         }
 492
 493         return intel_panel_get_modes(connector);
 494 }
 495
 496 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 497         .get_modes = intel_lvds_get_modes,
 498         .mode_valid = intel_lvds_mode_valid,
 499         .atomic_check = intel_digital_connector_atomic_check,
 500 };
 501
 502 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 503         .detect = intel_panel_detect,
 504         .fill_modes = drm_helper_probe_single_connector_modes,
 505         .atomic_get_property = intel_digital_connector_atomic_get_property,
 506         .atomic_set_property = intel_digital_connector_atomic_set_property,
 507         .late_register = intel_connector_register,
 508         .early_unregister = intel_connector_unregister,
 509         .destroy = intel_connector_destroy,
 510         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 511         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 512 };
 513
 514 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 515         .destroy = intel_encoder_destroy,
 516 };
 517
 518 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 519 {
 520         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 521         return 1;
 522 }
 523
 524 /* These systems claim to have LVDS, but really don't */
 525 static const struct dmi_system_id intel_no_lvds[] = {
 526         {
 527                 .callback = intel_no_lvds_dmi_callback,
 528                 .ident = "Apple Mac Mini (Core series)",
 529                 .matches = {
 530                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 531                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 532                 },
 533         },
 534         {
 535                 .callback = intel_no_lvds_dmi_callback,
 536                 .ident = "Apple Mac Mini (Core 2 series)",
 537                 .matches = {
 538                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 539                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 540                 },
 541         },
 542         {
 543                 .callback = intel_no_lvds_dmi_callback,
 544                 .ident = "MSI IM-945GSE-A",
 545                 .matches = {
 546                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 547                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 548                 },
 549         },
 550         {
 551                 .callback = intel_no_lvds_dmi_callback,
 552                 .ident = "Dell Studio Hybrid",
 553                 .matches = {
 554                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 555                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 556                 },
 557         },
 558         {
 559                 .callback = intel_no_lvds_dmi_callback,
 560                 .ident = "Dell OptiPlex FX170",
 561                 .matches = {
 562                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 563                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 564                 },
 565         },
 566         {
 567                 .callback = intel_no_lvds_dmi_callback,
 568                 .ident = "AOpen Mini PC",
 569                 .matches = {
 570                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 571                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 572                 },
 573         },
 574         {
 575                 .callback = intel_no_lvds_dmi_callback,
 576                 .ident = "AOpen Mini PC MP915",
 577                 .matches = {
 578                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 579                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 580                 },
 581         },
 582         {
 583                 .callback = intel_no_lvds_dmi_callback,
 584                 .ident = "AOpen i915GMm-HFS",
 585                 .matches = {
 586                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 587                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 588                 },
 589         },
 590         {
 591                 .callback = intel_no_lvds_dmi_callback,
 592                 .ident = "AOpen i45GMx-I",
 593                 .matches = {
 594                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 595                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 596                 },
 597         },
 598         {
 599                 .callback = intel_no_lvds_dmi_callback,
 600                 .ident = "Aopen i945GTt-VFA",
 601                 .matches = {
 602                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 603                 },
 604         },
 605         {
 606                 .callback = intel_no_lvds_dmi_callback,
 607                 .ident = "Clientron U800",
 608                 .matches = {
 609                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 610                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 611                 },
 612         },
 613         {
 614                 .callback = intel_no_lvds_dmi_callback,
 615                 .ident = "Clientron E830",
 616                 .matches = {
 617                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 618                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 619                 },
 620         },
 621         {
 622                 .callback = intel_no_lvds_dmi_callback,
 623                 .ident = "Asus EeeBox PC EB1007",
 624                 .matches = {
 625                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 626                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 627                 },
 628         },
 629         {
 630                 .callback = intel_no_lvds_dmi_callback,
 631                 .ident = "Asus AT5NM10T-I",
 632                 .matches = {
 633                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 634                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 635                 },
 636         },
 637         {
 638                 .callback = intel_no_lvds_dmi_callback,
 639                 .ident = "Hewlett-Packard HP t5740",
 640                 .matches = {
 641                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 642                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 643                 },
 644         },
 645         {
 646                 .callback = intel_no_lvds_dmi_callback,
 647                 .ident = "Hewlett-Packard t5745",
 648                 .matches = {
 649                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 650                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 651                 },
 652         },
 653         {
 654                 .callback = intel_no_lvds_dmi_callback,
 655                 .ident = "Hewlett-Packard st5747",
 656                 .matches = {
 657                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 658                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 659                 },
 660         },
 661         {
 662                 .callback = intel_no_lvds_dmi_callback,
 663                 .ident = "MSI Wind Box DC500",
 664                 .matches = {
 665                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 666                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 667                 },
 668         },
 669         {
 670                 .callback = intel_no_lvds_dmi_callback,
 671                 .ident = "Gigabyte GA-D525TUD",
 672                 .matches = {
 673                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 674                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 675                 },
 676         },
 677         {
 678                 .callback = intel_no_lvds_dmi_callback,
 679                 .ident = "Supermicro X7SPA-H",
 680                 .matches = {
 681                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 682                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 683                 },
 684         },
 685         {
 686                 .callback = intel_no_lvds_dmi_callback,
 687                 .ident = "Fujitsu Esprimo Q900",
 688                 .matches = {
 689                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 690                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 691                 },
 692         },
 693         {
 694                 .callback = intel_no_lvds_dmi_callback,
 695                 .ident = "Intel D410PT",
 696                 .matches = {
 697                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 698                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 699                 },
 700         },
 701         {
 702                 .callback = intel_no_lvds_dmi_callback,
 703                 .ident = "Intel D425KT",
 704                 .matches = {
 705                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 706                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 707                 },
 708         },
 709         {
 710                 .callback = intel_no_lvds_dmi_callback,
 711                 .ident = "Intel D510MO",
 712                 .matches = {
 713                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 714                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 715                 },
 716         },
 717         {
 718                 .callback = intel_no_lvds_dmi_callback,
 719                 .ident = "Intel D525MW",
 720                 .matches = {
 721                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 722                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 723                 },
 724         },
 725         {
 726                 .callback = intel_no_lvds_dmi_callback,
 727                 .ident = "Radiant P845",
 728                 .matches = {
 729                         DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
 730                         DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
 731                 },
 732         },
 733
 734         { }     /* terminating entry */
 735 };
 736
 737 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 738 {
 739         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 740         return 1;
 741 }
 742
 743 static const struct dmi_system_id intel_dual_link_lvds[] = {
 744         {
 745                 .callback = intel_dual_link_lvds_callback,
 746                 .ident = "Apple MacBook Pro 15\" (2010)",
 747                 .matches = {
 748                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 749                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 750                 },
 751         },
 752         {
 753                 .callback = intel_dual_link_lvds_callback,
 754                 .ident = "Apple MacBook Pro 15\" (2011)",
 755                 .matches = {
 756                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 757                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 758                 },
 759         },
 760         {
 761                 .callback = intel_dual_link_lvds_callback,
 762                 .ident = "Apple MacBook Pro 15\" (2012)",
 763                 .matches = {
 764                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 765                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 766                 },
 767         },
 768         { }     /* terminating entry */
 769 };
 770
 771 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *i915)
 772 {
 773         struct intel_encoder *encoder;
 774
 775         for_each_intel_encoder(&i915->drm, encoder) {
 776                 if (encoder->type == INTEL_OUTPUT_LVDS)
 777                         return encoder;
 778         }
 779
 780         return NULL;
 781 }
 782
 783 bool intel_is_dual_link_lvds(struct drm_i915_private *i915)
 784 {
 785         struct intel_encoder *encoder = intel_get_lvds_encoder(i915);
 786
 787         return encoder && to_lvds_encoder(encoder)->is_dual_link;
 788 }
 789
 790 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 791 {
 792         struct drm_i915_private *i915 = to_i915(lvds_encoder->base.base.dev);
 793         struct intel_connector *connector = lvds_encoder->attached_connector;
 794         const struct drm_display_mode *fixed_mode =
 795                 intel_panel_preferred_fixed_mode(connector);
 796         unsigned int val;
 797
 798         /* use the module option value if specified */
 799         if (i915->display.params.lvds_channel_mode > 0)
 800                 return i915->display.params.lvds_channel_mode == 2;
 801
 802         /* single channel LVDS is limited to 112 MHz */
 803         if (fixed_mode->clock > 112999)
 804                 return true;
 805
 806         if (dmi_check_system(intel_dual_link_lvds))
 807                 return true;
 808
 809         /*
 810          * BIOS should set the proper LVDS register value at boot, but
 811          * in reality, it doesn't set the value when the lid is closed;
 812          * we need to check "the value to be set" in VBT when LVDS
 813          * register is uninitialized.
 814          */
 815         val = intel_de_read(i915, lvds_encoder->reg);
 816         if (HAS_PCH_CPT(i915))
 817                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
 818         else
 819                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
 820         if (val == 0)
 821                 val = connector->panel.vbt.bios_lvds_val;
 822
 823         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 824 }
 825
 826 static void intel_lvds_add_properties(struct drm_connector *connector)
 827 {
 828         intel_attach_scaling_mode_property(connector);
 829 }
 830
 831 /**
 832  * intel_lvds_init - setup LVDS connectors on this device
 833  * @i915: i915 device
 834  *
 835  * Create the connector, register the LVDS DDC bus, and try to figure out what
 836  * modes we can display on the LVDS panel (if present).
 837  */
 838 void intel_lvds_init(struct drm_i915_private *i915)
 839 {
 840         struct intel_lvds_encoder *lvds_encoder;
 841         struct intel_connector *connector;
 842         const struct drm_edid *drm_edid;
 843         struct intel_encoder *encoder;
 844         i915_reg_t lvds_reg;
 845         u32 lvds;
 846         u8 ddc_pin;
 847
 848         /* Skip init on machines we know falsely report LVDS */
 849         if (dmi_check_system(intel_no_lvds)) {
 850                 drm_WARN(&i915->drm, !i915->display.vbt.int_lvds_support,
 851                          "Useless DMI match. Internal LVDS support disabled by VBT\n");
 852                 return;
 853         }
 854
 855         if (!i915->display.vbt.int_lvds_support) {
 856                 drm_dbg_kms(&i915->drm,
 857                             "Internal LVDS support disabled by VBT\n");
 858                 return;
 859         }
 860
 861         if (HAS_PCH_SPLIT(i915))
 862                 lvds_reg = PCH_LVDS;
 863         else
 864                 lvds_reg = LVDS;
 865
 866         lvds = intel_de_read(i915, lvds_reg);
 867
 868         if (HAS_PCH_SPLIT(i915)) {
 869                 if ((lvds & LVDS_DETECTED) == 0)
 870                         return;
 871         }
 872
 873         ddc_pin = GMBUS_PIN_PANEL;
 874         if (!intel_bios_is_lvds_present(i915, &ddc_pin)) {
 875                 if ((lvds & LVDS_PORT_EN) == 0) {
 876                         drm_dbg_kms(&i915->drm,
 877                                     "LVDS is not present in VBT\n");
 878                         return;
 879                 }
 880                 drm_dbg_kms(&i915->drm,
 881                             "LVDS is not present in VBT, but enabled anyway\n");
 882         }
 883
 884         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
 885         if (!lvds_encoder)
 886                 return;
 887
 888         connector = intel_connector_alloc();
 889         if (!connector) {
 890                 kfree(lvds_encoder);
 891                 return;
 892         }
 893
 894         lvds_encoder->attached_connector = connector;
 895         encoder = &lvds_encoder->base;
 896
 897         drm_connector_init_with_ddc(&i915->drm, &connector->base,
 898                                     &intel_lvds_connector_funcs,
 899                                     DRM_MODE_CONNECTOR_LVDS,
 900                                     intel_gmbus_get_adapter(i915, ddc_pin));
 901
 902         drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs,
 903                          DRM_MODE_ENCODER_LVDS, "LVDS");
 904
 905         encoder->enable = intel_enable_lvds;
 906         encoder->pre_enable = intel_pre_enable_lvds;
 907         encoder->compute_config = intel_lvds_compute_config;
 908         if (HAS_PCH_SPLIT(i915)) {
 909                 encoder->disable = pch_disable_lvds;
 910                 encoder->post_disable = pch_post_disable_lvds;
 911         } else {
 912                 encoder->disable = gmch_disable_lvds;
 913         }
 914         encoder->get_hw_state = intel_lvds_get_hw_state;
 915         encoder->get_config = intel_lvds_get_config;
 916         encoder->update_pipe = intel_backlight_update;
 917         encoder->shutdown = intel_lvds_shutdown;
 918         connector->get_hw_state = intel_connector_get_hw_state;
 919
 920         intel_connector_attach_encoder(connector, encoder);
 921
 922         encoder->type = INTEL_OUTPUT_LVDS;
 923         encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
 924         encoder->port = PORT_NONE;
 925         encoder->cloneable = 0;
 926         if (DISPLAY_VER(i915) < 4)
 927                 encoder->pipe_mask = BIT(PIPE_B);
 928         else
 929                 encoder->pipe_mask = ~0;
 930
 931         drm_connector_helper_add(&connector->base, &intel_lvds_connector_helper_funcs);
 932         connector->base.display_info.subpixel_order = SubPixelHorizontalRGB;
 933
 934         lvds_encoder->reg = lvds_reg;
 935
 936         intel_lvds_add_properties(&connector->base);
 937
 938         intel_lvds_pps_get_hw_state(i915, &lvds_encoder->init_pps);
 939         lvds_encoder->init_lvds_val = lvds;
 940
 941         /*
 942          * LVDS discovery:
 943          * 1) check for EDID on DDC
 944          * 2) check for VBT data
 945          * 3) check to see if LVDS is already on
 946          *    if none of the above, no panel
 947          */
 948
 949         /*
 950          * Attempt to get the fixed panel mode from DDC.  Assume that the
 951          * preferred mode is the right one.
 952          */
 953         mutex_lock(&i915->drm.mode_config.mutex);
 954         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
 955                 drm_edid = drm_edid_read_switcheroo(&connector->base, connector->base.ddc);
 956         else
 957                 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);
 958         if (drm_edid) {
 959                 if (drm_edid_connector_update(&connector->base, drm_edid) ||
 960                     !drm_edid_connector_add_modes(&connector->base)) {
 961                         drm_edid_connector_update(&connector->base, NULL);
 962                         drm_edid_free(drm_edid);
 963                         drm_edid = ERR_PTR(-EINVAL);
 964                 }
 965         } else {
 966                 drm_edid = ERR_PTR(-ENOENT);
 967         }
 968         intel_bios_init_panel_late(i915, &connector->panel, NULL,
 969                                    IS_ERR(drm_edid) ? NULL : drm_edid);
 970
 971         /* Try EDID first */
 972         intel_panel_add_edid_fixed_modes(connector, true);
 973
 974         /* Failed to get EDID, what about VBT? */
 975         if (!intel_panel_preferred_fixed_mode(connector))
 976                 intel_panel_add_vbt_lfp_fixed_mode(connector);
 977
 978         /*
 979          * If we didn't get a fixed mode from EDID or VBT, try checking
 980          * if the panel is already turned on.  If so, assume that
 981          * whatever is currently programmed is the correct mode.
 982          */
 983         if (!intel_panel_preferred_fixed_mode(connector))
 984                 intel_panel_add_encoder_fixed_mode(connector, encoder);
 985
 986         mutex_unlock(&i915->drm.mode_config.mutex);
 987
 988         /* If we still don't have a mode after all that, give up. */
 989         if (!intel_panel_preferred_fixed_mode(connector))
 990                 goto failed;
 991
 992         intel_panel_init(connector, drm_edid);
 993
 994         intel_backlight_setup(connector, INVALID_PIPE);
 995
 996         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
 997         drm_dbg_kms(&i915->drm, "detected %s-link lvds configuration\n",
 998                     lvds_encoder->is_dual_link ? "dual" : "single");
 999
1000         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1001
1002         return;
1003
1004 failed:
1005         drm_dbg_kms(&i915->drm, "No LVDS modes found, disabling.\n");
1006         drm_connector_cleanup(&connector->base);
1007         drm_encoder_cleanup(&encoder->base);
1008         kfree(lvds_encoder);
1009         intel_connector_free(connector);
1010         return;
1011 }