drivers/gpu/drm/i915/display/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <[email protected]>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <[email protected]>
  26  *      Dave Airlie <[email protected]>
  27  *      Jesse Barnes <[email protected]>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/acpi.h>
  32 #include <linux/dmi.h>
  33 #include <linux/i2c.h>
  34 #include <linux/slab.h>
  35 #include <linux/vga_switcheroo.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_probe_helper.h>
  41
  42 #include "i915_drv.h"
  43 #include "i915_reg.h"
  44 #include "intel_atomic.h"
  45 #include "intel_backlight.h"
  46 #include "intel_connector.h"
  47 #include "intel_de.h"
  48 #include "intel_display_types.h"
  49 #include "intel_dpll.h"
  50 #include "intel_fdi.h"
  51 #include "intel_gmbus.h"
  52 #include "intel_lvds.h"
  53 #include "intel_lvds_regs.h"
  54 #include "intel_panel.h"
  55 #include "intel_pfit.h"
  56 #include "intel_pps_regs.h"
  57
  58 /* Private structure for the integrated LVDS support */
  59 struct intel_lvds_pps {
  60         struct intel_pps_delays delays;
  61
  62         int divider;
  63
  64         int port;
  65         bool powerdown_on_reset;
  66 };
  67
  68 struct intel_lvds_encoder {
  69         struct intel_encoder base;
  70
  71         bool is_dual_link;
  72         i915_reg_t reg;
  73         u32 a3_power;
  74
  75         struct intel_lvds_pps init_pps;
  76         u32 init_lvds_val;
  77
  78         struct intel_connector *attached_connector;
  79 };
  80
  81 static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder)
  82 {
  83         return container_of(encoder, struct intel_lvds_encoder, base);
  84 }
  85
  86 bool intel_lvds_port_enabled(struct drm_i915_private *i915,
  87                              i915_reg_t lvds_reg, enum pipe *pipe)
  88 {
  89         u32 val;
  90
  91         val = intel_de_read(i915, lvds_reg);
  92
  93         /* asserts want to know the pipe even if the port is disabled */
  94         if (HAS_PCH_CPT(i915))
  95                 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val);
  96         else
  97                 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val);
  98
  99         return val & LVDS_PORT_EN;
 100 }
 101
 102 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
 103                                     enum pipe *pipe)
 104 {
 105         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 106         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 107         intel_wakeref_t wakeref;
 108         bool ret;
 109
 110         wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain);
 111         if (!wakeref)
 112                 return false;
 113
 114         ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe);
 115
 116         intel_display_power_put(i915, encoder->power_domain, wakeref);
 117
 118         return ret;
 119 }
 120
 121 static void intel_lvds_get_config(struct intel_encoder *encoder,
 122                                   struct intel_crtc_state *crtc_state)
 123 {
 124         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 125         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 126         u32 tmp, flags = 0;
 127
 128         crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS);
 129
 130         tmp = intel_de_read(dev_priv, lvds_encoder->reg);
 131         if (tmp & LVDS_HSYNC_POLARITY)
 132                 flags |= DRM_MODE_FLAG_NHSYNC;
 133         else
 134                 flags |= DRM_MODE_FLAG_PHSYNC;
 135         if (tmp & LVDS_VSYNC_POLARITY)
 136                 flags |= DRM_MODE_FLAG_NVSYNC;
 137         else
 138                 flags |= DRM_MODE_FLAG_PVSYNC;
 139
 140         crtc_state->hw.adjusted_mode.flags |= flags;
 141
 142         if (DISPLAY_VER(dev_priv) < 5)
 143                 crtc_state->gmch_pfit.lvds_border_bits =
 144                         tmp & LVDS_BORDER_ENABLE;
 145
 146         /* gen2/3 store dither state in pfit control, needs to match */
 147         if (DISPLAY_VER(dev_priv) < 4) {
 148                 tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
 149
 150                 crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
 151         }
 152
 153         crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
 154 }
 155
 156 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 157                                         struct intel_lvds_pps *pps)
 158 {
 159         u32 val;
 160
 161         pps->powerdown_on_reset = intel_de_read(dev_priv,
 162                                                 PP_CONTROL(dev_priv, 0)) & PANEL_POWER_RESET;
 163
 164         val = intel_de_read(dev_priv, PP_ON_DELAYS(dev_priv, 0));
 165         pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
 166         pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
 167         pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
 168
 169         val = intel_de_read(dev_priv, PP_OFF_DELAYS(dev_priv, 0));
 170         pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
 171         pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
 172
 173         val = intel_de_read(dev_priv, PP_DIVISOR(dev_priv, 0));
 174         pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
 175         val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
 176         /*
 177          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 178          * too short power-cycle delay due to the asynchronous programming of
 179          * the register.
 180          */
 181         if (val)
 182                 val--;
 183         /* Convert from 100ms to 100us units */
 184         pps->delays.power_cycle = val * 1000;
 185
 186         if (DISPLAY_VER(dev_priv) < 5 &&
 187             pps->delays.power_up == 0 &&
 188             pps->delays.backlight_on == 0 &&
 189             pps->delays.power_down == 0 &&
 190             pps->delays.backlight_off == 0) {
 191                 drm_dbg_kms(&dev_priv->drm,
 192                             "Panel power timings uninitialized, "
 193                             "setting defaults\n");
 194                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 195                 pps->delays.power_up = 40 * 10;
 196                 pps->delays.backlight_on = 200 * 10;
 197                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 198                 pps->delays.power_down = 35 * 10;
 199                 pps->delays.backlight_off = 200 * 10;
 200         }
 201
 202         drm_dbg(&dev_priv->drm, "LVDS PPS:power_up %d power_down %d power_cycle %d backlight_on %d backlight_off %d "
 203                 "divider %d port %d powerdown_on_reset %d\n",
 204                 pps->delays.power_up, pps->delays.power_down,
 205                 pps->delays.power_cycle, pps->delays.backlight_on,
 206                 pps->delays.backlight_off, pps->divider,
 207                 pps->port, pps->powerdown_on_reset);
 208 }
 209
 210 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 211                                    struct intel_lvds_pps *pps)
 212 {
 213         u32 val;
 214
 215         val = intel_de_read(dev_priv, PP_CONTROL(dev_priv, 0));
 216         drm_WARN_ON(&dev_priv->drm,
 217                     (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 218         if (pps->powerdown_on_reset)
 219                 val |= PANEL_POWER_RESET;
 220         intel_de_write(dev_priv, PP_CONTROL(dev_priv, 0), val);
 221
 222         intel_de_write(dev_priv, PP_ON_DELAYS(dev_priv, 0),
 223                        REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |
 224                        REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->delays.power_up) |
 225                        REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->delays.backlight_on));
 226
 227         intel_de_write(dev_priv, PP_OFF_DELAYS(dev_priv, 0),
 228                        REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->delays.power_down) |
 229                        REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->delays.backlight_off));
 230
 231         intel_de_write(dev_priv, PP_DIVISOR(dev_priv, 0),
 232                        REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
 233                        REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,
 234                                       DIV_ROUND_UP(pps->delays.power_cycle, 1000) + 1));
 235 }
 236
 237 static void intel_pre_enable_lvds(struct intel_atomic_state *state,
 238                                   struct intel_encoder *encoder,
 239                                   const struct intel_crtc_state *crtc_state,
 240                                   const struct drm_connector_state *conn_state)
 241 {
 242         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 243         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 244         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 245         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 246         enum pipe pipe = crtc->pipe;
 247         u32 temp;
 248
 249         if (HAS_PCH_SPLIT(i915)) {
 250                 assert_fdi_rx_pll_disabled(i915, pipe);
 251                 assert_shared_dpll_disabled(i915, crtc_state->shared_dpll);
 252         } else {
 253                 assert_pll_disabled(i915, pipe);
 254         }
 255
 256         intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps);
 257
 258         temp = lvds_encoder->init_lvds_val;
 259         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 260
 261         if (HAS_PCH_CPT(i915)) {
 262                 temp &= ~LVDS_PIPE_SEL_MASK_CPT;
 263                 temp |= LVDS_PIPE_SEL_CPT(pipe);
 264         } else {
 265                 temp &= ~LVDS_PIPE_SEL_MASK;
 266                 temp |= LVDS_PIPE_SEL(pipe);
 267         }
 268
 269         /* set the corresponding LVDS_BORDER bit */
 270         temp &= ~LVDS_BORDER_ENABLE;
 271         temp |= crtc_state->gmch_pfit.lvds_border_bits;
 272
 273         /*
 274          * Set the B0-B3 data pairs corresponding to whether we're going to
 275          * set the DPLLs for dual-channel mode or not.
 276          */
 277         if (lvds_encoder->is_dual_link)
 278                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 279         else
 280                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 281
 282         /*
 283          * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 284          * appropriately here, but we need to look more thoroughly into how
 285          * panels behave in the two modes. For now, let's just maintain the
 286          * value we got from the BIOS.
 287          */
 288         temp &= ~LVDS_A3_POWER_MASK;
 289         temp |= lvds_encoder->a3_power;
 290
 291         /*
 292          * Set the dithering flag on LVDS as needed, note that there is no
 293          * special lvds dither control bit on pch-split platforms, dithering is
 294          * only controlled through the TRANSCONF reg.
 295          */
 296         if (DISPLAY_VER(i915) == 4) {
 297                 /*
 298                  * Bspec wording suggests that LVDS port dithering only exists
 299                  * for 18bpp panels.
 300                  */
 301                 if (crtc_state->dither && crtc_state->pipe_bpp == 18)
 302                         temp |= LVDS_ENABLE_DITHER;
 303                 else
 304                         temp &= ~LVDS_ENABLE_DITHER;
 305         }
 306         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 307         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 308                 temp |= LVDS_HSYNC_POLARITY;
 309         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 310                 temp |= LVDS_VSYNC_POLARITY;
 311
 312         intel_de_write(i915, lvds_encoder->reg, temp);
 313 }
 314
 315 /*
 316  * Sets the power state for the panel.
 317  */
 318 static void intel_enable_lvds(struct intel_atomic_state *state,
 319                               struct intel_encoder *encoder,
 320                               const struct intel_crtc_state *crtc_state,
 321                               const struct drm_connector_state *conn_state)
 322 {
 323         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 324         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 325
 326         intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN);
 327
 328         intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), 0, PANEL_POWER_ON);
 329         intel_de_posting_read(dev_priv, lvds_encoder->reg);
 330
 331         if (intel_de_wait_for_set(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 5000))
 332                 drm_err(&dev_priv->drm,
 333                         "timed out waiting for panel to power on\n");
 334
 335         intel_backlight_enable(crtc_state, conn_state);
 336 }
 337
 338 static void intel_disable_lvds(struct intel_atomic_state *state,
 339                                struct intel_encoder *encoder,
 340                                const struct intel_crtc_state *old_crtc_state,
 341                                const struct drm_connector_state *old_conn_state)
 342 {
 343         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 344         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 345
 346         intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), PANEL_POWER_ON, 0);
 347         if (intel_de_wait_for_clear(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 1000))
 348                 drm_err(&dev_priv->drm,
 349                         "timed out waiting for panel to power off\n");
 350
 351         intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0);
 352         intel_de_posting_read(dev_priv, lvds_encoder->reg);
 353 }
 354
 355 static void gmch_disable_lvds(struct intel_atomic_state *state,
 356                               struct intel_encoder *encoder,
 357                               const struct intel_crtc_state *old_crtc_state,
 358                               const struct drm_connector_state *old_conn_state)
 359
 360 {
 361         intel_backlight_disable(old_conn_state);
 362
 363         intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
 364 }
 365
 366 static void pch_disable_lvds(struct intel_atomic_state *state,
 367                              struct intel_encoder *encoder,
 368                              const struct intel_crtc_state *old_crtc_state,
 369                              const struct drm_connector_state *old_conn_state)
 370 {
 371         intel_backlight_disable(old_conn_state);
 372 }
 373
 374 static void pch_post_disable_lvds(struct intel_atomic_state *state,
 375                                   struct intel_encoder *encoder,
 376                                   const struct intel_crtc_state *old_crtc_state,
 377                                   const struct drm_connector_state *old_conn_state)
 378 {
 379         intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
 380 }
 381
 382 static void intel_lvds_shutdown(struct intel_encoder *encoder)
 383 {
 384         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 385
 386         if (intel_de_wait_for_clear(dev_priv, PP_STATUS(dev_priv, 0), PP_CYCLE_DELAY_ACTIVE, 5000))
 387                 drm_err(&dev_priv->drm,
 388                         "timed out waiting for panel power cycle delay\n");
 389 }
 390
 391 static enum drm_mode_status
 392 intel_lvds_mode_valid(struct drm_connector *_connector,
 393                       struct drm_display_mode *mode)
 394 {
 395         struct intel_connector *connector = to_intel_connector(_connector);
 396         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 397         const struct drm_display_mode *fixed_mode =
 398                 intel_panel_fixed_mode(connector, mode);
 399         int max_pixclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq;
 400         enum drm_mode_status status;
 401
 402         status = intel_cpu_transcoder_mode_valid(i915, mode);
 403         if (status != MODE_OK)
 404                 return status;
 405
 406         status = intel_panel_mode_valid(connector, mode);
 407         if (status != MODE_OK)
 408                 return status;
 409
 410         if (fixed_mode->clock > max_pixclk)
 411                 return MODE_CLOCK_HIGH;
 412
 413         return MODE_OK;
 414 }
 415
 416 static int intel_lvds_compute_config(struct intel_encoder *encoder,
 417                                      struct intel_crtc_state *crtc_state,
 418                                      struct drm_connector_state *conn_state)
 419 {
 420         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 421         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 422         struct intel_connector *connector = lvds_encoder->attached_connector;
 423         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 424         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 425         unsigned int lvds_bpp;
 426         int ret;
 427
 428         /* Should never happen!! */
 429         if (DISPLAY_VER(i915) < 4 && crtc->pipe == 0) {
 430                 drm_err(&i915->drm, "Can't support LVDS on pipe A\n");
 431                 return -EINVAL;
 432         }
 433
 434         if (HAS_PCH_SPLIT(i915)) {
 435                 crtc_state->has_pch_encoder = true;
 436                 if (!intel_fdi_compute_pipe_bpp(crtc_state))
 437                         return -EINVAL;
 438         }
 439
 440         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 441                 lvds_bpp = 8*3;
 442         else
 443                 lvds_bpp = 6*3;
 444
 445         /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
 446         if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) {
 447                 drm_dbg_kms(&i915->drm,
 448                             "forcing display bpp (was %d) to LVDS (%d)\n",
 449                             crtc_state->pipe_bpp, lvds_bpp);
 450                 crtc_state->pipe_bpp = lvds_bpp;
 451         }
 452
 453         crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
 454         crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
 455
 456         /*
 457          * We have timings from the BIOS for the panel, put them in
 458          * to the adjusted mode.  The CRTC will be set up for this mode,
 459          * with the panel scaling set up to source from the H/VDisplay
 460          * of the original mode.
 461          */
 462         ret = intel_panel_compute_config(connector, adjusted_mode);
 463         if (ret)
 464                 return ret;
 465
 466         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 467                 return -EINVAL;
 468
 469         ret = intel_panel_fitting(crtc_state, conn_state);
 470         if (ret)
 471                 return ret;
 472
 473         /*
 474          * XXX: It would be nice to support lower refresh rates on the
 475          * panels to reduce power consumption, and perhaps match the
 476          * user's requested refresh rate.
 477          */
 478
 479         return 0;
 480 }
 481
 482 /*
 483  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 484  */
 485 static int intel_lvds_get_modes(struct drm_connector *_connector)
 486 {
 487         struct intel_connector *connector = to_intel_connector(_connector);
 488         const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
 489
 490         /* Use panel fixed edid if we have one */
 491         if (!IS_ERR_OR_NULL(fixed_edid)) {
 492                 drm_edid_connector_update(&connector->base, fixed_edid);
 493
 494                 return drm_edid_connector_add_modes(&connector->base);
 495         }
 496
 497         return intel_panel_get_modes(connector);
 498 }
 499
 500 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 501         .get_modes = intel_lvds_get_modes,
 502         .mode_valid = intel_lvds_mode_valid,
 503         .atomic_check = intel_digital_connector_atomic_check,
 504 };
 505
 506 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 507         .detect = intel_panel_detect,
 508         .fill_modes = drm_helper_probe_single_connector_modes,
 509         .atomic_get_property = intel_digital_connector_atomic_get_property,
 510         .atomic_set_property = intel_digital_connector_atomic_set_property,
 511         .late_register = intel_connector_register,
 512         .early_unregister = intel_connector_unregister,
 513         .destroy = intel_connector_destroy,
 514         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 515         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 516 };
 517
 518 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 519         .destroy = intel_encoder_destroy,
 520 };
 521
 522 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 523 {
 524         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 525         return 1;
 526 }
 527
 528 /* These systems claim to have LVDS, but really don't */
 529 static const struct dmi_system_id intel_no_lvds[] = {
 530         {
 531                 .callback = intel_no_lvds_dmi_callback,
 532                 .ident = "Apple Mac Mini (Core series)",
 533                 .matches = {
 534                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 535                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 536                 },
 537         },
 538         {
 539                 .callback = intel_no_lvds_dmi_callback,
 540                 .ident = "Apple Mac Mini (Core 2 series)",
 541                 .matches = {
 542                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 543                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 544                 },
 545         },
 546         {
 547                 .callback = intel_no_lvds_dmi_callback,
 548                 .ident = "MSI IM-945GSE-A",
 549                 .matches = {
 550                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 551                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 552                 },
 553         },
 554         {
 555                 .callback = intel_no_lvds_dmi_callback,
 556                 .ident = "Dell Studio Hybrid",
 557                 .matches = {
 558                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 559                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 560                 },
 561         },
 562         {
 563                 .callback = intel_no_lvds_dmi_callback,
 564                 .ident = "Dell OptiPlex FX170",
 565                 .matches = {
 566                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 567                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 568                 },
 569         },
 570         {
 571                 .callback = intel_no_lvds_dmi_callback,
 572                 .ident = "AOpen Mini PC",
 573                 .matches = {
 574                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 575                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 576                 },
 577         },
 578         {
 579                 .callback = intel_no_lvds_dmi_callback,
 580                 .ident = "AOpen Mini PC MP915",
 581                 .matches = {
 582                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 583                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 584                 },
 585         },
 586         {
 587                 .callback = intel_no_lvds_dmi_callback,
 588                 .ident = "AOpen i915GMm-HFS",
 589                 .matches = {
 590                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 591                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 592                 },
 593         },
 594         {
 595                 .callback = intel_no_lvds_dmi_callback,
 596                 .ident = "AOpen i45GMx-I",
 597                 .matches = {
 598                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 599                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 600                 },
 601         },
 602         {
 603                 .callback = intel_no_lvds_dmi_callback,
 604                 .ident = "Aopen i945GTt-VFA",
 605                 .matches = {
 606                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 607                 },
 608         },
 609         {
 610                 .callback = intel_no_lvds_dmi_callback,
 611                 .ident = "Clientron U800",
 612                 .matches = {
 613                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 614                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 615                 },
 616         },
 617         {
 618                 .callback = intel_no_lvds_dmi_callback,
 619                 .ident = "Clientron E830",
 620                 .matches = {
 621                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 622                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 623                 },
 624         },
 625         {
 626                 .callback = intel_no_lvds_dmi_callback,
 627                 .ident = "Asus EeeBox PC EB1007",
 628                 .matches = {
 629                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 630                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 631                 },
 632         },
 633         {
 634                 .callback = intel_no_lvds_dmi_callback,
 635                 .ident = "Asus AT5NM10T-I",
 636                 .matches = {
 637                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 638                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 639                 },
 640         },
 641         {
 642                 .callback = intel_no_lvds_dmi_callback,
 643                 .ident = "Hewlett-Packard HP t5740",
 644                 .matches = {
 645                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 646                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 647                 },
 648         },
 649         {
 650                 .callback = intel_no_lvds_dmi_callback,
 651                 .ident = "Hewlett-Packard t5745",
 652                 .matches = {
 653                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 654                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 655                 },
 656         },
 657         {
 658                 .callback = intel_no_lvds_dmi_callback,
 659                 .ident = "Hewlett-Packard st5747",
 660                 .matches = {
 661                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 662                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 663                 },
 664         },
 665         {
 666                 .callback = intel_no_lvds_dmi_callback,
 667                 .ident = "MSI Wind Box DC500",
 668                 .matches = {
 669                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 670                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 671                 },
 672         },
 673         {
 674                 .callback = intel_no_lvds_dmi_callback,
 675                 .ident = "Gigabyte GA-D525TUD",
 676                 .matches = {
 677                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 678                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 679                 },
 680         },
 681         {
 682                 .callback = intel_no_lvds_dmi_callback,
 683                 .ident = "Supermicro X7SPA-H",
 684                 .matches = {
 685                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 686                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 687                 },
 688         },
 689         {
 690                 .callback = intel_no_lvds_dmi_callback,
 691                 .ident = "Fujitsu Esprimo Q900",
 692                 .matches = {
 693                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 694                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 695                 },
 696         },
 697         {
 698                 .callback = intel_no_lvds_dmi_callback,
 699                 .ident = "Intel D410PT",
 700                 .matches = {
 701                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 702                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 703                 },
 704         },
 705         {
 706                 .callback = intel_no_lvds_dmi_callback,
 707                 .ident = "Intel D425KT",
 708                 .matches = {
 709                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 710                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 711                 },
 712         },
 713         {
 714                 .callback = intel_no_lvds_dmi_callback,
 715                 .ident = "Intel D510MO",
 716                 .matches = {
 717                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 718                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 719                 },
 720         },
 721         {
 722                 .callback = intel_no_lvds_dmi_callback,
 723                 .ident = "Intel D525MW",
 724                 .matches = {
 725                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 726                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 727                 },
 728         },
 729         {
 730                 .callback = intel_no_lvds_dmi_callback,
 731                 .ident = "Radiant P845",
 732                 .matches = {
 733                         DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
 734                         DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
 735                 },
 736         },
 737
 738         { }     /* terminating entry */
 739 };
 740
 741 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 742 {
 743         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 744         return 1;
 745 }
 746
 747 static const struct dmi_system_id intel_dual_link_lvds[] = {
 748         {
 749                 .callback = intel_dual_link_lvds_callback,
 750                 .ident = "Apple MacBook Pro 15\" (2010)",
 751                 .matches = {
 752                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 753                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 754                 },
 755         },
 756         {
 757                 .callback = intel_dual_link_lvds_callback,
 758                 .ident = "Apple MacBook Pro 15\" (2011)",
 759                 .matches = {
 760                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 761                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 762                 },
 763         },
 764         {
 765                 .callback = intel_dual_link_lvds_callback,
 766                 .ident = "Apple MacBook Pro 15\" (2012)",
 767                 .matches = {
 768                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 769                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 770                 },
 771         },
 772         { }     /* terminating entry */
 773 };
 774
 775 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *i915)
 776 {
 777         struct intel_encoder *encoder;
 778
 779         for_each_intel_encoder(&i915->drm, encoder) {
 780                 if (encoder->type == INTEL_OUTPUT_LVDS)
 781                         return encoder;
 782         }
 783
 784         return NULL;
 785 }
 786
 787 bool intel_is_dual_link_lvds(struct drm_i915_private *i915)
 788 {
 789         struct intel_encoder *encoder = intel_get_lvds_encoder(i915);
 790
 791         return encoder && to_lvds_encoder(encoder)->is_dual_link;
 792 }
 793
 794 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 795 {
 796         struct drm_i915_private *i915 = to_i915(lvds_encoder->base.base.dev);
 797         struct intel_connector *connector = lvds_encoder->attached_connector;
 798         const struct drm_display_mode *fixed_mode =
 799                 intel_panel_preferred_fixed_mode(connector);
 800         unsigned int val;
 801
 802         /* use the module option value if specified */
 803         if (i915->display.params.lvds_channel_mode > 0)
 804                 return i915->display.params.lvds_channel_mode == 2;
 805
 806         /* single channel LVDS is limited to 112 MHz */
 807         if (fixed_mode->clock > 112999)
 808                 return true;
 809
 810         if (dmi_check_system(intel_dual_link_lvds))
 811                 return true;
 812
 813         /*
 814          * BIOS should set the proper LVDS register value at boot, but
 815          * in reality, it doesn't set the value when the lid is closed;
 816          * we need to check "the value to be set" in VBT when LVDS
 817          * register is uninitialized.
 818          */
 819         val = intel_de_read(i915, lvds_encoder->reg);
 820         if (HAS_PCH_CPT(i915))
 821                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
 822         else
 823                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
 824         if (val == 0)
 825                 val = connector->panel.vbt.bios_lvds_val;
 826
 827         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 828 }
 829
 830 static void intel_lvds_add_properties(struct drm_connector *connector)
 831 {
 832         intel_attach_scaling_mode_property(connector);
 833 }
 834
 835 /**
 836  * intel_lvds_init - setup LVDS connectors on this device
 837  * @i915: i915 device
 838  *
 839  * Create the connector, register the LVDS DDC bus, and try to figure out what
 840  * modes we can display on the LVDS panel (if present).
 841  */
 842 void intel_lvds_init(struct drm_i915_private *i915)
 843 {
 844         struct intel_display *display = &i915->display;
 845         struct intel_lvds_encoder *lvds_encoder;
 846         struct intel_connector *connector;
 847         const struct drm_edid *drm_edid;
 848         struct intel_encoder *encoder;
 849         i915_reg_t lvds_reg;
 850         u32 lvds;
 851         u8 ddc_pin;
 852
 853         /* Skip init on machines we know falsely report LVDS */
 854         if (dmi_check_system(intel_no_lvds)) {
 855                 drm_WARN(&i915->drm, !i915->display.vbt.int_lvds_support,
 856                          "Useless DMI match. Internal LVDS support disabled by VBT\n");
 857                 return;
 858         }
 859
 860         if (!i915->display.vbt.int_lvds_support) {
 861                 drm_dbg_kms(&i915->drm,
 862                             "Internal LVDS support disabled by VBT\n");
 863                 return;
 864         }
 865
 866         if (HAS_PCH_SPLIT(i915))
 867                 lvds_reg = PCH_LVDS;
 868         else
 869                 lvds_reg = LVDS;
 870
 871         lvds = intel_de_read(i915, lvds_reg);
 872
 873         if (HAS_PCH_SPLIT(i915)) {
 874                 if ((lvds & LVDS_DETECTED) == 0)
 875                         return;
 876         }
 877
 878         ddc_pin = GMBUS_PIN_PANEL;
 879         if (!intel_bios_is_lvds_present(display, &ddc_pin)) {
 880                 if ((lvds & LVDS_PORT_EN) == 0) {
 881                         drm_dbg_kms(&i915->drm,
 882                                     "LVDS is not present in VBT\n");
 883                         return;
 884                 }
 885                 drm_dbg_kms(&i915->drm,
 886                             "LVDS is not present in VBT, but enabled anyway\n");
 887         }
 888
 889         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
 890         if (!lvds_encoder)
 891                 return;
 892
 893         connector = intel_connector_alloc();
 894         if (!connector) {
 895                 kfree(lvds_encoder);
 896                 return;
 897         }
 898
 899         lvds_encoder->attached_connector = connector;
 900         encoder = &lvds_encoder->base;
 901
 902         drm_connector_init_with_ddc(&i915->drm, &connector->base,
 903                                     &intel_lvds_connector_funcs,
 904                                     DRM_MODE_CONNECTOR_LVDS,
 905                                     intel_gmbus_get_adapter(display, ddc_pin));
 906
 907         drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs,
 908                          DRM_MODE_ENCODER_LVDS, "LVDS");
 909
 910         encoder->enable = intel_enable_lvds;
 911         encoder->pre_enable = intel_pre_enable_lvds;
 912         encoder->compute_config = intel_lvds_compute_config;
 913         if (HAS_PCH_SPLIT(i915)) {
 914                 encoder->disable = pch_disable_lvds;
 915                 encoder->post_disable = pch_post_disable_lvds;
 916         } else {
 917                 encoder->disable = gmch_disable_lvds;
 918         }
 919         encoder->get_hw_state = intel_lvds_get_hw_state;
 920         encoder->get_config = intel_lvds_get_config;
 921         encoder->update_pipe = intel_backlight_update;
 922         encoder->shutdown = intel_lvds_shutdown;
 923         connector->get_hw_state = intel_connector_get_hw_state;
 924
 925         intel_connector_attach_encoder(connector, encoder);
 926
 927         encoder->type = INTEL_OUTPUT_LVDS;
 928         encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
 929         encoder->port = PORT_NONE;
 930         encoder->cloneable = 0;
 931         if (DISPLAY_VER(i915) < 4)
 932                 encoder->pipe_mask = BIT(PIPE_B);
 933         else
 934                 encoder->pipe_mask = ~0;
 935
 936         drm_connector_helper_add(&connector->base, &intel_lvds_connector_helper_funcs);
 937         connector->base.display_info.subpixel_order = SubPixelHorizontalRGB;
 938
 939         lvds_encoder->reg = lvds_reg;
 940
 941         intel_lvds_add_properties(&connector->base);
 942
 943         intel_lvds_pps_get_hw_state(i915, &lvds_encoder->init_pps);
 944         lvds_encoder->init_lvds_val = lvds;
 945
 946         /*
 947          * LVDS discovery:
 948          * 1) check for EDID on DDC
 949          * 2) check for VBT data
 950          * 3) check to see if LVDS is already on
 951          *    if none of the above, no panel
 952          */
 953
 954         /*
 955          * Attempt to get the fixed panel mode from DDC.  Assume that the
 956          * preferred mode is the right one.
 957          */
 958         mutex_lock(&i915->drm.mode_config.mutex);
 959         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
 960                 drm_edid = drm_edid_read_switcheroo(&connector->base, connector->base.ddc);
 961         else
 962                 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);
 963         if (drm_edid) {
 964                 if (drm_edid_connector_update(&connector->base, drm_edid) ||
 965                     !drm_edid_connector_add_modes(&connector->base)) {
 966                         drm_edid_connector_update(&connector->base, NULL);
 967                         drm_edid_free(drm_edid);
 968                         drm_edid = ERR_PTR(-EINVAL);
 969                 }
 970         } else {
 971                 drm_edid = ERR_PTR(-ENOENT);
 972         }
 973         intel_bios_init_panel_late(display, &connector->panel, NULL,
 974                                    IS_ERR(drm_edid) ? NULL : drm_edid);
 975
 976         /* Try EDID first */
 977         intel_panel_add_edid_fixed_modes(connector, true);
 978
 979         /* Failed to get EDID, what about VBT? */
 980         if (!intel_panel_preferred_fixed_mode(connector))
 981                 intel_panel_add_vbt_lfp_fixed_mode(connector);
 982
 983         /*
 984          * If we didn't get a fixed mode from EDID or VBT, try checking
 985          * if the panel is already turned on.  If so, assume that
 986          * whatever is currently programmed is the correct mode.
 987          */
 988         if (!intel_panel_preferred_fixed_mode(connector))
 989                 intel_panel_add_encoder_fixed_mode(connector, encoder);
 990
 991         mutex_unlock(&i915->drm.mode_config.mutex);
 992
 993         /* If we still don't have a mode after all that, give up. */
 994         if (!intel_panel_preferred_fixed_mode(connector))
 995                 goto failed;
 996
 997         intel_panel_init(connector, drm_edid);
 998
 999         intel_backlight_setup(connector, INVALID_PIPE);
1000
1001         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1002         drm_dbg_kms(&i915->drm, "detected %s-link lvds configuration\n",
1003                     lvds_encoder->is_dual_link ? "dual" : "single");
1004
1005         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1006
1007         return;
1008
1009 failed:
1010         drm_dbg_kms(&i915->drm, "No LVDS modes found, disabling.\n");
1011         drm_connector_cleanup(&connector->base);
1012         drm_encoder_cleanup(&encoder->base);
1013         kfree(lvds_encoder);
1014         intel_connector_free(connector);
1015         return;
1016 }