drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_sched.h"
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/pm_runtime.h>
  39 #include "amdgpu_amdkfd.h"
  40 #include "amdgpu_gem.h"
  41 #include "amdgpu_display.h"
  42
  43 /**
  44  * amdgpu_driver_unload_kms - Main unload function for KMS.
  45  *
  46  * @dev: drm dev pointer
  47  *
  48  * This is the main unload function for KMS (all asics).
  49  * Returns 0 on success.
  50  */
  51 void amdgpu_driver_unload_kms(struct drm_device *dev)
  52 {
  53         struct amdgpu_device *adev = dev->dev_private;
  54
  55         if (adev == NULL)
  56                 return;
  57
  58         if (adev->rmmio == NULL)
  59                 goto done_free;
  60
  61         if (amdgpu_sriov_vf(adev))
  62                 amdgpu_virt_request_full_gpu(adev, false);
  63
  64         if (amdgpu_device_is_px(dev)) {
  65                 pm_runtime_get_sync(dev->dev);
  66                 pm_runtime_forbid(dev->dev);
  67         }
  68
  69         amdgpu_acpi_fini(adev);
  70
  71         amdgpu_device_fini(adev);
  72
  73 done_free:
  74         kfree(adev);
  75         dev->dev_private = NULL;
  76 }
  77
  78 /**
  79  * amdgpu_driver_load_kms - Main load function for KMS.
  80  *
  81  * @dev: drm dev pointer
  82  * @flags: device flags
  83  *
  84  * This is the main load function for KMS (all asics).
  85  * Returns 0 on success, error on failure.
  86  */
  87 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
  88 {
  89         struct amdgpu_device *adev;
  90         int r, acpi_status;
  91
  92 #ifdef CONFIG_DRM_AMDGPU_SI
  93         if (!amdgpu_si_support) {
  94                 switch (flags & AMD_ASIC_MASK) {
  95                 case CHIP_TAHITI:
  96                 case CHIP_PITCAIRN:
  97                 case CHIP_VERDE:
  98                 case CHIP_OLAND:
  99                 case CHIP_HAINAN:
 100                         dev_info(dev->dev,
 101                                  "SI support provided by radeon.\n");
 102                         dev_info(dev->dev,
 103                                  "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
 104                                 );
 105                         return -ENODEV;
 106                 }
 107         }
 108 #endif
 109 #ifdef CONFIG_DRM_AMDGPU_CIK
 110         if (!amdgpu_cik_support) {
 111                 switch (flags & AMD_ASIC_MASK) {
 112                 case CHIP_KAVERI:
 113                 case CHIP_BONAIRE:
 114                 case CHIP_HAWAII:
 115                 case CHIP_KABINI:
 116                 case CHIP_MULLINS:
 117                         dev_info(dev->dev,
 118                                  "CIK support provided by radeon.\n");
 119                         dev_info(dev->dev,
 120                                  "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
 121                                 );
 122                         return -ENODEV;
 123                 }
 124         }
 125 #endif
 126
 127         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 128         if (adev == NULL) {
 129                 return -ENOMEM;
 130         }
 131         dev->dev_private = (void *)adev;
 132
 133         if ((amdgpu_runtime_pm != 0) &&
 134             amdgpu_has_atpx() &&
 135             (amdgpu_is_atpx_hybrid() ||
 136              amdgpu_has_atpx_dgpu_power_cntl()) &&
 137             ((flags & AMD_IS_APU) == 0) &&
 138             !pci_is_thunderbolt_attached(dev->pdev))
 139                 flags |= AMD_IS_PX;
 140
 141         /* amdgpu_device_init should report only fatal error
 142          * like memory allocation failure or iomapping failure,
 143          * or memory manager initialization failure, it must
 144          * properly initialize the GPU MC controller and permit
 145          * VRAM allocation
 146          */
 147         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 148         if (r) {
 149                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 150                 goto out;
 151         }
 152
 153         /* Call ACPI methods: require modeset init
 154          * but failure is not fatal
 155          */
 156         if (!r) {
 157                 acpi_status = amdgpu_acpi_init(adev);
 158                 if (acpi_status)
 159                 dev_dbg(&dev->pdev->dev,
 160                                 "Error during ACPI methods call\n");
 161         }
 162
 163         if (amdgpu_device_is_px(dev)) {
 164                 pm_runtime_use_autosuspend(dev->dev);
 165                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 166                 pm_runtime_set_active(dev->dev);
 167                 pm_runtime_allow(dev->dev);
 168                 pm_runtime_mark_last_busy(dev->dev);
 169                 pm_runtime_put_autosuspend(dev->dev);
 170         }
 171
 172 out:
 173         if (r) {
 174                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 175                 if (adev->rmmio && amdgpu_device_is_px(dev))
 176                         pm_runtime_put_noidle(dev->dev);
 177                 amdgpu_driver_unload_kms(dev);
 178         }
 179
 180         return r;
 181 }
 182
 183 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 184                                 struct drm_amdgpu_query_fw *query_fw,
 185                                 struct amdgpu_device *adev)
 186 {
 187         switch (query_fw->fw_type) {
 188         case AMDGPU_INFO_FW_VCE:
 189                 fw_info->ver = adev->vce.fw_version;
 190                 fw_info->feature = adev->vce.fb_version;
 191                 break;
 192         case AMDGPU_INFO_FW_UVD:
 193                 fw_info->ver = adev->uvd.fw_version;
 194                 fw_info->feature = 0;
 195                 break;
 196         case AMDGPU_INFO_FW_VCN:
 197                 fw_info->ver = adev->vcn.fw_version;
 198                 fw_info->feature = 0;
 199                 break;
 200         case AMDGPU_INFO_FW_GMC:
 201                 fw_info->ver = adev->gmc.fw_version;
 202                 fw_info->feature = 0;
 203                 break;
 204         case AMDGPU_INFO_FW_GFX_ME:
 205                 fw_info->ver = adev->gfx.me_fw_version;
 206                 fw_info->feature = adev->gfx.me_feature_version;
 207                 break;
 208         case AMDGPU_INFO_FW_GFX_PFP:
 209                 fw_info->ver = adev->gfx.pfp_fw_version;
 210                 fw_info->feature = adev->gfx.pfp_feature_version;
 211                 break;
 212         case AMDGPU_INFO_FW_GFX_CE:
 213                 fw_info->ver = adev->gfx.ce_fw_version;
 214                 fw_info->feature = adev->gfx.ce_feature_version;
 215                 break;
 216         case AMDGPU_INFO_FW_GFX_RLC:
 217                 fw_info->ver = adev->gfx.rlc_fw_version;
 218                 fw_info->feature = adev->gfx.rlc_feature_version;
 219                 break;
 220         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 221                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 222                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 223                 break;
 224         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 225                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 226                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 227                 break;
 228         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 229                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 230                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 231                 break;
 232         case AMDGPU_INFO_FW_GFX_MEC:
 233                 if (query_fw->index == 0) {
 234                         fw_info->ver = adev->gfx.mec_fw_version;
 235                         fw_info->feature = adev->gfx.mec_feature_version;
 236                 } else if (query_fw->index == 1) {
 237                         fw_info->ver = adev->gfx.mec2_fw_version;
 238                         fw_info->feature = adev->gfx.mec2_feature_version;
 239                 } else
 240                         return -EINVAL;
 241                 break;
 242         case AMDGPU_INFO_FW_SMC:
 243                 fw_info->ver = adev->pm.fw_version;
 244                 fw_info->feature = 0;
 245                 break;
 246         case AMDGPU_INFO_FW_SDMA:
 247                 if (query_fw->index >= adev->sdma.num_instances)
 248                         return -EINVAL;
 249                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 250                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 251                 break;
 252         case AMDGPU_INFO_FW_SOS:
 253                 fw_info->ver = adev->psp.sos_fw_version;
 254                 fw_info->feature = adev->psp.sos_feature_version;
 255                 break;
 256         case AMDGPU_INFO_FW_ASD:
 257                 fw_info->ver = adev->psp.asd_fw_version;
 258                 fw_info->feature = adev->psp.asd_feature_version;
 259                 break;
 260         case AMDGPU_INFO_FW_DMCU:
 261                 fw_info->ver = adev->dm.dmcu_fw_version;
 262                 fw_info->feature = 0;
 263                 break;
 264         default:
 265                 return -EINVAL;
 266         }
 267         return 0;
 268 }
 269
 270 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 271                              struct drm_amdgpu_info *info,
 272                              struct drm_amdgpu_info_hw_ip *result)
 273 {
 274         uint32_t ib_start_alignment = 0;
 275         uint32_t ib_size_alignment = 0;
 276         enum amd_ip_block_type type;
 277         unsigned int num_rings = 0;
 278         unsigned int i, j;
 279
 280         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 281                 return -EINVAL;
 282
 283         switch (info->query_hw_ip.type) {
 284         case AMDGPU_HW_IP_GFX:
 285                 type = AMD_IP_BLOCK_TYPE_GFX;
 286                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 287                         if (adev->gfx.gfx_ring[i].ready)
 288                                 ++num_rings;
 289                 ib_start_alignment = 32;
 290                 ib_size_alignment = 32;
 291                 break;
 292         case AMDGPU_HW_IP_COMPUTE:
 293                 type = AMD_IP_BLOCK_TYPE_GFX;
 294                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 295                         if (adev->gfx.compute_ring[i].ready)
 296                                 ++num_rings;
 297                 ib_start_alignment = 32;
 298                 ib_size_alignment = 32;
 299                 break;
 300         case AMDGPU_HW_IP_DMA:
 301                 type = AMD_IP_BLOCK_TYPE_SDMA;
 302                 for (i = 0; i < adev->sdma.num_instances; i++)
 303                         if (adev->sdma.instance[i].ring.ready)
 304                                 ++num_rings;
 305                 ib_start_alignment = 256;
 306                 ib_size_alignment = 4;
 307                 break;
 308         case AMDGPU_HW_IP_UVD:
 309                 type = AMD_IP_BLOCK_TYPE_UVD;
 310                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 311                         if (adev->uvd.harvest_config & (1 << i))
 312                                 continue;
 313
 314                         if (adev->uvd.inst[i].ring.ready)
 315                                 ++num_rings;
 316                 }
 317                 ib_start_alignment = 64;
 318                 ib_size_alignment = 64;
 319                 break;
 320         case AMDGPU_HW_IP_VCE:
 321                 type = AMD_IP_BLOCK_TYPE_VCE;
 322                 for (i = 0; i < adev->vce.num_rings; i++)
 323                         if (adev->vce.ring[i].ready)
 324                                 ++num_rings;
 325                 ib_start_alignment = 4;
 326                 ib_size_alignment = 1;
 327                 break;
 328         case AMDGPU_HW_IP_UVD_ENC:
 329                 type = AMD_IP_BLOCK_TYPE_UVD;
 330                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 331                         if (adev->uvd.harvest_config & (1 << i))
 332                                 continue;
 333
 334                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 335                                 if (adev->uvd.inst[i].ring_enc[j].ready)
 336                                         ++num_rings;
 337                 }
 338                 ib_start_alignment = 64;
 339                 ib_size_alignment = 64;
 340                 break;
 341         case AMDGPU_HW_IP_VCN_DEC:
 342                 type = AMD_IP_BLOCK_TYPE_VCN;
 343                 if (adev->vcn.ring_dec.ready)
 344                         ++num_rings;
 345                 ib_start_alignment = 16;
 346                 ib_size_alignment = 16;
 347                 break;
 348         case AMDGPU_HW_IP_VCN_ENC:
 349                 type = AMD_IP_BLOCK_TYPE_VCN;
 350                 for (i = 0; i < adev->vcn.num_enc_rings; i++)
 351                         if (adev->vcn.ring_enc[i].ready)
 352                                 ++num_rings;
 353                 ib_start_alignment = 64;
 354                 ib_size_alignment = 1;
 355                 break;
 356         case AMDGPU_HW_IP_VCN_JPEG:
 357                 type = AMD_IP_BLOCK_TYPE_VCN;
 358                 if (adev->vcn.ring_jpeg.ready)
 359                         ++num_rings;
 360                 ib_start_alignment = 16;
 361                 ib_size_alignment = 16;
 362                 break;
 363         default:
 364                 return -EINVAL;
 365         }
 366
 367         for (i = 0; i < adev->num_ip_blocks; i++)
 368                 if (adev->ip_blocks[i].version->type == type &&
 369                     adev->ip_blocks[i].status.valid)
 370                         break;
 371
 372         if (i == adev->num_ip_blocks)
 373                 return 0;
 374
 375         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 376                         num_rings);
 377
 378         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 379         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 380         result->capabilities_flags = 0;
 381         result->available_rings = (1 << num_rings) - 1;
 382         result->ib_start_alignment = ib_start_alignment;
 383         result->ib_size_alignment = ib_size_alignment;
 384         return 0;
 385 }
 386
 387 /*
 388  * Userspace get information ioctl
 389  */
 390 /**
 391  * amdgpu_info_ioctl - answer a device specific request.
 392  *
 393  * @adev: amdgpu device pointer
 394  * @data: request object
 395  * @filp: drm filp
 396  *
 397  * This function is used to pass device specific parameters to the userspace
 398  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 399  * etc. (all asics).
 400  * Returns 0 on success, -EINVAL on failure.
 401  */
 402 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 403 {
 404         struct amdgpu_device *adev = dev->dev_private;
 405         struct drm_amdgpu_info *info = data;
 406         struct amdgpu_mode_info *minfo = &adev->mode_info;
 407         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 408         uint32_t size = info->return_size;
 409         struct drm_crtc *crtc;
 410         uint32_t ui32 = 0;
 411         uint64_t ui64 = 0;
 412         int i, found;
 413         int ui32_size = sizeof(ui32);
 414
 415         if (!info->return_size || !info->return_pointer)
 416                 return -EINVAL;
 417
 418         /* Ensure IB tests are run on ring */
 419         flush_delayed_work(&adev->late_init_work);
 420
 421         switch (info->query) {
 422         case AMDGPU_INFO_ACCEL_WORKING:
 423                 ui32 = adev->accel_working;
 424                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 425         case AMDGPU_INFO_CRTC_FROM_ID:
 426                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 427                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 428                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 429                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 430                                 ui32 = amdgpu_crtc->crtc_id;
 431                                 found = 1;
 432                                 break;
 433                         }
 434                 }
 435                 if (!found) {
 436                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 437                         return -EINVAL;
 438                 }
 439                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 440         case AMDGPU_INFO_HW_IP_INFO: {
 441                 struct drm_amdgpu_info_hw_ip ip = {};
 442                 int ret;
 443
 444                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 445                 if (ret)
 446                         return ret;
 447
 448                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 449                 return ret ? -EFAULT : 0;
 450         }
 451         case AMDGPU_INFO_HW_IP_COUNT: {
 452                 enum amd_ip_block_type type;
 453                 uint32_t count = 0;
 454
 455                 switch (info->query_hw_ip.type) {
 456                 case AMDGPU_HW_IP_GFX:
 457                         type = AMD_IP_BLOCK_TYPE_GFX;
 458                         break;
 459                 case AMDGPU_HW_IP_COMPUTE:
 460                         type = AMD_IP_BLOCK_TYPE_GFX;
 461                         break;
 462                 case AMDGPU_HW_IP_DMA:
 463                         type = AMD_IP_BLOCK_TYPE_SDMA;
 464                         break;
 465                 case AMDGPU_HW_IP_UVD:
 466                         type = AMD_IP_BLOCK_TYPE_UVD;
 467                         break;
 468                 case AMDGPU_HW_IP_VCE:
 469                         type = AMD_IP_BLOCK_TYPE_VCE;
 470                         break;
 471                 case AMDGPU_HW_IP_UVD_ENC:
 472                         type = AMD_IP_BLOCK_TYPE_UVD;
 473                         break;
 474                 case AMDGPU_HW_IP_VCN_DEC:
 475                 case AMDGPU_HW_IP_VCN_ENC:
 476                 case AMDGPU_HW_IP_VCN_JPEG:
 477                         type = AMD_IP_BLOCK_TYPE_VCN;
 478                         break;
 479                 default:
 480                         return -EINVAL;
 481                 }
 482
 483                 for (i = 0; i < adev->num_ip_blocks; i++)
 484                         if (adev->ip_blocks[i].version->type == type &&
 485                             adev->ip_blocks[i].status.valid &&
 486                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 487                                 count++;
 488
 489                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 490         }
 491         case AMDGPU_INFO_TIMESTAMP:
 492                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 493                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 494         case AMDGPU_INFO_FW_VERSION: {
 495                 struct drm_amdgpu_info_firmware fw_info;
 496                 int ret;
 497
 498                 /* We only support one instance of each IP block right now. */
 499                 if (info->query_fw.ip_instance != 0)
 500                         return -EINVAL;
 501
 502                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 503                 if (ret)
 504                         return ret;
 505
 506                 return copy_to_user(out, &fw_info,
 507                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 508         }
 509         case AMDGPU_INFO_NUM_BYTES_MOVED:
 510                 ui64 = atomic64_read(&adev->num_bytes_moved);
 511                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 512         case AMDGPU_INFO_NUM_EVICTIONS:
 513                 ui64 = atomic64_read(&adev->num_evictions);
 514                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 515         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 516                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 517                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 518         case AMDGPU_INFO_VRAM_USAGE:
 519                 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 520                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 521         case AMDGPU_INFO_VIS_VRAM_USAGE:
 522                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 523                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 524         case AMDGPU_INFO_GTT_USAGE:
 525                 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 526                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 527         case AMDGPU_INFO_GDS_CONFIG: {
 528                 struct drm_amdgpu_info_gds gds_info;
 529
 530                 memset(&gds_info, 0, sizeof(gds_info));
 531                 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size;
 532                 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size;
 533                 gds_info.gds_total_size = adev->gds.mem.total_size;
 534                 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size;
 535                 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size;
 536                 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size;
 537                 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size;
 538                 return copy_to_user(out, &gds_info,
 539                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 540         }
 541         case AMDGPU_INFO_VRAM_GTT: {
 542                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 543
 544                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 545                         atomic64_read(&adev->vram_pin_size);
 546                 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
 547                         atomic64_read(&adev->visible_pin_size);
 548                 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
 549                 vram_gtt.gtt_size *= PAGE_SIZE;
 550                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 551                 return copy_to_user(out, &vram_gtt,
 552                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 553         }
 554         case AMDGPU_INFO_MEMORY: {
 555                 struct drm_amdgpu_memory_info mem;
 556
 557                 memset(&mem, 0, sizeof(mem));
 558                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 559                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 560                         atomic64_read(&adev->vram_pin_size);
 561                 mem.vram.heap_usage =
 562                         amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 563                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 564
 565                 mem.cpu_accessible_vram.total_heap_size =
 566                         adev->gmc.visible_vram_size;
 567                 mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
 568                         atomic64_read(&adev->visible_pin_size);
 569                 mem.cpu_accessible_vram.heap_usage =
 570                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 571                 mem.cpu_accessible_vram.max_allocation =
 572                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 573
 574                 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
 575                 mem.gtt.total_heap_size *= PAGE_SIZE;
 576                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 577                         atomic64_read(&adev->gart_pin_size);
 578                 mem.gtt.heap_usage =
 579                         amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 580                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 581
 582                 return copy_to_user(out, &mem,
 583                                     min((size_t)size, sizeof(mem)))
 584                                     ? -EFAULT : 0;
 585         }
 586         case AMDGPU_INFO_READ_MMR_REG: {
 587                 unsigned n, alloc_size;
 588                 uint32_t *regs;
 589                 unsigned se_num = (info->read_mmr_reg.instance >>
 590                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 591                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 592                 unsigned sh_num = (info->read_mmr_reg.instance >>
 593                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 594                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 595
 596                 /* set full masks if the userspace set all bits
 597                  * in the bitfields */
 598                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 599                         se_num = 0xffffffff;
 600                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 601                         sh_num = 0xffffffff;
 602
 603                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 604                 if (!regs)
 605                         return -ENOMEM;
 606                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 607
 608                 for (i = 0; i < info->read_mmr_reg.count; i++)
 609                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 610                                                       info->read_mmr_reg.dword_offset + i,
 611                                                       &regs[i])) {
 612                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 613                                               info->read_mmr_reg.dword_offset + i);
 614                                 kfree(regs);
 615                                 return -EFAULT;
 616                         }
 617                 n = copy_to_user(out, regs, min(size, alloc_size));
 618                 kfree(regs);
 619                 return n ? -EFAULT : 0;
 620         }
 621         case AMDGPU_INFO_DEV_INFO: {
 622                 struct drm_amdgpu_info_device dev_info = {};
 623                 uint64_t vm_size;
 624
 625                 dev_info.device_id = dev->pdev->device;
 626                 dev_info.chip_rev = adev->rev_id;
 627                 dev_info.external_rev = adev->external_rev_id;
 628                 dev_info.pci_rev = dev->pdev->revision;
 629                 dev_info.family = adev->family;
 630                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 631                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 632                 /* return all clocks in KHz */
 633                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 634                 if (adev->pm.dpm_enabled) {
 635                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 636                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 637                 } else {
 638                         dev_info.max_engine_clock = adev->clock.default_sclk * 10;
 639                         dev_info.max_memory_clock = adev->clock.default_mclk * 10;
 640                 }
 641                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 642                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 643                         adev->gfx.config.max_shader_engines;
 644                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 645                 dev_info._pad = 0;
 646                 dev_info.ids_flags = 0;
 647                 if (adev->flags & AMD_IS_APU)
 648                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 649                 if (amdgpu_sriov_vf(adev))
 650                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 651
 652                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 653                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 654
 655                 /* Older VCE FW versions are buggy and can handle only 40bits */
 656                 if (adev->vce.fw_version &&
 657                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 658                         vm_size = min(vm_size, 1ULL << 40);
 659
 660                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 661                 dev_info.virtual_address_max =
 662                         min(vm_size, AMDGPU_GMC_HOLE_START);
 663
 664                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 665                         dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
 666                         dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 667                 }
 668                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 669                 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 670                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 671                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 672                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 673                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 674                 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 675                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 676                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 677                        sizeof(adev->gfx.cu_info.bitmap));
 678                 dev_info.vram_type = adev->gmc.vram_type;
 679                 dev_info.vram_bit_width = adev->gmc.vram_width;
 680                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 681                 dev_info.gc_double_offchip_lds_buf =
 682                         adev->gfx.config.double_offchip_lds_buf;
 683
 684                 if (amdgpu_ngg) {
 685                         dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
 686                         dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
 687                         dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
 688                         dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
 689                         dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
 690                         dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
 691                         dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
 692                         dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
 693                 }
 694                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
 695                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 696                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 697                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 698                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 699                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 700                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 701
 702                 return copy_to_user(out, &dev_info,
 703                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 704         }
 705         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 706                 unsigned i;
 707                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 708                 struct amd_vce_state *vce_state;
 709
 710                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 711                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 712                         if (vce_state) {
 713                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 714                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 715                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 716                                 vce_clk_table.num_valid_entries++;
 717                         }
 718                 }
 719
 720                 return copy_to_user(out, &vce_clk_table,
 721                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 722         }
 723         case AMDGPU_INFO_VBIOS: {
 724                 uint32_t bios_size = adev->bios_size;
 725
 726                 switch (info->vbios_info.type) {
 727                 case AMDGPU_INFO_VBIOS_SIZE:
 728                         return copy_to_user(out, &bios_size,
 729                                         min((size_t)size, sizeof(bios_size)))
 730                                         ? -EFAULT : 0;
 731                 case AMDGPU_INFO_VBIOS_IMAGE: {
 732                         uint8_t *bios;
 733                         uint32_t bios_offset = info->vbios_info.offset;
 734
 735                         if (bios_offset >= bios_size)
 736                                 return -EINVAL;
 737
 738                         bios = adev->bios + bios_offset;
 739                         return copy_to_user(out, bios,
 740                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 741                                         ? -EFAULT : 0;
 742                 }
 743                 default:
 744                         DRM_DEBUG_KMS("Invalid request %d\n",
 745                                         info->vbios_info.type);
 746                         return -EINVAL;
 747                 }
 748         }
 749         case AMDGPU_INFO_NUM_HANDLES: {
 750                 struct drm_amdgpu_info_num_handles handle;
 751
 752                 switch (info->query_hw_ip.type) {
 753                 case AMDGPU_HW_IP_UVD:
 754                         /* Starting Polaris, we support unlimited UVD handles */
 755                         if (adev->asic_type < CHIP_POLARIS10) {
 756                                 handle.uvd_max_handles = adev->uvd.max_handles;
 757                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 758
 759                                 return copy_to_user(out, &handle,
 760                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 761                         } else {
 762                                 return -ENODATA;
 763                         }
 764
 765                         break;
 766                 default:
 767                         return -EINVAL;
 768                 }
 769         }
 770         case AMDGPU_INFO_SENSOR: {
 771                 if (!adev->pm.dpm_enabled)
 772                         return -ENOENT;
 773
 774                 switch (info->sensor_info.type) {
 775                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 776                         /* get sclk in Mhz */
 777                         if (amdgpu_dpm_read_sensor(adev,
 778                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 779                                                    (void *)&ui32, &ui32_size)) {
 780                                 return -EINVAL;
 781                         }
 782                         ui32 /= 100;
 783                         break;
 784                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 785                         /* get mclk in Mhz */
 786                         if (amdgpu_dpm_read_sensor(adev,
 787                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 788                                                    (void *)&ui32, &ui32_size)) {
 789                                 return -EINVAL;
 790                         }
 791                         ui32 /= 100;
 792                         break;
 793                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 794                         /* get temperature in millidegrees C */
 795                         if (amdgpu_dpm_read_sensor(adev,
 796                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 797                                                    (void *)&ui32, &ui32_size)) {
 798                                 return -EINVAL;
 799                         }
 800                         break;
 801                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 802                         /* get GPU load */
 803                         if (amdgpu_dpm_read_sensor(adev,
 804                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 805                                                    (void *)&ui32, &ui32_size)) {
 806                                 return -EINVAL;
 807                         }
 808                         break;
 809                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 810                         /* get average GPU power */
 811                         if (amdgpu_dpm_read_sensor(adev,
 812                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 813                                                    (void *)&ui32, &ui32_size)) {
 814                                 return -EINVAL;
 815                         }
 816                         ui32 >>= 8;
 817                         break;
 818                 case AMDGPU_INFO_SENSOR_VDDNB:
 819                         /* get VDDNB in millivolts */
 820                         if (amdgpu_dpm_read_sensor(adev,
 821                                                    AMDGPU_PP_SENSOR_VDDNB,
 822                                                    (void *)&ui32, &ui32_size)) {
 823                                 return -EINVAL;
 824                         }
 825                         break;
 826                 case AMDGPU_INFO_SENSOR_VDDGFX:
 827                         /* get VDDGFX in millivolts */
 828                         if (amdgpu_dpm_read_sensor(adev,
 829                                                    AMDGPU_PP_SENSOR_VDDGFX,
 830                                                    (void *)&ui32, &ui32_size)) {
 831                                 return -EINVAL;
 832                         }
 833                         break;
 834                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 835                         /* get stable pstate sclk in Mhz */
 836                         if (amdgpu_dpm_read_sensor(adev,
 837                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 838                                                    (void *)&ui32, &ui32_size)) {
 839                                 return -EINVAL;
 840                         }
 841                         ui32 /= 100;
 842                         break;
 843                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 844                         /* get stable pstate mclk in Mhz */
 845                         if (amdgpu_dpm_read_sensor(adev,
 846                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 847                                                    (void *)&ui32, &ui32_size)) {
 848                                 return -EINVAL;
 849                         }
 850                         ui32 /= 100;
 851                         break;
 852                 default:
 853                         DRM_DEBUG_KMS("Invalid request %d\n",
 854                                       info->sensor_info.type);
 855                         return -EINVAL;
 856                 }
 857                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 858         }
 859         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 860                 ui32 = atomic_read(&adev->vram_lost_counter);
 861                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 862         default:
 863                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 864                 return -EINVAL;
 865         }
 866         return 0;
 867 }
 868
 869
 870 /*
 871  * Outdated mess for old drm with Xorg being in charge (void function now).
 872  */
 873 /**
 874  * amdgpu_driver_lastclose_kms - drm callback for last close
 875  *
 876  * @dev: drm dev pointer
 877  *
 878  * Switch vga_switcheroo state after last close (all asics).
 879  */
 880 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 881 {
 882         drm_fb_helper_lastclose(dev);
 883         vga_switcheroo_process_delayed_switch();
 884 }
 885
 886 /**
 887  * amdgpu_driver_open_kms - drm callback for open
 888  *
 889  * @dev: drm dev pointer
 890  * @file_priv: drm file
 891  *
 892  * On device open, init vm on cayman+ (all asics).
 893  * Returns 0 on success, error on failure.
 894  */
 895 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 896 {
 897         struct amdgpu_device *adev = dev->dev_private;
 898         struct amdgpu_fpriv *fpriv;
 899         int r, pasid;
 900
 901         file_priv->driver_priv = NULL;
 902
 903         r = pm_runtime_get_sync(dev->dev);
 904         if (r < 0)
 905                 return r;
 906
 907         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 908         if (unlikely(!fpriv)) {
 909                 r = -ENOMEM;
 910                 goto out_suspend;
 911         }
 912
 913         pasid = amdgpu_pasid_alloc(16);
 914         if (pasid < 0) {
 915                 dev_warn(adev->dev, "No more PASIDs available!");
 916                 pasid = 0;
 917         }
 918         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
 919         if (r)
 920                 goto error_pasid;
 921
 922         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
 923         if (!fpriv->prt_va) {
 924                 r = -ENOMEM;
 925                 goto error_vm;
 926         }
 927
 928         if (amdgpu_sriov_vf(adev)) {
 929                 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
 930                 if (r)
 931                         goto error_vm;
 932         }
 933
 934         mutex_init(&fpriv->bo_list_lock);
 935         idr_init(&fpriv->bo_list_handles);
 936
 937         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
 938
 939         file_priv->driver_priv = fpriv;
 940         goto out_suspend;
 941
 942 error_vm:
 943         amdgpu_vm_fini(adev, &fpriv->vm);
 944
 945 error_pasid:
 946         if (pasid)
 947                 amdgpu_pasid_free(pasid);
 948
 949         kfree(fpriv);
 950
 951 out_suspend:
 952         pm_runtime_mark_last_busy(dev->dev);
 953         pm_runtime_put_autosuspend(dev->dev);
 954
 955         return r;
 956 }
 957
 958 /**
 959  * amdgpu_driver_postclose_kms - drm callback for post close
 960  *
 961  * @dev: drm dev pointer
 962  * @file_priv: drm file
 963  *
 964  * On device post close, tear down vm on cayman+ (all asics).
 965  */
 966 void amdgpu_driver_postclose_kms(struct drm_device *dev,
 967                                  struct drm_file *file_priv)
 968 {
 969         struct amdgpu_device *adev = dev->dev_private;
 970         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 971         struct amdgpu_bo_list *list;
 972         struct amdgpu_bo *pd;
 973         unsigned int pasid;
 974         int handle;
 975
 976         if (!fpriv)
 977                 return;
 978
 979         pm_runtime_get_sync(dev->dev);
 980
 981         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
 982                 amdgpu_uvd_free_handles(adev, file_priv);
 983         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
 984                 amdgpu_vce_free_handles(adev, file_priv);
 985
 986         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
 987
 988         if (amdgpu_sriov_vf(adev)) {
 989                 /* TODO: how to handle reserve failure */
 990                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
 991                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
 992                 fpriv->csa_va = NULL;
 993                 amdgpu_bo_unreserve(adev->virt.csa_obj);
 994         }
 995
 996         pasid = fpriv->vm.pasid;
 997         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
 998
 999         amdgpu_vm_fini(adev, &fpriv->vm);
1000         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1001
1002         if (pasid)
1003                 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
1004         amdgpu_bo_unref(&pd);
1005
1006         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1007                 amdgpu_bo_list_put(list);
1008
1009         idr_destroy(&fpriv->bo_list_handles);
1010         mutex_destroy(&fpriv->bo_list_lock);
1011
1012         kfree(fpriv);
1013         file_priv->driver_priv = NULL;
1014
1015         pm_runtime_mark_last_busy(dev->dev);
1016         pm_runtime_put_autosuspend(dev->dev);
1017 }
1018
1019 /*
1020  * VBlank related functions.
1021  */
1022 /**
1023  * amdgpu_get_vblank_counter_kms - get frame count
1024  *
1025  * @dev: drm dev pointer
1026  * @pipe: crtc to get the frame count from
1027  *
1028  * Gets the frame count on the requested crtc (all asics).
1029  * Returns frame count on success, -EINVAL on failure.
1030  */
1031 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
1032 {
1033         struct amdgpu_device *adev = dev->dev_private;
1034         int vpos, hpos, stat;
1035         u32 count;
1036
1037         if (pipe >= adev->mode_info.num_crtc) {
1038                 DRM_ERROR("Invalid crtc %u\n", pipe);
1039                 return -EINVAL;
1040         }
1041
1042         /* The hw increments its frame counter at start of vsync, not at start
1043          * of vblank, as is required by DRM core vblank counter handling.
1044          * Cook the hw count here to make it appear to the caller as if it
1045          * incremented at start of vblank. We measure distance to start of
1046          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1047          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1048          * result by 1 to give the proper appearance to caller.
1049          */
1050         if (adev->mode_info.crtcs[pipe]) {
1051                 /* Repeat readout if needed to provide stable result if
1052                  * we cross start of vsync during the queries.
1053                  */
1054                 do {
1055                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1056                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1057                          * vpos as distance to start of vblank, instead of
1058                          * regular vertical scanout pos.
1059                          */
1060                         stat = amdgpu_display_get_crtc_scanoutpos(
1061                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1062                                 &vpos, &hpos, NULL, NULL,
1063                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1064                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1065
1066                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1067                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1068                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1069                 } else {
1070                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1071                                       pipe, vpos);
1072
1073                         /* Bump counter if we are at >= leading edge of vblank,
1074                          * but before vsync where vpos would turn negative and
1075                          * the hw counter really increments.
1076                          */
1077                         if (vpos >= 0)
1078                                 count++;
1079                 }
1080         } else {
1081                 /* Fallback to use value as is. */
1082                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1083                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1084         }
1085
1086         return count;
1087 }
1088
1089 /**
1090  * amdgpu_enable_vblank_kms - enable vblank interrupt
1091  *
1092  * @dev: drm dev pointer
1093  * @pipe: crtc to enable vblank interrupt for
1094  *
1095  * Enable the interrupt on the requested crtc (all asics).
1096  * Returns 0 on success, -EINVAL on failure.
1097  */
1098 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1099 {
1100         struct amdgpu_device *adev = dev->dev_private;
1101         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1102
1103         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1104 }
1105
1106 /**
1107  * amdgpu_disable_vblank_kms - disable vblank interrupt
1108  *
1109  * @dev: drm dev pointer
1110  * @pipe: crtc to disable vblank interrupt for
1111  *
1112  * Disable the interrupt on the requested crtc (all asics).
1113  */
1114 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1115 {
1116         struct amdgpu_device *adev = dev->dev_private;
1117         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1118
1119         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1120 }
1121
1122 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1123         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1124         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1125         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1126         DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1127         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1128         DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1129         /* KMS */
1130         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1131         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1132         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1133         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1134         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1135         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1136         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1137         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1138         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1139         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1140 };
1141 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1142
1143 /*
1144  * Debugfs info
1145  */
1146 #if defined(CONFIG_DEBUG_FS)
1147
1148 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1149 {
1150         struct drm_info_node *node = (struct drm_info_node *) m->private;
1151         struct drm_device *dev = node->minor->dev;
1152         struct amdgpu_device *adev = dev->dev_private;
1153         struct drm_amdgpu_info_firmware fw_info;
1154         struct drm_amdgpu_query_fw query_fw;
1155         struct atom_context *ctx = adev->mode_info.atom_context;
1156         int ret, i;
1157
1158         /* VCE */
1159         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1160         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1161         if (ret)
1162                 return ret;
1163         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1164                    fw_info.feature, fw_info.ver);
1165
1166         /* UVD */
1167         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1168         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1169         if (ret)
1170                 return ret;
1171         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1172                    fw_info.feature, fw_info.ver);
1173
1174         /* GMC */
1175         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1176         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1177         if (ret)
1178                 return ret;
1179         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1180                    fw_info.feature, fw_info.ver);
1181
1182         /* ME */
1183         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1184         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1185         if (ret)
1186                 return ret;
1187         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1188                    fw_info.feature, fw_info.ver);
1189
1190         /* PFP */
1191         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1192         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1193         if (ret)
1194                 return ret;
1195         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1196                    fw_info.feature, fw_info.ver);
1197
1198         /* CE */
1199         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1200         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1201         if (ret)
1202                 return ret;
1203         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1204                    fw_info.feature, fw_info.ver);
1205
1206         /* RLC */
1207         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1208         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1209         if (ret)
1210                 return ret;
1211         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1212                    fw_info.feature, fw_info.ver);
1213
1214         /* RLC SAVE RESTORE LIST CNTL */
1215         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1216         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1217         if (ret)
1218                 return ret;
1219         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1220                    fw_info.feature, fw_info.ver);
1221
1222         /* RLC SAVE RESTORE LIST GPM MEM */
1223         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1224         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1225         if (ret)
1226                 return ret;
1227         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1228                    fw_info.feature, fw_info.ver);
1229
1230         /* RLC SAVE RESTORE LIST SRM MEM */
1231         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1232         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1233         if (ret)
1234                 return ret;
1235         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1236                    fw_info.feature, fw_info.ver);
1237
1238         /* MEC */
1239         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1240         query_fw.index = 0;
1241         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1242         if (ret)
1243                 return ret;
1244         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1245                    fw_info.feature, fw_info.ver);
1246
1247         /* MEC2 */
1248         if (adev->asic_type == CHIP_KAVERI ||
1249             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1250                 query_fw.index = 1;
1251                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1252                 if (ret)
1253                         return ret;
1254                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1255                            fw_info.feature, fw_info.ver);
1256         }
1257
1258         /* PSP SOS */
1259         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1260         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1261         if (ret)
1262                 return ret;
1263         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1264                    fw_info.feature, fw_info.ver);
1265
1266
1267         /* PSP ASD */
1268         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1269         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1270         if (ret)
1271                 return ret;
1272         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1273                    fw_info.feature, fw_info.ver);
1274
1275         /* SMC */
1276         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1277         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1278         if (ret)
1279                 return ret;
1280         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1281                    fw_info.feature, fw_info.ver);
1282
1283         /* SDMA */
1284         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1285         for (i = 0; i < adev->sdma.num_instances; i++) {
1286                 query_fw.index = i;
1287                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1288                 if (ret)
1289                         return ret;
1290                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1291                            i, fw_info.feature, fw_info.ver);
1292         }
1293
1294         /* VCN */
1295         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1296         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1297         if (ret)
1298                 return ret;
1299         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1300                    fw_info.feature, fw_info.ver);
1301
1302         /* DMCU */
1303         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1304         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1305         if (ret)
1306                 return ret;
1307         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1308                    fw_info.feature, fw_info.ver);
1309
1310
1311         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1312
1313         return 0;
1314 }
1315
1316 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1317         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1318 };
1319 #endif
1320
1321 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1322 {
1323 #if defined(CONFIG_DEBUG_FS)
1324         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1325                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1326 #else
1327         return 0;
1328 #endif
1329 }