drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_ih.h"
  27 #include "amdgpu_gfx.h"
  28 #include "cikd.h"
  29 #include "cik.h"
  30 #include "atom.h"
  31 #include "amdgpu_ucode.h"
  32 #include "clearstate_ci.h"
  33
  34 #include "uvd/uvd_4_2_d.h"
  35
  36 #include "dce/dce_8_0_d.h"
  37 #include "dce/dce_8_0_sh_mask.h"
  38
  39 #include "bif/bif_4_1_d.h"
  40 #include "bif/bif_4_1_sh_mask.h"
  41
  42 #include "gca/gfx_7_0_d.h"
  43 #include "gca/gfx_7_2_enum.h"
  44 #include "gca/gfx_7_2_sh_mask.h"
  45
  46 #include "gmc/gmc_7_0_d.h"
  47 #include "gmc/gmc_7_0_sh_mask.h"
  48
  49 #include "oss/oss_2_0_d.h"
  50 #include "oss/oss_2_0_sh_mask.h"
  51
  52 #define GFX7_NUM_GFX_RINGS     1
  53 #define GFX7_NUM_COMPUTE_RINGS 8
  54
  55 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  56 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  57 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
  58 int gfx_v7_0_get_cu_info(struct amdgpu_device *, struct amdgpu_cu_info *);
  59
  60 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
  61 MODULE_FIRMWARE("radeon/bonaire_me.bin");
  62 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
  63 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
  64 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
  65
  66 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
  67 MODULE_FIRMWARE("radeon/hawaii_me.bin");
  68 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
  69 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
  70 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
  71
  72 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
  73 MODULE_FIRMWARE("radeon/kaveri_me.bin");
  74 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
  75 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
  76 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
  77 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
  78
  79 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
  80 MODULE_FIRMWARE("radeon/kabini_me.bin");
  81 MODULE_FIRMWARE("radeon/kabini_ce.bin");
  82 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
  83 MODULE_FIRMWARE("radeon/kabini_mec.bin");
  84
  85 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
  86 MODULE_FIRMWARE("radeon/mullins_me.bin");
  87 MODULE_FIRMWARE("radeon/mullins_ce.bin");
  88 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
  89 MODULE_FIRMWARE("radeon/mullins_mec.bin");
  90
  91 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  92 {
  93         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  94         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  95         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  96         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  97         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
  98         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
  99         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
 100         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 101         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 102         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 103         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 104         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 105         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 106         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 107         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 108         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 109 };
 110
 111 static const u32 spectre_rlc_save_restore_register_list[] =
 112 {
 113         (0x0e00 << 16) | (0xc12c >> 2),
 114         0x00000000,
 115         (0x0e00 << 16) | (0xc140 >> 2),
 116         0x00000000,
 117         (0x0e00 << 16) | (0xc150 >> 2),
 118         0x00000000,
 119         (0x0e00 << 16) | (0xc15c >> 2),
 120         0x00000000,
 121         (0x0e00 << 16) | (0xc168 >> 2),
 122         0x00000000,
 123         (0x0e00 << 16) | (0xc170 >> 2),
 124         0x00000000,
 125         (0x0e00 << 16) | (0xc178 >> 2),
 126         0x00000000,
 127         (0x0e00 << 16) | (0xc204 >> 2),
 128         0x00000000,
 129         (0x0e00 << 16) | (0xc2b4 >> 2),
 130         0x00000000,
 131         (0x0e00 << 16) | (0xc2b8 >> 2),
 132         0x00000000,
 133         (0x0e00 << 16) | (0xc2bc >> 2),
 134         0x00000000,
 135         (0x0e00 << 16) | (0xc2c0 >> 2),
 136         0x00000000,
 137         (0x0e00 << 16) | (0x8228 >> 2),
 138         0x00000000,
 139         (0x0e00 << 16) | (0x829c >> 2),
 140         0x00000000,
 141         (0x0e00 << 16) | (0x869c >> 2),
 142         0x00000000,
 143         (0x0600 << 16) | (0x98f4 >> 2),
 144         0x00000000,
 145         (0x0e00 << 16) | (0x98f8 >> 2),
 146         0x00000000,
 147         (0x0e00 << 16) | (0x9900 >> 2),
 148         0x00000000,
 149         (0x0e00 << 16) | (0xc260 >> 2),
 150         0x00000000,
 151         (0x0e00 << 16) | (0x90e8 >> 2),
 152         0x00000000,
 153         (0x0e00 << 16) | (0x3c000 >> 2),
 154         0x00000000,
 155         (0x0e00 << 16) | (0x3c00c >> 2),
 156         0x00000000,
 157         (0x0e00 << 16) | (0x8c1c >> 2),
 158         0x00000000,
 159         (0x0e00 << 16) | (0x9700 >> 2),
 160         0x00000000,
 161         (0x0e00 << 16) | (0xcd20 >> 2),
 162         0x00000000,
 163         (0x4e00 << 16) | (0xcd20 >> 2),
 164         0x00000000,
 165         (0x5e00 << 16) | (0xcd20 >> 2),
 166         0x00000000,
 167         (0x6e00 << 16) | (0xcd20 >> 2),
 168         0x00000000,
 169         (0x7e00 << 16) | (0xcd20 >> 2),
 170         0x00000000,
 171         (0x8e00 << 16) | (0xcd20 >> 2),
 172         0x00000000,
 173         (0x9e00 << 16) | (0xcd20 >> 2),
 174         0x00000000,
 175         (0xae00 << 16) | (0xcd20 >> 2),
 176         0x00000000,
 177         (0xbe00 << 16) | (0xcd20 >> 2),
 178         0x00000000,
 179         (0x0e00 << 16) | (0x89bc >> 2),
 180         0x00000000,
 181         (0x0e00 << 16) | (0x8900 >> 2),
 182         0x00000000,
 183         0x3,
 184         (0x0e00 << 16) | (0xc130 >> 2),
 185         0x00000000,
 186         (0x0e00 << 16) | (0xc134 >> 2),
 187         0x00000000,
 188         (0x0e00 << 16) | (0xc1fc >> 2),
 189         0x00000000,
 190         (0x0e00 << 16) | (0xc208 >> 2),
 191         0x00000000,
 192         (0x0e00 << 16) | (0xc264 >> 2),
 193         0x00000000,
 194         (0x0e00 << 16) | (0xc268 >> 2),
 195         0x00000000,
 196         (0x0e00 << 16) | (0xc26c >> 2),
 197         0x00000000,
 198         (0x0e00 << 16) | (0xc270 >> 2),
 199         0x00000000,
 200         (0x0e00 << 16) | (0xc274 >> 2),
 201         0x00000000,
 202         (0x0e00 << 16) | (0xc278 >> 2),
 203         0x00000000,
 204         (0x0e00 << 16) | (0xc27c >> 2),
 205         0x00000000,
 206         (0x0e00 << 16) | (0xc280 >> 2),
 207         0x00000000,
 208         (0x0e00 << 16) | (0xc284 >> 2),
 209         0x00000000,
 210         (0x0e00 << 16) | (0xc288 >> 2),
 211         0x00000000,
 212         (0x0e00 << 16) | (0xc28c >> 2),
 213         0x00000000,
 214         (0x0e00 << 16) | (0xc290 >> 2),
 215         0x00000000,
 216         (0x0e00 << 16) | (0xc294 >> 2),
 217         0x00000000,
 218         (0x0e00 << 16) | (0xc298 >> 2),
 219         0x00000000,
 220         (0x0e00 << 16) | (0xc29c >> 2),
 221         0x00000000,
 222         (0x0e00 << 16) | (0xc2a0 >> 2),
 223         0x00000000,
 224         (0x0e00 << 16) | (0xc2a4 >> 2),
 225         0x00000000,
 226         (0x0e00 << 16) | (0xc2a8 >> 2),
 227         0x00000000,
 228         (0x0e00 << 16) | (0xc2ac  >> 2),
 229         0x00000000,
 230         (0x0e00 << 16) | (0xc2b0 >> 2),
 231         0x00000000,
 232         (0x0e00 << 16) | (0x301d0 >> 2),
 233         0x00000000,
 234         (0x0e00 << 16) | (0x30238 >> 2),
 235         0x00000000,
 236         (0x0e00 << 16) | (0x30250 >> 2),
 237         0x00000000,
 238         (0x0e00 << 16) | (0x30254 >> 2),
 239         0x00000000,
 240         (0x0e00 << 16) | (0x30258 >> 2),
 241         0x00000000,
 242         (0x0e00 << 16) | (0x3025c >> 2),
 243         0x00000000,
 244         (0x4e00 << 16) | (0xc900 >> 2),
 245         0x00000000,
 246         (0x5e00 << 16) | (0xc900 >> 2),
 247         0x00000000,
 248         (0x6e00 << 16) | (0xc900 >> 2),
 249         0x00000000,
 250         (0x7e00 << 16) | (0xc900 >> 2),
 251         0x00000000,
 252         (0x8e00 << 16) | (0xc900 >> 2),
 253         0x00000000,
 254         (0x9e00 << 16) | (0xc900 >> 2),
 255         0x00000000,
 256         (0xae00 << 16) | (0xc900 >> 2),
 257         0x00000000,
 258         (0xbe00 << 16) | (0xc900 >> 2),
 259         0x00000000,
 260         (0x4e00 << 16) | (0xc904 >> 2),
 261         0x00000000,
 262         (0x5e00 << 16) | (0xc904 >> 2),
 263         0x00000000,
 264         (0x6e00 << 16) | (0xc904 >> 2),
 265         0x00000000,
 266         (0x7e00 << 16) | (0xc904 >> 2),
 267         0x00000000,
 268         (0x8e00 << 16) | (0xc904 >> 2),
 269         0x00000000,
 270         (0x9e00 << 16) | (0xc904 >> 2),
 271         0x00000000,
 272         (0xae00 << 16) | (0xc904 >> 2),
 273         0x00000000,
 274         (0xbe00 << 16) | (0xc904 >> 2),
 275         0x00000000,
 276         (0x4e00 << 16) | (0xc908 >> 2),
 277         0x00000000,
 278         (0x5e00 << 16) | (0xc908 >> 2),
 279         0x00000000,
 280         (0x6e00 << 16) | (0xc908 >> 2),
 281         0x00000000,
 282         (0x7e00 << 16) | (0xc908 >> 2),
 283         0x00000000,
 284         (0x8e00 << 16) | (0xc908 >> 2),
 285         0x00000000,
 286         (0x9e00 << 16) | (0xc908 >> 2),
 287         0x00000000,
 288         (0xae00 << 16) | (0xc908 >> 2),
 289         0x00000000,
 290         (0xbe00 << 16) | (0xc908 >> 2),
 291         0x00000000,
 292         (0x4e00 << 16) | (0xc90c >> 2),
 293         0x00000000,
 294         (0x5e00 << 16) | (0xc90c >> 2),
 295         0x00000000,
 296         (0x6e00 << 16) | (0xc90c >> 2),
 297         0x00000000,
 298         (0x7e00 << 16) | (0xc90c >> 2),
 299         0x00000000,
 300         (0x8e00 << 16) | (0xc90c >> 2),
 301         0x00000000,
 302         (0x9e00 << 16) | (0xc90c >> 2),
 303         0x00000000,
 304         (0xae00 << 16) | (0xc90c >> 2),
 305         0x00000000,
 306         (0xbe00 << 16) | (0xc90c >> 2),
 307         0x00000000,
 308         (0x4e00 << 16) | (0xc910 >> 2),
 309         0x00000000,
 310         (0x5e00 << 16) | (0xc910 >> 2),
 311         0x00000000,
 312         (0x6e00 << 16) | (0xc910 >> 2),
 313         0x00000000,
 314         (0x7e00 << 16) | (0xc910 >> 2),
 315         0x00000000,
 316         (0x8e00 << 16) | (0xc910 >> 2),
 317         0x00000000,
 318         (0x9e00 << 16) | (0xc910 >> 2),
 319         0x00000000,
 320         (0xae00 << 16) | (0xc910 >> 2),
 321         0x00000000,
 322         (0xbe00 << 16) | (0xc910 >> 2),
 323         0x00000000,
 324         (0x0e00 << 16) | (0xc99c >> 2),
 325         0x00000000,
 326         (0x0e00 << 16) | (0x9834 >> 2),
 327         0x00000000,
 328         (0x0000 << 16) | (0x30f00 >> 2),
 329         0x00000000,
 330         (0x0001 << 16) | (0x30f00 >> 2),
 331         0x00000000,
 332         (0x0000 << 16) | (0x30f04 >> 2),
 333         0x00000000,
 334         (0x0001 << 16) | (0x30f04 >> 2),
 335         0x00000000,
 336         (0x0000 << 16) | (0x30f08 >> 2),
 337         0x00000000,
 338         (0x0001 << 16) | (0x30f08 >> 2),
 339         0x00000000,
 340         (0x0000 << 16) | (0x30f0c >> 2),
 341         0x00000000,
 342         (0x0001 << 16) | (0x30f0c >> 2),
 343         0x00000000,
 344         (0x0600 << 16) | (0x9b7c >> 2),
 345         0x00000000,
 346         (0x0e00 << 16) | (0x8a14 >> 2),
 347         0x00000000,
 348         (0x0e00 << 16) | (0x8a18 >> 2),
 349         0x00000000,
 350         (0x0600 << 16) | (0x30a00 >> 2),
 351         0x00000000,
 352         (0x0e00 << 16) | (0x8bf0 >> 2),
 353         0x00000000,
 354         (0x0e00 << 16) | (0x8bcc >> 2),
 355         0x00000000,
 356         (0x0e00 << 16) | (0x8b24 >> 2),
 357         0x00000000,
 358         (0x0e00 << 16) | (0x30a04 >> 2),
 359         0x00000000,
 360         (0x0600 << 16) | (0x30a10 >> 2),
 361         0x00000000,
 362         (0x0600 << 16) | (0x30a14 >> 2),
 363         0x00000000,
 364         (0x0600 << 16) | (0x30a18 >> 2),
 365         0x00000000,
 366         (0x0600 << 16) | (0x30a2c >> 2),
 367         0x00000000,
 368         (0x0e00 << 16) | (0xc700 >> 2),
 369         0x00000000,
 370         (0x0e00 << 16) | (0xc704 >> 2),
 371         0x00000000,
 372         (0x0e00 << 16) | (0xc708 >> 2),
 373         0x00000000,
 374         (0x0e00 << 16) | (0xc768 >> 2),
 375         0x00000000,
 376         (0x0400 << 16) | (0xc770 >> 2),
 377         0x00000000,
 378         (0x0400 << 16) | (0xc774 >> 2),
 379         0x00000000,
 380         (0x0400 << 16) | (0xc778 >> 2),
 381         0x00000000,
 382         (0x0400 << 16) | (0xc77c >> 2),
 383         0x00000000,
 384         (0x0400 << 16) | (0xc780 >> 2),
 385         0x00000000,
 386         (0x0400 << 16) | (0xc784 >> 2),
 387         0x00000000,
 388         (0x0400 << 16) | (0xc788 >> 2),
 389         0x00000000,
 390         (0x0400 << 16) | (0xc78c >> 2),
 391         0x00000000,
 392         (0x0400 << 16) | (0xc798 >> 2),
 393         0x00000000,
 394         (0x0400 << 16) | (0xc79c >> 2),
 395         0x00000000,
 396         (0x0400 << 16) | (0xc7a0 >> 2),
 397         0x00000000,
 398         (0x0400 << 16) | (0xc7a4 >> 2),
 399         0x00000000,
 400         (0x0400 << 16) | (0xc7a8 >> 2),
 401         0x00000000,
 402         (0x0400 << 16) | (0xc7ac >> 2),
 403         0x00000000,
 404         (0x0400 << 16) | (0xc7b0 >> 2),
 405         0x00000000,
 406         (0x0400 << 16) | (0xc7b4 >> 2),
 407         0x00000000,
 408         (0x0e00 << 16) | (0x9100 >> 2),
 409         0x00000000,
 410         (0x0e00 << 16) | (0x3c010 >> 2),
 411         0x00000000,
 412         (0x0e00 << 16) | (0x92a8 >> 2),
 413         0x00000000,
 414         (0x0e00 << 16) | (0x92ac >> 2),
 415         0x00000000,
 416         (0x0e00 << 16) | (0x92b4 >> 2),
 417         0x00000000,
 418         (0x0e00 << 16) | (0x92b8 >> 2),
 419         0x00000000,
 420         (0x0e00 << 16) | (0x92bc >> 2),
 421         0x00000000,
 422         (0x0e00 << 16) | (0x92c0 >> 2),
 423         0x00000000,
 424         (0x0e00 << 16) | (0x92c4 >> 2),
 425         0x00000000,
 426         (0x0e00 << 16) | (0x92c8 >> 2),
 427         0x00000000,
 428         (0x0e00 << 16) | (0x92cc >> 2),
 429         0x00000000,
 430         (0x0e00 << 16) | (0x92d0 >> 2),
 431         0x00000000,
 432         (0x0e00 << 16) | (0x8c00 >> 2),
 433         0x00000000,
 434         (0x0e00 << 16) | (0x8c04 >> 2),
 435         0x00000000,
 436         (0x0e00 << 16) | (0x8c20 >> 2),
 437         0x00000000,
 438         (0x0e00 << 16) | (0x8c38 >> 2),
 439         0x00000000,
 440         (0x0e00 << 16) | (0x8c3c >> 2),
 441         0x00000000,
 442         (0x0e00 << 16) | (0xae00 >> 2),
 443         0x00000000,
 444         (0x0e00 << 16) | (0x9604 >> 2),
 445         0x00000000,
 446         (0x0e00 << 16) | (0xac08 >> 2),
 447         0x00000000,
 448         (0x0e00 << 16) | (0xac0c >> 2),
 449         0x00000000,
 450         (0x0e00 << 16) | (0xac10 >> 2),
 451         0x00000000,
 452         (0x0e00 << 16) | (0xac14 >> 2),
 453         0x00000000,
 454         (0x0e00 << 16) | (0xac58 >> 2),
 455         0x00000000,
 456         (0x0e00 << 16) | (0xac68 >> 2),
 457         0x00000000,
 458         (0x0e00 << 16) | (0xac6c >> 2),
 459         0x00000000,
 460         (0x0e00 << 16) | (0xac70 >> 2),
 461         0x00000000,
 462         (0x0e00 << 16) | (0xac74 >> 2),
 463         0x00000000,
 464         (0x0e00 << 16) | (0xac78 >> 2),
 465         0x00000000,
 466         (0x0e00 << 16) | (0xac7c >> 2),
 467         0x00000000,
 468         (0x0e00 << 16) | (0xac80 >> 2),
 469         0x00000000,
 470         (0x0e00 << 16) | (0xac84 >> 2),
 471         0x00000000,
 472         (0x0e00 << 16) | (0xac88 >> 2),
 473         0x00000000,
 474         (0x0e00 << 16) | (0xac8c >> 2),
 475         0x00000000,
 476         (0x0e00 << 16) | (0x970c >> 2),
 477         0x00000000,
 478         (0x0e00 << 16) | (0x9714 >> 2),
 479         0x00000000,
 480         (0x0e00 << 16) | (0x9718 >> 2),
 481         0x00000000,
 482         (0x0e00 << 16) | (0x971c >> 2),
 483         0x00000000,
 484         (0x0e00 << 16) | (0x31068 >> 2),
 485         0x00000000,
 486         (0x4e00 << 16) | (0x31068 >> 2),
 487         0x00000000,
 488         (0x5e00 << 16) | (0x31068 >> 2),
 489         0x00000000,
 490         (0x6e00 << 16) | (0x31068 >> 2),
 491         0x00000000,
 492         (0x7e00 << 16) | (0x31068 >> 2),
 493         0x00000000,
 494         (0x8e00 << 16) | (0x31068 >> 2),
 495         0x00000000,
 496         (0x9e00 << 16) | (0x31068 >> 2),
 497         0x00000000,
 498         (0xae00 << 16) | (0x31068 >> 2),
 499         0x00000000,
 500         (0xbe00 << 16) | (0x31068 >> 2),
 501         0x00000000,
 502         (0x0e00 << 16) | (0xcd10 >> 2),
 503         0x00000000,
 504         (0x0e00 << 16) | (0xcd14 >> 2),
 505         0x00000000,
 506         (0x0e00 << 16) | (0x88b0 >> 2),
 507         0x00000000,
 508         (0x0e00 << 16) | (0x88b4 >> 2),
 509         0x00000000,
 510         (0x0e00 << 16) | (0x88b8 >> 2),
 511         0x00000000,
 512         (0x0e00 << 16) | (0x88bc >> 2),
 513         0x00000000,
 514         (0x0400 << 16) | (0x89c0 >> 2),
 515         0x00000000,
 516         (0x0e00 << 16) | (0x88c4 >> 2),
 517         0x00000000,
 518         (0x0e00 << 16) | (0x88c8 >> 2),
 519         0x00000000,
 520         (0x0e00 << 16) | (0x88d0 >> 2),
 521         0x00000000,
 522         (0x0e00 << 16) | (0x88d4 >> 2),
 523         0x00000000,
 524         (0x0e00 << 16) | (0x88d8 >> 2),
 525         0x00000000,
 526         (0x0e00 << 16) | (0x8980 >> 2),
 527         0x00000000,
 528         (0x0e00 << 16) | (0x30938 >> 2),
 529         0x00000000,
 530         (0x0e00 << 16) | (0x3093c >> 2),
 531         0x00000000,
 532         (0x0e00 << 16) | (0x30940 >> 2),
 533         0x00000000,
 534         (0x0e00 << 16) | (0x89a0 >> 2),
 535         0x00000000,
 536         (0x0e00 << 16) | (0x30900 >> 2),
 537         0x00000000,
 538         (0x0e00 << 16) | (0x30904 >> 2),
 539         0x00000000,
 540         (0x0e00 << 16) | (0x89b4 >> 2),
 541         0x00000000,
 542         (0x0e00 << 16) | (0x3c210 >> 2),
 543         0x00000000,
 544         (0x0e00 << 16) | (0x3c214 >> 2),
 545         0x00000000,
 546         (0x0e00 << 16) | (0x3c218 >> 2),
 547         0x00000000,
 548         (0x0e00 << 16) | (0x8904 >> 2),
 549         0x00000000,
 550         0x5,
 551         (0x0e00 << 16) | (0x8c28 >> 2),
 552         (0x0e00 << 16) | (0x8c2c >> 2),
 553         (0x0e00 << 16) | (0x8c30 >> 2),
 554         (0x0e00 << 16) | (0x8c34 >> 2),
 555         (0x0e00 << 16) | (0x9600 >> 2),
 556 };
 557
 558 static const u32 kalindi_rlc_save_restore_register_list[] =
 559 {
 560         (0x0e00 << 16) | (0xc12c >> 2),
 561         0x00000000,
 562         (0x0e00 << 16) | (0xc140 >> 2),
 563         0x00000000,
 564         (0x0e00 << 16) | (0xc150 >> 2),
 565         0x00000000,
 566         (0x0e00 << 16) | (0xc15c >> 2),
 567         0x00000000,
 568         (0x0e00 << 16) | (0xc168 >> 2),
 569         0x00000000,
 570         (0x0e00 << 16) | (0xc170 >> 2),
 571         0x00000000,
 572         (0x0e00 << 16) | (0xc204 >> 2),
 573         0x00000000,
 574         (0x0e00 << 16) | (0xc2b4 >> 2),
 575         0x00000000,
 576         (0x0e00 << 16) | (0xc2b8 >> 2),
 577         0x00000000,
 578         (0x0e00 << 16) | (0xc2bc >> 2),
 579         0x00000000,
 580         (0x0e00 << 16) | (0xc2c0 >> 2),
 581         0x00000000,
 582         (0x0e00 << 16) | (0x8228 >> 2),
 583         0x00000000,
 584         (0x0e00 << 16) | (0x829c >> 2),
 585         0x00000000,
 586         (0x0e00 << 16) | (0x869c >> 2),
 587         0x00000000,
 588         (0x0600 << 16) | (0x98f4 >> 2),
 589         0x00000000,
 590         (0x0e00 << 16) | (0x98f8 >> 2),
 591         0x00000000,
 592         (0x0e00 << 16) | (0x9900 >> 2),
 593         0x00000000,
 594         (0x0e00 << 16) | (0xc260 >> 2),
 595         0x00000000,
 596         (0x0e00 << 16) | (0x90e8 >> 2),
 597         0x00000000,
 598         (0x0e00 << 16) | (0x3c000 >> 2),
 599         0x00000000,
 600         (0x0e00 << 16) | (0x3c00c >> 2),
 601         0x00000000,
 602         (0x0e00 << 16) | (0x8c1c >> 2),
 603         0x00000000,
 604         (0x0e00 << 16) | (0x9700 >> 2),
 605         0x00000000,
 606         (0x0e00 << 16) | (0xcd20 >> 2),
 607         0x00000000,
 608         (0x4e00 << 16) | (0xcd20 >> 2),
 609         0x00000000,
 610         (0x5e00 << 16) | (0xcd20 >> 2),
 611         0x00000000,
 612         (0x6e00 << 16) | (0xcd20 >> 2),
 613         0x00000000,
 614         (0x7e00 << 16) | (0xcd20 >> 2),
 615         0x00000000,
 616         (0x0e00 << 16) | (0x89bc >> 2),
 617         0x00000000,
 618         (0x0e00 << 16) | (0x8900 >> 2),
 619         0x00000000,
 620         0x3,
 621         (0x0e00 << 16) | (0xc130 >> 2),
 622         0x00000000,
 623         (0x0e00 << 16) | (0xc134 >> 2),
 624         0x00000000,
 625         (0x0e00 << 16) | (0xc1fc >> 2),
 626         0x00000000,
 627         (0x0e00 << 16) | (0xc208 >> 2),
 628         0x00000000,
 629         (0x0e00 << 16) | (0xc264 >> 2),
 630         0x00000000,
 631         (0x0e00 << 16) | (0xc268 >> 2),
 632         0x00000000,
 633         (0x0e00 << 16) | (0xc26c >> 2),
 634         0x00000000,
 635         (0x0e00 << 16) | (0xc270 >> 2),
 636         0x00000000,
 637         (0x0e00 << 16) | (0xc274 >> 2),
 638         0x00000000,
 639         (0x0e00 << 16) | (0xc28c >> 2),
 640         0x00000000,
 641         (0x0e00 << 16) | (0xc290 >> 2),
 642         0x00000000,
 643         (0x0e00 << 16) | (0xc294 >> 2),
 644         0x00000000,
 645         (0x0e00 << 16) | (0xc298 >> 2),
 646         0x00000000,
 647         (0x0e00 << 16) | (0xc2a0 >> 2),
 648         0x00000000,
 649         (0x0e00 << 16) | (0xc2a4 >> 2),
 650         0x00000000,
 651         (0x0e00 << 16) | (0xc2a8 >> 2),
 652         0x00000000,
 653         (0x0e00 << 16) | (0xc2ac >> 2),
 654         0x00000000,
 655         (0x0e00 << 16) | (0x301d0 >> 2),
 656         0x00000000,
 657         (0x0e00 << 16) | (0x30238 >> 2),
 658         0x00000000,
 659         (0x0e00 << 16) | (0x30250 >> 2),
 660         0x00000000,
 661         (0x0e00 << 16) | (0x30254 >> 2),
 662         0x00000000,
 663         (0x0e00 << 16) | (0x30258 >> 2),
 664         0x00000000,
 665         (0x0e00 << 16) | (0x3025c >> 2),
 666         0x00000000,
 667         (0x4e00 << 16) | (0xc900 >> 2),
 668         0x00000000,
 669         (0x5e00 << 16) | (0xc900 >> 2),
 670         0x00000000,
 671         (0x6e00 << 16) | (0xc900 >> 2),
 672         0x00000000,
 673         (0x7e00 << 16) | (0xc900 >> 2),
 674         0x00000000,
 675         (0x4e00 << 16) | (0xc904 >> 2),
 676         0x00000000,
 677         (0x5e00 << 16) | (0xc904 >> 2),
 678         0x00000000,
 679         (0x6e00 << 16) | (0xc904 >> 2),
 680         0x00000000,
 681         (0x7e00 << 16) | (0xc904 >> 2),
 682         0x00000000,
 683         (0x4e00 << 16) | (0xc908 >> 2),
 684         0x00000000,
 685         (0x5e00 << 16) | (0xc908 >> 2),
 686         0x00000000,
 687         (0x6e00 << 16) | (0xc908 >> 2),
 688         0x00000000,
 689         (0x7e00 << 16) | (0xc908 >> 2),
 690         0x00000000,
 691         (0x4e00 << 16) | (0xc90c >> 2),
 692         0x00000000,
 693         (0x5e00 << 16) | (0xc90c >> 2),
 694         0x00000000,
 695         (0x6e00 << 16) | (0xc90c >> 2),
 696         0x00000000,
 697         (0x7e00 << 16) | (0xc90c >> 2),
 698         0x00000000,
 699         (0x4e00 << 16) | (0xc910 >> 2),
 700         0x00000000,
 701         (0x5e00 << 16) | (0xc910 >> 2),
 702         0x00000000,
 703         (0x6e00 << 16) | (0xc910 >> 2),
 704         0x00000000,
 705         (0x7e00 << 16) | (0xc910 >> 2),
 706         0x00000000,
 707         (0x0e00 << 16) | (0xc99c >> 2),
 708         0x00000000,
 709         (0x0e00 << 16) | (0x9834 >> 2),
 710         0x00000000,
 711         (0x0000 << 16) | (0x30f00 >> 2),
 712         0x00000000,
 713         (0x0000 << 16) | (0x30f04 >> 2),
 714         0x00000000,
 715         (0x0000 << 16) | (0x30f08 >> 2),
 716         0x00000000,
 717         (0x0000 << 16) | (0x30f0c >> 2),
 718         0x00000000,
 719         (0x0600 << 16) | (0x9b7c >> 2),
 720         0x00000000,
 721         (0x0e00 << 16) | (0x8a14 >> 2),
 722         0x00000000,
 723         (0x0e00 << 16) | (0x8a18 >> 2),
 724         0x00000000,
 725         (0x0600 << 16) | (0x30a00 >> 2),
 726         0x00000000,
 727         (0x0e00 << 16) | (0x8bf0 >> 2),
 728         0x00000000,
 729         (0x0e00 << 16) | (0x8bcc >> 2),
 730         0x00000000,
 731         (0x0e00 << 16) | (0x8b24 >> 2),
 732         0x00000000,
 733         (0x0e00 << 16) | (0x30a04 >> 2),
 734         0x00000000,
 735         (0x0600 << 16) | (0x30a10 >> 2),
 736         0x00000000,
 737         (0x0600 << 16) | (0x30a14 >> 2),
 738         0x00000000,
 739         (0x0600 << 16) | (0x30a18 >> 2),
 740         0x00000000,
 741         (0x0600 << 16) | (0x30a2c >> 2),
 742         0x00000000,
 743         (0x0e00 << 16) | (0xc700 >> 2),
 744         0x00000000,
 745         (0x0e00 << 16) | (0xc704 >> 2),
 746         0x00000000,
 747         (0x0e00 << 16) | (0xc708 >> 2),
 748         0x00000000,
 749         (0x0e00 << 16) | (0xc768 >> 2),
 750         0x00000000,
 751         (0x0400 << 16) | (0xc770 >> 2),
 752         0x00000000,
 753         (0x0400 << 16) | (0xc774 >> 2),
 754         0x00000000,
 755         (0x0400 << 16) | (0xc798 >> 2),
 756         0x00000000,
 757         (0x0400 << 16) | (0xc79c >> 2),
 758         0x00000000,
 759         (0x0e00 << 16) | (0x9100 >> 2),
 760         0x00000000,
 761         (0x0e00 << 16) | (0x3c010 >> 2),
 762         0x00000000,
 763         (0x0e00 << 16) | (0x8c00 >> 2),
 764         0x00000000,
 765         (0x0e00 << 16) | (0x8c04 >> 2),
 766         0x00000000,
 767         (0x0e00 << 16) | (0x8c20 >> 2),
 768         0x00000000,
 769         (0x0e00 << 16) | (0x8c38 >> 2),
 770         0x00000000,
 771         (0x0e00 << 16) | (0x8c3c >> 2),
 772         0x00000000,
 773         (0x0e00 << 16) | (0xae00 >> 2),
 774         0x00000000,
 775         (0x0e00 << 16) | (0x9604 >> 2),
 776         0x00000000,
 777         (0x0e00 << 16) | (0xac08 >> 2),
 778         0x00000000,
 779         (0x0e00 << 16) | (0xac0c >> 2),
 780         0x00000000,
 781         (0x0e00 << 16) | (0xac10 >> 2),
 782         0x00000000,
 783         (0x0e00 << 16) | (0xac14 >> 2),
 784         0x00000000,
 785         (0x0e00 << 16) | (0xac58 >> 2),
 786         0x00000000,
 787         (0x0e00 << 16) | (0xac68 >> 2),
 788         0x00000000,
 789         (0x0e00 << 16) | (0xac6c >> 2),
 790         0x00000000,
 791         (0x0e00 << 16) | (0xac70 >> 2),
 792         0x00000000,
 793         (0x0e00 << 16) | (0xac74 >> 2),
 794         0x00000000,
 795         (0x0e00 << 16) | (0xac78 >> 2),
 796         0x00000000,
 797         (0x0e00 << 16) | (0xac7c >> 2),
 798         0x00000000,
 799         (0x0e00 << 16) | (0xac80 >> 2),
 800         0x00000000,
 801         (0x0e00 << 16) | (0xac84 >> 2),
 802         0x00000000,
 803         (0x0e00 << 16) | (0xac88 >> 2),
 804         0x00000000,
 805         (0x0e00 << 16) | (0xac8c >> 2),
 806         0x00000000,
 807         (0x0e00 << 16) | (0x970c >> 2),
 808         0x00000000,
 809         (0x0e00 << 16) | (0x9714 >> 2),
 810         0x00000000,
 811         (0x0e00 << 16) | (0x9718 >> 2),
 812         0x00000000,
 813         (0x0e00 << 16) | (0x971c >> 2),
 814         0x00000000,
 815         (0x0e00 << 16) | (0x31068 >> 2),
 816         0x00000000,
 817         (0x4e00 << 16) | (0x31068 >> 2),
 818         0x00000000,
 819         (0x5e00 << 16) | (0x31068 >> 2),
 820         0x00000000,
 821         (0x6e00 << 16) | (0x31068 >> 2),
 822         0x00000000,
 823         (0x7e00 << 16) | (0x31068 >> 2),
 824         0x00000000,
 825         (0x0e00 << 16) | (0xcd10 >> 2),
 826         0x00000000,
 827         (0x0e00 << 16) | (0xcd14 >> 2),
 828         0x00000000,
 829         (0x0e00 << 16) | (0x88b0 >> 2),
 830         0x00000000,
 831         (0x0e00 << 16) | (0x88b4 >> 2),
 832         0x00000000,
 833         (0x0e00 << 16) | (0x88b8 >> 2),
 834         0x00000000,
 835         (0x0e00 << 16) | (0x88bc >> 2),
 836         0x00000000,
 837         (0x0400 << 16) | (0x89c0 >> 2),
 838         0x00000000,
 839         (0x0e00 << 16) | (0x88c4 >> 2),
 840         0x00000000,
 841         (0x0e00 << 16) | (0x88c8 >> 2),
 842         0x00000000,
 843         (0x0e00 << 16) | (0x88d0 >> 2),
 844         0x00000000,
 845         (0x0e00 << 16) | (0x88d4 >> 2),
 846         0x00000000,
 847         (0x0e00 << 16) | (0x88d8 >> 2),
 848         0x00000000,
 849         (0x0e00 << 16) | (0x8980 >> 2),
 850         0x00000000,
 851         (0x0e00 << 16) | (0x30938 >> 2),
 852         0x00000000,
 853         (0x0e00 << 16) | (0x3093c >> 2),
 854         0x00000000,
 855         (0x0e00 << 16) | (0x30940 >> 2),
 856         0x00000000,
 857         (0x0e00 << 16) | (0x89a0 >> 2),
 858         0x00000000,
 859         (0x0e00 << 16) | (0x30900 >> 2),
 860         0x00000000,
 861         (0x0e00 << 16) | (0x30904 >> 2),
 862         0x00000000,
 863         (0x0e00 << 16) | (0x89b4 >> 2),
 864         0x00000000,
 865         (0x0e00 << 16) | (0x3e1fc >> 2),
 866         0x00000000,
 867         (0x0e00 << 16) | (0x3c210 >> 2),
 868         0x00000000,
 869         (0x0e00 << 16) | (0x3c214 >> 2),
 870         0x00000000,
 871         (0x0e00 << 16) | (0x3c218 >> 2),
 872         0x00000000,
 873         (0x0e00 << 16) | (0x8904 >> 2),
 874         0x00000000,
 875         0x5,
 876         (0x0e00 << 16) | (0x8c28 >> 2),
 877         (0x0e00 << 16) | (0x8c2c >> 2),
 878         (0x0e00 << 16) | (0x8c30 >> 2),
 879         (0x0e00 << 16) | (0x8c34 >> 2),
 880         (0x0e00 << 16) | (0x9600 >> 2),
 881 };
 882
 883 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
 884 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
 885 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
 886 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
 887
 888 /*
 889  * Core functions
 890  */
 891 /**
 892  * gfx_v7_0_init_microcode - load ucode images from disk
 893  *
 894  * @adev: amdgpu_device pointer
 895  *
 896  * Use the firmware interface to load the ucode images into
 897  * the driver (not loaded into hw).
 898  * Returns 0 on success, error on failure.
 899  */
 900 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
 901 {
 902         const char *chip_name;
 903         char fw_name[30];
 904         int err;
 905
 906         DRM_DEBUG("\n");
 907
 908         switch (adev->asic_type) {
 909         case CHIP_BONAIRE:
 910                 chip_name = "bonaire";
 911                 break;
 912         case CHIP_HAWAII:
 913                 chip_name = "hawaii";
 914                 break;
 915         case CHIP_KAVERI:
 916                 chip_name = "kaveri";
 917                 break;
 918         case CHIP_KABINI:
 919                 chip_name = "kabini";
 920                 break;
 921         case CHIP_MULLINS:
 922                 chip_name = "mullins";
 923                 break;
 924         default: BUG();
 925         }
 926
 927         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 928         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 929         if (err)
 930                 goto out;
 931         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 932         if (err)
 933                 goto out;
 934
 935         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 936         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 937         if (err)
 938                 goto out;
 939         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 940         if (err)
 941                 goto out;
 942
 943         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 944         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 945         if (err)
 946                 goto out;
 947         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 948         if (err)
 949                 goto out;
 950
 951         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
 952         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 953         if (err)
 954                 goto out;
 955         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 956         if (err)
 957                 goto out;
 958
 959         if (adev->asic_type == CHIP_KAVERI) {
 960                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
 961                 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 962                 if (err)
 963                         goto out;
 964                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 965                 if (err)
 966                         goto out;
 967         }
 968
 969         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
 970         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 971         if (err)
 972                 goto out;
 973         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 974
 975 out:
 976         if (err) {
 977                 printk(KERN_ERR
 978                        "gfx7: Failed to load firmware \"%s\"\n",
 979                        fw_name);
 980                 release_firmware(adev->gfx.pfp_fw);
 981                 adev->gfx.pfp_fw = NULL;
 982                 release_firmware(adev->gfx.me_fw);
 983                 adev->gfx.me_fw = NULL;
 984                 release_firmware(adev->gfx.ce_fw);
 985                 adev->gfx.ce_fw = NULL;
 986                 release_firmware(adev->gfx.mec_fw);
 987                 adev->gfx.mec_fw = NULL;
 988                 release_firmware(adev->gfx.mec2_fw);
 989                 adev->gfx.mec2_fw = NULL;
 990                 release_firmware(adev->gfx.rlc_fw);
 991                 adev->gfx.rlc_fw = NULL;
 992         }
 993         return err;
 994 }
 995
 996 /**
 997  * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
 998  *
 999  * @adev: amdgpu_device pointer
1000  *
1001  * Starting with SI, the tiling setup is done globally in a
1002  * set of 32 tiling modes.  Rather than selecting each set of
1003  * parameters per surface as on older asics, we just select
1004  * which index in the tiling table we want to use, and the
1005  * surface uses those parameters (CIK).
1006  */
1007 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1008 {
1009         const u32 num_tile_mode_states = 32;
1010         const u32 num_secondary_tile_mode_states = 16;
1011         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1012
1013         switch (adev->gfx.config.mem_row_size_in_kb) {
1014         case 1:
1015                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1016                 break;
1017         case 2:
1018         default:
1019                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1020                 break;
1021         case 4:
1022                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1023                 break;
1024         }
1025
1026         switch (adev->asic_type) {
1027         case CHIP_BONAIRE:
1028                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1029                         switch (reg_offset) {
1030                         case 0:
1031                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1032                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1033                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1034                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1035                                 break;
1036                         case 1:
1037                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1038                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1039                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1040                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1041                                 break;
1042                         case 2:
1043                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1044                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1045                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1046                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1047                                 break;
1048                         case 3:
1049                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1050                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1051                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1052                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1053                                 break;
1054                         case 4:
1055                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1056                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1057                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1058                                                 TILE_SPLIT(split_equal_to_row_size));
1059                                 break;
1060                         case 5:
1061                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1062                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1063                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1064                                 break;
1065                         case 6:
1066                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1067                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1068                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1069                                                 TILE_SPLIT(split_equal_to_row_size));
1070                                 break;
1071                         case 7:
1072                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1073                                 break;
1074
1075                         case 8:
1076                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1077                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1078                                 break;
1079                         case 9:
1080                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1081                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1082                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1083                                 break;
1084                         case 10:
1085                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1086                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1087                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1088                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1089                                 break;
1090                         case 11:
1091                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1092                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1093                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1094                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1095                                 break;
1096                         case 12:
1097                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1098                                 break;
1099                         case 13:
1100                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1101                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1102                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1103                                 break;
1104                         case 14:
1105                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1106                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1107                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1108                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1109                                 break;
1110                         case 15:
1111                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1112                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1113                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1114                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1115                                 break;
1116                         case 16:
1117                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1118                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1119                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1120                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1121                                 break;
1122                         case 17:
1123                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1124                                 break;
1125                         case 18:
1126                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1127                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1128                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1129                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1130                                 break;
1131                         case 19:
1132                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1133                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1134                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1135                                 break;
1136                         case 20:
1137                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1138                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1139                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1140                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1141                                 break;
1142                         case 21:
1143                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1144                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1145                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1146                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1147                                 break;
1148                         case 22:
1149                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1150                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1151                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1152                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1153                                 break;
1154                         case 23:
1155                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1156                                 break;
1157                         case 24:
1158                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1159                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1160                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1161                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1162                                 break;
1163                         case 25:
1164                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1165                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1166                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1167                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1168                                 break;
1169                         case 26:
1170                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1171                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1172                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1173                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1174                                 break;
1175                         case 27:
1176                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1177                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1178                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1179                                 break;
1180                         case 28:
1181                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1182                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1183                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1184                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1185                                 break;
1186                         case 29:
1187                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1188                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1189                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1190                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1191                                 break;
1192                         case 30:
1193                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1194                                 break;
1195                         default:
1196                                 gb_tile_moden = 0;
1197                                 break;
1198                         }
1199                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1200                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1201                 }
1202                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1203                         switch (reg_offset) {
1204                         case 0:
1205                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1206                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1207                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1208                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1209                                 break;
1210                         case 1:
1211                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1212                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1213                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1214                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1215                                 break;
1216                         case 2:
1217                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1218                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1219                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1220                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1221                                 break;
1222                         case 3:
1223                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1224                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1225                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1226                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1227                                 break;
1228                         case 4:
1229                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1230                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1231                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1232                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1233                                 break;
1234                         case 5:
1235                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1236                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1237                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1238                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1239                                 break;
1240                         case 6:
1241                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1242                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1243                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1244                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1245                                 break;
1246                         case 8:
1247                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1248                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1249                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1250                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1251                                 break;
1252                         case 9:
1253                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1254                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1255                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1256                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1257                                 break;
1258                         case 10:
1259                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1260                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1261                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1262                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1263                                 break;
1264                         case 11:
1265                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1266                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1267                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1268                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1269                                 break;
1270                         case 12:
1271                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1272                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1273                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1274                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1275                                 break;
1276                         case 13:
1277                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1278                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1279                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1280                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1281                                 break;
1282                         case 14:
1283                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1284                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1285                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1286                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1287                                 break;
1288                         default:
1289                                 gb_tile_moden = 0;
1290                                 break;
1291                         }
1292                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1293                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1294                 }
1295                 break;
1296         case CHIP_HAWAII:
1297                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1298                         switch (reg_offset) {
1299                         case 0:
1300                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1301                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1302                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1303                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1304                                 break;
1305                         case 1:
1306                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1307                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1308                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1309                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1310                                 break;
1311                         case 2:
1312                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1313                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1314                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1315                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1316                                 break;
1317                         case 3:
1318                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1319                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1320                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1321                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1322                                 break;
1323                         case 4:
1324                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1325                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1326                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1327                                                 TILE_SPLIT(split_equal_to_row_size));
1328                                 break;
1329                         case 5:
1330                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1331                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1332                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1333                                                 TILE_SPLIT(split_equal_to_row_size));
1334                                 break;
1335                         case 6:
1336                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1337                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1338                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1339                                                 TILE_SPLIT(split_equal_to_row_size));
1340                                 break;
1341                         case 7:
1342                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1343                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1344                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1345                                                 TILE_SPLIT(split_equal_to_row_size));
1346                                 break;
1347
1348                         case 8:
1349                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1350                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1351                                 break;
1352                         case 9:
1353                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1354                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1355                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1356                                 break;
1357                         case 10:
1358                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1359                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1360                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1361                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1362                                 break;
1363                         case 11:
1364                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1365                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1366                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1367                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1368                                 break;
1369                         case 12:
1370                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1371                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1372                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1373                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1374                                 break;
1375                         case 13:
1376                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1377                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1378                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1379                                 break;
1380                         case 14:
1381                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1382                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1383                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1384                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1385                                 break;
1386                         case 15:
1387                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1388                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1389                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1390                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1391                                 break;
1392                         case 16:
1393                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1394                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1395                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1396                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1397                                 break;
1398                         case 17:
1399                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1400                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1401                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1402                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1403                                 break;
1404                         case 18:
1405                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1406                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1407                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1408                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1409                                 break;
1410                         case 19:
1411                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1412                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1413                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1414                                 break;
1415                         case 20:
1416                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1417                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1418                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1419                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1420                                 break;
1421                         case 21:
1422                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1423                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1424                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1425                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1426                                 break;
1427                         case 22:
1428                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1429                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1430                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1431                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1432                                 break;
1433                         case 23:
1434                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1435                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1436                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1437                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1438                                 break;
1439                         case 24:
1440                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1441                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1442                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1443                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1444                                 break;
1445                         case 25:
1446                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1447                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1448                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1449                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1450                                 break;
1451                         case 26:
1452                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1453                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1454                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1455                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1456                                 break;
1457                         case 27:
1458                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1459                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1460                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1461                                 break;
1462                         case 28:
1463                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1464                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1465                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1466                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1467                                 break;
1468                         case 29:
1469                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1470                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1471                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1472                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1473                                 break;
1474                         case 30:
1475                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1476                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1477                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1478                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1479                                 break;
1480                         default:
1481                                 gb_tile_moden = 0;
1482                                 break;
1483                         }
1484                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1485                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1486                 }
1487                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1488                         switch (reg_offset) {
1489                         case 0:
1490                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1491                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1492                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1493                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1494                                 break;
1495                         case 1:
1496                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1497                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1498                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1499                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1500                                 break;
1501                         case 2:
1502                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1503                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1504                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1505                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1506                                 break;
1507                         case 3:
1508                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1509                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1510                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1511                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1512                                 break;
1513                         case 4:
1514                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1515                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1516                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1517                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1518                                 break;
1519                         case 5:
1520                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1521                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1522                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1523                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1524                                 break;
1525                         case 6:
1526                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1527                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1528                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1529                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1530                                 break;
1531                         case 8:
1532                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1533                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1534                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1535                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1536                                 break;
1537                         case 9:
1538                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1539                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1540                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1541                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1542                                 break;
1543                         case 10:
1544                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1545                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1546                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1547                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1548                                 break;
1549                         case 11:
1550                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1551                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1552                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1553                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1554                                 break;
1555                         case 12:
1556                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1557                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1558                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1559                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1560                                 break;
1561                         case 13:
1562                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1563                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1564                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1565                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1566                                 break;
1567                         case 14:
1568                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1569                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1570                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1571                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1572                                 break;
1573                         default:
1574                                 gb_tile_moden = 0;
1575                                 break;
1576                         }
1577                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1578                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1579                 }
1580                 break;
1581         case CHIP_KABINI:
1582         case CHIP_KAVERI:
1583         case CHIP_MULLINS:
1584         default:
1585                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1586                         switch (reg_offset) {
1587                         case 0:
1588                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1589                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1590                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1591                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1592                                 break;
1593                         case 1:
1594                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1595                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1596                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1597                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1598                                 break;
1599                         case 2:
1600                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1601                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1602                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1603                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1604                                 break;
1605                         case 3:
1606                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1607                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1608                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1609                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1610                                 break;
1611                         case 4:
1612                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1613                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1614                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1615                                                 TILE_SPLIT(split_equal_to_row_size));
1616                                 break;
1617                         case 5:
1618                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1619                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1620                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1621                                 break;
1622                         case 6:
1623                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1624                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1625                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1626                                                 TILE_SPLIT(split_equal_to_row_size));
1627                                 break;
1628                         case 7:
1629                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1630                                 break;
1631
1632                         case 8:
1633                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1634                                                 PIPE_CONFIG(ADDR_SURF_P2));
1635                                 break;
1636                         case 9:
1637                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1638                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1639                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1640                                 break;
1641                         case 10:
1642                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1643                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1644                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1645                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1646                                 break;
1647                         case 11:
1648                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1649                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1650                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1651                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1652                                 break;
1653                         case 12:
1654                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1655                                 break;
1656                         case 13:
1657                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1658                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1659                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1660                                 break;
1661                         case 14:
1662                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1663                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1664                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1665                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1666                                 break;
1667                         case 15:
1668                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1669                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1670                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1671                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1672                                 break;
1673                         case 16:
1674                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1675                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1676                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1677                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1678                                 break;
1679                         case 17:
1680                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1681                                 break;
1682                         case 18:
1683                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1684                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1685                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1686                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1687                                 break;
1688                         case 19:
1689                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1690                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1691                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1692                                 break;
1693                         case 20:
1694                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1695                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1696                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1697                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1698                                 break;
1699                         case 21:
1700                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1701                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1702                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1703                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1704                                 break;
1705                         case 22:
1706                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1707                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1708                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1709                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1710                                 break;
1711                         case 23:
1712                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1713                                 break;
1714                         case 24:
1715                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1716                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1717                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1718                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1719                                 break;
1720                         case 25:
1721                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1722                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1723                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1724                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1725                                 break;
1726                         case 26:
1727                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1728                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1729                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1730                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1731                                 break;
1732                         case 27:
1733                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1734                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1735                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1736                                 break;
1737                         case 28:
1738                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1739                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1740                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1741                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1742                                 break;
1743                         case 29:
1744                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1745                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1746                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1747                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1748                                 break;
1749                         case 30:
1750                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1751                                 break;
1752                         default:
1753                                 gb_tile_moden = 0;
1754                                 break;
1755                         }
1756                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1757                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1758                 }
1759                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1760                         switch (reg_offset) {
1761                         case 0:
1762                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1763                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1764                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1765                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1766                                 break;
1767                         case 1:
1768                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1769                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1770                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1771                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1772                                 break;
1773                         case 2:
1774                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1775                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1776                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1777                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1778                                 break;
1779                         case 3:
1780                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1781                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1782                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1783                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1784                                 break;
1785                         case 4:
1786                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1787                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1788                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1789                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1790                                 break;
1791                         case 5:
1792                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1793                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1794                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1795                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1796                                 break;
1797                         case 6:
1798                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1799                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1800                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1801                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1802                                 break;
1803                         case 8:
1804                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1805                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1806                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1807                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1808                                 break;
1809                         case 9:
1810                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1811                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1812                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1813                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1814                                 break;
1815                         case 10:
1816                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1817                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1818                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1819                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1820                                 break;
1821                         case 11:
1822                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1823                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1824                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1825                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1826                                 break;
1827                         case 12:
1828                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1829                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1830                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1831                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1832                                 break;
1833                         case 13:
1834                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1835                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1836                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1837                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1838                                 break;
1839                         case 14:
1840                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1841                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1842                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1843                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1844                                 break;
1845                         default:
1846                                 gb_tile_moden = 0;
1847                                 break;
1848                         }
1849                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1850                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1851                 }
1852                 break;
1853         }
1854 }
1855
1856 /**
1857  * gfx_v7_0_select_se_sh - select which SE, SH to address
1858  *
1859  * @adev: amdgpu_device pointer
1860  * @se_num: shader engine to address
1861  * @sh_num: sh block to address
1862  *
1863  * Select which SE, SH combinations to address. Certain
1864  * registers are instanced per SE or SH.  0xffffffff means
1865  * broadcast to all SEs or SHs (CIK).
1866  */
1867 void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1868 {
1869         u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK;
1870
1871         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1872                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1873                         GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1874         else if (se_num == 0xffffffff)
1875                 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1876                         (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1877         else if (sh_num == 0xffffffff)
1878                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1879                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1880         else
1881                 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1882                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1883         WREG32(mmGRBM_GFX_INDEX, data);
1884 }
1885
1886 /**
1887  * gfx_v7_0_create_bitmask - create a bitmask
1888  *
1889  * @bit_width: length of the mask
1890  *
1891  * create a variable length bit mask (CIK).
1892  * Returns the bitmask.
1893  */
1894 static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1895 {
1896         u32 i, mask = 0;
1897
1898         for (i = 0; i < bit_width; i++) {
1899                 mask <<= 1;
1900                 mask |= 1;
1901         }
1902         return mask;
1903 }
1904
1905 /**
1906  * gfx_v7_0_get_rb_disabled - computes the mask of disabled RBs
1907  *
1908  * @adev: amdgpu_device pointer
1909  * @max_rb_num: max RBs (render backends) for the asic
1910  * @se_num: number of SEs (shader engines) for the asic
1911  * @sh_per_se: number of SH blocks per SE for the asic
1912  *
1913  * Calculates the bitmask of disabled RBs (CIK).
1914  * Returns the disabled RB bitmask.
1915  */
1916 static u32 gfx_v7_0_get_rb_disabled(struct amdgpu_device *adev,
1917                                     u32 max_rb_num_per_se,
1918                                     u32 sh_per_se)
1919 {
1920         u32 data, mask;
1921
1922         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1923         if (data & 1)
1924                 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1925         else
1926                 data = 0;
1927
1928         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1929
1930         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1931
1932         mask = gfx_v7_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1933
1934         return data & mask;
1935 }
1936
1937 /**
1938  * gfx_v7_0_setup_rb - setup the RBs on the asic
1939  *
1940  * @adev: amdgpu_device pointer
1941  * @se_num: number of SEs (shader engines) for the asic
1942  * @sh_per_se: number of SH blocks per SE for the asic
1943  * @max_rb_num: max RBs (render backends) for the asic
1944  *
1945  * Configures per-SE/SH RB registers (CIK).
1946  */
1947 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev,
1948                               u32 se_num, u32 sh_per_se,
1949                               u32 max_rb_num_per_se)
1950 {
1951         int i, j;
1952         u32 data, mask;
1953         u32 disabled_rbs = 0;
1954         u32 enabled_rbs = 0;
1955
1956         mutex_lock(&adev->grbm_idx_mutex);
1957         for (i = 0; i < se_num; i++) {
1958                 for (j = 0; j < sh_per_se; j++) {
1959                         gfx_v7_0_select_se_sh(adev, i, j);
1960                         data = gfx_v7_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
1961                         if (adev->asic_type == CHIP_HAWAII)
1962                                 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
1963                         else
1964                                 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
1965                 }
1966         }
1967         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1968         mutex_unlock(&adev->grbm_idx_mutex);
1969
1970         mask = 1;
1971         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1972                 if (!(disabled_rbs & mask))
1973                         enabled_rbs |= mask;
1974                 mask <<= 1;
1975         }
1976
1977         adev->gfx.config.backend_enable_mask = enabled_rbs;
1978
1979         mutex_lock(&adev->grbm_idx_mutex);
1980         for (i = 0; i < se_num; i++) {
1981                 gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
1982                 data = 0;
1983                 for (j = 0; j < sh_per_se; j++) {
1984                         switch (enabled_rbs & 3) {
1985                         case 0:
1986                                 if (j == 0)
1987                                         data |= (RASTER_CONFIG_RB_MAP_3 <<
1988                                                 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1989                                 else
1990                                         data |= (RASTER_CONFIG_RB_MAP_0 <<
1991                                                 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1992                                 break;
1993                         case 1:
1994                                 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1995                                 break;
1996                         case 2:
1997                                 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1998                                 break;
1999                         case 3:
2000                         default:
2001                                 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
2002                                 break;
2003                         }
2004                         enabled_rbs >>= 2;
2005                 }
2006                 WREG32(mmPA_SC_RASTER_CONFIG, data);
2007         }
2008         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2009         mutex_unlock(&adev->grbm_idx_mutex);
2010 }
2011
2012 /**
2013  * gfx_v7_0_gpu_init - setup the 3D engine
2014  *
2015  * @adev: amdgpu_device pointer
2016  *
2017  * Configures the 3D engine and tiling configuration
2018  * registers so that the 3D engine is usable.
2019  */
2020 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
2021 {
2022         u32 gb_addr_config;
2023         u32 mc_shared_chmap, mc_arb_ramcfg;
2024         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
2025         u32 sh_mem_cfg;
2026         u32 tmp;
2027         int i;
2028
2029         switch (adev->asic_type) {
2030         case CHIP_BONAIRE:
2031                 adev->gfx.config.max_shader_engines = 2;
2032                 adev->gfx.config.max_tile_pipes = 4;
2033                 adev->gfx.config.max_cu_per_sh = 7;
2034                 adev->gfx.config.max_sh_per_se = 1;
2035                 adev->gfx.config.max_backends_per_se = 2;
2036                 adev->gfx.config.max_texture_channel_caches = 4;
2037                 adev->gfx.config.max_gprs = 256;
2038                 adev->gfx.config.max_gs_threads = 32;
2039                 adev->gfx.config.max_hw_contexts = 8;
2040
2041                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2042                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2043                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2044                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2045                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
2046                 break;
2047         case CHIP_HAWAII:
2048                 adev->gfx.config.max_shader_engines = 4;
2049                 adev->gfx.config.max_tile_pipes = 16;
2050                 adev->gfx.config.max_cu_per_sh = 11;
2051                 adev->gfx.config.max_sh_per_se = 1;
2052                 adev->gfx.config.max_backends_per_se = 4;
2053                 adev->gfx.config.max_texture_channel_caches = 16;
2054                 adev->gfx.config.max_gprs = 256;
2055                 adev->gfx.config.max_gs_threads = 32;
2056                 adev->gfx.config.max_hw_contexts = 8;
2057
2058                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2059                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2060                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2061                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2062                 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
2063                 break;
2064         case CHIP_KAVERI:
2065                 adev->gfx.config.max_shader_engines = 1;
2066                 adev->gfx.config.max_tile_pipes = 4;
2067                 if ((adev->pdev->device == 0x1304) ||
2068                     (adev->pdev->device == 0x1305) ||
2069                     (adev->pdev->device == 0x130C) ||
2070                     (adev->pdev->device == 0x130F) ||
2071                     (adev->pdev->device == 0x1310) ||
2072                     (adev->pdev->device == 0x1311) ||
2073                     (adev->pdev->device == 0x131C)) {
2074                         adev->gfx.config.max_cu_per_sh = 8;
2075                         adev->gfx.config.max_backends_per_se = 2;
2076                 } else if ((adev->pdev->device == 0x1309) ||
2077                            (adev->pdev->device == 0x130A) ||
2078                            (adev->pdev->device == 0x130D) ||
2079                            (adev->pdev->device == 0x1313) ||
2080                            (adev->pdev->device == 0x131D)) {
2081                         adev->gfx.config.max_cu_per_sh = 6;
2082                         adev->gfx.config.max_backends_per_se = 2;
2083                 } else if ((adev->pdev->device == 0x1306) ||
2084                            (adev->pdev->device == 0x1307) ||
2085                            (adev->pdev->device == 0x130B) ||
2086                            (adev->pdev->device == 0x130E) ||
2087                            (adev->pdev->device == 0x1315) ||
2088                            (adev->pdev->device == 0x131B)) {
2089                         adev->gfx.config.max_cu_per_sh = 4;
2090                         adev->gfx.config.max_backends_per_se = 1;
2091                 } else {
2092                         adev->gfx.config.max_cu_per_sh = 3;
2093                         adev->gfx.config.max_backends_per_se = 1;
2094                 }
2095                 adev->gfx.config.max_sh_per_se = 1;
2096                 adev->gfx.config.max_texture_channel_caches = 4;
2097                 adev->gfx.config.max_gprs = 256;
2098                 adev->gfx.config.max_gs_threads = 16;
2099                 adev->gfx.config.max_hw_contexts = 8;
2100
2101                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2102                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2103                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2104                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2105                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
2106                 break;
2107         case CHIP_KABINI:
2108         case CHIP_MULLINS:
2109         default:
2110                 adev->gfx.config.max_shader_engines = 1;
2111                 adev->gfx.config.max_tile_pipes = 2;
2112                 adev->gfx.config.max_cu_per_sh = 2;
2113                 adev->gfx.config.max_sh_per_se = 1;
2114                 adev->gfx.config.max_backends_per_se = 1;
2115                 adev->gfx.config.max_texture_channel_caches = 2;
2116                 adev->gfx.config.max_gprs = 256;
2117                 adev->gfx.config.max_gs_threads = 16;
2118                 adev->gfx.config.max_hw_contexts = 8;
2119
2120                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2121                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2122                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2123                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2124                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
2125                 break;
2126         }
2127
2128         WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
2129
2130         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
2131         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2132         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
2133
2134         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2135         adev->gfx.config.mem_max_burst_length_bytes = 256;
2136         if (adev->flags & AMDGPU_IS_APU) {
2137                 /* Get memory bank mapping mode. */
2138                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2139                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2140                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2141
2142                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
2143                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2144                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2145
2146                 /* Validate settings in case only one DIMM installed. */
2147                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
2148                         dimm00_addr_map = 0;
2149                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
2150                         dimm01_addr_map = 0;
2151                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
2152                         dimm10_addr_map = 0;
2153                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
2154                         dimm11_addr_map = 0;
2155
2156                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
2157                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
2158                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
2159                         adev->gfx.config.mem_row_size_in_kb = 2;
2160                 else
2161                         adev->gfx.config.mem_row_size_in_kb = 1;
2162         } else {
2163                 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
2164                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
2165                 if (adev->gfx.config.mem_row_size_in_kb > 4)
2166                         adev->gfx.config.mem_row_size_in_kb = 4;
2167         }
2168         /* XXX use MC settings? */
2169         adev->gfx.config.shader_engine_tile_size = 32;
2170         adev->gfx.config.num_gpus = 1;
2171         adev->gfx.config.multi_gpu_tile_size = 64;
2172
2173         /* fix up row size */
2174         gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
2175         switch (adev->gfx.config.mem_row_size_in_kb) {
2176         case 1:
2177         default:
2178                 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
2179                 break;
2180         case 2:
2181                 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
2182                 break;
2183         case 4:
2184                 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
2185                 break;
2186         }
2187         adev->gfx.config.gb_addr_config = gb_addr_config;
2188
2189         WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
2190         WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
2191         WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
2192         WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
2193         WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
2194         WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
2195         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2196         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2197
2198         gfx_v7_0_tiling_mode_table_init(adev);
2199
2200         gfx_v7_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2201                           adev->gfx.config.max_sh_per_se,
2202                           adev->gfx.config.max_backends_per_se);
2203
2204         /* set HW defaults for 3D engine */
2205         WREG32(mmCP_MEQ_THRESHOLDS,
2206                         (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
2207                         (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
2208
2209         mutex_lock(&adev->grbm_idx_mutex);
2210         /*
2211          * making sure that the following register writes will be broadcasted
2212          * to all the shaders
2213          */
2214         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2215
2216         /* XXX SH_MEM regs */
2217         /* where to put LDS, scratch, GPUVM in FSA64 space */
2218         sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
2219                                    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2220
2221         mutex_lock(&adev->srbm_mutex);
2222         for (i = 0; i < 16; i++) {
2223                 cik_srbm_select(adev, 0, 0, 0, i);
2224                 /* CP and shaders */
2225                 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
2226                 WREG32(mmSH_MEM_APE1_BASE, 1);
2227                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2228                 WREG32(mmSH_MEM_BASES, 0);
2229         }
2230         cik_srbm_select(adev, 0, 0, 0, 0);
2231         mutex_unlock(&adev->srbm_mutex);
2232
2233         WREG32(mmSX_DEBUG_1, 0x20);
2234
2235         WREG32(mmTA_CNTL_AUX, 0x00010000);
2236
2237         tmp = RREG32(mmSPI_CONFIG_CNTL);
2238         tmp |= 0x03000000;
2239         WREG32(mmSPI_CONFIG_CNTL, tmp);
2240
2241         WREG32(mmSQ_CONFIG, 1);
2242
2243         WREG32(mmDB_DEBUG, 0);
2244
2245         tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
2246         tmp |= 0x00000400;
2247         WREG32(mmDB_DEBUG2, tmp);
2248
2249         tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
2250         tmp |= 0x00020200;
2251         WREG32(mmDB_DEBUG3, tmp);
2252
2253         tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
2254         tmp |= 0x00018208;
2255         WREG32(mmCB_HW_CONTROL, tmp);
2256
2257         WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
2258
2259         WREG32(mmPA_SC_FIFO_SIZE,
2260                 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2261                 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2262                 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2263                 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
2264
2265         WREG32(mmVGT_NUM_INSTANCES, 1);
2266
2267         WREG32(mmCP_PERFMON_CNTL, 0);
2268
2269         WREG32(mmSQ_CONFIG, 0);
2270
2271         WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
2272                 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
2273                 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
2274
2275         WREG32(mmVGT_CACHE_INVALIDATION,
2276                 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
2277                 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
2278
2279         WREG32(mmVGT_GS_VERTEX_REUSE, 16);
2280         WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
2281
2282         WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
2283                         (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
2284         WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
2285         mutex_unlock(&adev->grbm_idx_mutex);
2286
2287         udelay(50);
2288 }
2289
2290 /*
2291  * GPU scratch registers helpers function.
2292  */
2293 /**
2294  * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
2295  *
2296  * @adev: amdgpu_device pointer
2297  *
2298  * Set up the number and offset of the CP scratch registers.
2299  * NOTE: use of CP scratch registers is a legacy inferface and
2300  * is not used by default on newer asics (r6xx+).  On newer asics,
2301  * memory buffers are used for fences rather than scratch regs.
2302  */
2303 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
2304 {
2305         int i;
2306
2307         adev->gfx.scratch.num_reg = 7;
2308         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
2309         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
2310                 adev->gfx.scratch.free[i] = true;
2311                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
2312         }
2313 }
2314
2315 /**
2316  * gfx_v7_0_ring_test_ring - basic gfx ring test
2317  *
2318  * @adev: amdgpu_device pointer
2319  * @ring: amdgpu_ring structure holding ring information
2320  *
2321  * Allocate a scratch register and write to it using the gfx ring (CIK).
2322  * Provides a basic gfx ring test to verify that the ring is working.
2323  * Used by gfx_v7_0_cp_gfx_resume();
2324  * Returns 0 on success, error on failure.
2325  */
2326 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2327 {
2328         struct amdgpu_device *adev = ring->adev;
2329         uint32_t scratch;
2330         uint32_t tmp = 0;
2331         unsigned i;
2332         int r;
2333
2334         r = amdgpu_gfx_scratch_get(adev, &scratch);
2335         if (r) {
2336                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
2337                 return r;
2338         }
2339         WREG32(scratch, 0xCAFEDEAD);
2340         r = amdgpu_ring_lock(ring, 3);
2341         if (r) {
2342                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
2343                 amdgpu_gfx_scratch_free(adev, scratch);
2344                 return r;
2345         }
2346         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2347         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2348         amdgpu_ring_write(ring, 0xDEADBEEF);
2349         amdgpu_ring_unlock_commit(ring);
2350
2351         for (i = 0; i < adev->usec_timeout; i++) {
2352                 tmp = RREG32(scratch);
2353                 if (tmp == 0xDEADBEEF)
2354                         break;
2355                 DRM_UDELAY(1);
2356         }
2357         if (i < adev->usec_timeout) {
2358                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2359         } else {
2360                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2361                           ring->idx, scratch, tmp);
2362                 r = -EINVAL;
2363         }
2364         amdgpu_gfx_scratch_free(adev, scratch);
2365         return r;
2366 }
2367
2368 /**
2369  * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
2370  *
2371  * @adev: amdgpu_device pointer
2372  * @ridx: amdgpu ring index
2373  *
2374  * Emits an hdp flush on the cp.
2375  */
2376 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2377 {
2378         u32 ref_and_mask;
2379         int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
2380
2381         if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
2382                 switch (ring->me) {
2383                 case 1:
2384                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2385                         break;
2386                 case 2:
2387                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2388                         break;
2389                 default:
2390                         return;
2391                 }
2392         } else {
2393                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2394         }
2395
2396         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2397         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2398                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
2399                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
2400         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2401         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2402         amdgpu_ring_write(ring, ref_and_mask);
2403         amdgpu_ring_write(ring, ref_and_mask);
2404         amdgpu_ring_write(ring, 0x20); /* poll interval */
2405 }
2406
2407 /**
2408  * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2409  *
2410  * @adev: amdgpu_device pointer
2411  * @fence: amdgpu fence object
2412  *
2413  * Emits a fence sequnce number on the gfx ring and flushes
2414  * GPU caches.
2415  */
2416 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2417                                          u64 seq, unsigned flags)
2418 {
2419         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2420         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2421         /* Workaround for cache flush problems. First send a dummy EOP
2422          * event down the pipe with seq one below.
2423          */
2424         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2425         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2426                                  EOP_TC_ACTION_EN |
2427                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2428                                  EVENT_INDEX(5)));
2429         amdgpu_ring_write(ring, addr & 0xfffffffc);
2430         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2431                                 DATA_SEL(1) | INT_SEL(0));
2432         amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2433         amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2434
2435         /* Then send the real EOP event down the pipe. */
2436         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2437         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2438                                  EOP_TC_ACTION_EN |
2439                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2440                                  EVENT_INDEX(5)));
2441         amdgpu_ring_write(ring, addr & 0xfffffffc);
2442         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2443                                 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2444         amdgpu_ring_write(ring, lower_32_bits(seq));
2445         amdgpu_ring_write(ring, upper_32_bits(seq));
2446 }
2447
2448 /**
2449  * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2450  *
2451  * @adev: amdgpu_device pointer
2452  * @fence: amdgpu fence object
2453  *
2454  * Emits a fence sequnce number on the compute ring and flushes
2455  * GPU caches.
2456  */
2457 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2458                                              u64 addr, u64 seq,
2459                                              unsigned flags)
2460 {
2461         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2462         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2463
2464         /* RELEASE_MEM - flush caches, send int */
2465         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2466         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2467                                  EOP_TC_ACTION_EN |
2468                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2469                                  EVENT_INDEX(5)));
2470         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2471         amdgpu_ring_write(ring, addr & 0xfffffffc);
2472         amdgpu_ring_write(ring, upper_32_bits(addr));
2473         amdgpu_ring_write(ring, lower_32_bits(seq));
2474         amdgpu_ring_write(ring, upper_32_bits(seq));
2475 }
2476
2477 /**
2478  * gfx_v7_0_ring_emit_semaphore - emit a semaphore on the CP ring
2479  *
2480  * @ring: amdgpu ring buffer object
2481  * @semaphore: amdgpu semaphore object
2482  * @emit_wait: Is this a sempahore wait?
2483  *
2484  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2485  * from running ahead of semaphore waits.
2486  */
2487 static bool gfx_v7_0_ring_emit_semaphore(struct amdgpu_ring *ring,
2488                                          struct amdgpu_semaphore *semaphore,
2489                                          bool emit_wait)
2490 {
2491         uint64_t addr = semaphore->gpu_addr;
2492         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2493
2494         amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2495         amdgpu_ring_write(ring, addr & 0xffffffff);
2496         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
2497
2498         if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
2499                 /* Prevent the PFP from running ahead of the semaphore wait */
2500                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2501                 amdgpu_ring_write(ring, 0x0);
2502         }
2503
2504         return true;
2505 }
2506
2507 /*
2508  * IB stuff
2509  */
2510 /**
2511  * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2512  *
2513  * @ring: amdgpu_ring structure holding ring information
2514  * @ib: amdgpu indirect buffer object
2515  *
2516  * Emits an DE (drawing engine) or CE (constant engine) IB
2517  * on the gfx ring.  IBs are usually generated by userspace
2518  * acceleration drivers and submitted to the kernel for
2519  * sheduling on the ring.  This function schedules the IB
2520  * on the gfx ring for execution by the GPU.
2521  */
2522 static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
2523                                   struct amdgpu_ib *ib)
2524 {
2525         bool need_ctx_switch = ring->current_ctx != ib->ctx;
2526         u32 header, control = 0;
2527         u32 next_rptr = ring->wptr + 5;
2528
2529         /* drop the CE preamble IB for the same context */
2530         if ((ring->type == AMDGPU_RING_TYPE_GFX) &&
2531             (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
2532             !need_ctx_switch)
2533                 return;
2534
2535         if (ring->type == AMDGPU_RING_TYPE_COMPUTE)
2536                 control |= INDIRECT_BUFFER_VALID;
2537
2538         if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
2539                 next_rptr += 2;
2540
2541         next_rptr += 4;
2542         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2543         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2544         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2545         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2546         amdgpu_ring_write(ring, next_rptr);
2547
2548         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2549         if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) {
2550                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2551                 amdgpu_ring_write(ring, 0);
2552         }
2553
2554         if (ib->flags & AMDGPU_IB_FLAG_CE)
2555                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2556         else
2557                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2558
2559         control |= ib->length_dw |
2560                 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
2561
2562         amdgpu_ring_write(ring, header);
2563         amdgpu_ring_write(ring,
2564 #ifdef __BIG_ENDIAN
2565                           (2 << 0) |
2566 #endif
2567                           (ib->gpu_addr & 0xFFFFFFFC));
2568         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2569         amdgpu_ring_write(ring, control);
2570 }
2571
2572 /**
2573  * gfx_v7_0_ring_test_ib - basic ring IB test
2574  *
2575  * @ring: amdgpu_ring structure holding ring information
2576  *
2577  * Allocate an IB and execute it on the gfx ring (CIK).
2578  * Provides a basic gfx ring test to verify that IBs are working.
2579  * Returns 0 on success, error on failure.
2580  */
2581 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2582 {
2583         struct amdgpu_device *adev = ring->adev;
2584         struct amdgpu_ib ib;
2585         uint32_t scratch;
2586         uint32_t tmp = 0;
2587         unsigned i;
2588         int r;
2589
2590         r = amdgpu_gfx_scratch_get(adev, &scratch);
2591         if (r) {
2592                 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
2593                 return r;
2594         }
2595         WREG32(scratch, 0xCAFEDEAD);
2596         r = amdgpu_ib_get(ring, NULL, 256, &ib);
2597         if (r) {
2598                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
2599                 amdgpu_gfx_scratch_free(adev, scratch);
2600                 return r;
2601         }
2602         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2603         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2604         ib.ptr[2] = 0xDEADBEEF;
2605         ib.length_dw = 3;
2606         r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
2607         if (r) {
2608                 amdgpu_gfx_scratch_free(adev, scratch);
2609                 amdgpu_ib_free(adev, &ib);
2610                 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
2611                 return r;
2612         }
2613         r = amdgpu_fence_wait(ib.fence, false);
2614         if (r) {
2615                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
2616                 amdgpu_gfx_scratch_free(adev, scratch);
2617                 amdgpu_ib_free(adev, &ib);
2618                 return r;
2619         }
2620         for (i = 0; i < adev->usec_timeout; i++) {
2621                 tmp = RREG32(scratch);
2622                 if (tmp == 0xDEADBEEF)
2623                         break;
2624                 DRM_UDELAY(1);
2625         }
2626         if (i < adev->usec_timeout) {
2627                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
2628                          ib.fence->ring->idx, i);
2629         } else {
2630                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2631                           scratch, tmp);
2632                 r = -EINVAL;
2633         }
2634         amdgpu_gfx_scratch_free(adev, scratch);
2635         amdgpu_ib_free(adev, &ib);
2636         return r;
2637 }
2638
2639 /*
2640  * CP.
2641  * On CIK, gfx and compute now have independant command processors.
2642  *
2643  * GFX
2644  * Gfx consists of a single ring and can process both gfx jobs and
2645  * compute jobs.  The gfx CP consists of three microengines (ME):
2646  * PFP - Pre-Fetch Parser
2647  * ME - Micro Engine
2648  * CE - Constant Engine
2649  * The PFP and ME make up what is considered the Drawing Engine (DE).
2650  * The CE is an asynchronous engine used for updating buffer desciptors
2651  * used by the DE so that they can be loaded into cache in parallel
2652  * while the DE is processing state update packets.
2653  *
2654  * Compute
2655  * The compute CP consists of two microengines (ME):
2656  * MEC1 - Compute MicroEngine 1
2657  * MEC2 - Compute MicroEngine 2
2658  * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2659  * The queues are exposed to userspace and are programmed directly
2660  * by the compute runtime.
2661  */
2662 /**
2663  * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2664  *
2665  * @adev: amdgpu_device pointer
2666  * @enable: enable or disable the MEs
2667  *
2668  * Halts or unhalts the gfx MEs.
2669  */
2670 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2671 {
2672         int i;
2673
2674         if (enable) {
2675                 WREG32(mmCP_ME_CNTL, 0);
2676         } else {
2677                 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2678                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2679                         adev->gfx.gfx_ring[i].ready = false;
2680         }
2681         udelay(50);
2682 }
2683
2684 /**
2685  * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2686  *
2687  * @adev: amdgpu_device pointer
2688  *
2689  * Loads the gfx PFP, ME, and CE ucode.
2690  * Returns 0 for success, -EINVAL if the ucode is not available.
2691  */
2692 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2693 {
2694         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2695         const struct gfx_firmware_header_v1_0 *ce_hdr;
2696         const struct gfx_firmware_header_v1_0 *me_hdr;
2697         const __le32 *fw_data;
2698         unsigned i, fw_size;
2699
2700         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2701                 return -EINVAL;
2702
2703         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2704         ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2705         me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2706
2707         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2708         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2709         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2710         adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2711         adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2712         adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2713         adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2714         adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2715         adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2716
2717         gfx_v7_0_cp_gfx_enable(adev, false);
2718
2719         /* PFP */
2720         fw_data = (const __le32 *)
2721                 (adev->gfx.pfp_fw->data +
2722                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2723         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2724         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2725         for (i = 0; i < fw_size; i++)
2726                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2727         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2728
2729         /* CE */
2730         fw_data = (const __le32 *)
2731                 (adev->gfx.ce_fw->data +
2732                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2733         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2734         WREG32(mmCP_CE_UCODE_ADDR, 0);
2735         for (i = 0; i < fw_size; i++)
2736                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2737         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2738
2739         /* ME */
2740         fw_data = (const __le32 *)
2741                 (adev->gfx.me_fw->data +
2742                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2743         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2744         WREG32(mmCP_ME_RAM_WADDR, 0);
2745         for (i = 0; i < fw_size; i++)
2746                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2747         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2748
2749         return 0;
2750 }
2751
2752 /**
2753  * gfx_v7_0_cp_gfx_start - start the gfx ring
2754  *
2755  * @adev: amdgpu_device pointer
2756  *
2757  * Enables the ring and loads the clear state context and other
2758  * packets required to init the ring.
2759  * Returns 0 for success, error for failure.
2760  */
2761 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2762 {
2763         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2764         const struct cs_section_def *sect = NULL;
2765         const struct cs_extent_def *ext = NULL;
2766         int r, i;
2767
2768         /* init the CP */
2769         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2770         WREG32(mmCP_ENDIAN_SWAP, 0);
2771         WREG32(mmCP_DEVICE_ID, 1);
2772
2773         gfx_v7_0_cp_gfx_enable(adev, true);
2774
2775         r = amdgpu_ring_lock(ring, gfx_v7_0_get_csb_size(adev) + 8);
2776         if (r) {
2777                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2778                 return r;
2779         }
2780
2781         /* init the CE partitions.  CE only used for gfx on CIK */
2782         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2783         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2784         amdgpu_ring_write(ring, 0x8000);
2785         amdgpu_ring_write(ring, 0x8000);
2786
2787         /* clear state buffer */
2788         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2789         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2790
2791         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2792         amdgpu_ring_write(ring, 0x80000000);
2793         amdgpu_ring_write(ring, 0x80000000);
2794
2795         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2796                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2797                         if (sect->id == SECT_CONTEXT) {
2798                                 amdgpu_ring_write(ring,
2799                                                   PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2800                                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2801                                 for (i = 0; i < ext->reg_count; i++)
2802                                         amdgpu_ring_write(ring, ext->extent[i]);
2803                         }
2804                 }
2805         }
2806
2807         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2808         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2809         switch (adev->asic_type) {
2810         case CHIP_BONAIRE:
2811                 amdgpu_ring_write(ring, 0x16000012);
2812                 amdgpu_ring_write(ring, 0x00000000);
2813                 break;
2814         case CHIP_KAVERI:
2815                 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2816                 amdgpu_ring_write(ring, 0x00000000);
2817                 break;
2818         case CHIP_KABINI:
2819         case CHIP_MULLINS:
2820                 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2821                 amdgpu_ring_write(ring, 0x00000000);
2822                 break;
2823         case CHIP_HAWAII:
2824                 amdgpu_ring_write(ring, 0x3a00161a);
2825                 amdgpu_ring_write(ring, 0x0000002e);
2826                 break;
2827         default:
2828                 amdgpu_ring_write(ring, 0x00000000);
2829                 amdgpu_ring_write(ring, 0x00000000);
2830                 break;
2831         }
2832
2833         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2834         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2835
2836         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2837         amdgpu_ring_write(ring, 0);
2838
2839         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2840         amdgpu_ring_write(ring, 0x00000316);
2841         amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2842         amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2843
2844         amdgpu_ring_unlock_commit(ring);
2845
2846         return 0;
2847 }
2848
2849 /**
2850  * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2851  *
2852  * @adev: amdgpu_device pointer
2853  *
2854  * Program the location and size of the gfx ring buffer
2855  * and test it to make sure it's working.
2856  * Returns 0 for success, error for failure.
2857  */
2858 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2859 {
2860         struct amdgpu_ring *ring;
2861         u32 tmp;
2862         u32 rb_bufsz;
2863         u64 rb_addr, rptr_addr;
2864         int r;
2865
2866         WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2867         if (adev->asic_type != CHIP_HAWAII)
2868                 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2869
2870         /* Set the write pointer delay */
2871         WREG32(mmCP_RB_WPTR_DELAY, 0);
2872
2873         /* set the RB to use vmid 0 */
2874         WREG32(mmCP_RB_VMID, 0);
2875
2876         WREG32(mmSCRATCH_ADDR, 0);
2877
2878         /* ring 0 - compute and gfx */
2879         /* Set ring buffer size */
2880         ring = &adev->gfx.gfx_ring[0];
2881         rb_bufsz = order_base_2(ring->ring_size / 8);
2882         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2883 #ifdef __BIG_ENDIAN
2884         tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2885 #endif
2886         WREG32(mmCP_RB0_CNTL, tmp);
2887
2888         /* Initialize the ring buffer's read and write pointers */
2889         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2890         ring->wptr = 0;
2891         WREG32(mmCP_RB0_WPTR, ring->wptr);
2892
2893         /* set the wb address wether it's enabled or not */
2894         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2895         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2896         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2897
2898         /* scratch register shadowing is no longer supported */
2899         WREG32(mmSCRATCH_UMSK, 0);
2900
2901         mdelay(1);
2902         WREG32(mmCP_RB0_CNTL, tmp);
2903
2904         rb_addr = ring->gpu_addr >> 8;
2905         WREG32(mmCP_RB0_BASE, rb_addr);
2906         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2907
2908         /* start the ring */
2909         gfx_v7_0_cp_gfx_start(adev);
2910         ring->ready = true;
2911         r = amdgpu_ring_test_ring(ring);
2912         if (r) {
2913                 ring->ready = false;
2914                 return r;
2915         }
2916
2917         return 0;
2918 }
2919
2920 static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2921 {
2922         u32 rptr;
2923
2924         rptr = ring->adev->wb.wb[ring->rptr_offs];
2925
2926         return rptr;
2927 }
2928
2929 static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2930 {
2931         struct amdgpu_device *adev = ring->adev;
2932         u32 wptr;
2933
2934         wptr = RREG32(mmCP_RB0_WPTR);
2935
2936         return wptr;
2937 }
2938
2939 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2940 {
2941         struct amdgpu_device *adev = ring->adev;
2942
2943         WREG32(mmCP_RB0_WPTR, ring->wptr);
2944         (void)RREG32(mmCP_RB0_WPTR);
2945 }
2946
2947 static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2948 {
2949         u32 rptr;
2950
2951         rptr = ring->adev->wb.wb[ring->rptr_offs];
2952
2953         return rptr;
2954 }
2955
2956 static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2957 {
2958         u32 wptr;
2959
2960         /* XXX check if swapping is necessary on BE */
2961         wptr = ring->adev->wb.wb[ring->wptr_offs];
2962
2963         return wptr;
2964 }
2965
2966 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2967 {
2968         struct amdgpu_device *adev = ring->adev;
2969
2970         /* XXX check if swapping is necessary on BE */
2971         adev->wb.wb[ring->wptr_offs] = ring->wptr;
2972         WDOORBELL32(ring->doorbell_index, ring->wptr);
2973 }
2974
2975 /**
2976  * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2977  *
2978  * @adev: amdgpu_device pointer
2979  * @enable: enable or disable the MEs
2980  *
2981  * Halts or unhalts the compute MEs.
2982  */
2983 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2984 {
2985         int i;
2986
2987         if (enable) {
2988                 WREG32(mmCP_MEC_CNTL, 0);
2989         } else {
2990                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2991                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2992                         adev->gfx.compute_ring[i].ready = false;
2993         }
2994         udelay(50);
2995 }
2996
2997 /**
2998  * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2999  *
3000  * @adev: amdgpu_device pointer
3001  *
3002  * Loads the compute MEC1&2 ucode.
3003  * Returns 0 for success, -EINVAL if the ucode is not available.
3004  */
3005 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3006 {
3007         const struct gfx_firmware_header_v1_0 *mec_hdr;
3008         const __le32 *fw_data;
3009         unsigned i, fw_size;
3010
3011         if (!adev->gfx.mec_fw)
3012                 return -EINVAL;
3013
3014         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3015         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3016         adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
3017
3018         gfx_v7_0_cp_compute_enable(adev, false);
3019
3020         /* MEC1 */
3021         fw_data = (const __le32 *)
3022                 (adev->gfx.mec_fw->data +
3023                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3024         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
3025         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
3026         for (i = 0; i < fw_size; i++)
3027                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
3028         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
3029
3030         if (adev->asic_type == CHIP_KAVERI) {
3031                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
3032
3033                 if (!adev->gfx.mec2_fw)
3034                         return -EINVAL;
3035
3036                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3037                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
3038                 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
3039
3040                 /* MEC2 */
3041                 fw_data = (const __le32 *)
3042                         (adev->gfx.mec2_fw->data +
3043                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
3044                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
3045                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
3046                 for (i = 0; i < fw_size; i++)
3047                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
3048                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
3049         }
3050
3051         return 0;
3052 }
3053
3054 /**
3055  * gfx_v7_0_cp_compute_start - start the compute queues
3056  *
3057  * @adev: amdgpu_device pointer
3058  *
3059  * Enable the compute queues.
3060  * Returns 0 for success, error for failure.
3061  */
3062 static int gfx_v7_0_cp_compute_start(struct amdgpu_device *adev)
3063 {
3064         gfx_v7_0_cp_compute_enable(adev, true);
3065
3066         return 0;
3067 }
3068
3069 /**
3070  * gfx_v7_0_cp_compute_fini - stop the compute queues
3071  *
3072  * @adev: amdgpu_device pointer
3073  *
3074  * Stop the compute queues and tear down the driver queue
3075  * info.
3076  */
3077 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
3078 {
3079         int i, r;
3080
3081         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3082                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3083
3084                 if (ring->mqd_obj) {
3085                         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3086                         if (unlikely(r != 0))
3087                                 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3088
3089                         amdgpu_bo_unpin(ring->mqd_obj);
3090                         amdgpu_bo_unreserve(ring->mqd_obj);
3091
3092                         amdgpu_bo_unref(&ring->mqd_obj);
3093                         ring->mqd_obj = NULL;
3094                 }
3095         }
3096 }
3097
3098 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
3099 {
3100         int r;
3101
3102         if (adev->gfx.mec.hpd_eop_obj) {
3103                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
3104                 if (unlikely(r != 0))
3105                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
3106                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
3107                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
3108
3109                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
3110                 adev->gfx.mec.hpd_eop_obj = NULL;
3111         }
3112 }
3113
3114 #define MEC_HPD_SIZE 2048
3115
3116 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
3117 {
3118         int r;
3119         u32 *hpd;
3120
3121         /*
3122          * KV:    2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
3123          * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
3124          * Nonetheless, we assign only 1 pipe because all other pipes will
3125          * be handled by KFD
3126          */
3127         adev->gfx.mec.num_mec = 1;
3128         adev->gfx.mec.num_pipe = 1;
3129         adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
3130
3131         if (adev->gfx.mec.hpd_eop_obj == NULL) {
3132                 r = amdgpu_bo_create(adev,
3133                                      adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
3134                                      PAGE_SIZE, true,
3135                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3136                                      &adev->gfx.mec.hpd_eop_obj);
3137                 if (r) {
3138                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
3139                         return r;
3140                 }
3141         }
3142
3143         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
3144         if (unlikely(r != 0)) {
3145                 gfx_v7_0_mec_fini(adev);
3146                 return r;
3147         }
3148         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
3149                           &adev->gfx.mec.hpd_eop_gpu_addr);
3150         if (r) {
3151                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
3152                 gfx_v7_0_mec_fini(adev);
3153                 return r;
3154         }
3155         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
3156         if (r) {
3157                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
3158                 gfx_v7_0_mec_fini(adev);
3159                 return r;
3160         }
3161
3162         /* clear memory.  Not sure if this is required or not */
3163         memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
3164
3165         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
3166         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
3167
3168         return 0;
3169 }
3170
3171 struct hqd_registers
3172 {
3173         u32 cp_mqd_base_addr;
3174         u32 cp_mqd_base_addr_hi;
3175         u32 cp_hqd_active;
3176         u32 cp_hqd_vmid;
3177         u32 cp_hqd_persistent_state;
3178         u32 cp_hqd_pipe_priority;
3179         u32 cp_hqd_queue_priority;
3180         u32 cp_hqd_quantum;
3181         u32 cp_hqd_pq_base;
3182         u32 cp_hqd_pq_base_hi;
3183         u32 cp_hqd_pq_rptr;
3184         u32 cp_hqd_pq_rptr_report_addr;
3185         u32 cp_hqd_pq_rptr_report_addr_hi;
3186         u32 cp_hqd_pq_wptr_poll_addr;
3187         u32 cp_hqd_pq_wptr_poll_addr_hi;
3188         u32 cp_hqd_pq_doorbell_control;
3189         u32 cp_hqd_pq_wptr;
3190         u32 cp_hqd_pq_control;
3191         u32 cp_hqd_ib_base_addr;
3192         u32 cp_hqd_ib_base_addr_hi;
3193         u32 cp_hqd_ib_rptr;
3194         u32 cp_hqd_ib_control;
3195         u32 cp_hqd_iq_timer;
3196         u32 cp_hqd_iq_rptr;
3197         u32 cp_hqd_dequeue_request;
3198         u32 cp_hqd_dma_offload;
3199         u32 cp_hqd_sema_cmd;
3200         u32 cp_hqd_msg_type;
3201         u32 cp_hqd_atomic0_preop_lo;
3202         u32 cp_hqd_atomic0_preop_hi;
3203         u32 cp_hqd_atomic1_preop_lo;
3204         u32 cp_hqd_atomic1_preop_hi;
3205         u32 cp_hqd_hq_scheduler0;
3206         u32 cp_hqd_hq_scheduler1;
3207         u32 cp_mqd_control;
3208 };
3209
3210 struct bonaire_mqd
3211 {
3212         u32 header;
3213         u32 dispatch_initiator;
3214         u32 dimensions[3];
3215         u32 start_idx[3];
3216         u32 num_threads[3];
3217         u32 pipeline_stat_enable;
3218         u32 perf_counter_enable;
3219         u32 pgm[2];
3220         u32 tba[2];
3221         u32 tma[2];
3222         u32 pgm_rsrc[2];
3223         u32 vmid;
3224         u32 resource_limits;
3225         u32 static_thread_mgmt01[2];
3226         u32 tmp_ring_size;
3227         u32 static_thread_mgmt23[2];
3228         u32 restart[3];
3229         u32 thread_trace_enable;
3230         u32 reserved1;
3231         u32 user_data[16];
3232         u32 vgtcs_invoke_count[2];
3233         struct hqd_registers queue_state;
3234         u32 dequeue_cntr;
3235         u32 interrupt_queue[64];
3236 };
3237
3238 /**
3239  * gfx_v7_0_cp_compute_resume - setup the compute queue registers
3240  *
3241  * @adev: amdgpu_device pointer
3242  *
3243  * Program the compute queues and test them to make sure they
3244  * are working.
3245  * Returns 0 for success, error for failure.
3246  */
3247 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
3248 {
3249         int r, i, j;
3250         u32 tmp;
3251         bool use_doorbell = true;
3252         u64 hqd_gpu_addr;
3253         u64 mqd_gpu_addr;
3254         u64 eop_gpu_addr;
3255         u64 wb_gpu_addr;
3256         u32 *buf;
3257         struct bonaire_mqd *mqd;
3258
3259         r = gfx_v7_0_cp_compute_start(adev);
3260         if (r)
3261                 return r;
3262
3263         /* fix up chicken bits */
3264         tmp = RREG32(mmCP_CPF_DEBUG);
3265         tmp |= (1 << 23);
3266         WREG32(mmCP_CPF_DEBUG, tmp);
3267
3268         /* init the pipes */
3269         mutex_lock(&adev->srbm_mutex);
3270         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3271                 int me = (i < 4) ? 1 : 2;
3272                 int pipe = (i < 4) ? i : (i - 4);
3273
3274                 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
3275
3276                 cik_srbm_select(adev, me, pipe, 0, 0);
3277
3278                 /* write the EOP addr */
3279                 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
3280                 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
3281
3282                 /* set the VMID assigned */
3283                 WREG32(mmCP_HPD_EOP_VMID, 0);
3284
3285                 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3286                 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
3287                 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
3288                 tmp |= order_base_2(MEC_HPD_SIZE / 8);
3289                 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
3290         }
3291         cik_srbm_select(adev, 0, 0, 0, 0);
3292         mutex_unlock(&adev->srbm_mutex);
3293
3294         /* init the queues.  Just two for now. */
3295         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3296                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3297
3298                 if (ring->mqd_obj == NULL) {
3299                         r = amdgpu_bo_create(adev,
3300                                              sizeof(struct bonaire_mqd),
3301                                              PAGE_SIZE, true,
3302                                              AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3303                                              &ring->mqd_obj);
3304                         if (r) {
3305                                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3306                                 return r;
3307                         }
3308                 }
3309
3310                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3311                 if (unlikely(r != 0)) {
3312                         gfx_v7_0_cp_compute_fini(adev);
3313                         return r;
3314                 }
3315                 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3316                                   &mqd_gpu_addr);
3317                 if (r) {
3318                         dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3319                         gfx_v7_0_cp_compute_fini(adev);
3320                         return r;
3321                 }
3322                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3323                 if (r) {
3324                         dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3325                         gfx_v7_0_cp_compute_fini(adev);
3326                         return r;
3327                 }
3328
3329                 /* init the mqd struct */
3330                 memset(buf, 0, sizeof(struct bonaire_mqd));
3331
3332                 mqd = (struct bonaire_mqd *)buf;
3333                 mqd->header = 0xC0310800;
3334                 mqd->static_thread_mgmt01[0] = 0xffffffff;
3335                 mqd->static_thread_mgmt01[1] = 0xffffffff;
3336                 mqd->static_thread_mgmt23[0] = 0xffffffff;
3337                 mqd->static_thread_mgmt23[1] = 0xffffffff;
3338
3339                 mutex_lock(&adev->srbm_mutex);
3340                 cik_srbm_select(adev, ring->me,
3341                                 ring->pipe,
3342                                 ring->queue, 0);
3343
3344                 /* disable wptr polling */
3345                 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3346                 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
3347                 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3348
3349                 /* enable doorbell? */
3350                 mqd->queue_state.cp_hqd_pq_doorbell_control =
3351                         RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3352                 if (use_doorbell)
3353                         mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3354                 else
3355                         mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3356                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3357                        mqd->queue_state.cp_hqd_pq_doorbell_control);
3358
3359                 /* disable the queue if it's active */
3360                 mqd->queue_state.cp_hqd_dequeue_request = 0;
3361                 mqd->queue_state.cp_hqd_pq_rptr = 0;
3362                 mqd->queue_state.cp_hqd_pq_wptr= 0;
3363                 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3364                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3365                         for (j = 0; j < adev->usec_timeout; j++) {
3366                                 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3367                                         break;
3368                                 udelay(1);
3369                         }
3370                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
3371                         WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
3372                         WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3373                 }
3374
3375                 /* set the pointer to the MQD */
3376                 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
3377                 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3378                 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
3379                 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
3380                 /* set MQD vmid to 0 */
3381                 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
3382                 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
3383                 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
3384
3385                 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3386                 hqd_gpu_addr = ring->gpu_addr >> 8;
3387                 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
3388                 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3389                 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
3390                 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
3391
3392                 /* set up the HQD, this is similar to CP_RB0_CNTL */
3393                 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
3394                 mqd->queue_state.cp_hqd_pq_control &=
3395                         ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
3396                                         CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
3397
3398                 mqd->queue_state.cp_hqd_pq_control |=
3399                         order_base_2(ring->ring_size / 8);
3400                 mqd->queue_state.cp_hqd_pq_control |=
3401                         (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
3402 #ifdef __BIG_ENDIAN
3403                 mqd->queue_state.cp_hqd_pq_control |=
3404                         2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
3405 #endif
3406                 mqd->queue_state.cp_hqd_pq_control &=
3407                         ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
3408                                 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
3409                                 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
3410                 mqd->queue_state.cp_hqd_pq_control |=
3411                         CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
3412                         CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
3413                 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
3414
3415                 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3416                 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3417                 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3418                 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3419                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
3420                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3421                        mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
3422
3423                 /* set the wb address wether it's enabled or not */
3424                 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3425                 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
3426                 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
3427                         upper_32_bits(wb_gpu_addr) & 0xffff;
3428                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3429                        mqd->queue_state.cp_hqd_pq_rptr_report_addr);
3430                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3431                        mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
3432
3433                 /* enable the doorbell if requested */
3434                 if (use_doorbell) {
3435                         mqd->queue_state.cp_hqd_pq_doorbell_control =
3436                                 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3437                         mqd->queue_state.cp_hqd_pq_doorbell_control &=
3438                                 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
3439                         mqd->queue_state.cp_hqd_pq_doorbell_control |=
3440                                 (ring->doorbell_index <<
3441                                  CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
3442                         mqd->queue_state.cp_hqd_pq_doorbell_control |=
3443                                 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3444                         mqd->queue_state.cp_hqd_pq_doorbell_control &=
3445                                 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
3446                                 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
3447
3448                 } else {
3449                         mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
3450                 }
3451                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3452                        mqd->queue_state.cp_hqd_pq_doorbell_control);
3453
3454                 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3455                 ring->wptr = 0;
3456                 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
3457                 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3458                 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3459
3460                 /* set the vmid for the queue */
3461                 mqd->queue_state.cp_hqd_vmid = 0;
3462                 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
3463
3464                 /* activate the queue */
3465                 mqd->queue_state.cp_hqd_active = 1;
3466                 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
3467
3468                 cik_srbm_select(adev, 0, 0, 0, 0);
3469                 mutex_unlock(&adev->srbm_mutex);
3470
3471                 amdgpu_bo_kunmap(ring->mqd_obj);
3472                 amdgpu_bo_unreserve(ring->mqd_obj);
3473
3474                 ring->ready = true;
3475                 r = amdgpu_ring_test_ring(ring);
3476                 if (r)
3477                         ring->ready = false;
3478         }
3479
3480         return 0;
3481 }
3482
3483 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3484 {
3485         gfx_v7_0_cp_gfx_enable(adev, enable);
3486         gfx_v7_0_cp_compute_enable(adev, enable);
3487 }
3488
3489 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3490 {
3491         int r;
3492
3493         r = gfx_v7_0_cp_gfx_load_microcode(adev);
3494         if (r)
3495                 return r;
3496         r = gfx_v7_0_cp_compute_load_microcode(adev);
3497         if (r)
3498                 return r;
3499
3500         return 0;
3501 }
3502
3503 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3504                                                bool enable)
3505 {
3506         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3507
3508         if (enable)
3509                 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3510                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3511         else
3512                 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3513                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3514         WREG32(mmCP_INT_CNTL_RING0, tmp);
3515 }
3516
3517 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3518 {
3519         int r;
3520
3521         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3522
3523         r = gfx_v7_0_cp_load_microcode(adev);
3524         if (r)
3525                 return r;
3526
3527         r = gfx_v7_0_cp_gfx_resume(adev);
3528         if (r)
3529                 return r;
3530         r = gfx_v7_0_cp_compute_resume(adev);
3531         if (r)
3532                 return r;
3533
3534         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3535
3536         return 0;
3537 }
3538
3539 static void gfx_v7_0_ce_sync_me(struct amdgpu_ring *ring)
3540 {
3541         struct amdgpu_device *adev = ring->adev;
3542         u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
3543
3544         /* instruct DE to set a magic number */
3545         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3546         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3547                                                          WRITE_DATA_DST_SEL(5)));
3548         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3549         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3550         amdgpu_ring_write(ring, 1);
3551
3552         /* let CE wait till condition satisfied */
3553         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3554         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3555                                                          WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3556                                                          WAIT_REG_MEM_FUNCTION(3) |  /* == */
3557                                                          WAIT_REG_MEM_ENGINE(2)));   /* ce */
3558         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3559         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3560         amdgpu_ring_write(ring, 1);
3561         amdgpu_ring_write(ring, 0xffffffff);
3562         amdgpu_ring_write(ring, 4); /* poll interval */
3563
3564         /* instruct CE to reset wb of ce_sync to zero */
3565         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3566         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3567                                                          WRITE_DATA_DST_SEL(5) |
3568                                                          WR_CONFIRM));
3569         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3570         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3571         amdgpu_ring_write(ring, 0);
3572 }
3573
3574 /*
3575  * vm
3576  * VMID 0 is the physical GPU addresses as used by the kernel.
3577  * VMIDs 1-15 are used for userspace clients and are handled
3578  * by the amdgpu vm/hsa code.
3579  */
3580 /**
3581  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3582  *
3583  * @adev: amdgpu_device pointer
3584  *
3585  * Update the page table base and flush the VM TLB
3586  * using the CP (CIK).
3587  */
3588 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3589                                         unsigned vm_id, uint64_t pd_addr)
3590 {
3591         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3592
3593         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3594         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3595                                  WRITE_DATA_DST_SEL(0)));
3596         if (vm_id < 8) {
3597                 amdgpu_ring_write(ring,
3598                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3599         } else {
3600                 amdgpu_ring_write(ring,
3601                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3602         }
3603         amdgpu_ring_write(ring, 0);
3604         amdgpu_ring_write(ring, pd_addr >> 12);
3605
3606         /* bits 0-15 are the VM contexts0-15 */
3607         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3608         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3609                                  WRITE_DATA_DST_SEL(0)));
3610         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3611         amdgpu_ring_write(ring, 0);
3612         amdgpu_ring_write(ring, 1 << vm_id);
3613
3614         /* wait for the invalidate to complete */
3615         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3616         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3617                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
3618                                  WAIT_REG_MEM_ENGINE(0))); /* me */
3619         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3620         amdgpu_ring_write(ring, 0);
3621         amdgpu_ring_write(ring, 0); /* ref */
3622         amdgpu_ring_write(ring, 0); /* mask */
3623         amdgpu_ring_write(ring, 0x20); /* poll interval */
3624
3625         /* compute doesn't have PFP */
3626         if (usepfp) {
3627                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3628                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3629                 amdgpu_ring_write(ring, 0x0);
3630
3631                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3632                 gfx_v7_0_ce_sync_me(ring);
3633         }
3634 }
3635
3636 /*
3637  * RLC
3638  * The RLC is a multi-purpose microengine that handles a
3639  * variety of functions.
3640  */
3641 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3642 {
3643         int r;
3644
3645         /* save restore block */
3646         if (adev->gfx.rlc.save_restore_obj) {
3647                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3648                 if (unlikely(r != 0))
3649                         dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3650                 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3651                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3652
3653                 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3654                 adev->gfx.rlc.save_restore_obj = NULL;
3655         }
3656
3657         /* clear state block */
3658         if (adev->gfx.rlc.clear_state_obj) {
3659                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3660                 if (unlikely(r != 0))
3661                         dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3662                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3663                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3664
3665                 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3666                 adev->gfx.rlc.clear_state_obj = NULL;
3667         }
3668
3669         /* clear state block */
3670         if (adev->gfx.rlc.cp_table_obj) {
3671                 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3672                 if (unlikely(r != 0))
3673                         dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3674                 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3675                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3676
3677                 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3678                 adev->gfx.rlc.cp_table_obj = NULL;
3679         }
3680 }
3681
3682 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3683 {
3684         const u32 *src_ptr;
3685         volatile u32 *dst_ptr;
3686         u32 dws, i;
3687         const struct cs_section_def *cs_data;
3688         int r;
3689
3690         /* allocate rlc buffers */
3691         if (adev->flags & AMDGPU_IS_APU) {
3692                 if (adev->asic_type == CHIP_KAVERI) {
3693                         adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3694                         adev->gfx.rlc.reg_list_size =
3695                                 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3696                 } else {
3697                         adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3698                         adev->gfx.rlc.reg_list_size =
3699                                 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3700                 }
3701         }
3702         adev->gfx.rlc.cs_data = ci_cs_data;
3703         adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;
3704
3705         src_ptr = adev->gfx.rlc.reg_list;
3706         dws = adev->gfx.rlc.reg_list_size;
3707         dws += (5 * 16) + 48 + 48 + 64;
3708
3709         cs_data = adev->gfx.rlc.cs_data;
3710
3711         if (src_ptr) {
3712                 /* save restore block */
3713                 if (adev->gfx.rlc.save_restore_obj == NULL) {
3714                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3715                                              AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->gfx.rlc.save_restore_obj);
3716                         if (r) {
3717                                 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3718                                 return r;
3719                         }
3720                 }
3721
3722                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3723                 if (unlikely(r != 0)) {
3724                         gfx_v7_0_rlc_fini(adev);
3725                         return r;
3726                 }
3727                 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3728                                   &adev->gfx.rlc.save_restore_gpu_addr);
3729                 if (r) {
3730                         amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3731                         dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3732                         gfx_v7_0_rlc_fini(adev);
3733                         return r;
3734                 }
3735
3736                 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3737                 if (r) {
3738                         dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3739                         gfx_v7_0_rlc_fini(adev);
3740                         return r;
3741                 }
3742                 /* write the sr buffer */
3743                 dst_ptr = adev->gfx.rlc.sr_ptr;
3744                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3745                         dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3746                 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3747                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3748         }
3749
3750         if (cs_data) {
3751                 /* clear state block */
3752                 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3753
3754                 if (adev->gfx.rlc.clear_state_obj == NULL) {
3755                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3756                                              AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->gfx.rlc.clear_state_obj);
3757                         if (r) {
3758                                 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3759                                 gfx_v7_0_rlc_fini(adev);
3760                                 return r;
3761                         }
3762                 }
3763                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3764                 if (unlikely(r != 0)) {
3765                         gfx_v7_0_rlc_fini(adev);
3766                         return r;
3767                 }
3768                 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3769                                   &adev->gfx.rlc.clear_state_gpu_addr);
3770                 if (r) {
3771                         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3772                         dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3773                         gfx_v7_0_rlc_fini(adev);
3774                         return r;
3775                 }
3776
3777                 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3778                 if (r) {
3779                         dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3780                         gfx_v7_0_rlc_fini(adev);
3781                         return r;
3782                 }
3783                 /* set up the cs buffer */
3784                 dst_ptr = adev->gfx.rlc.cs_ptr;
3785                 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3786                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3787                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3788         }
3789
3790         if (adev->gfx.rlc.cp_table_size) {
3791                 if (adev->gfx.rlc.cp_table_obj == NULL) {
3792                         r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
3793                                              AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->gfx.rlc.cp_table_obj);
3794                         if (r) {
3795                                 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3796                                 gfx_v7_0_rlc_fini(adev);
3797                                 return r;
3798                         }
3799                 }
3800
3801                 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3802                 if (unlikely(r != 0)) {
3803                         dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3804                         gfx_v7_0_rlc_fini(adev);
3805                         return r;
3806                 }
3807                 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3808                                   &adev->gfx.rlc.cp_table_gpu_addr);
3809                 if (r) {
3810                         amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3811                         dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3812                         gfx_v7_0_rlc_fini(adev);
3813                         return r;
3814                 }
3815                 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3816                 if (r) {
3817                         dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3818                         gfx_v7_0_rlc_fini(adev);
3819                         return r;
3820                 }
3821
3822                 gfx_v7_0_init_cp_pg_table(adev);
3823
3824                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3825                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3826
3827         }
3828
3829         return 0;
3830 }
3831
3832 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3833 {
3834         u32 tmp;
3835
3836         tmp = RREG32(mmRLC_LB_CNTL);
3837         if (enable)
3838                 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3839         else
3840                 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3841         WREG32(mmRLC_LB_CNTL, tmp);
3842 }
3843
3844 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3845 {
3846         u32 i, j, k;
3847         u32 mask;
3848
3849         mutex_lock(&adev->grbm_idx_mutex);
3850         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3851                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3852                         gfx_v7_0_select_se_sh(adev, i, j);
3853                         for (k = 0; k < adev->usec_timeout; k++) {
3854                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3855                                         break;
3856                                 udelay(1);
3857                         }
3858                 }
3859         }
3860         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3861         mutex_unlock(&adev->grbm_idx_mutex);
3862
3863         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3864                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3865                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3866                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3867         for (k = 0; k < adev->usec_timeout; k++) {
3868                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3869                         break;
3870                 udelay(1);
3871         }
3872 }
3873
3874 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3875 {
3876         u32 tmp;
3877
3878         tmp = RREG32(mmRLC_CNTL);
3879         if (tmp != rlc)
3880                 WREG32(mmRLC_CNTL, rlc);
3881 }
3882
3883 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3884 {
3885         u32 data, orig;
3886
3887         orig = data = RREG32(mmRLC_CNTL);
3888
3889         if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3890                 u32 i;
3891
3892                 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3893                 WREG32(mmRLC_CNTL, data);
3894
3895                 for (i = 0; i < adev->usec_timeout; i++) {
3896                         if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3897                                 break;
3898                         udelay(1);
3899                 }
3900
3901                 gfx_v7_0_wait_for_rlc_serdes(adev);
3902         }
3903
3904         return orig;
3905 }
3906
3907 void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3908 {
3909         u32 tmp, i, mask;
3910
3911         tmp = 0x1 | (1 << 1);
3912         WREG32(mmRLC_GPR_REG2, tmp);
3913
3914         mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3915                 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3916         for (i = 0; i < adev->usec_timeout; i++) {
3917                 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3918                         break;
3919                 udelay(1);
3920         }
3921
3922         for (i = 0; i < adev->usec_timeout; i++) {
3923                 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3924                         break;
3925                 udelay(1);
3926         }
3927 }
3928
3929 void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3930 {
3931         u32 tmp;
3932
3933         tmp = 0x1 | (0 << 1);
3934         WREG32(mmRLC_GPR_REG2, tmp);
3935 }
3936
3937 /**
3938  * gfx_v7_0_rlc_stop - stop the RLC ME
3939  *
3940  * @adev: amdgpu_device pointer
3941  *
3942  * Halt the RLC ME (MicroEngine) (CIK).
3943  */
3944 void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3945 {
3946         WREG32(mmRLC_CNTL, 0);
3947
3948         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3949
3950         gfx_v7_0_wait_for_rlc_serdes(adev);
3951 }
3952
3953 /**
3954  * gfx_v7_0_rlc_start - start the RLC ME
3955  *
3956  * @adev: amdgpu_device pointer
3957  *
3958  * Unhalt the RLC ME (MicroEngine) (CIK).
3959  */
3960 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3961 {
3962         WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3963
3964         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3965
3966         udelay(50);
3967 }
3968
3969 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3970 {
3971         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3972
3973         tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3974         WREG32(mmGRBM_SOFT_RESET, tmp);
3975         udelay(50);
3976         tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3977         WREG32(mmGRBM_SOFT_RESET, tmp);
3978         udelay(50);
3979 }
3980
3981 /**
3982  * gfx_v7_0_rlc_resume - setup the RLC hw
3983  *
3984  * @adev: amdgpu_device pointer
3985  *
3986  * Initialize the RLC registers, load the ucode,
3987  * and start the RLC (CIK).
3988  * Returns 0 for success, -EINVAL if the ucode is not available.
3989  */
3990 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3991 {
3992         const struct rlc_firmware_header_v1_0 *hdr;
3993         const __le32 *fw_data;
3994         unsigned i, fw_size;
3995         u32 tmp;
3996
3997         if (!adev->gfx.rlc_fw)
3998                 return -EINVAL;
3999
4000         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
4001         amdgpu_ucode_print_rlc_hdr(&hdr->header);
4002         adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
4003
4004         gfx_v7_0_rlc_stop(adev);
4005
4006         /* disable CG */
4007         tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
4008         WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
4009
4010         gfx_v7_0_rlc_reset(adev);
4011
4012         gfx_v7_0_init_pg(adev);
4013
4014         WREG32(mmRLC_LB_CNTR_INIT, 0);
4015         WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
4016
4017         mutex_lock(&adev->grbm_idx_mutex);
4018         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4019         WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
4020         WREG32(mmRLC_LB_PARAMS, 0x00600408);
4021         WREG32(mmRLC_LB_CNTL, 0x80000004);
4022         mutex_unlock(&adev->grbm_idx_mutex);
4023
4024         WREG32(mmRLC_MC_CNTL, 0);
4025         WREG32(mmRLC_UCODE_CNTL, 0);
4026
4027         fw_data = (const __le32 *)
4028                 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4029         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4030         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
4031         for (i = 0; i < fw_size; i++)
4032                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
4033         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4034
4035         /* XXX - find out what chips support lbpw */
4036         gfx_v7_0_enable_lbpw(adev, false);
4037
4038         if (adev->asic_type == CHIP_BONAIRE)
4039                 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
4040
4041         gfx_v7_0_rlc_start(adev);
4042
4043         return 0;
4044 }
4045
4046 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
4047 {
4048         u32 data, orig, tmp, tmp2;
4049
4050         orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
4051
4052         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGCG)) {
4053                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4054
4055                 tmp = gfx_v7_0_halt_rlc(adev);
4056
4057                 mutex_lock(&adev->grbm_idx_mutex);
4058                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4059                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
4060                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
4061                 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
4062                         RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
4063                         RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
4064                 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
4065                 mutex_unlock(&adev->grbm_idx_mutex);
4066
4067                 gfx_v7_0_update_rlc(adev, tmp);
4068
4069                 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4070         } else {
4071                 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4072
4073                 RREG32(mmCB_CGTT_SCLK_CTRL);
4074                 RREG32(mmCB_CGTT_SCLK_CTRL);
4075                 RREG32(mmCB_CGTT_SCLK_CTRL);
4076                 RREG32(mmCB_CGTT_SCLK_CTRL);
4077
4078                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4079         }
4080
4081         if (orig != data)
4082                 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
4083
4084 }
4085
4086 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
4087 {
4088         u32 data, orig, tmp = 0;
4089
4090         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGCG)) {
4091                 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) {
4092                         if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CP_LS) {
4093                                 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
4094                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4095                                 if (orig != data)
4096                                         WREG32(mmCP_MEM_SLP_CNTL, data);
4097                         }
4098                 }
4099
4100                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4101                 data |= 0x00000001;
4102                 data &= 0xfffffffd;
4103                 if (orig != data)
4104                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
4105
4106                 tmp = gfx_v7_0_halt_rlc(adev);
4107
4108                 mutex_lock(&adev->grbm_idx_mutex);
4109                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4110                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
4111                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
4112                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
4113                         RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
4114                 WREG32(mmRLC_SERDES_WR_CTRL, data);
4115                 mutex_unlock(&adev->grbm_idx_mutex);
4116
4117                 gfx_v7_0_update_rlc(adev, tmp);
4118
4119                 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS) {
4120                         orig = data = RREG32(mmCGTS_SM_CTRL_REG);
4121                         data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
4122                         data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
4123                         data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
4124                         data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
4125                         if ((adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) &&
4126                             (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS_LS))
4127                                 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
4128                         data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
4129                         data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
4130                         data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
4131                         if (orig != data)
4132                                 WREG32(mmCGTS_SM_CTRL_REG, data);
4133                 }
4134         } else {
4135                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4136                 data |= 0x00000003;
4137                 if (orig != data)
4138                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
4139
4140                 data = RREG32(mmRLC_MEM_SLP_CNTL);
4141                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4142                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4143                         WREG32(mmRLC_MEM_SLP_CNTL, data);
4144                 }
4145
4146                 data = RREG32(mmCP_MEM_SLP_CNTL);
4147                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4148                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4149                         WREG32(mmCP_MEM_SLP_CNTL, data);
4150                 }
4151
4152                 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
4153                 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
4154                 if (orig != data)
4155                         WREG32(mmCGTS_SM_CTRL_REG, data);
4156
4157                 tmp = gfx_v7_0_halt_rlc(adev);
4158
4159                 mutex_lock(&adev->grbm_idx_mutex);
4160                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4161                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
4162                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
4163                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
4164                 WREG32(mmRLC_SERDES_WR_CTRL, data);
4165                 mutex_unlock(&adev->grbm_idx_mutex);
4166
4167                 gfx_v7_0_update_rlc(adev, tmp);
4168         }
4169 }
4170
4171 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
4172                                bool enable)
4173 {
4174         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4175         /* order matters! */
4176         if (enable) {
4177                 gfx_v7_0_enable_mgcg(adev, true);
4178                 gfx_v7_0_enable_cgcg(adev, true);
4179         } else {
4180                 gfx_v7_0_enable_cgcg(adev, false);
4181                 gfx_v7_0_enable_mgcg(adev, false);
4182         }
4183         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4184 }
4185
4186 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
4187                                                 bool enable)
4188 {
4189         u32 data, orig;
4190
4191         orig = data = RREG32(mmRLC_PG_CNTL);
4192         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
4193                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
4194         else
4195                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
4196         if (orig != data)
4197                 WREG32(mmRLC_PG_CNTL, data);
4198 }
4199
4200 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
4201                                                 bool enable)
4202 {
4203         u32 data, orig;
4204
4205         orig = data = RREG32(mmRLC_PG_CNTL);
4206         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
4207                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
4208         else
4209                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
4210         if (orig != data)
4211                 WREG32(mmRLC_PG_CNTL, data);
4212 }
4213
4214 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
4215 {
4216         u32 data, orig;
4217
4218         orig = data = RREG32(mmRLC_PG_CNTL);
4219         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_CP))
4220                 data &= ~0x8000;
4221         else
4222                 data |= 0x8000;
4223         if (orig != data)
4224                 WREG32(mmRLC_PG_CNTL, data);
4225 }
4226
4227 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
4228 {
4229         u32 data, orig;
4230
4231         orig = data = RREG32(mmRLC_PG_CNTL);
4232         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GDS))
4233                 data &= ~0x2000;
4234         else
4235                 data |= 0x2000;
4236         if (orig != data)
4237                 WREG32(mmRLC_PG_CNTL, data);
4238 }
4239
4240 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
4241 {
4242         const __le32 *fw_data;
4243         volatile u32 *dst_ptr;
4244         int me, i, max_me = 4;
4245         u32 bo_offset = 0;
4246         u32 table_offset, table_size;
4247
4248         if (adev->asic_type == CHIP_KAVERI)
4249                 max_me = 5;
4250
4251         if (adev->gfx.rlc.cp_table_ptr == NULL)
4252                 return;
4253
4254         /* write the cp table buffer */
4255         dst_ptr = adev->gfx.rlc.cp_table_ptr;
4256         for (me = 0; me < max_me; me++) {
4257                 if (me == 0) {
4258                         const struct gfx_firmware_header_v1_0 *hdr =
4259                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4260                         fw_data = (const __le32 *)
4261                                 (adev->gfx.ce_fw->data +
4262                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4263                         table_offset = le32_to_cpu(hdr->jt_offset);
4264                         table_size = le32_to_cpu(hdr->jt_size);
4265                 } else if (me == 1) {
4266                         const struct gfx_firmware_header_v1_0 *hdr =
4267                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4268                         fw_data = (const __le32 *)
4269                                 (adev->gfx.pfp_fw->data +
4270                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4271                         table_offset = le32_to_cpu(hdr->jt_offset);
4272                         table_size = le32_to_cpu(hdr->jt_size);
4273                 } else if (me == 2) {
4274                         const struct gfx_firmware_header_v1_0 *hdr =
4275                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4276                         fw_data = (const __le32 *)
4277                                 (adev->gfx.me_fw->data +
4278                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4279                         table_offset = le32_to_cpu(hdr->jt_offset);
4280                         table_size = le32_to_cpu(hdr->jt_size);
4281                 } else if (me == 3) {
4282                         const struct gfx_firmware_header_v1_0 *hdr =
4283                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4284                         fw_data = (const __le32 *)
4285                                 (adev->gfx.mec_fw->data +
4286                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4287                         table_offset = le32_to_cpu(hdr->jt_offset);
4288                         table_size = le32_to_cpu(hdr->jt_size);
4289                 } else {
4290                         const struct gfx_firmware_header_v1_0 *hdr =
4291                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
4292                         fw_data = (const __le32 *)
4293                                 (adev->gfx.mec2_fw->data +
4294                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4295                         table_offset = le32_to_cpu(hdr->jt_offset);
4296                         table_size = le32_to_cpu(hdr->jt_size);
4297                 }
4298
4299                 for (i = 0; i < table_size; i ++) {
4300                         dst_ptr[bo_offset + i] =
4301                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
4302                 }
4303
4304                 bo_offset += table_size;
4305         }
4306 }
4307
4308 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
4309                                      bool enable)
4310 {
4311         u32 data, orig;
4312
4313         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)) {
4314                 orig = data = RREG32(mmRLC_PG_CNTL);
4315                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4316                 if (orig != data)
4317                         WREG32(mmRLC_PG_CNTL, data);
4318
4319                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4320                 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4321                 if (orig != data)
4322                         WREG32(mmRLC_AUTO_PG_CTRL, data);
4323         } else {
4324                 orig = data = RREG32(mmRLC_PG_CNTL);
4325                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4326                 if (orig != data)
4327                         WREG32(mmRLC_PG_CNTL, data);
4328
4329                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4330                 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4331                 if (orig != data)
4332                         WREG32(mmRLC_AUTO_PG_CTRL, data);
4333
4334                 data = RREG32(mmDB_RENDER_CONTROL);
4335         }
4336 }
4337
4338 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4339                                          u32 se, u32 sh)
4340 {
4341         u32 mask = 0, tmp, tmp1;
4342         int i;
4343
4344         gfx_v7_0_select_se_sh(adev, se, sh);
4345         tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4346         tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4347         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4348
4349         tmp &= 0xffff0000;
4350
4351         tmp |= tmp1;
4352         tmp >>= 16;
4353
4354         for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4355                 mask <<= 1;
4356                 mask |= 1;
4357         }
4358
4359         return (~tmp) & mask;
4360 }
4361
4362 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
4363 {
4364         uint32_t tmp, active_cu_number;
4365         struct amdgpu_cu_info cu_info;
4366
4367         gfx_v7_0_get_cu_info(adev, &cu_info);
4368         tmp = cu_info.ao_cu_mask;
4369         active_cu_number = cu_info.number;
4370
4371         WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, tmp);
4372
4373         tmp = RREG32(mmRLC_MAX_PG_CU);
4374         tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
4375         tmp |= (active_cu_number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
4376         WREG32(mmRLC_MAX_PG_CU, tmp);
4377 }
4378
4379 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
4380                                             bool enable)
4381 {
4382         u32 data, orig;
4383
4384         orig = data = RREG32(mmRLC_PG_CNTL);
4385         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG))
4386                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4387         else
4388                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4389         if (orig != data)
4390                 WREG32(mmRLC_PG_CNTL, data);
4391 }
4392
4393 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
4394                                              bool enable)
4395 {
4396         u32 data, orig;
4397
4398         orig = data = RREG32(mmRLC_PG_CNTL);
4399         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG))
4400                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4401         else
4402                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4403         if (orig != data)
4404                 WREG32(mmRLC_PG_CNTL, data);
4405 }
4406
4407 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
4408 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
4409
4410 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
4411 {
4412         u32 data, orig;
4413         u32 i;
4414
4415         if (adev->gfx.rlc.cs_data) {
4416                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4417                 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4418                 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4419                 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
4420         } else {
4421                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4422                 for (i = 0; i < 3; i++)
4423                         WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
4424         }
4425         if (adev->gfx.rlc.reg_list) {
4426                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
4427                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
4428                         WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
4429         }
4430
4431         orig = data = RREG32(mmRLC_PG_CNTL);
4432         data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
4433         if (orig != data)
4434                 WREG32(mmRLC_PG_CNTL, data);
4435
4436         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
4437         WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4438
4439         data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
4440         data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
4441         data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4442         WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
4443
4444         data = 0x10101010;
4445         WREG32(mmRLC_PG_DELAY, data);
4446
4447         data = RREG32(mmRLC_PG_DELAY_2);
4448         data &= ~0xff;
4449         data |= 0x3;
4450         WREG32(mmRLC_PG_DELAY_2, data);
4451
4452         data = RREG32(mmRLC_AUTO_PG_CTRL);
4453         data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
4454         data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
4455         WREG32(mmRLC_AUTO_PG_CTRL, data);
4456
4457 }
4458
4459 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
4460 {
4461         gfx_v7_0_enable_gfx_cgpg(adev, enable);
4462         gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
4463         gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
4464 }
4465
4466 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4467 {
4468         u32 count = 0;
4469         const struct cs_section_def *sect = NULL;
4470         const struct cs_extent_def *ext = NULL;
4471
4472         if (adev->gfx.rlc.cs_data == NULL)
4473                 return 0;
4474
4475         /* begin clear state */
4476         count += 2;
4477         /* context control state */
4478         count += 3;
4479
4480         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4481                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4482                         if (sect->id == SECT_CONTEXT)
4483                                 count += 2 + ext->reg_count;
4484                         else
4485                                 return 0;
4486                 }
4487         }
4488         /* pa_sc_raster_config/pa_sc_raster_config1 */
4489         count += 4;
4490         /* end clear state */
4491         count += 2;
4492         /* clear state */
4493         count += 2;
4494
4495         return count;
4496 }
4497
4498 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4499                                     volatile u32 *buffer)
4500 {
4501         u32 count = 0, i;
4502         const struct cs_section_def *sect = NULL;
4503         const struct cs_extent_def *ext = NULL;
4504
4505         if (adev->gfx.rlc.cs_data == NULL)
4506                 return;
4507         if (buffer == NULL)
4508                 return;
4509
4510         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4511         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4512
4513         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4514         buffer[count++] = cpu_to_le32(0x80000000);
4515         buffer[count++] = cpu_to_le32(0x80000000);
4516
4517         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4518                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4519                         if (sect->id == SECT_CONTEXT) {
4520                                 buffer[count++] =
4521                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4522                                 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4523                                 for (i = 0; i < ext->reg_count; i++)
4524                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4525                         } else {
4526                                 return;
4527                         }
4528                 }
4529         }
4530
4531         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4532         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4533         switch (adev->asic_type) {
4534         case CHIP_BONAIRE:
4535                 buffer[count++] = cpu_to_le32(0x16000012);
4536                 buffer[count++] = cpu_to_le32(0x00000000);
4537                 break;
4538         case CHIP_KAVERI:
4539                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4540                 buffer[count++] = cpu_to_le32(0x00000000);
4541                 break;
4542         case CHIP_KABINI:
4543         case CHIP_MULLINS:
4544                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4545                 buffer[count++] = cpu_to_le32(0x00000000);
4546                 break;
4547         case CHIP_HAWAII:
4548                 buffer[count++] = cpu_to_le32(0x3a00161a);
4549                 buffer[count++] = cpu_to_le32(0x0000002e);
4550                 break;
4551         default:
4552                 buffer[count++] = cpu_to_le32(0x00000000);
4553                 buffer[count++] = cpu_to_le32(0x00000000);
4554                 break;
4555         }
4556
4557         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4558         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4559
4560         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4561         buffer[count++] = cpu_to_le32(0);
4562 }
4563
4564 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4565 {
4566         if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
4567                               AMDGPU_PG_SUPPORT_GFX_SMG |
4568                               AMDGPU_PG_SUPPORT_GFX_DMG |
4569                               AMDGPU_PG_SUPPORT_CP |
4570                               AMDGPU_PG_SUPPORT_GDS |
4571                               AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
4572                 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4573                 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4574                 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
4575                         gfx_v7_0_init_gfx_cgpg(adev);
4576                         gfx_v7_0_enable_cp_pg(adev, true);
4577                         gfx_v7_0_enable_gds_pg(adev, true);
4578                 }
4579                 gfx_v7_0_init_ao_cu_mask(adev);
4580                 gfx_v7_0_update_gfx_pg(adev, true);
4581         }
4582 }
4583
4584 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4585 {
4586         if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
4587                               AMDGPU_PG_SUPPORT_GFX_SMG |
4588                               AMDGPU_PG_SUPPORT_GFX_DMG |
4589                               AMDGPU_PG_SUPPORT_CP |
4590                               AMDGPU_PG_SUPPORT_GDS |
4591                               AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
4592                 gfx_v7_0_update_gfx_pg(adev, false);
4593                 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
4594                         gfx_v7_0_enable_cp_pg(adev, false);
4595                         gfx_v7_0_enable_gds_pg(adev, false);
4596                 }
4597         }
4598 }
4599
4600 /**
4601  * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4602  *
4603  * @adev: amdgpu_device pointer
4604  *
4605  * Fetches a GPU clock counter snapshot (SI).
4606  * Returns the 64 bit clock counter snapshot.
4607  */
4608 uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4609 {
4610         uint64_t clock;
4611
4612         mutex_lock(&adev->gfx.gpu_clock_mutex);
4613         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4614         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4615                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4616         mutex_unlock(&adev->gfx.gpu_clock_mutex);
4617         return clock;
4618 }
4619
4620 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4621                                           uint32_t vmid,
4622                                           uint32_t gds_base, uint32_t gds_size,
4623                                           uint32_t gws_base, uint32_t gws_size,
4624                                           uint32_t oa_base, uint32_t oa_size)
4625 {
4626         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4627         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4628
4629         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4630         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4631
4632         oa_base = oa_base >> AMDGPU_OA_SHIFT;
4633         oa_size = oa_size >> AMDGPU_OA_SHIFT;
4634
4635         /* GDS Base */
4636         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4637         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4638                                 WRITE_DATA_DST_SEL(0)));
4639         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4640         amdgpu_ring_write(ring, 0);
4641         amdgpu_ring_write(ring, gds_base);
4642
4643         /* GDS Size */
4644         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4645         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4646                                 WRITE_DATA_DST_SEL(0)));
4647         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4648         amdgpu_ring_write(ring, 0);
4649         amdgpu_ring_write(ring, gds_size);
4650
4651         /* GWS */
4652         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4653         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4654                                 WRITE_DATA_DST_SEL(0)));
4655         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4656         amdgpu_ring_write(ring, 0);
4657         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4658
4659         /* OA */
4660         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4661         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4662                                 WRITE_DATA_DST_SEL(0)));
4663         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4664         amdgpu_ring_write(ring, 0);
4665         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4666 }
4667
4668 static int gfx_v7_0_early_init(void *handle)
4669 {
4670         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4671
4672         adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4673         adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
4674         gfx_v7_0_set_ring_funcs(adev);
4675         gfx_v7_0_set_irq_funcs(adev);
4676         gfx_v7_0_set_gds_init(adev);
4677
4678         return 0;
4679 }
4680
4681 static int gfx_v7_0_sw_init(void *handle)
4682 {
4683         struct amdgpu_ring *ring;
4684         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4685         int i, r;
4686
4687         /* EOP Event */
4688         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4689         if (r)
4690                 return r;
4691
4692         /* Privileged reg */
4693         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4694         if (r)
4695                 return r;
4696
4697         /* Privileged inst */
4698         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4699         if (r)
4700                 return r;
4701
4702         gfx_v7_0_scratch_init(adev);
4703
4704         r = gfx_v7_0_init_microcode(adev);
4705         if (r) {
4706                 DRM_ERROR("Failed to load gfx firmware!\n");
4707                 return r;
4708         }
4709
4710         r = gfx_v7_0_rlc_init(adev);
4711         if (r) {
4712                 DRM_ERROR("Failed to init rlc BOs!\n");
4713                 return r;
4714         }
4715
4716         /* allocate mec buffers */
4717         r = gfx_v7_0_mec_init(adev);
4718         if (r) {
4719                 DRM_ERROR("Failed to init MEC BOs!\n");
4720                 return r;
4721         }
4722
4723         r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
4724         if (r) {
4725                 DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
4726                 return r;
4727         }
4728
4729         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4730                 ring = &adev->gfx.gfx_ring[i];
4731                 ring->ring_obj = NULL;
4732                 sprintf(ring->name, "gfx");
4733                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
4734                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4735                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
4736                                      AMDGPU_RING_TYPE_GFX);
4737                 if (r)
4738                         return r;
4739         }
4740
4741         /* set up the compute queues */
4742         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4743                 unsigned irq_type;
4744
4745                 /* max 32 queues per MEC */
4746                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4747                         DRM_ERROR("Too many (%d) compute rings!\n", i);
4748                         break;
4749                 }
4750                 ring = &adev->gfx.compute_ring[i];
4751                 ring->ring_obj = NULL;
4752                 ring->use_doorbell = true;
4753                 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4754                 ring->me = 1; /* first MEC */
4755                 ring->pipe = i / 8;
4756                 ring->queue = i % 8;
4757                 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
4758                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4759                 /* type-2 packets are deprecated on MEC, use type-3 instead */
4760                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
4761                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4762                                      &adev->gfx.eop_irq, irq_type,
4763                                      AMDGPU_RING_TYPE_COMPUTE);
4764                 if (r)
4765                         return r;
4766         }
4767
4768         /* reserve GDS, GWS and OA resource for gfx */
4769         r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
4770                         PAGE_SIZE, true,
4771                         AMDGPU_GEM_DOMAIN_GDS, 0,
4772                         NULL, &adev->gds.gds_gfx_bo);
4773         if (r)
4774                 return r;
4775
4776         r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
4777                 PAGE_SIZE, true,
4778                 AMDGPU_GEM_DOMAIN_GWS, 0,
4779                 NULL, &adev->gds.gws_gfx_bo);
4780         if (r)
4781                 return r;
4782
4783         r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
4784                         PAGE_SIZE, true,
4785                         AMDGPU_GEM_DOMAIN_OA, 0,
4786                         NULL, &adev->gds.oa_gfx_bo);
4787         if (r)
4788                 return r;
4789
4790         return r;
4791 }
4792
4793 static int gfx_v7_0_sw_fini(void *handle)
4794 {
4795         int i;
4796         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4797
4798         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
4799         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
4800         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
4801
4802         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4803                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4804         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4805                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4806
4807         amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
4808
4809         gfx_v7_0_cp_compute_fini(adev);
4810         gfx_v7_0_rlc_fini(adev);
4811         gfx_v7_0_mec_fini(adev);
4812
4813         return 0;
4814 }
4815
4816 static int gfx_v7_0_hw_init(void *handle)
4817 {
4818         int r;
4819         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4820
4821         gfx_v7_0_gpu_init(adev);
4822
4823         /* init rlc */
4824         r = gfx_v7_0_rlc_resume(adev);
4825         if (r)
4826                 return r;
4827
4828         r = gfx_v7_0_cp_resume(adev);
4829         if (r)
4830                 return r;
4831
4832         adev->gfx.ce_ram_size = 0x8000;
4833
4834         return r;
4835 }
4836
4837 static int gfx_v7_0_hw_fini(void *handle)
4838 {
4839         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4840
4841         gfx_v7_0_cp_enable(adev, false);
4842         gfx_v7_0_rlc_stop(adev);
4843         gfx_v7_0_fini_pg(adev);
4844
4845         return 0;
4846 }
4847
4848 static int gfx_v7_0_suspend(void *handle)
4849 {
4850         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4851
4852         return gfx_v7_0_hw_fini(adev);
4853 }
4854
4855 static int gfx_v7_0_resume(void *handle)
4856 {
4857         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4858
4859         return gfx_v7_0_hw_init(adev);
4860 }
4861
4862 static bool gfx_v7_0_is_idle(void *handle)
4863 {
4864         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4865
4866         if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4867                 return false;
4868         else
4869                 return true;
4870 }
4871
4872 static int gfx_v7_0_wait_for_idle(void *handle)
4873 {
4874         unsigned i;
4875         u32 tmp;
4876         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4877
4878         for (i = 0; i < adev->usec_timeout; i++) {
4879                 /* read MC_STATUS */
4880                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4881
4882                 if (!tmp)
4883                         return 0;
4884                 udelay(1);
4885         }
4886         return -ETIMEDOUT;
4887 }
4888
4889 static void gfx_v7_0_print_status(void *handle)
4890 {
4891         int i;
4892         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4893
4894         dev_info(adev->dev, "GFX 7.x registers\n");
4895         dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
4896                 RREG32(mmGRBM_STATUS));
4897         dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
4898                 RREG32(mmGRBM_STATUS2));
4899         dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
4900                 RREG32(mmGRBM_STATUS_SE0));
4901         dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
4902                 RREG32(mmGRBM_STATUS_SE1));
4903         dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
4904                 RREG32(mmGRBM_STATUS_SE2));
4905         dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
4906                 RREG32(mmGRBM_STATUS_SE3));
4907         dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
4908         dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
4909                  RREG32(mmCP_STALLED_STAT1));
4910         dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
4911                  RREG32(mmCP_STALLED_STAT2));
4912         dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
4913                  RREG32(mmCP_STALLED_STAT3));
4914         dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
4915                  RREG32(mmCP_CPF_BUSY_STAT));
4916         dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
4917                  RREG32(mmCP_CPF_STALLED_STAT1));
4918         dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
4919         dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
4920         dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
4921                  RREG32(mmCP_CPC_STALLED_STAT1));
4922         dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
4923
4924         for (i = 0; i < 32; i++) {
4925                 dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
4926                          i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
4927         }
4928         for (i = 0; i < 16; i++) {
4929                 dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
4930                          i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
4931         }
4932         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4933                 dev_info(adev->dev, "  se: %d\n", i);
4934                 gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
4935                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
4936                          RREG32(mmPA_SC_RASTER_CONFIG));
4937                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
4938                          RREG32(mmPA_SC_RASTER_CONFIG_1));
4939         }
4940         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4941
4942         dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
4943                  RREG32(mmGB_ADDR_CONFIG));
4944         dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
4945                  RREG32(mmHDP_ADDR_CONFIG));
4946         dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
4947                  RREG32(mmDMIF_ADDR_CALC));
4948         dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
4949                  RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
4950         dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
4951                  RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
4952         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
4953                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
4954         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
4955                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
4956         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
4957                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
4958
4959         dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
4960                  RREG32(mmCP_MEQ_THRESHOLDS));
4961         dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
4962                  RREG32(mmSX_DEBUG_1));
4963         dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
4964                  RREG32(mmTA_CNTL_AUX));
4965         dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
4966                  RREG32(mmSPI_CONFIG_CNTL));
4967         dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
4968                  RREG32(mmSQ_CONFIG));
4969         dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
4970                  RREG32(mmDB_DEBUG));
4971         dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
4972                  RREG32(mmDB_DEBUG2));
4973         dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
4974                  RREG32(mmDB_DEBUG3));
4975         dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
4976                  RREG32(mmCB_HW_CONTROL));
4977         dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
4978                  RREG32(mmSPI_CONFIG_CNTL_1));
4979         dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
4980                  RREG32(mmPA_SC_FIFO_SIZE));
4981         dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
4982                  RREG32(mmVGT_NUM_INSTANCES));
4983         dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
4984                  RREG32(mmCP_PERFMON_CNTL));
4985         dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
4986                  RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
4987         dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
4988                  RREG32(mmVGT_CACHE_INVALIDATION));
4989         dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
4990                  RREG32(mmVGT_GS_VERTEX_REUSE));
4991         dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
4992                  RREG32(mmPA_SC_LINE_STIPPLE_STATE));
4993         dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
4994                  RREG32(mmPA_CL_ENHANCE));
4995         dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
4996                  RREG32(mmPA_SC_ENHANCE));
4997
4998         dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
4999                  RREG32(mmCP_ME_CNTL));
5000         dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
5001                  RREG32(mmCP_MAX_CONTEXT));
5002         dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
5003                  RREG32(mmCP_ENDIAN_SWAP));
5004         dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
5005                  RREG32(mmCP_DEVICE_ID));
5006
5007         dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
5008                  RREG32(mmCP_SEM_WAIT_TIMER));
5009         if (adev->asic_type != CHIP_HAWAII)
5010                 dev_info(adev->dev, "  CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
5011                          RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL));
5012
5013         dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
5014                  RREG32(mmCP_RB_WPTR_DELAY));
5015         dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
5016                  RREG32(mmCP_RB_VMID));
5017         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
5018                  RREG32(mmCP_RB0_CNTL));
5019         dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
5020                  RREG32(mmCP_RB0_WPTR));
5021         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
5022                  RREG32(mmCP_RB0_RPTR_ADDR));
5023         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
5024                  RREG32(mmCP_RB0_RPTR_ADDR_HI));
5025         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
5026                  RREG32(mmCP_RB0_CNTL));
5027         dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
5028                  RREG32(mmCP_RB0_BASE));
5029         dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
5030                  RREG32(mmCP_RB0_BASE_HI));
5031         dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
5032                  RREG32(mmCP_MEC_CNTL));
5033         dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
5034                  RREG32(mmCP_CPF_DEBUG));
5035
5036         dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
5037                  RREG32(mmSCRATCH_ADDR));
5038         dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
5039                  RREG32(mmSCRATCH_UMSK));
5040
5041         /* init the pipes */
5042         mutex_lock(&adev->srbm_mutex);
5043         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
5044                 int me = (i < 4) ? 1 : 2;
5045                 int pipe = (i < 4) ? i : (i - 4);
5046                 int queue;
5047
5048                 dev_info(adev->dev, "  me: %d, pipe: %d\n", me, pipe);
5049                 cik_srbm_select(adev, me, pipe, 0, 0);
5050                 dev_info(adev->dev, "  CP_HPD_EOP_BASE_ADDR=0x%08X\n",
5051                          RREG32(mmCP_HPD_EOP_BASE_ADDR));
5052                 dev_info(adev->dev, "  CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n",
5053                          RREG32(mmCP_HPD_EOP_BASE_ADDR_HI));
5054                 dev_info(adev->dev, "  CP_HPD_EOP_VMID=0x%08X\n",
5055                          RREG32(mmCP_HPD_EOP_VMID));
5056                 dev_info(adev->dev, "  CP_HPD_EOP_CONTROL=0x%08X\n",
5057                          RREG32(mmCP_HPD_EOP_CONTROL));
5058
5059                 for (queue = 0; queue < 8; i++) {
5060                         cik_srbm_select(adev, me, pipe, queue, 0);
5061                         dev_info(adev->dev, "  queue: %d\n", queue);
5062                         dev_info(adev->dev, "  CP_PQ_WPTR_POLL_CNTL=0x%08X\n",
5063                                  RREG32(mmCP_PQ_WPTR_POLL_CNTL));
5064                         dev_info(adev->dev, "  CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
5065                                  RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
5066                         dev_info(adev->dev, "  CP_HQD_ACTIVE=0x%08X\n",
5067                                  RREG32(mmCP_HQD_ACTIVE));
5068                         dev_info(adev->dev, "  CP_HQD_DEQUEUE_REQUEST=0x%08X\n",
5069                                  RREG32(mmCP_HQD_DEQUEUE_REQUEST));
5070                         dev_info(adev->dev, "  CP_HQD_PQ_RPTR=0x%08X\n",
5071                                  RREG32(mmCP_HQD_PQ_RPTR));
5072                         dev_info(adev->dev, "  CP_HQD_PQ_WPTR=0x%08X\n",
5073                                  RREG32(mmCP_HQD_PQ_WPTR));
5074                         dev_info(adev->dev, "  CP_HQD_PQ_BASE=0x%08X\n",
5075                                  RREG32(mmCP_HQD_PQ_BASE));
5076                         dev_info(adev->dev, "  CP_HQD_PQ_BASE_HI=0x%08X\n",
5077                                  RREG32(mmCP_HQD_PQ_BASE_HI));
5078                         dev_info(adev->dev, "  CP_HQD_PQ_CONTROL=0x%08X\n",
5079                                  RREG32(mmCP_HQD_PQ_CONTROL));
5080                         dev_info(adev->dev, "  CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n",
5081                                  RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR));
5082                         dev_info(adev->dev, "  CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n",
5083                                  RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI));
5084                         dev_info(adev->dev, "  CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n",
5085                                  RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR));
5086                         dev_info(adev->dev, "  CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n",
5087                                  RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI));
5088                         dev_info(adev->dev, "  CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
5089                                  RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
5090                         dev_info(adev->dev, "  CP_HQD_PQ_WPTR=0x%08X\n",
5091                                  RREG32(mmCP_HQD_PQ_WPTR));
5092                         dev_info(adev->dev, "  CP_HQD_VMID=0x%08X\n",
5093                                  RREG32(mmCP_HQD_VMID));
5094                         dev_info(adev->dev, "  CP_MQD_BASE_ADDR=0x%08X\n",
5095                                  RREG32(mmCP_MQD_BASE_ADDR));
5096                         dev_info(adev->dev, "  CP_MQD_BASE_ADDR_HI=0x%08X\n",
5097                                  RREG32(mmCP_MQD_BASE_ADDR_HI));
5098                         dev_info(adev->dev, "  CP_MQD_CONTROL=0x%08X\n",
5099                                  RREG32(mmCP_MQD_CONTROL));
5100                 }
5101         }
5102         cik_srbm_select(adev, 0, 0, 0, 0);
5103         mutex_unlock(&adev->srbm_mutex);
5104
5105         dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
5106                  RREG32(mmCP_INT_CNTL_RING0));
5107         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
5108                  RREG32(mmRLC_LB_CNTL));
5109         dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
5110                  RREG32(mmRLC_CNTL));
5111         dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
5112                  RREG32(mmRLC_CGCG_CGLS_CTRL));
5113         dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
5114                  RREG32(mmRLC_LB_CNTR_INIT));
5115         dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
5116                  RREG32(mmRLC_LB_CNTR_MAX));
5117         dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
5118                  RREG32(mmRLC_LB_INIT_CU_MASK));
5119         dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
5120                  RREG32(mmRLC_LB_PARAMS));
5121         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
5122                  RREG32(mmRLC_LB_CNTL));
5123         dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
5124                  RREG32(mmRLC_MC_CNTL));
5125         dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
5126                  RREG32(mmRLC_UCODE_CNTL));
5127
5128         if (adev->asic_type == CHIP_BONAIRE)
5129                 dev_info(adev->dev, "  RLC_DRIVER_CPDMA_STATUS=0x%08X\n",
5130                          RREG32(mmRLC_DRIVER_CPDMA_STATUS));
5131
5132         mutex_lock(&adev->srbm_mutex);
5133         for (i = 0; i < 16; i++) {
5134                 cik_srbm_select(adev, 0, 0, 0, i);
5135                 dev_info(adev->dev, "  VM %d:\n", i);
5136                 dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
5137                          RREG32(mmSH_MEM_CONFIG));
5138                 dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
5139                          RREG32(mmSH_MEM_APE1_BASE));
5140                 dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
5141                          RREG32(mmSH_MEM_APE1_LIMIT));
5142                 dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
5143                          RREG32(mmSH_MEM_BASES));
5144         }
5145         cik_srbm_select(adev, 0, 0, 0, 0);
5146         mutex_unlock(&adev->srbm_mutex);
5147 }
5148
5149 static int gfx_v7_0_soft_reset(void *handle)
5150 {
5151         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5152         u32 tmp;
5153         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5154
5155         /* GRBM_STATUS */
5156         tmp = RREG32(mmGRBM_STATUS);
5157         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
5158                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
5159                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
5160                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
5161                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
5162                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
5163                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
5164                         GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
5165
5166         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
5167                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
5168                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
5169         }
5170
5171         /* GRBM_STATUS2 */
5172         tmp = RREG32(mmGRBM_STATUS2);
5173         if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
5174                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
5175
5176         /* SRBM_STATUS */
5177         tmp = RREG32(mmSRBM_STATUS);
5178         if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
5179                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
5180
5181         if (grbm_soft_reset || srbm_soft_reset) {
5182                 gfx_v7_0_print_status((void *)adev);
5183                 /* disable CG/PG */
5184                 gfx_v7_0_fini_pg(adev);
5185                 gfx_v7_0_update_cg(adev, false);
5186
5187                 /* stop the rlc */
5188                 gfx_v7_0_rlc_stop(adev);
5189
5190                 /* Disable GFX parsing/prefetching */
5191                 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
5192
5193                 /* Disable MEC parsing/prefetching */
5194                 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
5195
5196                 if (grbm_soft_reset) {
5197                         tmp = RREG32(mmGRBM_SOFT_RESET);
5198                         tmp |= grbm_soft_reset;
5199                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5200                         WREG32(mmGRBM_SOFT_RESET, tmp);
5201                         tmp = RREG32(mmGRBM_SOFT_RESET);
5202
5203                         udelay(50);
5204
5205                         tmp &= ~grbm_soft_reset;
5206                         WREG32(mmGRBM_SOFT_RESET, tmp);
5207                         tmp = RREG32(mmGRBM_SOFT_RESET);
5208                 }
5209
5210                 if (srbm_soft_reset) {
5211                         tmp = RREG32(mmSRBM_SOFT_RESET);
5212                         tmp |= srbm_soft_reset;
5213                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5214                         WREG32(mmSRBM_SOFT_RESET, tmp);
5215                         tmp = RREG32(mmSRBM_SOFT_RESET);
5216
5217                         udelay(50);
5218
5219                         tmp &= ~srbm_soft_reset;
5220                         WREG32(mmSRBM_SOFT_RESET, tmp);
5221                         tmp = RREG32(mmSRBM_SOFT_RESET);
5222                 }
5223                 /* Wait a little for things to settle down */
5224                 udelay(50);
5225                 gfx_v7_0_print_status((void *)adev);
5226         }
5227         return 0;
5228 }
5229
5230 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5231                                                  enum amdgpu_interrupt_state state)
5232 {
5233         u32 cp_int_cntl;
5234
5235         switch (state) {
5236         case AMDGPU_IRQ_STATE_DISABLE:
5237                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5238                 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5239                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5240                 break;
5241         case AMDGPU_IRQ_STATE_ENABLE:
5242                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5243                 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5244                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5245                 break;
5246         default:
5247                 break;
5248         }
5249 }
5250
5251 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5252                                                      int me, int pipe,
5253                                                      enum amdgpu_interrupt_state state)
5254 {
5255         u32 mec_int_cntl, mec_int_cntl_reg;
5256
5257         /*
5258          * amdgpu controls only pipe 0 of MEC1. That's why this function only
5259          * handles the setting of interrupts for this specific pipe. All other
5260          * pipes' interrupts are set by amdkfd.
5261          */
5262
5263         if (me == 1) {
5264                 switch (pipe) {
5265                 case 0:
5266                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
5267                         break;
5268                 default:
5269                         DRM_DEBUG("invalid pipe %d\n", pipe);
5270                         return;
5271                 }
5272         } else {
5273                 DRM_DEBUG("invalid me %d\n", me);
5274                 return;
5275         }
5276
5277         switch (state) {
5278         case AMDGPU_IRQ_STATE_DISABLE:
5279                 mec_int_cntl = RREG32(mec_int_cntl_reg);
5280                 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5281                 WREG32(mec_int_cntl_reg, mec_int_cntl);
5282                 break;
5283         case AMDGPU_IRQ_STATE_ENABLE:
5284                 mec_int_cntl = RREG32(mec_int_cntl_reg);
5285                 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5286                 WREG32(mec_int_cntl_reg, mec_int_cntl);
5287                 break;
5288         default:
5289                 break;
5290         }
5291 }
5292
5293 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5294                                              struct amdgpu_irq_src *src,
5295                                              unsigned type,
5296                                              enum amdgpu_interrupt_state state)
5297 {
5298         u32 cp_int_cntl;
5299
5300         switch (state) {
5301         case AMDGPU_IRQ_STATE_DISABLE:
5302                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5303                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
5304                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5305                 break;
5306         case AMDGPU_IRQ_STATE_ENABLE:
5307                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5308                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
5309                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5310                 break;
5311         default:
5312                 break;
5313         }
5314
5315         return 0;
5316 }
5317
5318 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5319                                               struct amdgpu_irq_src *src,
5320                                               unsigned type,
5321                                               enum amdgpu_interrupt_state state)
5322 {
5323         u32 cp_int_cntl;
5324
5325         switch (state) {
5326         case AMDGPU_IRQ_STATE_DISABLE:
5327                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5328                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5329                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5330                 break;
5331         case AMDGPU_IRQ_STATE_ENABLE:
5332                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5333                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5334                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5335                 break;
5336         default:
5337                 break;
5338         }
5339
5340         return 0;
5341 }
5342
5343 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5344                                             struct amdgpu_irq_src *src,
5345                                             unsigned type,
5346                                             enum amdgpu_interrupt_state state)
5347 {
5348         switch (type) {
5349         case AMDGPU_CP_IRQ_GFX_EOP:
5350                 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
5351                 break;
5352         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5353                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5354                 break;
5355         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5356                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5357                 break;
5358         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5359                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5360                 break;
5361         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5362                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5363                 break;
5364         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5365                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5366                 break;
5367         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5368                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5369                 break;
5370         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5371                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5372                 break;
5373         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5374                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5375                 break;
5376         default:
5377                 break;
5378         }
5379         return 0;
5380 }
5381
5382 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
5383                             struct amdgpu_irq_src *source,
5384                             struct amdgpu_iv_entry *entry)
5385 {
5386         u8 me_id, pipe_id;
5387         struct amdgpu_ring *ring;
5388         int i;
5389
5390         DRM_DEBUG("IH: CP EOP\n");
5391         me_id = (entry->ring_id & 0x0c) >> 2;
5392         pipe_id = (entry->ring_id & 0x03) >> 0;
5393         switch (me_id) {
5394         case 0:
5395                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5396                 break;
5397         case 1:
5398         case 2:
5399                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5400                         ring = &adev->gfx.compute_ring[i];
5401                         if ((ring->me == me_id) & (ring->pipe == pipe_id))
5402                                 amdgpu_fence_process(ring);
5403                 }
5404                 break;
5405         }
5406         return 0;
5407 }
5408
5409 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
5410                                  struct amdgpu_irq_src *source,
5411                                  struct amdgpu_iv_entry *entry)
5412 {
5413         DRM_ERROR("Illegal register access in command stream\n");
5414         schedule_work(&adev->reset_work);
5415         return 0;
5416 }
5417
5418 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5419                                   struct amdgpu_irq_src *source,
5420                                   struct amdgpu_iv_entry *entry)
5421 {
5422         DRM_ERROR("Illegal instruction in command stream\n");
5423         // XXX soft reset the gfx block only
5424         schedule_work(&adev->reset_work);
5425         return 0;
5426 }
5427
5428 static int gfx_v7_0_set_clockgating_state(void *handle,
5429                                           enum amd_clockgating_state state)
5430 {
5431         bool gate = false;
5432         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5433
5434         if (state == AMD_CG_STATE_GATE)
5435                 gate = true;
5436
5437         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
5438         /* order matters! */
5439         if (gate) {
5440                 gfx_v7_0_enable_mgcg(adev, true);
5441                 gfx_v7_0_enable_cgcg(adev, true);
5442         } else {
5443                 gfx_v7_0_enable_cgcg(adev, false);
5444                 gfx_v7_0_enable_mgcg(adev, false);
5445         }
5446         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5447
5448         return 0;
5449 }
5450
5451 static int gfx_v7_0_set_powergating_state(void *handle,
5452                                           enum amd_powergating_state state)
5453 {
5454         bool gate = false;
5455         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5456
5457         if (state == AMD_PG_STATE_GATE)
5458                 gate = true;
5459
5460         if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
5461                               AMDGPU_PG_SUPPORT_GFX_SMG |
5462                               AMDGPU_PG_SUPPORT_GFX_DMG |
5463                               AMDGPU_PG_SUPPORT_CP |
5464                               AMDGPU_PG_SUPPORT_GDS |
5465                               AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
5466                 gfx_v7_0_update_gfx_pg(adev, gate);
5467                 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
5468                         gfx_v7_0_enable_cp_pg(adev, gate);
5469                         gfx_v7_0_enable_gds_pg(adev, gate);
5470                 }
5471         }
5472
5473         return 0;
5474 }
5475
5476 const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5477         .early_init = gfx_v7_0_early_init,
5478         .late_init = NULL,
5479         .sw_init = gfx_v7_0_sw_init,
5480         .sw_fini = gfx_v7_0_sw_fini,
5481         .hw_init = gfx_v7_0_hw_init,
5482         .hw_fini = gfx_v7_0_hw_fini,
5483         .suspend = gfx_v7_0_suspend,
5484         .resume = gfx_v7_0_resume,
5485         .is_idle = gfx_v7_0_is_idle,
5486         .wait_for_idle = gfx_v7_0_wait_for_idle,
5487         .soft_reset = gfx_v7_0_soft_reset,
5488         .print_status = gfx_v7_0_print_status,
5489         .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5490         .set_powergating_state = gfx_v7_0_set_powergating_state,
5491 };
5492
5493 /**
5494  * gfx_v7_0_ring_is_lockup - check if the 3D engine is locked up
5495  *
5496  * @adev: amdgpu_device pointer
5497  * @ring: amdgpu_ring structure holding ring information
5498  *
5499  * Check if the 3D engine is locked up (CIK).
5500  * Returns true if the engine is locked, false if not.
5501  */
5502 static bool gfx_v7_0_ring_is_lockup(struct amdgpu_ring *ring)
5503 {
5504         if (gfx_v7_0_is_idle(ring->adev)) {
5505                 amdgpu_ring_lockup_update(ring);
5506                 return false;
5507         }
5508         return amdgpu_ring_test_lockup(ring);
5509 }
5510
5511 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5512         .get_rptr = gfx_v7_0_ring_get_rptr_gfx,
5513         .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5514         .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5515         .parse_cs = NULL,
5516         .emit_ib = gfx_v7_0_ring_emit_ib,
5517         .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
5518         .emit_semaphore = gfx_v7_0_ring_emit_semaphore,
5519         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5520         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5521         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5522         .test_ring = gfx_v7_0_ring_test_ring,
5523         .test_ib = gfx_v7_0_ring_test_ib,
5524         .is_lockup = gfx_v7_0_ring_is_lockup,
5525 };
5526
5527 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5528         .get_rptr = gfx_v7_0_ring_get_rptr_compute,
5529         .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5530         .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5531         .parse_cs = NULL,
5532         .emit_ib = gfx_v7_0_ring_emit_ib,
5533         .emit_fence = gfx_v7_0_ring_emit_fence_compute,
5534         .emit_semaphore = gfx_v7_0_ring_emit_semaphore,
5535         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5536         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5537         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5538         .test_ring = gfx_v7_0_ring_test_ring,
5539         .test_ib = gfx_v7_0_ring_test_ib,
5540         .is_lockup = gfx_v7_0_ring_is_lockup,
5541 };
5542
5543 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5544 {
5545         int i;
5546
5547         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5548                 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5549         for (i = 0; i < adev->gfx.num_compute_rings; i++)
5550                 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5551 }
5552
5553 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5554         .set = gfx_v7_0_set_eop_interrupt_state,
5555         .process = gfx_v7_0_eop_irq,
5556 };
5557
5558 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5559         .set = gfx_v7_0_set_priv_reg_fault_state,
5560         .process = gfx_v7_0_priv_reg_irq,
5561 };
5562
5563 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5564         .set = gfx_v7_0_set_priv_inst_fault_state,
5565         .process = gfx_v7_0_priv_inst_irq,
5566 };
5567
5568 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5569 {
5570         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5571         adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5572
5573         adev->gfx.priv_reg_irq.num_types = 1;
5574         adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5575
5576         adev->gfx.priv_inst_irq.num_types = 1;
5577         adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5578 }
5579
5580 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5581 {
5582         /* init asci gds info */
5583         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5584         adev->gds.gws.total_size = 64;
5585         adev->gds.oa.total_size = 16;
5586
5587         if (adev->gds.mem.total_size == 64 * 1024) {
5588                 adev->gds.mem.gfx_partition_size = 4096;
5589                 adev->gds.mem.cs_partition_size = 4096;
5590
5591                 adev->gds.gws.gfx_partition_size = 4;
5592                 adev->gds.gws.cs_partition_size = 4;
5593
5594                 adev->gds.oa.gfx_partition_size = 4;
5595                 adev->gds.oa.cs_partition_size = 1;
5596         } else {
5597                 adev->gds.mem.gfx_partition_size = 1024;
5598                 adev->gds.mem.cs_partition_size = 1024;
5599
5600                 adev->gds.gws.gfx_partition_size = 16;
5601                 adev->gds.gws.cs_partition_size = 16;
5602
5603                 adev->gds.oa.gfx_partition_size = 4;
5604                 adev->gds.oa.cs_partition_size = 4;
5605         }
5606 }
5607
5608
5609 int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
5610                                                                    struct amdgpu_cu_info *cu_info)
5611 {
5612         int i, j, k, counter, active_cu_number = 0;
5613         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5614
5615         if (!adev || !cu_info)
5616                 return -EINVAL;
5617
5618         mutex_lock(&adev->grbm_idx_mutex);
5619         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5620                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5621                         mask = 1;
5622                         ao_bitmap = 0;
5623                         counter = 0;
5624                         bitmap = gfx_v7_0_get_cu_active_bitmap(adev, i, j);
5625                         cu_info->bitmap[i][j] = bitmap;
5626
5627                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
5628                                 if (bitmap & mask) {
5629                                         if (counter < 2)
5630                                                 ao_bitmap |= mask;
5631                                         counter ++;
5632                                 }
5633                                 mask <<= 1;
5634                         }
5635                         active_cu_number += counter;
5636                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5637                 }
5638         }
5639
5640         cu_info->number = active_cu_number;
5641         cu_info->ao_cu_mask = ao_cu_mask;
5642         mutex_unlock(&adev->grbm_idx_mutex);
5643         return 0;
5644 }