drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_ih.h"
  29 #include "amdgpu_gfx.h"
  30 #include "cikd.h"
  31 #include "cik.h"
  32 #include "cik_structs.h"
  33 #include "atom.h"
  34 #include "amdgpu_ucode.h"
  35 #include "clearstate_ci.h"
  36
  37 #include "dce/dce_8_0_d.h"
  38 #include "dce/dce_8_0_sh_mask.h"
  39
  40 #include "bif/bif_4_1_d.h"
  41 #include "bif/bif_4_1_sh_mask.h"
  42
  43 #include "gca/gfx_7_0_d.h"
  44 #include "gca/gfx_7_2_enum.h"
  45 #include "gca/gfx_7_2_sh_mask.h"
  46
  47 #include "gmc/gmc_7_0_d.h"
  48 #include "gmc/gmc_7_0_sh_mask.h"
  49
  50 #include "oss/oss_2_0_d.h"
  51 #include "oss/oss_2_0_sh_mask.h"
  52
  53 #define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */
  54
  55 #define GFX7_NUM_GFX_RINGS     1
  56 #define GFX7_MEC_HPD_SIZE      2048
  57
  58 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  59 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  60 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
  61
  62 MODULE_FIRMWARE("amdgpu/bonaire_pfp.bin");
  63 MODULE_FIRMWARE("amdgpu/bonaire_me.bin");
  64 MODULE_FIRMWARE("amdgpu/bonaire_ce.bin");
  65 MODULE_FIRMWARE("amdgpu/bonaire_rlc.bin");
  66 MODULE_FIRMWARE("amdgpu/bonaire_mec.bin");
  67
  68 MODULE_FIRMWARE("amdgpu/hawaii_pfp.bin");
  69 MODULE_FIRMWARE("amdgpu/hawaii_me.bin");
  70 MODULE_FIRMWARE("amdgpu/hawaii_ce.bin");
  71 MODULE_FIRMWARE("amdgpu/hawaii_rlc.bin");
  72 MODULE_FIRMWARE("amdgpu/hawaii_mec.bin");
  73
  74 MODULE_FIRMWARE("amdgpu/kaveri_pfp.bin");
  75 MODULE_FIRMWARE("amdgpu/kaveri_me.bin");
  76 MODULE_FIRMWARE("amdgpu/kaveri_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/kaveri_rlc.bin");
  78 MODULE_FIRMWARE("amdgpu/kaveri_mec.bin");
  79 MODULE_FIRMWARE("amdgpu/kaveri_mec2.bin");
  80
  81 MODULE_FIRMWARE("amdgpu/kabini_pfp.bin");
  82 MODULE_FIRMWARE("amdgpu/kabini_me.bin");
  83 MODULE_FIRMWARE("amdgpu/kabini_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/kabini_rlc.bin");
  85 MODULE_FIRMWARE("amdgpu/kabini_mec.bin");
  86
  87 MODULE_FIRMWARE("amdgpu/mullins_pfp.bin");
  88 MODULE_FIRMWARE("amdgpu/mullins_me.bin");
  89 MODULE_FIRMWARE("amdgpu/mullins_ce.bin");
  90 MODULE_FIRMWARE("amdgpu/mullins_rlc.bin");
  91 MODULE_FIRMWARE("amdgpu/mullins_mec.bin");
  92
  93 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = {
  94         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  95         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  96         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  97         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  98         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
  99         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
 100         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
 101         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 102         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 103         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 104         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 105         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 106         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 107         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 108         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 109         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 110 };
 111
 112 static const u32 spectre_rlc_save_restore_register_list[] = {
 113         (0x0e00 << 16) | (0xc12c >> 2),
 114         0x00000000,
 115         (0x0e00 << 16) | (0xc140 >> 2),
 116         0x00000000,
 117         (0x0e00 << 16) | (0xc150 >> 2),
 118         0x00000000,
 119         (0x0e00 << 16) | (0xc15c >> 2),
 120         0x00000000,
 121         (0x0e00 << 16) | (0xc168 >> 2),
 122         0x00000000,
 123         (0x0e00 << 16) | (0xc170 >> 2),
 124         0x00000000,
 125         (0x0e00 << 16) | (0xc178 >> 2),
 126         0x00000000,
 127         (0x0e00 << 16) | (0xc204 >> 2),
 128         0x00000000,
 129         (0x0e00 << 16) | (0xc2b4 >> 2),
 130         0x00000000,
 131         (0x0e00 << 16) | (0xc2b8 >> 2),
 132         0x00000000,
 133         (0x0e00 << 16) | (0xc2bc >> 2),
 134         0x00000000,
 135         (0x0e00 << 16) | (0xc2c0 >> 2),
 136         0x00000000,
 137         (0x0e00 << 16) | (0x8228 >> 2),
 138         0x00000000,
 139         (0x0e00 << 16) | (0x829c >> 2),
 140         0x00000000,
 141         (0x0e00 << 16) | (0x869c >> 2),
 142         0x00000000,
 143         (0x0600 << 16) | (0x98f4 >> 2),
 144         0x00000000,
 145         (0x0e00 << 16) | (0x98f8 >> 2),
 146         0x00000000,
 147         (0x0e00 << 16) | (0x9900 >> 2),
 148         0x00000000,
 149         (0x0e00 << 16) | (0xc260 >> 2),
 150         0x00000000,
 151         (0x0e00 << 16) | (0x90e8 >> 2),
 152         0x00000000,
 153         (0x0e00 << 16) | (0x3c000 >> 2),
 154         0x00000000,
 155         (0x0e00 << 16) | (0x3c00c >> 2),
 156         0x00000000,
 157         (0x0e00 << 16) | (0x8c1c >> 2),
 158         0x00000000,
 159         (0x0e00 << 16) | (0x9700 >> 2),
 160         0x00000000,
 161         (0x0e00 << 16) | (0xcd20 >> 2),
 162         0x00000000,
 163         (0x4e00 << 16) | (0xcd20 >> 2),
 164         0x00000000,
 165         (0x5e00 << 16) | (0xcd20 >> 2),
 166         0x00000000,
 167         (0x6e00 << 16) | (0xcd20 >> 2),
 168         0x00000000,
 169         (0x7e00 << 16) | (0xcd20 >> 2),
 170         0x00000000,
 171         (0x8e00 << 16) | (0xcd20 >> 2),
 172         0x00000000,
 173         (0x9e00 << 16) | (0xcd20 >> 2),
 174         0x00000000,
 175         (0xae00 << 16) | (0xcd20 >> 2),
 176         0x00000000,
 177         (0xbe00 << 16) | (0xcd20 >> 2),
 178         0x00000000,
 179         (0x0e00 << 16) | (0x89bc >> 2),
 180         0x00000000,
 181         (0x0e00 << 16) | (0x8900 >> 2),
 182         0x00000000,
 183         0x3,
 184         (0x0e00 << 16) | (0xc130 >> 2),
 185         0x00000000,
 186         (0x0e00 << 16) | (0xc134 >> 2),
 187         0x00000000,
 188         (0x0e00 << 16) | (0xc1fc >> 2),
 189         0x00000000,
 190         (0x0e00 << 16) | (0xc208 >> 2),
 191         0x00000000,
 192         (0x0e00 << 16) | (0xc264 >> 2),
 193         0x00000000,
 194         (0x0e00 << 16) | (0xc268 >> 2),
 195         0x00000000,
 196         (0x0e00 << 16) | (0xc26c >> 2),
 197         0x00000000,
 198         (0x0e00 << 16) | (0xc270 >> 2),
 199         0x00000000,
 200         (0x0e00 << 16) | (0xc274 >> 2),
 201         0x00000000,
 202         (0x0e00 << 16) | (0xc278 >> 2),
 203         0x00000000,
 204         (0x0e00 << 16) | (0xc27c >> 2),
 205         0x00000000,
 206         (0x0e00 << 16) | (0xc280 >> 2),
 207         0x00000000,
 208         (0x0e00 << 16) | (0xc284 >> 2),
 209         0x00000000,
 210         (0x0e00 << 16) | (0xc288 >> 2),
 211         0x00000000,
 212         (0x0e00 << 16) | (0xc28c >> 2),
 213         0x00000000,
 214         (0x0e00 << 16) | (0xc290 >> 2),
 215         0x00000000,
 216         (0x0e00 << 16) | (0xc294 >> 2),
 217         0x00000000,
 218         (0x0e00 << 16) | (0xc298 >> 2),
 219         0x00000000,
 220         (0x0e00 << 16) | (0xc29c >> 2),
 221         0x00000000,
 222         (0x0e00 << 16) | (0xc2a0 >> 2),
 223         0x00000000,
 224         (0x0e00 << 16) | (0xc2a4 >> 2),
 225         0x00000000,
 226         (0x0e00 << 16) | (0xc2a8 >> 2),
 227         0x00000000,
 228         (0x0e00 << 16) | (0xc2ac  >> 2),
 229         0x00000000,
 230         (0x0e00 << 16) | (0xc2b0 >> 2),
 231         0x00000000,
 232         (0x0e00 << 16) | (0x301d0 >> 2),
 233         0x00000000,
 234         (0x0e00 << 16) | (0x30238 >> 2),
 235         0x00000000,
 236         (0x0e00 << 16) | (0x30250 >> 2),
 237         0x00000000,
 238         (0x0e00 << 16) | (0x30254 >> 2),
 239         0x00000000,
 240         (0x0e00 << 16) | (0x30258 >> 2),
 241         0x00000000,
 242         (0x0e00 << 16) | (0x3025c >> 2),
 243         0x00000000,
 244         (0x4e00 << 16) | (0xc900 >> 2),
 245         0x00000000,
 246         (0x5e00 << 16) | (0xc900 >> 2),
 247         0x00000000,
 248         (0x6e00 << 16) | (0xc900 >> 2),
 249         0x00000000,
 250         (0x7e00 << 16) | (0xc900 >> 2),
 251         0x00000000,
 252         (0x8e00 << 16) | (0xc900 >> 2),
 253         0x00000000,
 254         (0x9e00 << 16) | (0xc900 >> 2),
 255         0x00000000,
 256         (0xae00 << 16) | (0xc900 >> 2),
 257         0x00000000,
 258         (0xbe00 << 16) | (0xc900 >> 2),
 259         0x00000000,
 260         (0x4e00 << 16) | (0xc904 >> 2),
 261         0x00000000,
 262         (0x5e00 << 16) | (0xc904 >> 2),
 263         0x00000000,
 264         (0x6e00 << 16) | (0xc904 >> 2),
 265         0x00000000,
 266         (0x7e00 << 16) | (0xc904 >> 2),
 267         0x00000000,
 268         (0x8e00 << 16) | (0xc904 >> 2),
 269         0x00000000,
 270         (0x9e00 << 16) | (0xc904 >> 2),
 271         0x00000000,
 272         (0xae00 << 16) | (0xc904 >> 2),
 273         0x00000000,
 274         (0xbe00 << 16) | (0xc904 >> 2),
 275         0x00000000,
 276         (0x4e00 << 16) | (0xc908 >> 2),
 277         0x00000000,
 278         (0x5e00 << 16) | (0xc908 >> 2),
 279         0x00000000,
 280         (0x6e00 << 16) | (0xc908 >> 2),
 281         0x00000000,
 282         (0x7e00 << 16) | (0xc908 >> 2),
 283         0x00000000,
 284         (0x8e00 << 16) | (0xc908 >> 2),
 285         0x00000000,
 286         (0x9e00 << 16) | (0xc908 >> 2),
 287         0x00000000,
 288         (0xae00 << 16) | (0xc908 >> 2),
 289         0x00000000,
 290         (0xbe00 << 16) | (0xc908 >> 2),
 291         0x00000000,
 292         (0x4e00 << 16) | (0xc90c >> 2),
 293         0x00000000,
 294         (0x5e00 << 16) | (0xc90c >> 2),
 295         0x00000000,
 296         (0x6e00 << 16) | (0xc90c >> 2),
 297         0x00000000,
 298         (0x7e00 << 16) | (0xc90c >> 2),
 299         0x00000000,
 300         (0x8e00 << 16) | (0xc90c >> 2),
 301         0x00000000,
 302         (0x9e00 << 16) | (0xc90c >> 2),
 303         0x00000000,
 304         (0xae00 << 16) | (0xc90c >> 2),
 305         0x00000000,
 306         (0xbe00 << 16) | (0xc90c >> 2),
 307         0x00000000,
 308         (0x4e00 << 16) | (0xc910 >> 2),
 309         0x00000000,
 310         (0x5e00 << 16) | (0xc910 >> 2),
 311         0x00000000,
 312         (0x6e00 << 16) | (0xc910 >> 2),
 313         0x00000000,
 314         (0x7e00 << 16) | (0xc910 >> 2),
 315         0x00000000,
 316         (0x8e00 << 16) | (0xc910 >> 2),
 317         0x00000000,
 318         (0x9e00 << 16) | (0xc910 >> 2),
 319         0x00000000,
 320         (0xae00 << 16) | (0xc910 >> 2),
 321         0x00000000,
 322         (0xbe00 << 16) | (0xc910 >> 2),
 323         0x00000000,
 324         (0x0e00 << 16) | (0xc99c >> 2),
 325         0x00000000,
 326         (0x0e00 << 16) | (0x9834 >> 2),
 327         0x00000000,
 328         (0x0000 << 16) | (0x30f00 >> 2),
 329         0x00000000,
 330         (0x0001 << 16) | (0x30f00 >> 2),
 331         0x00000000,
 332         (0x0000 << 16) | (0x30f04 >> 2),
 333         0x00000000,
 334         (0x0001 << 16) | (0x30f04 >> 2),
 335         0x00000000,
 336         (0x0000 << 16) | (0x30f08 >> 2),
 337         0x00000000,
 338         (0x0001 << 16) | (0x30f08 >> 2),
 339         0x00000000,
 340         (0x0000 << 16) | (0x30f0c >> 2),
 341         0x00000000,
 342         (0x0001 << 16) | (0x30f0c >> 2),
 343         0x00000000,
 344         (0x0600 << 16) | (0x9b7c >> 2),
 345         0x00000000,
 346         (0x0e00 << 16) | (0x8a14 >> 2),
 347         0x00000000,
 348         (0x0e00 << 16) | (0x8a18 >> 2),
 349         0x00000000,
 350         (0x0600 << 16) | (0x30a00 >> 2),
 351         0x00000000,
 352         (0x0e00 << 16) | (0x8bf0 >> 2),
 353         0x00000000,
 354         (0x0e00 << 16) | (0x8bcc >> 2),
 355         0x00000000,
 356         (0x0e00 << 16) | (0x8b24 >> 2),
 357         0x00000000,
 358         (0x0e00 << 16) | (0x30a04 >> 2),
 359         0x00000000,
 360         (0x0600 << 16) | (0x30a10 >> 2),
 361         0x00000000,
 362         (0x0600 << 16) | (0x30a14 >> 2),
 363         0x00000000,
 364         (0x0600 << 16) | (0x30a18 >> 2),
 365         0x00000000,
 366         (0x0600 << 16) | (0x30a2c >> 2),
 367         0x00000000,
 368         (0x0e00 << 16) | (0xc700 >> 2),
 369         0x00000000,
 370         (0x0e00 << 16) | (0xc704 >> 2),
 371         0x00000000,
 372         (0x0e00 << 16) | (0xc708 >> 2),
 373         0x00000000,
 374         (0x0e00 << 16) | (0xc768 >> 2),
 375         0x00000000,
 376         (0x0400 << 16) | (0xc770 >> 2),
 377         0x00000000,
 378         (0x0400 << 16) | (0xc774 >> 2),
 379         0x00000000,
 380         (0x0400 << 16) | (0xc778 >> 2),
 381         0x00000000,
 382         (0x0400 << 16) | (0xc77c >> 2),
 383         0x00000000,
 384         (0x0400 << 16) | (0xc780 >> 2),
 385         0x00000000,
 386         (0x0400 << 16) | (0xc784 >> 2),
 387         0x00000000,
 388         (0x0400 << 16) | (0xc788 >> 2),
 389         0x00000000,
 390         (0x0400 << 16) | (0xc78c >> 2),
 391         0x00000000,
 392         (0x0400 << 16) | (0xc798 >> 2),
 393         0x00000000,
 394         (0x0400 << 16) | (0xc79c >> 2),
 395         0x00000000,
 396         (0x0400 << 16) | (0xc7a0 >> 2),
 397         0x00000000,
 398         (0x0400 << 16) | (0xc7a4 >> 2),
 399         0x00000000,
 400         (0x0400 << 16) | (0xc7a8 >> 2),
 401         0x00000000,
 402         (0x0400 << 16) | (0xc7ac >> 2),
 403         0x00000000,
 404         (0x0400 << 16) | (0xc7b0 >> 2),
 405         0x00000000,
 406         (0x0400 << 16) | (0xc7b4 >> 2),
 407         0x00000000,
 408         (0x0e00 << 16) | (0x9100 >> 2),
 409         0x00000000,
 410         (0x0e00 << 16) | (0x3c010 >> 2),
 411         0x00000000,
 412         (0x0e00 << 16) | (0x92a8 >> 2),
 413         0x00000000,
 414         (0x0e00 << 16) | (0x92ac >> 2),
 415         0x00000000,
 416         (0x0e00 << 16) | (0x92b4 >> 2),
 417         0x00000000,
 418         (0x0e00 << 16) | (0x92b8 >> 2),
 419         0x00000000,
 420         (0x0e00 << 16) | (0x92bc >> 2),
 421         0x00000000,
 422         (0x0e00 << 16) | (0x92c0 >> 2),
 423         0x00000000,
 424         (0x0e00 << 16) | (0x92c4 >> 2),
 425         0x00000000,
 426         (0x0e00 << 16) | (0x92c8 >> 2),
 427         0x00000000,
 428         (0x0e00 << 16) | (0x92cc >> 2),
 429         0x00000000,
 430         (0x0e00 << 16) | (0x92d0 >> 2),
 431         0x00000000,
 432         (0x0e00 << 16) | (0x8c00 >> 2),
 433         0x00000000,
 434         (0x0e00 << 16) | (0x8c04 >> 2),
 435         0x00000000,
 436         (0x0e00 << 16) | (0x8c20 >> 2),
 437         0x00000000,
 438         (0x0e00 << 16) | (0x8c38 >> 2),
 439         0x00000000,
 440         (0x0e00 << 16) | (0x8c3c >> 2),
 441         0x00000000,
 442         (0x0e00 << 16) | (0xae00 >> 2),
 443         0x00000000,
 444         (0x0e00 << 16) | (0x9604 >> 2),
 445         0x00000000,
 446         (0x0e00 << 16) | (0xac08 >> 2),
 447         0x00000000,
 448         (0x0e00 << 16) | (0xac0c >> 2),
 449         0x00000000,
 450         (0x0e00 << 16) | (0xac10 >> 2),
 451         0x00000000,
 452         (0x0e00 << 16) | (0xac14 >> 2),
 453         0x00000000,
 454         (0x0e00 << 16) | (0xac58 >> 2),
 455         0x00000000,
 456         (0x0e00 << 16) | (0xac68 >> 2),
 457         0x00000000,
 458         (0x0e00 << 16) | (0xac6c >> 2),
 459         0x00000000,
 460         (0x0e00 << 16) | (0xac70 >> 2),
 461         0x00000000,
 462         (0x0e00 << 16) | (0xac74 >> 2),
 463         0x00000000,
 464         (0x0e00 << 16) | (0xac78 >> 2),
 465         0x00000000,
 466         (0x0e00 << 16) | (0xac7c >> 2),
 467         0x00000000,
 468         (0x0e00 << 16) | (0xac80 >> 2),
 469         0x00000000,
 470         (0x0e00 << 16) | (0xac84 >> 2),
 471         0x00000000,
 472         (0x0e00 << 16) | (0xac88 >> 2),
 473         0x00000000,
 474         (0x0e00 << 16) | (0xac8c >> 2),
 475         0x00000000,
 476         (0x0e00 << 16) | (0x970c >> 2),
 477         0x00000000,
 478         (0x0e00 << 16) | (0x9714 >> 2),
 479         0x00000000,
 480         (0x0e00 << 16) | (0x9718 >> 2),
 481         0x00000000,
 482         (0x0e00 << 16) | (0x971c >> 2),
 483         0x00000000,
 484         (0x0e00 << 16) | (0x31068 >> 2),
 485         0x00000000,
 486         (0x4e00 << 16) | (0x31068 >> 2),
 487         0x00000000,
 488         (0x5e00 << 16) | (0x31068 >> 2),
 489         0x00000000,
 490         (0x6e00 << 16) | (0x31068 >> 2),
 491         0x00000000,
 492         (0x7e00 << 16) | (0x31068 >> 2),
 493         0x00000000,
 494         (0x8e00 << 16) | (0x31068 >> 2),
 495         0x00000000,
 496         (0x9e00 << 16) | (0x31068 >> 2),
 497         0x00000000,
 498         (0xae00 << 16) | (0x31068 >> 2),
 499         0x00000000,
 500         (0xbe00 << 16) | (0x31068 >> 2),
 501         0x00000000,
 502         (0x0e00 << 16) | (0xcd10 >> 2),
 503         0x00000000,
 504         (0x0e00 << 16) | (0xcd14 >> 2),
 505         0x00000000,
 506         (0x0e00 << 16) | (0x88b0 >> 2),
 507         0x00000000,
 508         (0x0e00 << 16) | (0x88b4 >> 2),
 509         0x00000000,
 510         (0x0e00 << 16) | (0x88b8 >> 2),
 511         0x00000000,
 512         (0x0e00 << 16) | (0x88bc >> 2),
 513         0x00000000,
 514         (0x0400 << 16) | (0x89c0 >> 2),
 515         0x00000000,
 516         (0x0e00 << 16) | (0x88c4 >> 2),
 517         0x00000000,
 518         (0x0e00 << 16) | (0x88c8 >> 2),
 519         0x00000000,
 520         (0x0e00 << 16) | (0x88d0 >> 2),
 521         0x00000000,
 522         (0x0e00 << 16) | (0x88d4 >> 2),
 523         0x00000000,
 524         (0x0e00 << 16) | (0x88d8 >> 2),
 525         0x00000000,
 526         (0x0e00 << 16) | (0x8980 >> 2),
 527         0x00000000,
 528         (0x0e00 << 16) | (0x30938 >> 2),
 529         0x00000000,
 530         (0x0e00 << 16) | (0x3093c >> 2),
 531         0x00000000,
 532         (0x0e00 << 16) | (0x30940 >> 2),
 533         0x00000000,
 534         (0x0e00 << 16) | (0x89a0 >> 2),
 535         0x00000000,
 536         (0x0e00 << 16) | (0x30900 >> 2),
 537         0x00000000,
 538         (0x0e00 << 16) | (0x30904 >> 2),
 539         0x00000000,
 540         (0x0e00 << 16) | (0x89b4 >> 2),
 541         0x00000000,
 542         (0x0e00 << 16) | (0x3c210 >> 2),
 543         0x00000000,
 544         (0x0e00 << 16) | (0x3c214 >> 2),
 545         0x00000000,
 546         (0x0e00 << 16) | (0x3c218 >> 2),
 547         0x00000000,
 548         (0x0e00 << 16) | (0x8904 >> 2),
 549         0x00000000,
 550         0x5,
 551         (0x0e00 << 16) | (0x8c28 >> 2),
 552         (0x0e00 << 16) | (0x8c2c >> 2),
 553         (0x0e00 << 16) | (0x8c30 >> 2),
 554         (0x0e00 << 16) | (0x8c34 >> 2),
 555         (0x0e00 << 16) | (0x9600 >> 2),
 556 };
 557
 558 static const u32 kalindi_rlc_save_restore_register_list[] = {
 559         (0x0e00 << 16) | (0xc12c >> 2),
 560         0x00000000,
 561         (0x0e00 << 16) | (0xc140 >> 2),
 562         0x00000000,
 563         (0x0e00 << 16) | (0xc150 >> 2),
 564         0x00000000,
 565         (0x0e00 << 16) | (0xc15c >> 2),
 566         0x00000000,
 567         (0x0e00 << 16) | (0xc168 >> 2),
 568         0x00000000,
 569         (0x0e00 << 16) | (0xc170 >> 2),
 570         0x00000000,
 571         (0x0e00 << 16) | (0xc204 >> 2),
 572         0x00000000,
 573         (0x0e00 << 16) | (0xc2b4 >> 2),
 574         0x00000000,
 575         (0x0e00 << 16) | (0xc2b8 >> 2),
 576         0x00000000,
 577         (0x0e00 << 16) | (0xc2bc >> 2),
 578         0x00000000,
 579         (0x0e00 << 16) | (0xc2c0 >> 2),
 580         0x00000000,
 581         (0x0e00 << 16) | (0x8228 >> 2),
 582         0x00000000,
 583         (0x0e00 << 16) | (0x829c >> 2),
 584         0x00000000,
 585         (0x0e00 << 16) | (0x869c >> 2),
 586         0x00000000,
 587         (0x0600 << 16) | (0x98f4 >> 2),
 588         0x00000000,
 589         (0x0e00 << 16) | (0x98f8 >> 2),
 590         0x00000000,
 591         (0x0e00 << 16) | (0x9900 >> 2),
 592         0x00000000,
 593         (0x0e00 << 16) | (0xc260 >> 2),
 594         0x00000000,
 595         (0x0e00 << 16) | (0x90e8 >> 2),
 596         0x00000000,
 597         (0x0e00 << 16) | (0x3c000 >> 2),
 598         0x00000000,
 599         (0x0e00 << 16) | (0x3c00c >> 2),
 600         0x00000000,
 601         (0x0e00 << 16) | (0x8c1c >> 2),
 602         0x00000000,
 603         (0x0e00 << 16) | (0x9700 >> 2),
 604         0x00000000,
 605         (0x0e00 << 16) | (0xcd20 >> 2),
 606         0x00000000,
 607         (0x4e00 << 16) | (0xcd20 >> 2),
 608         0x00000000,
 609         (0x5e00 << 16) | (0xcd20 >> 2),
 610         0x00000000,
 611         (0x6e00 << 16) | (0xcd20 >> 2),
 612         0x00000000,
 613         (0x7e00 << 16) | (0xcd20 >> 2),
 614         0x00000000,
 615         (0x0e00 << 16) | (0x89bc >> 2),
 616         0x00000000,
 617         (0x0e00 << 16) | (0x8900 >> 2),
 618         0x00000000,
 619         0x3,
 620         (0x0e00 << 16) | (0xc130 >> 2),
 621         0x00000000,
 622         (0x0e00 << 16) | (0xc134 >> 2),
 623         0x00000000,
 624         (0x0e00 << 16) | (0xc1fc >> 2),
 625         0x00000000,
 626         (0x0e00 << 16) | (0xc208 >> 2),
 627         0x00000000,
 628         (0x0e00 << 16) | (0xc264 >> 2),
 629         0x00000000,
 630         (0x0e00 << 16) | (0xc268 >> 2),
 631         0x00000000,
 632         (0x0e00 << 16) | (0xc26c >> 2),
 633         0x00000000,
 634         (0x0e00 << 16) | (0xc270 >> 2),
 635         0x00000000,
 636         (0x0e00 << 16) | (0xc274 >> 2),
 637         0x00000000,
 638         (0x0e00 << 16) | (0xc28c >> 2),
 639         0x00000000,
 640         (0x0e00 << 16) | (0xc290 >> 2),
 641         0x00000000,
 642         (0x0e00 << 16) | (0xc294 >> 2),
 643         0x00000000,
 644         (0x0e00 << 16) | (0xc298 >> 2),
 645         0x00000000,
 646         (0x0e00 << 16) | (0xc2a0 >> 2),
 647         0x00000000,
 648         (0x0e00 << 16) | (0xc2a4 >> 2),
 649         0x00000000,
 650         (0x0e00 << 16) | (0xc2a8 >> 2),
 651         0x00000000,
 652         (0x0e00 << 16) | (0xc2ac >> 2),
 653         0x00000000,
 654         (0x0e00 << 16) | (0x301d0 >> 2),
 655         0x00000000,
 656         (0x0e00 << 16) | (0x30238 >> 2),
 657         0x00000000,
 658         (0x0e00 << 16) | (0x30250 >> 2),
 659         0x00000000,
 660         (0x0e00 << 16) | (0x30254 >> 2),
 661         0x00000000,
 662         (0x0e00 << 16) | (0x30258 >> 2),
 663         0x00000000,
 664         (0x0e00 << 16) | (0x3025c >> 2),
 665         0x00000000,
 666         (0x4e00 << 16) | (0xc900 >> 2),
 667         0x00000000,
 668         (0x5e00 << 16) | (0xc900 >> 2),
 669         0x00000000,
 670         (0x6e00 << 16) | (0xc900 >> 2),
 671         0x00000000,
 672         (0x7e00 << 16) | (0xc900 >> 2),
 673         0x00000000,
 674         (0x4e00 << 16) | (0xc904 >> 2),
 675         0x00000000,
 676         (0x5e00 << 16) | (0xc904 >> 2),
 677         0x00000000,
 678         (0x6e00 << 16) | (0xc904 >> 2),
 679         0x00000000,
 680         (0x7e00 << 16) | (0xc904 >> 2),
 681         0x00000000,
 682         (0x4e00 << 16) | (0xc908 >> 2),
 683         0x00000000,
 684         (0x5e00 << 16) | (0xc908 >> 2),
 685         0x00000000,
 686         (0x6e00 << 16) | (0xc908 >> 2),
 687         0x00000000,
 688         (0x7e00 << 16) | (0xc908 >> 2),
 689         0x00000000,
 690         (0x4e00 << 16) | (0xc90c >> 2),
 691         0x00000000,
 692         (0x5e00 << 16) | (0xc90c >> 2),
 693         0x00000000,
 694         (0x6e00 << 16) | (0xc90c >> 2),
 695         0x00000000,
 696         (0x7e00 << 16) | (0xc90c >> 2),
 697         0x00000000,
 698         (0x4e00 << 16) | (0xc910 >> 2),
 699         0x00000000,
 700         (0x5e00 << 16) | (0xc910 >> 2),
 701         0x00000000,
 702         (0x6e00 << 16) | (0xc910 >> 2),
 703         0x00000000,
 704         (0x7e00 << 16) | (0xc910 >> 2),
 705         0x00000000,
 706         (0x0e00 << 16) | (0xc99c >> 2),
 707         0x00000000,
 708         (0x0e00 << 16) | (0x9834 >> 2),
 709         0x00000000,
 710         (0x0000 << 16) | (0x30f00 >> 2),
 711         0x00000000,
 712         (0x0000 << 16) | (0x30f04 >> 2),
 713         0x00000000,
 714         (0x0000 << 16) | (0x30f08 >> 2),
 715         0x00000000,
 716         (0x0000 << 16) | (0x30f0c >> 2),
 717         0x00000000,
 718         (0x0600 << 16) | (0x9b7c >> 2),
 719         0x00000000,
 720         (0x0e00 << 16) | (0x8a14 >> 2),
 721         0x00000000,
 722         (0x0e00 << 16) | (0x8a18 >> 2),
 723         0x00000000,
 724         (0x0600 << 16) | (0x30a00 >> 2),
 725         0x00000000,
 726         (0x0e00 << 16) | (0x8bf0 >> 2),
 727         0x00000000,
 728         (0x0e00 << 16) | (0x8bcc >> 2),
 729         0x00000000,
 730         (0x0e00 << 16) | (0x8b24 >> 2),
 731         0x00000000,
 732         (0x0e00 << 16) | (0x30a04 >> 2),
 733         0x00000000,
 734         (0x0600 << 16) | (0x30a10 >> 2),
 735         0x00000000,
 736         (0x0600 << 16) | (0x30a14 >> 2),
 737         0x00000000,
 738         (0x0600 << 16) | (0x30a18 >> 2),
 739         0x00000000,
 740         (0x0600 << 16) | (0x30a2c >> 2),
 741         0x00000000,
 742         (0x0e00 << 16) | (0xc700 >> 2),
 743         0x00000000,
 744         (0x0e00 << 16) | (0xc704 >> 2),
 745         0x00000000,
 746         (0x0e00 << 16) | (0xc708 >> 2),
 747         0x00000000,
 748         (0x0e00 << 16) | (0xc768 >> 2),
 749         0x00000000,
 750         (0x0400 << 16) | (0xc770 >> 2),
 751         0x00000000,
 752         (0x0400 << 16) | (0xc774 >> 2),
 753         0x00000000,
 754         (0x0400 << 16) | (0xc798 >> 2),
 755         0x00000000,
 756         (0x0400 << 16) | (0xc79c >> 2),
 757         0x00000000,
 758         (0x0e00 << 16) | (0x9100 >> 2),
 759         0x00000000,
 760         (0x0e00 << 16) | (0x3c010 >> 2),
 761         0x00000000,
 762         (0x0e00 << 16) | (0x8c00 >> 2),
 763         0x00000000,
 764         (0x0e00 << 16) | (0x8c04 >> 2),
 765         0x00000000,
 766         (0x0e00 << 16) | (0x8c20 >> 2),
 767         0x00000000,
 768         (0x0e00 << 16) | (0x8c38 >> 2),
 769         0x00000000,
 770         (0x0e00 << 16) | (0x8c3c >> 2),
 771         0x00000000,
 772         (0x0e00 << 16) | (0xae00 >> 2),
 773         0x00000000,
 774         (0x0e00 << 16) | (0x9604 >> 2),
 775         0x00000000,
 776         (0x0e00 << 16) | (0xac08 >> 2),
 777         0x00000000,
 778         (0x0e00 << 16) | (0xac0c >> 2),
 779         0x00000000,
 780         (0x0e00 << 16) | (0xac10 >> 2),
 781         0x00000000,
 782         (0x0e00 << 16) | (0xac14 >> 2),
 783         0x00000000,
 784         (0x0e00 << 16) | (0xac58 >> 2),
 785         0x00000000,
 786         (0x0e00 << 16) | (0xac68 >> 2),
 787         0x00000000,
 788         (0x0e00 << 16) | (0xac6c >> 2),
 789         0x00000000,
 790         (0x0e00 << 16) | (0xac70 >> 2),
 791         0x00000000,
 792         (0x0e00 << 16) | (0xac74 >> 2),
 793         0x00000000,
 794         (0x0e00 << 16) | (0xac78 >> 2),
 795         0x00000000,
 796         (0x0e00 << 16) | (0xac7c >> 2),
 797         0x00000000,
 798         (0x0e00 << 16) | (0xac80 >> 2),
 799         0x00000000,
 800         (0x0e00 << 16) | (0xac84 >> 2),
 801         0x00000000,
 802         (0x0e00 << 16) | (0xac88 >> 2),
 803         0x00000000,
 804         (0x0e00 << 16) | (0xac8c >> 2),
 805         0x00000000,
 806         (0x0e00 << 16) | (0x970c >> 2),
 807         0x00000000,
 808         (0x0e00 << 16) | (0x9714 >> 2),
 809         0x00000000,
 810         (0x0e00 << 16) | (0x9718 >> 2),
 811         0x00000000,
 812         (0x0e00 << 16) | (0x971c >> 2),
 813         0x00000000,
 814         (0x0e00 << 16) | (0x31068 >> 2),
 815         0x00000000,
 816         (0x4e00 << 16) | (0x31068 >> 2),
 817         0x00000000,
 818         (0x5e00 << 16) | (0x31068 >> 2),
 819         0x00000000,
 820         (0x6e00 << 16) | (0x31068 >> 2),
 821         0x00000000,
 822         (0x7e00 << 16) | (0x31068 >> 2),
 823         0x00000000,
 824         (0x0e00 << 16) | (0xcd10 >> 2),
 825         0x00000000,
 826         (0x0e00 << 16) | (0xcd14 >> 2),
 827         0x00000000,
 828         (0x0e00 << 16) | (0x88b0 >> 2),
 829         0x00000000,
 830         (0x0e00 << 16) | (0x88b4 >> 2),
 831         0x00000000,
 832         (0x0e00 << 16) | (0x88b8 >> 2),
 833         0x00000000,
 834         (0x0e00 << 16) | (0x88bc >> 2),
 835         0x00000000,
 836         (0x0400 << 16) | (0x89c0 >> 2),
 837         0x00000000,
 838         (0x0e00 << 16) | (0x88c4 >> 2),
 839         0x00000000,
 840         (0x0e00 << 16) | (0x88c8 >> 2),
 841         0x00000000,
 842         (0x0e00 << 16) | (0x88d0 >> 2),
 843         0x00000000,
 844         (0x0e00 << 16) | (0x88d4 >> 2),
 845         0x00000000,
 846         (0x0e00 << 16) | (0x88d8 >> 2),
 847         0x00000000,
 848         (0x0e00 << 16) | (0x8980 >> 2),
 849         0x00000000,
 850         (0x0e00 << 16) | (0x30938 >> 2),
 851         0x00000000,
 852         (0x0e00 << 16) | (0x3093c >> 2),
 853         0x00000000,
 854         (0x0e00 << 16) | (0x30940 >> 2),
 855         0x00000000,
 856         (0x0e00 << 16) | (0x89a0 >> 2),
 857         0x00000000,
 858         (0x0e00 << 16) | (0x30900 >> 2),
 859         0x00000000,
 860         (0x0e00 << 16) | (0x30904 >> 2),
 861         0x00000000,
 862         (0x0e00 << 16) | (0x89b4 >> 2),
 863         0x00000000,
 864         (0x0e00 << 16) | (0x3e1fc >> 2),
 865         0x00000000,
 866         (0x0e00 << 16) | (0x3c210 >> 2),
 867         0x00000000,
 868         (0x0e00 << 16) | (0x3c214 >> 2),
 869         0x00000000,
 870         (0x0e00 << 16) | (0x3c218 >> 2),
 871         0x00000000,
 872         (0x0e00 << 16) | (0x8904 >> 2),
 873         0x00000000,
 874         0x5,
 875         (0x0e00 << 16) | (0x8c28 >> 2),
 876         (0x0e00 << 16) | (0x8c2c >> 2),
 877         (0x0e00 << 16) | (0x8c30 >> 2),
 878         (0x0e00 << 16) | (0x8c34 >> 2),
 879         (0x0e00 << 16) | (0x9600 >> 2),
 880 };
 881
 882 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
 883 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
 884 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
 885 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
 886
 887 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
 888 {
 889         amdgpu_ucode_release(&adev->gfx.pfp_fw);
 890         amdgpu_ucode_release(&adev->gfx.me_fw);
 891         amdgpu_ucode_release(&adev->gfx.ce_fw);
 892         amdgpu_ucode_release(&adev->gfx.mec_fw);
 893         amdgpu_ucode_release(&adev->gfx.mec2_fw);
 894         amdgpu_ucode_release(&adev->gfx.rlc_fw);
 895 }
 896
 897 /*
 898  * Core functions
 899  */
 900 /**
 901  * gfx_v7_0_init_microcode - load ucode images from disk
 902  *
 903  * @adev: amdgpu_device pointer
 904  *
 905  * Use the firmware interface to load the ucode images into
 906  * the driver (not loaded into hw).
 907  * Returns 0 on success, error on failure.
 908  */
 909 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
 910 {
 911         const char *chip_name;
 912         int err;
 913
 914         DRM_DEBUG("\n");
 915
 916         switch (adev->asic_type) {
 917         case CHIP_BONAIRE:
 918                 chip_name = "bonaire";
 919                 break;
 920         case CHIP_HAWAII:
 921                 chip_name = "hawaii";
 922                 break;
 923         case CHIP_KAVERI:
 924                 chip_name = "kaveri";
 925                 break;
 926         case CHIP_KABINI:
 927                 chip_name = "kabini";
 928                 break;
 929         case CHIP_MULLINS:
 930                 chip_name = "mullins";
 931                 break;
 932         default:
 933                 BUG();
 934         }
 935
 936         err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
 937                                    AMDGPU_UCODE_REQUIRED,
 938                                    "amdgpu/%s_pfp.bin", chip_name);
 939         if (err)
 940                 goto out;
 941
 942         err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
 943                                    AMDGPU_UCODE_REQUIRED,
 944                                    "amdgpu/%s_me.bin", chip_name);
 945         if (err)
 946                 goto out;
 947
 948         err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
 949                                    AMDGPU_UCODE_REQUIRED,
 950                                    "amdgpu/%s_ce.bin", chip_name);
 951         if (err)
 952                 goto out;
 953
 954         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
 955                                    AMDGPU_UCODE_REQUIRED,
 956                                    "amdgpu/%s_mec.bin", chip_name);
 957         if (err)
 958                 goto out;
 959
 960         if (adev->asic_type == CHIP_KAVERI) {
 961                 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
 962                                            AMDGPU_UCODE_REQUIRED,
 963                                            "amdgpu/%s_mec2.bin", chip_name);
 964                 if (err)
 965                         goto out;
 966         }
 967
 968         err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
 969                                    AMDGPU_UCODE_REQUIRED,
 970                                    "amdgpu/%s_rlc.bin", chip_name);
 971 out:
 972         if (err) {
 973                 pr_err("gfx7: Failed to load firmware %s gfx firmware\n", chip_name);
 974                 gfx_v7_0_free_microcode(adev);
 975         }
 976         return err;
 977 }
 978
 979 /**
 980  * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
 981  *
 982  * @adev: amdgpu_device pointer
 983  *
 984  * Starting with SI, the tiling setup is done globally in a
 985  * set of 32 tiling modes.  Rather than selecting each set of
 986  * parameters per surface as on older asics, we just select
 987  * which index in the tiling table we want to use, and the
 988  * surface uses those parameters (CIK).
 989  */
 990 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
 991 {
 992         const u32 num_tile_mode_states =
 993                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
 994         const u32 num_secondary_tile_mode_states =
 995                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
 996         u32 reg_offset, split_equal_to_row_size;
 997         uint32_t *tile, *macrotile;
 998
 999         tile = adev->gfx.config.tile_mode_array;
1000         macrotile = adev->gfx.config.macrotile_mode_array;
1001
1002         switch (adev->gfx.config.mem_row_size_in_kb) {
1003         case 1:
1004                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1005                 break;
1006         case 2:
1007         default:
1008                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1009                 break;
1010         case 4:
1011                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1012                 break;
1013         }
1014
1015         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1016                 tile[reg_offset] = 0;
1017         for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1018                 macrotile[reg_offset] = 0;
1019
1020         switch (adev->asic_type) {
1021         case CHIP_BONAIRE:
1022                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1023                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1024                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1025                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1026                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1027                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1028                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1029                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1030                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1031                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1032                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1033                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1034                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1035                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1036                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1037                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1038                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1039                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1040                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1041                            TILE_SPLIT(split_equal_to_row_size));
1042                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1043                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1044                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1045                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1046                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1047                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1048                            TILE_SPLIT(split_equal_to_row_size));
1049                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1050                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1051                            PIPE_CONFIG(ADDR_SURF_P4_16x16));
1052                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1053                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1054                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1055                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1056                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1057                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1058                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1059                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1060                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1061                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1062                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1063                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1064                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1065                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1066                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1067                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1068                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1069                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1070                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1071                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1072                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1073                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1074                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1075                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1076                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1077                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1078                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1079                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1080                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1081                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1082                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1083                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1084                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1085                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1086                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1087                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1088                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1089                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1090                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1091                 tile[21] =  (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1092                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1093                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1094                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1095                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1096                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1097                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1098                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1099                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1100                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1101                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1102                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1103                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1104                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1105                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1106                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1107                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1108                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1109                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1110                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1111                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1112                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1113                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1114                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1115                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1116                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1118                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1119                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1120                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1121                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1122                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1123                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1124
1125                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1126                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1127                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1128                                 NUM_BANKS(ADDR_SURF_16_BANK));
1129                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1130                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1131                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1132                                 NUM_BANKS(ADDR_SURF_16_BANK));
1133                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1134                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1135                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1136                                 NUM_BANKS(ADDR_SURF_16_BANK));
1137                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1138                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1139                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1140                                 NUM_BANKS(ADDR_SURF_16_BANK));
1141                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1142                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1143                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1144                                 NUM_BANKS(ADDR_SURF_16_BANK));
1145                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1146                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1147                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1148                                 NUM_BANKS(ADDR_SURF_8_BANK));
1149                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1150                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1151                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1152                                 NUM_BANKS(ADDR_SURF_4_BANK));
1153                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1154                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1155                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1156                                 NUM_BANKS(ADDR_SURF_16_BANK));
1157                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1158                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1159                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1160                                 NUM_BANKS(ADDR_SURF_16_BANK));
1161                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1162                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1163                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1164                                 NUM_BANKS(ADDR_SURF_16_BANK));
1165                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1166                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1167                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1168                                 NUM_BANKS(ADDR_SURF_16_BANK));
1169                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1171                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1172                                 NUM_BANKS(ADDR_SURF_16_BANK));
1173                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1174                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1175                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1176                                 NUM_BANKS(ADDR_SURF_8_BANK));
1177                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1178                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1179                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1180                                 NUM_BANKS(ADDR_SURF_4_BANK));
1181
1182                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1183                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1184                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1185                         if (reg_offset != 7)
1186                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1187                 break;
1188         case CHIP_HAWAII:
1189                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1190                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1191                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1192                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1193                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1194                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1195                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1196                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1197                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1198                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1199                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1200                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1201                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1202                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1203                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1204                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1205                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1206                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1207                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1208                            TILE_SPLIT(split_equal_to_row_size));
1209                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1210                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1211                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1212                            TILE_SPLIT(split_equal_to_row_size));
1213                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1214                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1215                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1216                            TILE_SPLIT(split_equal_to_row_size));
1217                 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1218                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1219                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1220                            TILE_SPLIT(split_equal_to_row_size));
1221                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1222                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1223                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1224                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1225                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1226                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1227                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1228                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1229                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1230                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1231                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1232                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1233                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1234                 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1235                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1236                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1237                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1238                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1239                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1240                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1241                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1242                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1243                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1244                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1245                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1246                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1247                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1248                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1249                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1250                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1251                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1252                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1253                 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1254                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1255                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1256                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1257                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1258                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1259                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1260                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1261                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1262                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1263                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1264                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1265                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1266                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1267                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1268                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1269                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1270                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1271                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1272                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1273                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1274                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1275                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1276                 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1277                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1278                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1279                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1280                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1281                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1282                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1283                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1284                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1285                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1286                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1287                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1288                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1289                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1290                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1291                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1292                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1293                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1294                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1295                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1296                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1298                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1299                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1300                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1301                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1302                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1303                 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1304                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1305                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1306                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1307
1308                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1309                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1310                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1311                                 NUM_BANKS(ADDR_SURF_16_BANK));
1312                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1313                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1314                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1315                                 NUM_BANKS(ADDR_SURF_16_BANK));
1316                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1317                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1318                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1319                                 NUM_BANKS(ADDR_SURF_16_BANK));
1320                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1321                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1322                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1323                                 NUM_BANKS(ADDR_SURF_16_BANK));
1324                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1325                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1326                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1327                                 NUM_BANKS(ADDR_SURF_8_BANK));
1328                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1329                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1330                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1331                                 NUM_BANKS(ADDR_SURF_4_BANK));
1332                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1333                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1334                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1335                                 NUM_BANKS(ADDR_SURF_4_BANK));
1336                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1337                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1338                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1339                                 NUM_BANKS(ADDR_SURF_16_BANK));
1340                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1341                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1342                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1343                                 NUM_BANKS(ADDR_SURF_16_BANK));
1344                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1345                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1346                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1347                                 NUM_BANKS(ADDR_SURF_16_BANK));
1348                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1349                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1350                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1351                                 NUM_BANKS(ADDR_SURF_8_BANK));
1352                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1353                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1354                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1355                                 NUM_BANKS(ADDR_SURF_16_BANK));
1356                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1357                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1358                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1359                                 NUM_BANKS(ADDR_SURF_8_BANK));
1360                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1361                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1362                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1363                                 NUM_BANKS(ADDR_SURF_4_BANK));
1364
1365                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1366                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1367                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1368                         if (reg_offset != 7)
1369                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1370                 break;
1371         case CHIP_KABINI:
1372         case CHIP_KAVERI:
1373         case CHIP_MULLINS:
1374         default:
1375                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1376                            PIPE_CONFIG(ADDR_SURF_P2) |
1377                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1378                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1379                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1380                            PIPE_CONFIG(ADDR_SURF_P2) |
1381                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1382                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1383                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1384                            PIPE_CONFIG(ADDR_SURF_P2) |
1385                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1386                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1387                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1388                            PIPE_CONFIG(ADDR_SURF_P2) |
1389                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1390                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1391                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1392                            PIPE_CONFIG(ADDR_SURF_P2) |
1393                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1394                            TILE_SPLIT(split_equal_to_row_size));
1395                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1396                            PIPE_CONFIG(ADDR_SURF_P2) |
1397                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1398                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1399                            PIPE_CONFIG(ADDR_SURF_P2) |
1400                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1401                            TILE_SPLIT(split_equal_to_row_size));
1402                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1403                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1404                            PIPE_CONFIG(ADDR_SURF_P2));
1405                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1406                            PIPE_CONFIG(ADDR_SURF_P2) |
1407                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1408                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1409                             PIPE_CONFIG(ADDR_SURF_P2) |
1410                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1411                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1412                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1413                             PIPE_CONFIG(ADDR_SURF_P2) |
1414                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1415                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1416                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1417                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1418                             PIPE_CONFIG(ADDR_SURF_P2) |
1419                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1420                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1421                             PIPE_CONFIG(ADDR_SURF_P2) |
1422                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1423                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1424                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1425                             PIPE_CONFIG(ADDR_SURF_P2) |
1426                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1427                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1428                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1429                             PIPE_CONFIG(ADDR_SURF_P2) |
1430                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1431                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1432                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1433                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1434                             PIPE_CONFIG(ADDR_SURF_P2) |
1435                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1436                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1437                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1438                             PIPE_CONFIG(ADDR_SURF_P2) |
1439                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1440                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1441                             PIPE_CONFIG(ADDR_SURF_P2) |
1442                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1443                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1444                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1445                             PIPE_CONFIG(ADDR_SURF_P2) |
1446                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1447                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1448                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1449                             PIPE_CONFIG(ADDR_SURF_P2) |
1450                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1451                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1452                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1453                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1454                             PIPE_CONFIG(ADDR_SURF_P2) |
1455                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1456                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1457                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1458                             PIPE_CONFIG(ADDR_SURF_P2) |
1459                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1460                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1461                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1462                             PIPE_CONFIG(ADDR_SURF_P2) |
1463                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1464                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1465                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1466                             PIPE_CONFIG(ADDR_SURF_P2) |
1467                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1468                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1469                             PIPE_CONFIG(ADDR_SURF_P2) |
1470                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1471                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1472                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1473                             PIPE_CONFIG(ADDR_SURF_P2) |
1474                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1475                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1476                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1477
1478                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1479                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1480                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1481                                 NUM_BANKS(ADDR_SURF_8_BANK));
1482                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1483                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1484                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1485                                 NUM_BANKS(ADDR_SURF_8_BANK));
1486                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1487                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1488                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1489                                 NUM_BANKS(ADDR_SURF_8_BANK));
1490                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1491                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1492                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1493                                 NUM_BANKS(ADDR_SURF_8_BANK));
1494                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1495                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1496                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1497                                 NUM_BANKS(ADDR_SURF_8_BANK));
1498                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1499                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1500                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1501                                 NUM_BANKS(ADDR_SURF_8_BANK));
1502                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1503                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1504                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1505                                 NUM_BANKS(ADDR_SURF_8_BANK));
1506                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1507                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1508                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1509                                 NUM_BANKS(ADDR_SURF_16_BANK));
1510                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1511                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1512                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1513                                 NUM_BANKS(ADDR_SURF_16_BANK));
1514                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1515                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1516                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1517                                 NUM_BANKS(ADDR_SURF_16_BANK));
1518                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1519                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1520                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1521                                 NUM_BANKS(ADDR_SURF_16_BANK));
1522                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1523                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1524                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1525                                 NUM_BANKS(ADDR_SURF_16_BANK));
1526                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1527                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1528                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1529                                 NUM_BANKS(ADDR_SURF_16_BANK));
1530                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1531                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1532                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1533                                 NUM_BANKS(ADDR_SURF_8_BANK));
1534
1535                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1536                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1537                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1538                         if (reg_offset != 7)
1539                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1540                 break;
1541         }
1542 }
1543
1544 /**
1545  * gfx_v7_0_select_se_sh - select which SE, SH to address
1546  *
1547  * @adev: amdgpu_device pointer
1548  * @se_num: shader engine to address
1549  * @sh_num: sh block to address
1550  * @instance: Certain registers are instanced per SE or SH.
1551  *            0xffffffff means broadcast to all SEs or SHs (CIK).
1552  * @xcc_id: xcc accelerated compute core id
1553  * Select which SE, SH combinations to address.
1554  */
1555 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
1556                                   u32 se_num, u32 sh_num, u32 instance,
1557                                   int xcc_id)
1558 {
1559         u32 data;
1560
1561         if (instance == 0xffffffff)
1562                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1563         else
1564                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1565
1566         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1567                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1568                         GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1569         else if (se_num == 0xffffffff)
1570                 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1571                         (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1572         else if (sh_num == 0xffffffff)
1573                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1574                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1575         else
1576                 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1577                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1578         WREG32(mmGRBM_GFX_INDEX, data);
1579 }
1580
1581 /**
1582  * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1583  *
1584  * @adev: amdgpu_device pointer
1585  *
1586  * Calculates the bitmask of enabled RBs (CIK).
1587  * Returns the enabled RB bitmask.
1588  */
1589 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1590 {
1591         u32 data, mask;
1592
1593         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1594         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1595
1596         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1597         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1598
1599         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1600                                          adev->gfx.config.max_sh_per_se);
1601
1602         return (~data) & mask;
1603 }
1604
1605 static void
1606 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1607 {
1608         switch (adev->asic_type) {
1609         case CHIP_BONAIRE:
1610                 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1611                           SE_XSEL(1) | SE_YSEL(1);
1612                 *rconf1 |= 0x0;
1613                 break;
1614         case CHIP_HAWAII:
1615                 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1616                           RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1617                           PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1618                           SE_YSEL(3);
1619                 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1620                            SE_PAIR_YSEL(2);
1621                 break;
1622         case CHIP_KAVERI:
1623                 *rconf |= RB_MAP_PKR0(2);
1624                 *rconf1 |= 0x0;
1625                 break;
1626         case CHIP_KABINI:
1627         case CHIP_MULLINS:
1628                 *rconf |= 0x0;
1629                 *rconf1 |= 0x0;
1630                 break;
1631         default:
1632                 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1633                 break;
1634         }
1635 }
1636
1637 static void
1638 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1639                                         u32 raster_config, u32 raster_config_1,
1640                                         unsigned rb_mask, unsigned num_rb)
1641 {
1642         unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1643         unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1644         unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1645         unsigned rb_per_se = num_rb / num_se;
1646         unsigned se_mask[4];
1647         unsigned se;
1648
1649         se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1650         se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1651         se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1652         se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1653
1654         WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1655         WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1656         WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1657
1658         if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1659                              (!se_mask[2] && !se_mask[3]))) {
1660                 raster_config_1 &= ~SE_PAIR_MAP_MASK;
1661
1662                 if (!se_mask[0] && !se_mask[1]) {
1663                         raster_config_1 |=
1664                                 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1665                 } else {
1666                         raster_config_1 |=
1667                                 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1668                 }
1669         }
1670
1671         for (se = 0; se < num_se; se++) {
1672                 unsigned raster_config_se = raster_config;
1673                 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1674                 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1675                 int idx = (se / 2) * 2;
1676
1677                 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1678                         raster_config_se &= ~SE_MAP_MASK;
1679
1680                         if (!se_mask[idx]) {
1681                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1682                         } else {
1683                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1684                         }
1685                 }
1686
1687                 pkr0_mask &= rb_mask;
1688                 pkr1_mask &= rb_mask;
1689                 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1690                         raster_config_se &= ~PKR_MAP_MASK;
1691
1692                         if (!pkr0_mask) {
1693                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1694                         } else {
1695                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1696                         }
1697                 }
1698
1699                 if (rb_per_se >= 2) {
1700                         unsigned rb0_mask = 1 << (se * rb_per_se);
1701                         unsigned rb1_mask = rb0_mask << 1;
1702
1703                         rb0_mask &= rb_mask;
1704                         rb1_mask &= rb_mask;
1705                         if (!rb0_mask || !rb1_mask) {
1706                                 raster_config_se &= ~RB_MAP_PKR0_MASK;
1707
1708                                 if (!rb0_mask) {
1709                                         raster_config_se |=
1710                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1711                                 } else {
1712                                         raster_config_se |=
1713                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1714                                 }
1715                         }
1716
1717                         if (rb_per_se > 2) {
1718                                 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1719                                 rb1_mask = rb0_mask << 1;
1720                                 rb0_mask &= rb_mask;
1721                                 rb1_mask &= rb_mask;
1722                                 if (!rb0_mask || !rb1_mask) {
1723                                         raster_config_se &= ~RB_MAP_PKR1_MASK;
1724
1725                                         if (!rb0_mask) {
1726                                                 raster_config_se |=
1727                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1728                                         } else {
1729                                                 raster_config_se |=
1730                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1731                                         }
1732                                 }
1733                         }
1734                 }
1735
1736                 /* GRBM_GFX_INDEX has a different offset on CI+ */
1737                 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0);
1738                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1739                 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1740         }
1741
1742         /* GRBM_GFX_INDEX has a different offset on CI+ */
1743         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1744 }
1745
1746 /**
1747  * gfx_v7_0_setup_rb - setup the RBs on the asic
1748  *
1749  * @adev: amdgpu_device pointer
1750  *
1751  * Configures per-SE/SH RB registers (CIK).
1752  */
1753 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1754 {
1755         int i, j;
1756         u32 data;
1757         u32 raster_config = 0, raster_config_1 = 0;
1758         u32 active_rbs = 0;
1759         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1760                                         adev->gfx.config.max_sh_per_se;
1761         unsigned num_rb_pipes;
1762
1763         mutex_lock(&adev->grbm_idx_mutex);
1764         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1765                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1766                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0);
1767                         data = gfx_v7_0_get_rb_active_bitmap(adev);
1768                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1769                                                rb_bitmap_width_per_sh);
1770                 }
1771         }
1772         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1773
1774         adev->gfx.config.backend_enable_mask = active_rbs;
1775         adev->gfx.config.num_rbs = hweight32(active_rbs);
1776
1777         num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1778                              adev->gfx.config.max_shader_engines, 16);
1779
1780         gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1781
1782         if (!adev->gfx.config.backend_enable_mask ||
1783                         adev->gfx.config.num_rbs >= num_rb_pipes) {
1784                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1785                 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1786         } else {
1787                 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1788                                                         adev->gfx.config.backend_enable_mask,
1789                                                         num_rb_pipes);
1790         }
1791
1792         /* cache the values for userspace */
1793         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1794                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1795                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0);
1796                         adev->gfx.config.rb_config[i][j].rb_backend_disable =
1797                                 RREG32(mmCC_RB_BACKEND_DISABLE);
1798                         adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1799                                 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1800                         adev->gfx.config.rb_config[i][j].raster_config =
1801                                 RREG32(mmPA_SC_RASTER_CONFIG);
1802                         adev->gfx.config.rb_config[i][j].raster_config_1 =
1803                                 RREG32(mmPA_SC_RASTER_CONFIG_1);
1804                 }
1805         }
1806         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1807         mutex_unlock(&adev->grbm_idx_mutex);
1808 }
1809
1810 #define DEFAULT_SH_MEM_BASES    (0x6000)
1811 /**
1812  * gfx_v7_0_init_compute_vmid - gart enable
1813  *
1814  * @adev: amdgpu_device pointer
1815  *
1816  * Initialize compute vmid sh_mem registers
1817  *
1818  */
1819 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1820 {
1821         int i;
1822         uint32_t sh_mem_config;
1823         uint32_t sh_mem_bases;
1824
1825         /*
1826          * Configure apertures:
1827          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1828          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1829          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1830         */
1831         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1832         sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1833                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1834         sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1835         mutex_lock(&adev->srbm_mutex);
1836         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1837                 cik_srbm_select(adev, 0, 0, 0, i);
1838                 /* CP and shaders */
1839                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1840                 WREG32(mmSH_MEM_APE1_BASE, 1);
1841                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1842                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1843         }
1844         cik_srbm_select(adev, 0, 0, 0, 0);
1845         mutex_unlock(&adev->srbm_mutex);
1846
1847         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1848            access. These should be enabled by FW for target VMIDs. */
1849         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1850                 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
1851                 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
1852                 WREG32(amdgpu_gds_reg_offset[i].gws, 0);
1853                 WREG32(amdgpu_gds_reg_offset[i].oa, 0);
1854         }
1855 }
1856
1857 static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
1858 {
1859         int vmid;
1860
1861         /*
1862          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1863          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1864          * the driver can enable them for graphics. VMID0 should maintain
1865          * access so that HWS firmware can save/restore entries.
1866          */
1867         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
1868                 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
1869                 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
1870                 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
1871                 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
1872         }
1873 }
1874
1875 static void gfx_v7_0_config_init(struct amdgpu_device *adev)
1876 {
1877         adev->gfx.config.double_offchip_lds_buf = 1;
1878 }
1879
1880 /**
1881  * gfx_v7_0_constants_init - setup the 3D engine
1882  *
1883  * @adev: amdgpu_device pointer
1884  *
1885  * init the gfx constants such as the 3D engine, tiling configuration
1886  * registers, maximum number of quad pipes, render backends...
1887  */
1888 static void gfx_v7_0_constants_init(struct amdgpu_device *adev)
1889 {
1890         u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
1891         u32 tmp;
1892         int i;
1893
1894         WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1895
1896         WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1897         WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1898         WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1899
1900         gfx_v7_0_tiling_mode_table_init(adev);
1901
1902         gfx_v7_0_setup_rb(adev);
1903         gfx_v7_0_get_cu_info(adev);
1904         gfx_v7_0_config_init(adev);
1905
1906         /* set HW defaults for 3D engine */
1907         WREG32(mmCP_MEQ_THRESHOLDS,
1908                (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1909                (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1910
1911         mutex_lock(&adev->grbm_idx_mutex);
1912         /*
1913          * making sure that the following register writes will be broadcasted
1914          * to all the shaders
1915          */
1916         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1917
1918         /* XXX SH_MEM regs */
1919         /* where to put LDS, scratch, GPUVM in FSA64 space */
1920         sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1921                                    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1922         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
1923                                    MTYPE_NC);
1924         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
1925                                    MTYPE_UC);
1926         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
1927
1928         sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
1929                                    SWIZZLE_ENABLE, 1);
1930         sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1931                                    ELEMENT_SIZE, 1);
1932         sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1933                                    INDEX_STRIDE, 3);
1934         WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
1935
1936         mutex_lock(&adev->srbm_mutex);
1937         for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
1938                 if (i == 0)
1939                         sh_mem_base = 0;
1940                 else
1941                         sh_mem_base = adev->gmc.shared_aperture_start >> 48;
1942                 cik_srbm_select(adev, 0, 0, 0, i);
1943                 /* CP and shaders */
1944                 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1945                 WREG32(mmSH_MEM_APE1_BASE, 1);
1946                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1947                 WREG32(mmSH_MEM_BASES, sh_mem_base);
1948         }
1949         cik_srbm_select(adev, 0, 0, 0, 0);
1950         mutex_unlock(&adev->srbm_mutex);
1951
1952         gfx_v7_0_init_compute_vmid(adev);
1953         gfx_v7_0_init_gds_vmid(adev);
1954
1955         WREG32(mmSX_DEBUG_1, 0x20);
1956
1957         WREG32(mmTA_CNTL_AUX, 0x00010000);
1958
1959         tmp = RREG32(mmSPI_CONFIG_CNTL);
1960         tmp |= 0x03000000;
1961         WREG32(mmSPI_CONFIG_CNTL, tmp);
1962
1963         WREG32(mmSQ_CONFIG, 1);
1964
1965         WREG32(mmDB_DEBUG, 0);
1966
1967         tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1968         tmp |= 0x00000400;
1969         WREG32(mmDB_DEBUG2, tmp);
1970
1971         tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1972         tmp |= 0x00020200;
1973         WREG32(mmDB_DEBUG3, tmp);
1974
1975         tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1976         tmp |= 0x00018208;
1977         WREG32(mmCB_HW_CONTROL, tmp);
1978
1979         WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1980
1981         WREG32(mmPA_SC_FIFO_SIZE,
1982                 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1983                 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1984                 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1985                 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1986
1987         WREG32(mmVGT_NUM_INSTANCES, 1);
1988
1989         WREG32(mmCP_PERFMON_CNTL, 0);
1990
1991         WREG32(mmSQ_CONFIG, 0);
1992
1993         WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1994                 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1995                 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1996
1997         WREG32(mmVGT_CACHE_INVALIDATION,
1998                 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1999                 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
2000
2001         WREG32(mmVGT_GS_VERTEX_REUSE, 16);
2002         WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
2003
2004         WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
2005                         (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
2006         WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
2007
2008         tmp = RREG32(mmSPI_ARB_PRIORITY);
2009         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
2010         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
2011         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
2012         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
2013         WREG32(mmSPI_ARB_PRIORITY, tmp);
2014
2015         mutex_unlock(&adev->grbm_idx_mutex);
2016
2017         udelay(50);
2018 }
2019
2020 /**
2021  * gfx_v7_0_ring_test_ring - basic gfx ring test
2022  *
2023  * @ring: amdgpu_ring structure holding ring information
2024  *
2025  * Allocate a scratch register and write to it using the gfx ring (CIK).
2026  * Provides a basic gfx ring test to verify that the ring is working.
2027  * Used by gfx_v7_0_cp_gfx_resume();
2028  * Returns 0 on success, error on failure.
2029  */
2030 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2031 {
2032         struct amdgpu_device *adev = ring->adev;
2033         uint32_t tmp = 0;
2034         unsigned i;
2035         int r;
2036
2037         WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
2038         r = amdgpu_ring_alloc(ring, 3);
2039         if (r)
2040                 return r;
2041
2042         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2043         amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
2044         amdgpu_ring_write(ring, 0xDEADBEEF);
2045         amdgpu_ring_commit(ring);
2046
2047         for (i = 0; i < adev->usec_timeout; i++) {
2048                 tmp = RREG32(mmSCRATCH_REG0);
2049                 if (tmp == 0xDEADBEEF)
2050                         break;
2051                 udelay(1);
2052         }
2053         if (i >= adev->usec_timeout)
2054                 r = -ETIMEDOUT;
2055         return r;
2056 }
2057
2058 /**
2059  * gfx_v7_0_ring_emit_hdp_flush - emit an hdp flush on the cp
2060  *
2061  * @ring: amdgpu_ring structure holding ring information
2062  *
2063  * Emits an hdp flush on the cp.
2064  */
2065 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2066 {
2067         u32 ref_and_mask;
2068         int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
2069
2070         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2071                 switch (ring->me) {
2072                 case 1:
2073                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2074                         break;
2075                 case 2:
2076                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2077                         break;
2078                 default:
2079                         return;
2080                 }
2081         } else {
2082                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2083         }
2084
2085         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2086         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2087                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
2088                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
2089         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2090         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2091         amdgpu_ring_write(ring, ref_and_mask);
2092         amdgpu_ring_write(ring, ref_and_mask);
2093         amdgpu_ring_write(ring, 0x20); /* poll interval */
2094 }
2095
2096 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2097 {
2098         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2099         amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2100                 EVENT_INDEX(4));
2101
2102         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2103         amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2104                 EVENT_INDEX(0));
2105 }
2106
2107 /**
2108  * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2109  *
2110  * @ring: amdgpu_ring structure holding ring information
2111  * @addr: address
2112  * @seq: sequence number
2113  * @flags: fence related flags
2114  *
2115  * Emits a fence sequence number on the gfx ring and flushes
2116  * GPU caches.
2117  */
2118 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2119                                          u64 seq, unsigned flags)
2120 {
2121         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2122         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2123         bool exec = flags & AMDGPU_FENCE_FLAG_EXEC;
2124
2125         /* Workaround for cache flush problems. First send a dummy EOP
2126          * event down the pipe with seq one below.
2127          */
2128         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2129         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2130                                  EOP_TC_ACTION_EN |
2131                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2132                                  EVENT_INDEX(5)));
2133         amdgpu_ring_write(ring, addr & 0xfffffffc);
2134         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2135                                 DATA_SEL(1) | INT_SEL(0));
2136         amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2137         amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2138
2139         /* Then send the real EOP event down the pipe. */
2140         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2141         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2142                                  EOP_TC_ACTION_EN |
2143                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2144                                  EVENT_INDEX(5) |
2145                                  (exec ? EOP_EXEC : 0)));
2146         amdgpu_ring_write(ring, addr & 0xfffffffc);
2147         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2148                                 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2149         amdgpu_ring_write(ring, lower_32_bits(seq));
2150         amdgpu_ring_write(ring, upper_32_bits(seq));
2151 }
2152
2153 /**
2154  * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2155  *
2156  * @ring: amdgpu_ring structure holding ring information
2157  * @addr: address
2158  * @seq: sequence number
2159  * @flags: fence related flags
2160  *
2161  * Emits a fence sequence number on the compute ring and flushes
2162  * GPU caches.
2163  */
2164 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2165                                              u64 addr, u64 seq,
2166                                              unsigned flags)
2167 {
2168         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2169         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2170
2171         /* RELEASE_MEM - flush caches, send int */
2172         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2173         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2174                                  EOP_TC_ACTION_EN |
2175                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2176                                  EVENT_INDEX(5)));
2177         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2178         amdgpu_ring_write(ring, addr & 0xfffffffc);
2179         amdgpu_ring_write(ring, upper_32_bits(addr));
2180         amdgpu_ring_write(ring, lower_32_bits(seq));
2181         amdgpu_ring_write(ring, upper_32_bits(seq));
2182 }
2183
2184 /*
2185  * IB stuff
2186  */
2187 /**
2188  * gfx_v7_0_ring_emit_ib_gfx - emit an IB (Indirect Buffer) on the ring
2189  *
2190  * @ring: amdgpu_ring structure holding ring information
2191  * @job: job to retrieve vmid from
2192  * @ib: amdgpu indirect buffer object
2193  * @flags: options (AMDGPU_HAVE_CTX_SWITCH)
2194  *
2195  * Emits an DE (drawing engine) or CE (constant engine) IB
2196  * on the gfx ring.  IBs are usually generated by userspace
2197  * acceleration drivers and submitted to the kernel for
2198  * scheduling on the ring.  This function schedules the IB
2199  * on the gfx ring for execution by the GPU.
2200  */
2201 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2202                                         struct amdgpu_job *job,
2203                                         struct amdgpu_ib *ib,
2204                                         uint32_t flags)
2205 {
2206         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2207         u32 header, control = 0;
2208
2209         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2210         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2211                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2212                 amdgpu_ring_write(ring, 0);
2213         }
2214
2215         if (ib->flags & AMDGPU_IB_FLAG_CE)
2216                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2217         else
2218                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2219
2220         control |= ib->length_dw | (vmid << 24);
2221
2222         amdgpu_ring_write(ring, header);
2223         amdgpu_ring_write(ring,
2224 #ifdef __BIG_ENDIAN
2225                           (2 << 0) |
2226 #endif
2227                           (ib->gpu_addr & 0xFFFFFFFC));
2228         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2229         amdgpu_ring_write(ring, control);
2230 }
2231
2232 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2233                                           struct amdgpu_job *job,
2234                                           struct amdgpu_ib *ib,
2235                                           uint32_t flags)
2236 {
2237         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2238         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2239
2240         /* Currently, there is a high possibility to get wave ID mismatch
2241          * between ME and GDS, leading to a hw deadlock, because ME generates
2242          * different wave IDs than the GDS expects. This situation happens
2243          * randomly when at least 5 compute pipes use GDS ordered append.
2244          * The wave IDs generated by ME are also wrong after suspend/resume.
2245          * Those are probably bugs somewhere else in the kernel driver.
2246          *
2247          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
2248          * GDS to 0 for this ring (me/pipe).
2249          */
2250         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
2251                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2252                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
2253                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
2254         }
2255
2256         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2257         amdgpu_ring_write(ring,
2258 #ifdef __BIG_ENDIAN
2259                                           (2 << 0) |
2260 #endif
2261                                           (ib->gpu_addr & 0xFFFFFFFC));
2262         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2263         amdgpu_ring_write(ring, control);
2264 }
2265
2266 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2267 {
2268         uint32_t dw2 = 0;
2269
2270         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2271         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2272                 gfx_v7_0_ring_emit_vgt_flush(ring);
2273                 /* set load_global_config & load_global_uconfig */
2274                 dw2 |= 0x8001;
2275                 /* set load_cs_sh_regs */
2276                 dw2 |= 0x01000000;
2277                 /* set load_per_context_state & load_gfx_sh_regs */
2278                 dw2 |= 0x10002;
2279         }
2280
2281         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2282         amdgpu_ring_write(ring, dw2);
2283         amdgpu_ring_write(ring, 0);
2284 }
2285
2286 /**
2287  * gfx_v7_0_ring_test_ib - basic ring IB test
2288  *
2289  * @ring: amdgpu_ring structure holding ring information
2290  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
2291  *
2292  * Allocate an IB and execute it on the gfx ring (CIK).
2293  * Provides a basic gfx ring test to verify that IBs are working.
2294  * Returns 0 on success, error on failure.
2295  */
2296 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
2297 {
2298         struct amdgpu_device *adev = ring->adev;
2299         struct amdgpu_ib ib;
2300         struct dma_fence *f = NULL;
2301         uint32_t tmp = 0;
2302         long r;
2303
2304         WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
2305         memset(&ib, 0, sizeof(ib));
2306         r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
2307         if (r)
2308                 return r;
2309
2310         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2311         ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START;
2312         ib.ptr[2] = 0xDEADBEEF;
2313         ib.length_dw = 3;
2314
2315         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
2316         if (r)
2317                 goto error;
2318
2319         r = dma_fence_wait_timeout(f, false, timeout);
2320         if (r == 0) {
2321                 r = -ETIMEDOUT;
2322                 goto error;
2323         } else if (r < 0) {
2324                 goto error;
2325         }
2326         tmp = RREG32(mmSCRATCH_REG0);
2327         if (tmp == 0xDEADBEEF)
2328                 r = 0;
2329         else
2330                 r = -EINVAL;
2331
2332 error:
2333         amdgpu_ib_free(&ib, NULL);
2334         dma_fence_put(f);
2335         return r;
2336 }
2337
2338 /*
2339  * CP.
2340  * On CIK, gfx and compute now have independent command processors.
2341  *
2342  * GFX
2343  * Gfx consists of a single ring and can process both gfx jobs and
2344  * compute jobs.  The gfx CP consists of three microengines (ME):
2345  * PFP - Pre-Fetch Parser
2346  * ME - Micro Engine
2347  * CE - Constant Engine
2348  * The PFP and ME make up what is considered the Drawing Engine (DE).
2349  * The CE is an asynchronous engine used for updating buffer desciptors
2350  * used by the DE so that they can be loaded into cache in parallel
2351  * while the DE is processing state update packets.
2352  *
2353  * Compute
2354  * The compute CP consists of two microengines (ME):
2355  * MEC1 - Compute MicroEngine 1
2356  * MEC2 - Compute MicroEngine 2
2357  * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2358  * The queues are exposed to userspace and are programmed directly
2359  * by the compute runtime.
2360  */
2361 /**
2362  * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2363  *
2364  * @adev: amdgpu_device pointer
2365  * @enable: enable or disable the MEs
2366  *
2367  * Halts or unhalts the gfx MEs.
2368  */
2369 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2370 {
2371         if (enable)
2372                 WREG32(mmCP_ME_CNTL, 0);
2373         else
2374                 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
2375                                       CP_ME_CNTL__PFP_HALT_MASK |
2376                                       CP_ME_CNTL__CE_HALT_MASK));
2377         udelay(50);
2378 }
2379
2380 /**
2381  * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2382  *
2383  * @adev: amdgpu_device pointer
2384  *
2385  * Loads the gfx PFP, ME, and CE ucode.
2386  * Returns 0 for success, -EINVAL if the ucode is not available.
2387  */
2388 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2389 {
2390         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2391         const struct gfx_firmware_header_v1_0 *ce_hdr;
2392         const struct gfx_firmware_header_v1_0 *me_hdr;
2393         const __le32 *fw_data;
2394         unsigned i, fw_size;
2395
2396         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2397                 return -EINVAL;
2398
2399         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2400         ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2401         me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2402
2403         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2404         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2405         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2406         adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2407         adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2408         adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2409         adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2410         adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2411         adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2412
2413         gfx_v7_0_cp_gfx_enable(adev, false);
2414
2415         /* PFP */
2416         fw_data = (const __le32 *)
2417                 (adev->gfx.pfp_fw->data +
2418                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2419         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2420         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2421         for (i = 0; i < fw_size; i++)
2422                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2423         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2424
2425         /* CE */
2426         fw_data = (const __le32 *)
2427                 (adev->gfx.ce_fw->data +
2428                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2429         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2430         WREG32(mmCP_CE_UCODE_ADDR, 0);
2431         for (i = 0; i < fw_size; i++)
2432                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2433         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2434
2435         /* ME */
2436         fw_data = (const __le32 *)
2437                 (adev->gfx.me_fw->data +
2438                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2439         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2440         WREG32(mmCP_ME_RAM_WADDR, 0);
2441         for (i = 0; i < fw_size; i++)
2442                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2443         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2444
2445         return 0;
2446 }
2447
2448 /**
2449  * gfx_v7_0_cp_gfx_start - start the gfx ring
2450  *
2451  * @adev: amdgpu_device pointer
2452  *
2453  * Enables the ring and loads the clear state context and other
2454  * packets required to init the ring.
2455  * Returns 0 for success, error for failure.
2456  */
2457 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2458 {
2459         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2460         const struct cs_section_def *sect = NULL;
2461         const struct cs_extent_def *ext = NULL;
2462         int r, i;
2463
2464         /* init the CP */
2465         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2466         WREG32(mmCP_ENDIAN_SWAP, 0);
2467         WREG32(mmCP_DEVICE_ID, 1);
2468
2469         gfx_v7_0_cp_gfx_enable(adev, true);
2470
2471         r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2472         if (r) {
2473                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2474                 return r;
2475         }
2476
2477         /* init the CE partitions.  CE only used for gfx on CIK */
2478         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2479         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2480         amdgpu_ring_write(ring, 0x8000);
2481         amdgpu_ring_write(ring, 0x8000);
2482
2483         /* clear state buffer */
2484         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2485         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2486
2487         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2488         amdgpu_ring_write(ring, 0x80000000);
2489         amdgpu_ring_write(ring, 0x80000000);
2490
2491         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2492                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2493                         if (sect->id == SECT_CONTEXT) {
2494                                 amdgpu_ring_write(ring,
2495                                                   PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2496                                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2497                                 for (i = 0; i < ext->reg_count; i++)
2498                                         amdgpu_ring_write(ring, ext->extent[i]);
2499                         }
2500                 }
2501         }
2502
2503         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2504         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2505         amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
2506         amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
2507
2508         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2509         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2510
2511         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2512         amdgpu_ring_write(ring, 0);
2513
2514         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2515         amdgpu_ring_write(ring, 0x00000316);
2516         amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2517         amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2518
2519         amdgpu_ring_commit(ring);
2520
2521         return 0;
2522 }
2523
2524 /**
2525  * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2526  *
2527  * @adev: amdgpu_device pointer
2528  *
2529  * Program the location and size of the gfx ring buffer
2530  * and test it to make sure it's working.
2531  * Returns 0 for success, error for failure.
2532  */
2533 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2534 {
2535         struct amdgpu_ring *ring;
2536         u32 tmp;
2537         u32 rb_bufsz;
2538         u64 rb_addr, rptr_addr;
2539         int r;
2540
2541         WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2542         if (adev->asic_type != CHIP_HAWAII)
2543                 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2544
2545         /* Set the write pointer delay */
2546         WREG32(mmCP_RB_WPTR_DELAY, 0);
2547
2548         /* set the RB to use vmid 0 */
2549         WREG32(mmCP_RB_VMID, 0);
2550
2551         WREG32(mmSCRATCH_ADDR, 0);
2552
2553         /* ring 0 - compute and gfx */
2554         /* Set ring buffer size */
2555         ring = &adev->gfx.gfx_ring[0];
2556         rb_bufsz = order_base_2(ring->ring_size / 8);
2557         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2558 #ifdef __BIG_ENDIAN
2559         tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2560 #endif
2561         WREG32(mmCP_RB0_CNTL, tmp);
2562
2563         /* Initialize the ring buffer's read and write pointers */
2564         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2565         ring->wptr = 0;
2566         WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2567
2568         /* set the wb address whether it's enabled or not */
2569         rptr_addr = ring->rptr_gpu_addr;
2570         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2571         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2572
2573         /* scratch register shadowing is no longer supported */
2574         WREG32(mmSCRATCH_UMSK, 0);
2575
2576         mdelay(1);
2577         WREG32(mmCP_RB0_CNTL, tmp);
2578
2579         rb_addr = ring->gpu_addr >> 8;
2580         WREG32(mmCP_RB0_BASE, rb_addr);
2581         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2582
2583         /* start the ring */
2584         gfx_v7_0_cp_gfx_start(adev);
2585         r = amdgpu_ring_test_helper(ring);
2586         if (r)
2587                 return r;
2588
2589         return 0;
2590 }
2591
2592 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
2593 {
2594         return *ring->rptr_cpu_addr;
2595 }
2596
2597 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2598 {
2599         struct amdgpu_device *adev = ring->adev;
2600
2601         return RREG32(mmCP_RB0_WPTR);
2602 }
2603
2604 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2605 {
2606         struct amdgpu_device *adev = ring->adev;
2607
2608         WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2609         (void)RREG32(mmCP_RB0_WPTR);
2610 }
2611
2612 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2613 {
2614         /* XXX check if swapping is necessary on BE */
2615         return *ring->wptr_cpu_addr;
2616 }
2617
2618 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2619 {
2620         struct amdgpu_device *adev = ring->adev;
2621
2622         /* XXX check if swapping is necessary on BE */
2623         *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
2624         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2625 }
2626
2627 /**
2628  * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2629  *
2630  * @adev: amdgpu_device pointer
2631  * @enable: enable or disable the MEs
2632  *
2633  * Halts or unhalts the compute MEs.
2634  */
2635 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2636 {
2637         if (enable)
2638                 WREG32(mmCP_MEC_CNTL, 0);
2639         else
2640                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
2641                                        CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2642         udelay(50);
2643 }
2644
2645 /**
2646  * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2647  *
2648  * @adev: amdgpu_device pointer
2649  *
2650  * Loads the compute MEC1&2 ucode.
2651  * Returns 0 for success, -EINVAL if the ucode is not available.
2652  */
2653 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2654 {
2655         const struct gfx_firmware_header_v1_0 *mec_hdr;
2656         const __le32 *fw_data;
2657         unsigned i, fw_size;
2658
2659         if (!adev->gfx.mec_fw)
2660                 return -EINVAL;
2661
2662         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2663         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2664         adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2665         adev->gfx.mec_feature_version = le32_to_cpu(
2666                                         mec_hdr->ucode_feature_version);
2667
2668         gfx_v7_0_cp_compute_enable(adev, false);
2669
2670         /* MEC1 */
2671         fw_data = (const __le32 *)
2672                 (adev->gfx.mec_fw->data +
2673                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2674         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2675         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2676         for (i = 0; i < fw_size; i++)
2677                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2678         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2679
2680         if (adev->asic_type == CHIP_KAVERI) {
2681                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2682
2683                 if (!adev->gfx.mec2_fw)
2684                         return -EINVAL;
2685
2686                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2687                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2688                 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2689                 adev->gfx.mec2_feature_version = le32_to_cpu(
2690                                 mec2_hdr->ucode_feature_version);
2691
2692                 /* MEC2 */
2693                 fw_data = (const __le32 *)
2694                         (adev->gfx.mec2_fw->data +
2695                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2696                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2697                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2698                 for (i = 0; i < fw_size; i++)
2699                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2700                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2701         }
2702
2703         return 0;
2704 }
2705
2706 /**
2707  * gfx_v7_0_cp_compute_fini - stop the compute queues
2708  *
2709  * @adev: amdgpu_device pointer
2710  *
2711  * Stop the compute queues and tear down the driver queue
2712  * info.
2713  */
2714 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2715 {
2716         int i;
2717
2718         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2719                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2720
2721                 amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL);
2722         }
2723 }
2724
2725 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2726 {
2727         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
2728 }
2729
2730 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2731 {
2732         int r;
2733         u32 *hpd;
2734         size_t mec_hpd_size;
2735
2736         bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2737
2738         /* take ownership of the relevant compute queues */
2739         amdgpu_gfx_compute_queue_acquire(adev);
2740
2741         /* allocate space for ALL pipes (even the ones we don't own) */
2742         mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec
2743                 * GFX7_MEC_HPD_SIZE * 2;
2744
2745         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
2746                                       AMDGPU_GEM_DOMAIN_VRAM |
2747                                       AMDGPU_GEM_DOMAIN_GTT,
2748                                       &adev->gfx.mec.hpd_eop_obj,
2749                                       &adev->gfx.mec.hpd_eop_gpu_addr,
2750                                       (void **)&hpd);
2751         if (r) {
2752                 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r);
2753                 gfx_v7_0_mec_fini(adev);
2754                 return r;
2755         }
2756
2757         /* clear memory.  Not sure if this is required or not */
2758         memset(hpd, 0, mec_hpd_size);
2759
2760         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2761         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2762
2763         return 0;
2764 }
2765
2766 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev,
2767                                        int mec, int pipe)
2768 {
2769         u64 eop_gpu_addr;
2770         u32 tmp;
2771         size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)
2772                             * GFX7_MEC_HPD_SIZE * 2;
2773
2774         mutex_lock(&adev->srbm_mutex);
2775         eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset;
2776
2777         cik_srbm_select(adev, mec + 1, pipe, 0, 0);
2778
2779         /* write the EOP addr */
2780         WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2781         WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2782
2783         /* set the VMID assigned */
2784         WREG32(mmCP_HPD_EOP_VMID, 0);
2785
2786         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2787         tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2788         tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2789         tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8);
2790         WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2791
2792         cik_srbm_select(adev, 0, 0, 0, 0);
2793         mutex_unlock(&adev->srbm_mutex);
2794 }
2795
2796 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev)
2797 {
2798         int i;
2799
2800         /* disable the queue if it's active */
2801         if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2802                 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2803                 for (i = 0; i < adev->usec_timeout; i++) {
2804                         if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2805                                 break;
2806                         udelay(1);
2807                 }
2808
2809                 if (i == adev->usec_timeout)
2810                         return -ETIMEDOUT;
2811
2812                 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
2813                 WREG32(mmCP_HQD_PQ_RPTR, 0);
2814                 WREG32(mmCP_HQD_PQ_WPTR, 0);
2815         }
2816
2817         return 0;
2818 }
2819
2820 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
2821                              struct cik_mqd *mqd,
2822                              uint64_t mqd_gpu_addr,
2823                              struct amdgpu_ring *ring)
2824 {
2825         u64 hqd_gpu_addr;
2826         u64 wb_gpu_addr;
2827
2828         /* init the mqd struct */
2829         memset(mqd, 0, sizeof(struct cik_mqd));
2830
2831         mqd->header = 0xC0310800;
2832         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2833         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2834         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2835         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2836
2837         /* enable doorbell? */
2838         mqd->cp_hqd_pq_doorbell_control =
2839                 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2840         if (ring->use_doorbell)
2841                 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2842         else
2843                 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2844
2845         /* set the pointer to the MQD */
2846         mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
2847         mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2848
2849         /* set MQD vmid to 0 */
2850         mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2851         mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2852
2853         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2854         hqd_gpu_addr = ring->gpu_addr >> 8;
2855         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2856         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2857
2858         /* set up the HQD, this is similar to CP_RB0_CNTL */
2859         mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2860         mqd->cp_hqd_pq_control &=
2861                 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2862                                 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2863
2864         mqd->cp_hqd_pq_control |=
2865                 order_base_2(ring->ring_size / 8);
2866         mqd->cp_hqd_pq_control |=
2867                 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2868 #ifdef __BIG_ENDIAN
2869         mqd->cp_hqd_pq_control |=
2870                 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
2871 #endif
2872         mqd->cp_hqd_pq_control &=
2873                 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2874                                 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2875                                 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2876         mqd->cp_hqd_pq_control |=
2877                 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2878                 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2879
2880         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2881         wb_gpu_addr = ring->wptr_gpu_addr;
2882         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2883         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2884
2885         /* set the wb address whether it's enabled or not */
2886         wb_gpu_addr = ring->rptr_gpu_addr;
2887         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2888         mqd->cp_hqd_pq_rptr_report_addr_hi =
2889                 upper_32_bits(wb_gpu_addr) & 0xffff;
2890
2891         /* enable the doorbell if requested */
2892         if (ring->use_doorbell) {
2893                 mqd->cp_hqd_pq_doorbell_control =
2894                         RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2895                 mqd->cp_hqd_pq_doorbell_control &=
2896                         ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2897                 mqd->cp_hqd_pq_doorbell_control |=
2898                         (ring->doorbell_index <<
2899                          CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2900                 mqd->cp_hqd_pq_doorbell_control |=
2901                         CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2902                 mqd->cp_hqd_pq_doorbell_control &=
2903                         ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2904                                         CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2905
2906         } else {
2907                 mqd->cp_hqd_pq_doorbell_control = 0;
2908         }
2909
2910         /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2911         ring->wptr = 0;
2912         mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
2913         mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2914
2915         /* set the vmid for the queue */
2916         mqd->cp_hqd_vmid = 0;
2917
2918         /* defaults */
2919         mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
2920         mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
2921         mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
2922         mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
2923         mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
2924         mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
2925         mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
2926         mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
2927         mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
2928         mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
2929         mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
2930         mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2931         mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
2932         mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
2933         mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
2934         mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
2935
2936         /* activate the queue */
2937         mqd->cp_hqd_active = 1;
2938 }
2939
2940 static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
2941 {
2942         uint32_t tmp;
2943         uint32_t mqd_reg;
2944         uint32_t *mqd_data;
2945
2946         /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */
2947         mqd_data = &mqd->cp_mqd_base_addr_lo;
2948
2949         /* disable wptr polling */
2950         tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2951         tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2952         WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2953
2954         /* program all HQD registers */
2955         for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++)
2956                 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
2957
2958         /* activate the HQD */
2959         for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
2960                 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
2961
2962         return 0;
2963 }
2964
2965 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id)
2966 {
2967         int r;
2968         u64 mqd_gpu_addr;
2969         struct cik_mqd *mqd;
2970         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
2971
2972         r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE,
2973                                       AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
2974                                       &mqd_gpu_addr, (void **)&mqd);
2975         if (r) {
2976                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2977                 return r;
2978         }
2979
2980         mutex_lock(&adev->srbm_mutex);
2981         cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2982
2983         gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring);
2984         gfx_v7_0_mqd_deactivate(adev);
2985         gfx_v7_0_mqd_commit(adev, mqd);
2986
2987         cik_srbm_select(adev, 0, 0, 0, 0);
2988         mutex_unlock(&adev->srbm_mutex);
2989
2990         amdgpu_bo_kunmap(ring->mqd_obj);
2991         amdgpu_bo_unreserve(ring->mqd_obj);
2992         return 0;
2993 }
2994
2995 /**
2996  * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2997  *
2998  * @adev: amdgpu_device pointer
2999  *
3000  * Program the compute queues and test them to make sure they
3001  * are working.
3002  * Returns 0 for success, error for failure.
3003  */
3004 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
3005 {
3006         int r, i, j;
3007         u32 tmp;
3008         struct amdgpu_ring *ring;
3009
3010         /* fix up chicken bits */
3011         tmp = RREG32(mmCP_CPF_DEBUG);
3012         tmp |= (1 << 23);
3013         WREG32(mmCP_CPF_DEBUG, tmp);
3014
3015         /* init all pipes (even the ones we don't own) */
3016         for (i = 0; i < adev->gfx.mec.num_mec; i++)
3017                 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++)
3018                         gfx_v7_0_compute_pipe_init(adev, i, j);
3019
3020         /* init the queues */
3021         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3022                 r = gfx_v7_0_compute_queue_init(adev, i);
3023                 if (r) {
3024                         gfx_v7_0_cp_compute_fini(adev);
3025                         return r;
3026                 }
3027         }
3028
3029         gfx_v7_0_cp_compute_enable(adev, true);
3030
3031         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3032                 ring = &adev->gfx.compute_ring[i];
3033                 amdgpu_ring_test_helper(ring);
3034         }
3035
3036         return 0;
3037 }
3038
3039 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3040 {
3041         gfx_v7_0_cp_gfx_enable(adev, enable);
3042         gfx_v7_0_cp_compute_enable(adev, enable);
3043 }
3044
3045 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3046 {
3047         int r;
3048
3049         r = gfx_v7_0_cp_gfx_load_microcode(adev);
3050         if (r)
3051                 return r;
3052         r = gfx_v7_0_cp_compute_load_microcode(adev);
3053         if (r)
3054                 return r;
3055
3056         return 0;
3057 }
3058
3059 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3060                                                bool enable)
3061 {
3062         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3063
3064         if (enable)
3065                 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3066                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3067         else
3068                 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3069                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3070         WREG32(mmCP_INT_CNTL_RING0, tmp);
3071 }
3072
3073 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3074 {
3075         int r;
3076
3077         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3078
3079         r = gfx_v7_0_cp_load_microcode(adev);
3080         if (r)
3081                 return r;
3082
3083         r = gfx_v7_0_cp_gfx_resume(adev);
3084         if (r)
3085                 return r;
3086         r = gfx_v7_0_cp_compute_resume(adev);
3087         if (r)
3088                 return r;
3089
3090         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3091
3092         return 0;
3093 }
3094
3095 /**
3096  * gfx_v7_0_ring_emit_pipeline_sync - cik vm flush using the CP
3097  *
3098  * @ring: the ring to emit the commands to
3099  *
3100  * Sync the command pipeline with the PFP. E.g. wait for everything
3101  * to be completed.
3102  */
3103 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3104 {
3105         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3106         uint32_t seq = ring->fence_drv.sync_seq;
3107         uint64_t addr = ring->fence_drv.gpu_addr;
3108
3109         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3110         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3111                                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
3112                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
3113         amdgpu_ring_write(ring, addr & 0xfffffffc);
3114         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3115         amdgpu_ring_write(ring, seq);
3116         amdgpu_ring_write(ring, 0xffffffff);
3117         amdgpu_ring_write(ring, 4); /* poll interval */
3118
3119         if (usepfp) {
3120                 /* sync CE with ME to prevent CE fetch CEIB before context switch done */
3121                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3122                 amdgpu_ring_write(ring, 0);
3123                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3124                 amdgpu_ring_write(ring, 0);
3125         }
3126 }
3127
3128 /*
3129  * vm
3130  * VMID 0 is the physical GPU addresses as used by the kernel.
3131  * VMIDs 1-15 are used for userspace clients and are handled
3132  * by the amdgpu vm/hsa code.
3133  */
3134 /**
3135  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3136  *
3137  * @ring: amdgpu_ring pointer
3138  * @vmid: vmid number to use
3139  * @pd_addr: address
3140  *
3141  * Update the page table base and flush the VM TLB
3142  * using the CP (CIK).
3143  */
3144 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3145                                         unsigned vmid, uint64_t pd_addr)
3146 {
3147         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3148
3149         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
3150
3151         /* wait for the invalidate to complete */
3152         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3153         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3154                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
3155                                  WAIT_REG_MEM_ENGINE(0))); /* me */
3156         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3157         amdgpu_ring_write(ring, 0);
3158         amdgpu_ring_write(ring, 0); /* ref */
3159         amdgpu_ring_write(ring, 0); /* mask */
3160         amdgpu_ring_write(ring, 0x20); /* poll interval */
3161
3162         /* compute doesn't have PFP */
3163         if (usepfp) {
3164                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3165                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3166                 amdgpu_ring_write(ring, 0x0);
3167
3168                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3169                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3170                 amdgpu_ring_write(ring, 0);
3171                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3172                 amdgpu_ring_write(ring, 0);
3173         }
3174 }
3175
3176 static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
3177                                     uint32_t reg, uint32_t val)
3178 {
3179         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3180
3181         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3182         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3183                                  WRITE_DATA_DST_SEL(0)));
3184         amdgpu_ring_write(ring, reg);
3185         amdgpu_ring_write(ring, 0);
3186         amdgpu_ring_write(ring, val);
3187 }
3188
3189 /*
3190  * RLC
3191  * The RLC is a multi-purpose microengine that handles a
3192  * variety of functions.
3193  */
3194 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3195 {
3196         const u32 *src_ptr;
3197         u32 dws;
3198         const struct cs_section_def *cs_data;
3199         int r;
3200
3201         /* allocate rlc buffers */
3202         if (adev->flags & AMD_IS_APU) {
3203                 if (adev->asic_type == CHIP_KAVERI) {
3204                         adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3205                         adev->gfx.rlc.reg_list_size =
3206                                 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3207                 } else {
3208                         adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3209                         adev->gfx.rlc.reg_list_size =
3210                                 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3211                 }
3212         }
3213         adev->gfx.rlc.cs_data = ci_cs_data;
3214         adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3215         adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3216
3217         src_ptr = adev->gfx.rlc.reg_list;
3218         dws = adev->gfx.rlc.reg_list_size;
3219         dws += (5 * 16) + 48 + 48 + 64;
3220
3221         cs_data = adev->gfx.rlc.cs_data;
3222
3223         if (src_ptr) {
3224                 /* init save restore block */
3225                 r = amdgpu_gfx_rlc_init_sr(adev, dws);
3226                 if (r)
3227                         return r;
3228         }
3229
3230         if (cs_data) {
3231                 /* init clear state block */
3232                 r = amdgpu_gfx_rlc_init_csb(adev);
3233                 if (r)
3234                         return r;
3235         }
3236
3237         if (adev->gfx.rlc.cp_table_size) {
3238                 r = amdgpu_gfx_rlc_init_cpt(adev);
3239                 if (r)
3240                         return r;
3241         }
3242
3243         /* init spm vmid with 0xf */
3244         if (adev->gfx.rlc.funcs->update_spm_vmid)
3245                 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
3246
3247         return 0;
3248 }
3249
3250 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3251 {
3252         u32 tmp;
3253
3254         tmp = RREG32(mmRLC_LB_CNTL);
3255         if (enable)
3256                 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3257         else
3258                 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3259         WREG32(mmRLC_LB_CNTL, tmp);
3260 }
3261
3262 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3263 {
3264         u32 i, j, k;
3265         u32 mask;
3266
3267         mutex_lock(&adev->grbm_idx_mutex);
3268         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3269                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3270                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0);
3271                         for (k = 0; k < adev->usec_timeout; k++) {
3272                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3273                                         break;
3274                                 udelay(1);
3275                         }
3276                 }
3277         }
3278         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3279         mutex_unlock(&adev->grbm_idx_mutex);
3280
3281         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3282                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3283                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3284                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3285         for (k = 0; k < adev->usec_timeout; k++) {
3286                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3287                         break;
3288                 udelay(1);
3289         }
3290 }
3291
3292 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3293 {
3294         u32 tmp;
3295
3296         tmp = RREG32(mmRLC_CNTL);
3297         if (tmp != rlc)
3298                 WREG32(mmRLC_CNTL, rlc);
3299 }
3300
3301 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3302 {
3303         u32 data, orig;
3304
3305         orig = data = RREG32(mmRLC_CNTL);
3306
3307         if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3308                 u32 i;
3309
3310                 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3311                 WREG32(mmRLC_CNTL, data);
3312
3313                 for (i = 0; i < adev->usec_timeout; i++) {
3314                         if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3315                                 break;
3316                         udelay(1);
3317                 }
3318
3319                 gfx_v7_0_wait_for_rlc_serdes(adev);
3320         }
3321
3322         return orig;
3323 }
3324
3325 static bool gfx_v7_0_is_rlc_enabled(struct amdgpu_device *adev)
3326 {
3327         return true;
3328 }
3329
3330 static void gfx_v7_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
3331 {
3332         u32 tmp, i, mask;
3333
3334         tmp = 0x1 | (1 << 1);
3335         WREG32(mmRLC_GPR_REG2, tmp);
3336
3337         mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3338                 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3339         for (i = 0; i < adev->usec_timeout; i++) {
3340                 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3341                         break;
3342                 udelay(1);
3343         }
3344
3345         for (i = 0; i < adev->usec_timeout; i++) {
3346                 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3347                         break;
3348                 udelay(1);
3349         }
3350 }
3351
3352 static void gfx_v7_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
3353 {
3354         u32 tmp;
3355
3356         tmp = 0x1 | (0 << 1);
3357         WREG32(mmRLC_GPR_REG2, tmp);
3358 }
3359
3360 /**
3361  * gfx_v7_0_rlc_stop - stop the RLC ME
3362  *
3363  * @adev: amdgpu_device pointer
3364  *
3365  * Halt the RLC ME (MicroEngine) (CIK).
3366  */
3367 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3368 {
3369         WREG32(mmRLC_CNTL, 0);
3370
3371         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3372
3373         gfx_v7_0_wait_for_rlc_serdes(adev);
3374 }
3375
3376 /**
3377  * gfx_v7_0_rlc_start - start the RLC ME
3378  *
3379  * @adev: amdgpu_device pointer
3380  *
3381  * Unhalt the RLC ME (MicroEngine) (CIK).
3382  */
3383 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3384 {
3385         WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3386
3387         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3388
3389         udelay(50);
3390 }
3391
3392 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3393 {
3394         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3395
3396         tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3397         WREG32(mmGRBM_SOFT_RESET, tmp);
3398         udelay(50);
3399         tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3400         WREG32(mmGRBM_SOFT_RESET, tmp);
3401         udelay(50);
3402 }
3403
3404 /**
3405  * gfx_v7_0_rlc_resume - setup the RLC hw
3406  *
3407  * @adev: amdgpu_device pointer
3408  *
3409  * Initialize the RLC registers, load the ucode,
3410  * and start the RLC (CIK).
3411  * Returns 0 for success, -EINVAL if the ucode is not available.
3412  */
3413 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3414 {
3415         const struct rlc_firmware_header_v1_0 *hdr;
3416         const __le32 *fw_data;
3417         unsigned i, fw_size;
3418         u32 tmp;
3419
3420         if (!adev->gfx.rlc_fw)
3421                 return -EINVAL;
3422
3423         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3424         amdgpu_ucode_print_rlc_hdr(&hdr->header);
3425         adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3426         adev->gfx.rlc_feature_version = le32_to_cpu(
3427                                         hdr->ucode_feature_version);
3428
3429         adev->gfx.rlc.funcs->stop(adev);
3430
3431         /* disable CG */
3432         tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3433         WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3434
3435         adev->gfx.rlc.funcs->reset(adev);
3436
3437         gfx_v7_0_init_pg(adev);
3438
3439         WREG32(mmRLC_LB_CNTR_INIT, 0);
3440         WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3441
3442         mutex_lock(&adev->grbm_idx_mutex);
3443         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3444         WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3445         WREG32(mmRLC_LB_PARAMS, 0x00600408);
3446         WREG32(mmRLC_LB_CNTL, 0x80000004);
3447         mutex_unlock(&adev->grbm_idx_mutex);
3448
3449         WREG32(mmRLC_MC_CNTL, 0);
3450         WREG32(mmRLC_UCODE_CNTL, 0);
3451
3452         fw_data = (const __le32 *)
3453                 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3454         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3455         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3456         for (i = 0; i < fw_size; i++)
3457                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3458         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3459
3460         /* XXX - find out what chips support lbpw */
3461         gfx_v7_0_enable_lbpw(adev, false);
3462
3463         if (adev->asic_type == CHIP_BONAIRE)
3464                 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3465
3466         adev->gfx.rlc.funcs->start(adev);
3467
3468         return 0;
3469 }
3470
3471 static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid)
3472 {
3473         u32 data;
3474
3475         amdgpu_gfx_off_ctrl(adev, false);
3476
3477         data = RREG32(mmRLC_SPM_VMID);
3478
3479         data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK;
3480         data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT;
3481
3482         WREG32(mmRLC_SPM_VMID, data);
3483
3484         amdgpu_gfx_off_ctrl(adev, true);
3485 }
3486
3487 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3488 {
3489         u32 data, orig, tmp, tmp2;
3490
3491         orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3492
3493         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3494                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3495
3496                 tmp = gfx_v7_0_halt_rlc(adev);
3497
3498                 mutex_lock(&adev->grbm_idx_mutex);
3499                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3500                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3501                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3502                 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3503                         RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3504                         RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3505                 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3506                 mutex_unlock(&adev->grbm_idx_mutex);
3507
3508                 gfx_v7_0_update_rlc(adev, tmp);
3509
3510                 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3511                 if (orig != data)
3512                         WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3513
3514         } else {
3515                 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3516
3517                 RREG32(mmCB_CGTT_SCLK_CTRL);
3518                 RREG32(mmCB_CGTT_SCLK_CTRL);
3519                 RREG32(mmCB_CGTT_SCLK_CTRL);
3520                 RREG32(mmCB_CGTT_SCLK_CTRL);
3521
3522                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3523                 if (orig != data)
3524                         WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3525
3526                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3527         }
3528 }
3529
3530 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3531 {
3532         u32 data, orig, tmp = 0;
3533
3534         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3535                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3536                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3537                                 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3538                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3539                                 if (orig != data)
3540                                         WREG32(mmCP_MEM_SLP_CNTL, data);
3541                         }
3542                 }
3543
3544                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3545                 data |= 0x00000001;
3546                 data &= 0xfffffffd;
3547                 if (orig != data)
3548                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3549
3550                 tmp = gfx_v7_0_halt_rlc(adev);
3551
3552                 mutex_lock(&adev->grbm_idx_mutex);
3553                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3554                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3555                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3556                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3557                         RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3558                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3559                 mutex_unlock(&adev->grbm_idx_mutex);
3560
3561                 gfx_v7_0_update_rlc(adev, tmp);
3562
3563                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3564                         orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3565                         data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3566                         data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3567                         data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3568                         data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3569                         if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3570                             (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3571                                 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3572                         data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3573                         data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3574                         data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3575                         if (orig != data)
3576                                 WREG32(mmCGTS_SM_CTRL_REG, data);
3577                 }
3578         } else {
3579                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3580                 data |= 0x00000003;
3581                 if (orig != data)
3582                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3583
3584                 data = RREG32(mmRLC_MEM_SLP_CNTL);
3585                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3586                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3587                         WREG32(mmRLC_MEM_SLP_CNTL, data);
3588                 }
3589
3590                 data = RREG32(mmCP_MEM_SLP_CNTL);
3591                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3592                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3593                         WREG32(mmCP_MEM_SLP_CNTL, data);
3594                 }
3595
3596                 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3597                 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3598                 if (orig != data)
3599                         WREG32(mmCGTS_SM_CTRL_REG, data);
3600
3601                 tmp = gfx_v7_0_halt_rlc(adev);
3602
3603                 mutex_lock(&adev->grbm_idx_mutex);
3604                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3605                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3606                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3607                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3608                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3609                 mutex_unlock(&adev->grbm_idx_mutex);
3610
3611                 gfx_v7_0_update_rlc(adev, tmp);
3612         }
3613 }
3614
3615 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3616                                bool enable)
3617 {
3618         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3619         /* order matters! */
3620         if (enable) {
3621                 gfx_v7_0_enable_mgcg(adev, true);
3622                 gfx_v7_0_enable_cgcg(adev, true);
3623         } else {
3624                 gfx_v7_0_enable_cgcg(adev, false);
3625                 gfx_v7_0_enable_mgcg(adev, false);
3626         }
3627         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3628 }
3629
3630 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3631                                                 bool enable)
3632 {
3633         u32 data, orig;
3634
3635         orig = data = RREG32(mmRLC_PG_CNTL);
3636         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3637                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3638         else
3639                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3640         if (orig != data)
3641                 WREG32(mmRLC_PG_CNTL, data);
3642 }
3643
3644 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3645                                                 bool enable)
3646 {
3647         u32 data, orig;
3648
3649         orig = data = RREG32(mmRLC_PG_CNTL);
3650         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3651                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3652         else
3653                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3654         if (orig != data)
3655                 WREG32(mmRLC_PG_CNTL, data);
3656 }
3657
3658 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3659 {
3660         u32 data, orig;
3661
3662         orig = data = RREG32(mmRLC_PG_CNTL);
3663         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3664                 data &= ~0x8000;
3665         else
3666                 data |= 0x8000;
3667         if (orig != data)
3668                 WREG32(mmRLC_PG_CNTL, data);
3669 }
3670
3671 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3672 {
3673         u32 data, orig;
3674
3675         orig = data = RREG32(mmRLC_PG_CNTL);
3676         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3677                 data &= ~0x2000;
3678         else
3679                 data |= 0x2000;
3680         if (orig != data)
3681                 WREG32(mmRLC_PG_CNTL, data);
3682 }
3683
3684 static int gfx_v7_0_cp_pg_table_num(struct amdgpu_device *adev)
3685 {
3686         if (adev->asic_type == CHIP_KAVERI)
3687                 return 5;
3688         else
3689                 return 4;
3690 }
3691
3692 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3693                                      bool enable)
3694 {
3695         u32 data, orig;
3696
3697         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3698                 orig = data = RREG32(mmRLC_PG_CNTL);
3699                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3700                 if (orig != data)
3701                         WREG32(mmRLC_PG_CNTL, data);
3702
3703                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3704                 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3705                 if (orig != data)
3706                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3707         } else {
3708                 orig = data = RREG32(mmRLC_PG_CNTL);
3709                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3710                 if (orig != data)
3711                         WREG32(mmRLC_PG_CNTL, data);
3712
3713                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3714                 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3715                 if (orig != data)
3716                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3717
3718                 data = RREG32(mmDB_RENDER_CONTROL);
3719         }
3720 }
3721
3722 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
3723                                                  u32 bitmap)
3724 {
3725         u32 data;
3726
3727         if (!bitmap)
3728                 return;
3729
3730         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3731         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3732
3733         WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
3734 }
3735
3736 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3737 {
3738         u32 data, mask;
3739
3740         data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3741         data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
3742
3743         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3744         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3745
3746         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
3747
3748         return (~data) & mask;
3749 }
3750
3751 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3752 {
3753         u32 tmp;
3754
3755         WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
3756
3757         tmp = RREG32(mmRLC_MAX_PG_CU);
3758         tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3759         tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3760         WREG32(mmRLC_MAX_PG_CU, tmp);
3761 }
3762
3763 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3764                                             bool enable)
3765 {
3766         u32 data, orig;
3767
3768         orig = data = RREG32(mmRLC_PG_CNTL);
3769         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
3770                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3771         else
3772                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3773         if (orig != data)
3774                 WREG32(mmRLC_PG_CNTL, data);
3775 }
3776
3777 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3778                                              bool enable)
3779 {
3780         u32 data, orig;
3781
3782         orig = data = RREG32(mmRLC_PG_CNTL);
3783         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
3784                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3785         else
3786                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3787         if (orig != data)
3788                 WREG32(mmRLC_PG_CNTL, data);
3789 }
3790
3791 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3792 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
3793
3794 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3795 {
3796         u32 data, orig;
3797         u32 i;
3798
3799         if (adev->gfx.rlc.cs_data) {
3800                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3801                 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3802                 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3803                 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3804         } else {
3805                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3806                 for (i = 0; i < 3; i++)
3807                         WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3808         }
3809         if (adev->gfx.rlc.reg_list) {
3810                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3811                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3812                         WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3813         }
3814
3815         orig = data = RREG32(mmRLC_PG_CNTL);
3816         data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3817         if (orig != data)
3818                 WREG32(mmRLC_PG_CNTL, data);
3819
3820         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3821         WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3822
3823         data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3824         data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3825         data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3826         WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3827
3828         data = 0x10101010;
3829         WREG32(mmRLC_PG_DELAY, data);
3830
3831         data = RREG32(mmRLC_PG_DELAY_2);
3832         data &= ~0xff;
3833         data |= 0x3;
3834         WREG32(mmRLC_PG_DELAY_2, data);
3835
3836         data = RREG32(mmRLC_AUTO_PG_CTRL);
3837         data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3838         data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3839         WREG32(mmRLC_AUTO_PG_CTRL, data);
3840
3841 }
3842
3843 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3844 {
3845         gfx_v7_0_enable_gfx_cgpg(adev, enable);
3846         gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
3847         gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
3848 }
3849
3850 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
3851 {
3852         u32 count = 0;
3853         const struct cs_section_def *sect = NULL;
3854         const struct cs_extent_def *ext = NULL;
3855
3856         if (adev->gfx.rlc.cs_data == NULL)
3857                 return 0;
3858
3859         /* begin clear state */
3860         count += 2;
3861         /* context control state */
3862         count += 3;
3863
3864         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3865                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3866                         if (sect->id == SECT_CONTEXT)
3867                                 count += 2 + ext->reg_count;
3868                         else
3869                                 return 0;
3870                 }
3871         }
3872         /* pa_sc_raster_config/pa_sc_raster_config1 */
3873         count += 4;
3874         /* end clear state */
3875         count += 2;
3876         /* clear state */
3877         count += 2;
3878
3879         return count;
3880 }
3881
3882 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
3883                                     volatile u32 *buffer)
3884 {
3885         u32 count = 0, i;
3886         const struct cs_section_def *sect = NULL;
3887         const struct cs_extent_def *ext = NULL;
3888
3889         if (adev->gfx.rlc.cs_data == NULL)
3890                 return;
3891         if (buffer == NULL)
3892                 return;
3893
3894         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3895         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3896
3897         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3898         buffer[count++] = cpu_to_le32(0x80000000);
3899         buffer[count++] = cpu_to_le32(0x80000000);
3900
3901         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3902                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3903                         if (sect->id == SECT_CONTEXT) {
3904                                 buffer[count++] =
3905                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3906                                 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
3907                                 for (i = 0; i < ext->reg_count; i++)
3908                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
3909                         } else {
3910                                 return;
3911                         }
3912                 }
3913         }
3914
3915         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3916         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
3917         switch (adev->asic_type) {
3918         case CHIP_BONAIRE:
3919                 buffer[count++] = cpu_to_le32(0x16000012);
3920                 buffer[count++] = cpu_to_le32(0x00000000);
3921                 break;
3922         case CHIP_KAVERI:
3923                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
3924                 buffer[count++] = cpu_to_le32(0x00000000);
3925                 break;
3926         case CHIP_KABINI:
3927         case CHIP_MULLINS:
3928                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
3929                 buffer[count++] = cpu_to_le32(0x00000000);
3930                 break;
3931         case CHIP_HAWAII:
3932                 buffer[count++] = cpu_to_le32(0x3a00161a);
3933                 buffer[count++] = cpu_to_le32(0x0000002e);
3934                 break;
3935         default:
3936                 buffer[count++] = cpu_to_le32(0x00000000);
3937                 buffer[count++] = cpu_to_le32(0x00000000);
3938                 break;
3939         }
3940
3941         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3942         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
3943
3944         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
3945         buffer[count++] = cpu_to_le32(0);
3946 }
3947
3948 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
3949 {
3950         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3951                               AMD_PG_SUPPORT_GFX_SMG |
3952                               AMD_PG_SUPPORT_GFX_DMG |
3953                               AMD_PG_SUPPORT_CP |
3954                               AMD_PG_SUPPORT_GDS |
3955                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
3956                 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
3957                 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
3958                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3959                         gfx_v7_0_init_gfx_cgpg(adev);
3960                         gfx_v7_0_enable_cp_pg(adev, true);
3961                         gfx_v7_0_enable_gds_pg(adev, true);
3962                 }
3963                 gfx_v7_0_init_ao_cu_mask(adev);
3964                 gfx_v7_0_update_gfx_pg(adev, true);
3965         }
3966 }
3967
3968 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
3969 {
3970         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3971                               AMD_PG_SUPPORT_GFX_SMG |
3972                               AMD_PG_SUPPORT_GFX_DMG |
3973                               AMD_PG_SUPPORT_CP |
3974                               AMD_PG_SUPPORT_GDS |
3975                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
3976                 gfx_v7_0_update_gfx_pg(adev, false);
3977                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3978                         gfx_v7_0_enable_cp_pg(adev, false);
3979                         gfx_v7_0_enable_gds_pg(adev, false);
3980                 }
3981         }
3982 }
3983
3984 /**
3985  * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
3986  *
3987  * @adev: amdgpu_device pointer
3988  *
3989  * Fetches a GPU clock counter snapshot (SI).
3990  * Returns the 64 bit clock counter snapshot.
3991  */
3992 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3993 {
3994         uint64_t clock;
3995
3996         mutex_lock(&adev->gfx.gpu_clock_mutex);
3997         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3998         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3999                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4000         mutex_unlock(&adev->gfx.gpu_clock_mutex);
4001         return clock;
4002 }
4003
4004 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4005                                           uint32_t vmid,
4006                                           uint32_t gds_base, uint32_t gds_size,
4007                                           uint32_t gws_base, uint32_t gws_size,
4008                                           uint32_t oa_base, uint32_t oa_size)
4009 {
4010         /* GDS Base */
4011         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4012         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4013                                 WRITE_DATA_DST_SEL(0)));
4014         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4015         amdgpu_ring_write(ring, 0);
4016         amdgpu_ring_write(ring, gds_base);
4017
4018         /* GDS Size */
4019         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4020         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4021                                 WRITE_DATA_DST_SEL(0)));
4022         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4023         amdgpu_ring_write(ring, 0);
4024         amdgpu_ring_write(ring, gds_size);
4025
4026         /* GWS */
4027         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4028         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4029                                 WRITE_DATA_DST_SEL(0)));
4030         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4031         amdgpu_ring_write(ring, 0);
4032         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4033
4034         /* OA */
4035         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4036         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4037                                 WRITE_DATA_DST_SEL(0)));
4038         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4039         amdgpu_ring_write(ring, 0);
4040         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4041 }
4042
4043 static void gfx_v7_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
4044 {
4045         struct amdgpu_device *adev = ring->adev;
4046         uint32_t value = 0;
4047
4048         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
4049         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
4050         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
4051         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
4052         WREG32(mmSQ_CMD, value);
4053 }
4054
4055 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4056 {
4057         WREG32(mmSQ_IND_INDEX,
4058                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4059                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4060                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
4061                 (SQ_IND_INDEX__FORCE_READ_MASK));
4062         return RREG32(mmSQ_IND_DATA);
4063 }
4064
4065 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4066                            uint32_t wave, uint32_t thread,
4067                            uint32_t regno, uint32_t num, uint32_t *out)
4068 {
4069         WREG32(mmSQ_IND_INDEX,
4070                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4071                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4072                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4073                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4074                 (SQ_IND_INDEX__FORCE_READ_MASK) |
4075                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4076         while (num--)
4077                 *(out++) = RREG32(mmSQ_IND_DATA);
4078 }
4079
4080 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4081 {
4082         /* type 0 wave data */
4083         dst[(*no_fields)++] = 0;
4084         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
4085         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
4086         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
4087         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
4088         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
4089         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
4090         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
4091         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
4092         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
4093         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
4094         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
4095         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
4096         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
4097         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
4098         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
4099         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
4100         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
4101         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
4102         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
4103 }
4104
4105 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4106                                      uint32_t wave, uint32_t start,
4107                                      uint32_t size, uint32_t *dst)
4108 {
4109         wave_read_regs(
4110                 adev, simd, wave, 0,
4111                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4112 }
4113
4114 static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev,
4115                                   u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4116 {
4117         cik_srbm_select(adev, me, pipe, q, vm);
4118 }
4119
4120 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4121         .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4122         .select_se_sh = &gfx_v7_0_select_se_sh,
4123         .read_wave_data = &gfx_v7_0_read_wave_data,
4124         .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4125         .select_me_pipe_q = &gfx_v7_0_select_me_pipe_q
4126 };
4127
4128 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4129         .is_rlc_enabled = gfx_v7_0_is_rlc_enabled,
4130         .set_safe_mode = gfx_v7_0_set_safe_mode,
4131         .unset_safe_mode = gfx_v7_0_unset_safe_mode,
4132         .init = gfx_v7_0_rlc_init,
4133         .get_csb_size = gfx_v7_0_get_csb_size,
4134         .get_csb_buffer = gfx_v7_0_get_csb_buffer,
4135         .get_cp_table_num = gfx_v7_0_cp_pg_table_num,
4136         .resume = gfx_v7_0_rlc_resume,
4137         .stop = gfx_v7_0_rlc_stop,
4138         .reset = gfx_v7_0_rlc_reset,
4139         .start = gfx_v7_0_rlc_start,
4140         .update_spm_vmid = gfx_v7_0_update_spm_vmid
4141 };
4142
4143 static int gfx_v7_0_early_init(struct amdgpu_ip_block *ip_block)
4144 {
4145         struct amdgpu_device *adev = ip_block->adev;
4146
4147         adev->gfx.xcc_mask = 1;
4148         adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4149         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
4150                                           AMDGPU_MAX_COMPUTE_RINGS);
4151         adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
4152         adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
4153         gfx_v7_0_set_ring_funcs(adev);
4154         gfx_v7_0_set_irq_funcs(adev);
4155         gfx_v7_0_set_gds_init(adev);
4156
4157         return 0;
4158 }
4159
4160 static int gfx_v7_0_late_init(struct amdgpu_ip_block *ip_block)
4161 {
4162         struct amdgpu_device *adev = ip_block->adev;
4163         int r;
4164
4165         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4166         if (r)
4167                 return r;
4168
4169         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4170         if (r)
4171                 return r;
4172
4173         return 0;
4174 }
4175
4176 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4177 {
4178         u32 gb_addr_config;
4179         u32 mc_arb_ramcfg;
4180         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4181         u32 tmp;
4182
4183         switch (adev->asic_type) {
4184         case CHIP_BONAIRE:
4185                 adev->gfx.config.max_shader_engines = 2;
4186                 adev->gfx.config.max_tile_pipes = 4;
4187                 adev->gfx.config.max_cu_per_sh = 7;
4188                 adev->gfx.config.max_sh_per_se = 1;
4189                 adev->gfx.config.max_backends_per_se = 2;
4190                 adev->gfx.config.max_texture_channel_caches = 4;
4191                 adev->gfx.config.max_gprs = 256;
4192                 adev->gfx.config.max_gs_threads = 32;
4193                 adev->gfx.config.max_hw_contexts = 8;
4194
4195                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4196                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4197                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4198                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4199                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4200                 break;
4201         case CHIP_HAWAII:
4202                 adev->gfx.config.max_shader_engines = 4;
4203                 adev->gfx.config.max_tile_pipes = 16;
4204                 adev->gfx.config.max_cu_per_sh = 11;
4205                 adev->gfx.config.max_sh_per_se = 1;
4206                 adev->gfx.config.max_backends_per_se = 4;
4207                 adev->gfx.config.max_texture_channel_caches = 16;
4208                 adev->gfx.config.max_gprs = 256;
4209                 adev->gfx.config.max_gs_threads = 32;
4210                 adev->gfx.config.max_hw_contexts = 8;
4211
4212                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4213                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4214                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4215                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4216                 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4217                 break;
4218         case CHIP_KAVERI:
4219                 adev->gfx.config.max_shader_engines = 1;
4220                 adev->gfx.config.max_tile_pipes = 4;
4221                 adev->gfx.config.max_cu_per_sh = 8;
4222                 adev->gfx.config.max_backends_per_se = 2;
4223                 adev->gfx.config.max_sh_per_se = 1;
4224                 adev->gfx.config.max_texture_channel_caches = 4;
4225                 adev->gfx.config.max_gprs = 256;
4226                 adev->gfx.config.max_gs_threads = 16;
4227                 adev->gfx.config.max_hw_contexts = 8;
4228
4229                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4230                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4231                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4232                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4233                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4234                 break;
4235         case CHIP_KABINI:
4236         case CHIP_MULLINS:
4237         default:
4238                 adev->gfx.config.max_shader_engines = 1;
4239                 adev->gfx.config.max_tile_pipes = 2;
4240                 adev->gfx.config.max_cu_per_sh = 2;
4241                 adev->gfx.config.max_sh_per_se = 1;
4242                 adev->gfx.config.max_backends_per_se = 1;
4243                 adev->gfx.config.max_texture_channel_caches = 2;
4244                 adev->gfx.config.max_gprs = 256;
4245                 adev->gfx.config.max_gs_threads = 16;
4246                 adev->gfx.config.max_hw_contexts = 8;
4247
4248                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4249                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4250                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4251                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4252                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4253                 break;
4254         }
4255
4256         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4257         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4258
4259         adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,
4260                                 MC_ARB_RAMCFG, NOOFBANK);
4261         adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,
4262                                 MC_ARB_RAMCFG, NOOFRANKS);
4263
4264         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4265         adev->gfx.config.mem_max_burst_length_bytes = 256;
4266         if (adev->flags & AMD_IS_APU) {
4267                 /* Get memory bank mapping mode. */
4268                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4269                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4270                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4271
4272                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4273                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4274                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4275
4276                 /* Validate settings in case only one DIMM installed. */
4277                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4278                         dimm00_addr_map = 0;
4279                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4280                         dimm01_addr_map = 0;
4281                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4282                         dimm10_addr_map = 0;
4283                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4284                         dimm11_addr_map = 0;
4285
4286                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4287                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4288                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4289                         adev->gfx.config.mem_row_size_in_kb = 2;
4290                 else
4291                         adev->gfx.config.mem_row_size_in_kb = 1;
4292         } else {
4293                 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4294                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4295                 if (adev->gfx.config.mem_row_size_in_kb > 4)
4296                         adev->gfx.config.mem_row_size_in_kb = 4;
4297         }
4298         /* XXX use MC settings? */
4299         adev->gfx.config.shader_engine_tile_size = 32;
4300         adev->gfx.config.num_gpus = 1;
4301         adev->gfx.config.multi_gpu_tile_size = 64;
4302
4303         /* fix up row size */
4304         gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4305         switch (adev->gfx.config.mem_row_size_in_kb) {
4306         case 1:
4307         default:
4308                 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4309                 break;
4310         case 2:
4311                 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4312                 break;
4313         case 4:
4314                 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4315                 break;
4316         }
4317         adev->gfx.config.gb_addr_config = gb_addr_config;
4318 }
4319
4320 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4321                                         int mec, int pipe, int queue)
4322 {
4323         int r;
4324         unsigned irq_type;
4325         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
4326
4327         /* mec0 is me1 */
4328         ring->me = mec + 1;
4329         ring->pipe = pipe;
4330         ring->queue = queue;
4331
4332         ring->ring_obj = NULL;
4333         ring->use_doorbell = true;
4334         ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
4335         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4336
4337         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4338                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4339                 + ring->pipe;
4340
4341         /* type-2 packets are deprecated on MEC, use type-3 instead */
4342         r = amdgpu_ring_init(adev, ring, 1024,
4343                              &adev->gfx.eop_irq, irq_type,
4344                              AMDGPU_RING_PRIO_DEFAULT, NULL);
4345         if (r)
4346                 return r;
4347
4348
4349         return 0;
4350 }
4351
4352 static int gfx_v7_0_sw_init(struct amdgpu_ip_block *ip_block)
4353 {
4354         struct amdgpu_ring *ring;
4355         struct amdgpu_device *adev = ip_block->adev;
4356         int i, j, k, r, ring_id;
4357
4358         switch (adev->asic_type) {
4359         case CHIP_KAVERI:
4360                 adev->gfx.mec.num_mec = 2;
4361                 break;
4362         case CHIP_BONAIRE:
4363         case CHIP_HAWAII:
4364         case CHIP_KABINI:
4365         case CHIP_MULLINS:
4366         default:
4367                 adev->gfx.mec.num_mec = 1;
4368                 break;
4369         }
4370         adev->gfx.mec.num_pipe_per_mec = 4;
4371         adev->gfx.mec.num_queue_per_pipe = 8;
4372
4373         /* EOP Event */
4374         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
4375         if (r)
4376                 return r;
4377
4378         /* Privileged reg */
4379         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184,
4380                               &adev->gfx.priv_reg_irq);
4381         if (r)
4382                 return r;
4383
4384         /* Privileged inst */
4385         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185,
4386                               &adev->gfx.priv_inst_irq);
4387         if (r)
4388                 return r;
4389
4390         r = gfx_v7_0_init_microcode(adev);
4391         if (r) {
4392                 DRM_ERROR("Failed to load gfx firmware!\n");
4393                 return r;
4394         }
4395
4396         r = adev->gfx.rlc.funcs->init(adev);
4397         if (r) {
4398                 DRM_ERROR("Failed to init rlc BOs!\n");
4399                 return r;
4400         }
4401
4402         /* allocate mec buffers */
4403         r = gfx_v7_0_mec_init(adev);
4404         if (r) {
4405                 DRM_ERROR("Failed to init MEC BOs!\n");
4406                 return r;
4407         }
4408
4409         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4410                 ring = &adev->gfx.gfx_ring[i];
4411                 ring->ring_obj = NULL;
4412                 sprintf(ring->name, "gfx");
4413                 r = amdgpu_ring_init(adev, ring, 1024,
4414                                      &adev->gfx.eop_irq,
4415                                      AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
4416                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
4417                 if (r)
4418                         return r;
4419         }
4420
4421         /* set up the compute queues - allocate horizontally across pipes */
4422         ring_id = 0;
4423         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4424                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4425                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4426                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4427                                                                      k, j))
4428                                         continue;
4429
4430                                 r = gfx_v7_0_compute_ring_init(adev,
4431                                                                 ring_id,
4432                                                                 i, k, j);
4433                                 if (r)
4434                                         return r;
4435
4436                                 ring_id++;
4437                         }
4438                 }
4439         }
4440
4441         adev->gfx.ce_ram_size = 0x8000;
4442
4443         gfx_v7_0_gpu_early_init(adev);
4444
4445         return r;
4446 }
4447
4448 static int gfx_v7_0_sw_fini(struct amdgpu_ip_block *ip_block)
4449 {
4450         struct amdgpu_device *adev = ip_block->adev;
4451         int i;
4452
4453         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4454                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4455         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4456                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4457
4458         gfx_v7_0_cp_compute_fini(adev);
4459         amdgpu_gfx_rlc_fini(adev);
4460         gfx_v7_0_mec_fini(adev);
4461         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4462                                 &adev->gfx.rlc.clear_state_gpu_addr,
4463                                 (void **)&adev->gfx.rlc.cs_ptr);
4464         if (adev->gfx.rlc.cp_table_size) {
4465                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4466                                 &adev->gfx.rlc.cp_table_gpu_addr,
4467                                 (void **)&adev->gfx.rlc.cp_table_ptr);
4468         }
4469         gfx_v7_0_free_microcode(adev);
4470
4471         return 0;
4472 }
4473
4474 static int gfx_v7_0_hw_init(struct amdgpu_ip_block *ip_block)
4475 {
4476         int r;
4477         struct amdgpu_device *adev = ip_block->adev;
4478
4479         gfx_v7_0_constants_init(adev);
4480
4481         /* init CSB */
4482         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4483         /* init rlc */
4484         r = adev->gfx.rlc.funcs->resume(adev);
4485         if (r)
4486                 return r;
4487
4488         r = gfx_v7_0_cp_resume(adev);
4489         if (r)
4490                 return r;
4491
4492         return r;
4493 }
4494
4495 static int gfx_v7_0_hw_fini(struct amdgpu_ip_block *ip_block)
4496 {
4497         struct amdgpu_device *adev = ip_block->adev;
4498
4499         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4500         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4501         gfx_v7_0_cp_enable(adev, false);
4502         adev->gfx.rlc.funcs->stop(adev);
4503         gfx_v7_0_fini_pg(adev);
4504
4505         return 0;
4506 }
4507
4508 static int gfx_v7_0_suspend(struct amdgpu_ip_block *ip_block)
4509 {
4510         return gfx_v7_0_hw_fini(ip_block);
4511 }
4512
4513 static int gfx_v7_0_resume(struct amdgpu_ip_block *ip_block)
4514 {
4515         return gfx_v7_0_hw_init(ip_block);
4516 }
4517
4518 static bool gfx_v7_0_is_idle(void *handle)
4519 {
4520         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4521
4522         if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4523                 return false;
4524         else
4525                 return true;
4526 }
4527
4528 static int gfx_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
4529 {
4530         unsigned i;
4531         u32 tmp;
4532         struct amdgpu_device *adev = ip_block->adev;
4533
4534         for (i = 0; i < adev->usec_timeout; i++) {
4535                 /* read MC_STATUS */
4536                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4537
4538                 if (!tmp)
4539                         return 0;
4540                 udelay(1);
4541         }
4542         return -ETIMEDOUT;
4543 }
4544
4545 static int gfx_v7_0_soft_reset(struct amdgpu_ip_block *ip_block)
4546 {
4547         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4548         u32 tmp;
4549         struct amdgpu_device *adev = ip_block->adev;
4550
4551         /* GRBM_STATUS */
4552         tmp = RREG32(mmGRBM_STATUS);
4553         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4554                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4555                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4556                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4557                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4558                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4559                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4560                         GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4561
4562         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4563                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4564                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4565         }
4566
4567         /* GRBM_STATUS2 */
4568         tmp = RREG32(mmGRBM_STATUS2);
4569         if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4570                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4571
4572         /* SRBM_STATUS */
4573         tmp = RREG32(mmSRBM_STATUS);
4574         if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4575                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4576
4577         if (grbm_soft_reset || srbm_soft_reset) {
4578                 /* disable CG/PG */
4579                 gfx_v7_0_fini_pg(adev);
4580                 gfx_v7_0_update_cg(adev, false);
4581
4582                 /* stop the rlc */
4583                 adev->gfx.rlc.funcs->stop(adev);
4584
4585                 /* Disable GFX parsing/prefetching */
4586                 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4587
4588                 /* Disable MEC parsing/prefetching */
4589                 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4590
4591                 if (grbm_soft_reset) {
4592                         tmp = RREG32(mmGRBM_SOFT_RESET);
4593                         tmp |= grbm_soft_reset;
4594                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4595                         WREG32(mmGRBM_SOFT_RESET, tmp);
4596                         tmp = RREG32(mmGRBM_SOFT_RESET);
4597
4598                         udelay(50);
4599
4600                         tmp &= ~grbm_soft_reset;
4601                         WREG32(mmGRBM_SOFT_RESET, tmp);
4602                         tmp = RREG32(mmGRBM_SOFT_RESET);
4603                 }
4604
4605                 if (srbm_soft_reset) {
4606                         tmp = RREG32(mmSRBM_SOFT_RESET);
4607                         tmp |= srbm_soft_reset;
4608                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4609                         WREG32(mmSRBM_SOFT_RESET, tmp);
4610                         tmp = RREG32(mmSRBM_SOFT_RESET);
4611
4612                         udelay(50);
4613
4614                         tmp &= ~srbm_soft_reset;
4615                         WREG32(mmSRBM_SOFT_RESET, tmp);
4616                         tmp = RREG32(mmSRBM_SOFT_RESET);
4617                 }
4618                 /* Wait a little for things to settle down */
4619                 udelay(50);
4620         }
4621         return 0;
4622 }
4623
4624 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4625                                                  enum amdgpu_interrupt_state state)
4626 {
4627         u32 cp_int_cntl;
4628
4629         switch (state) {
4630         case AMDGPU_IRQ_STATE_DISABLE:
4631                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4632                 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4633                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4634                 break;
4635         case AMDGPU_IRQ_STATE_ENABLE:
4636                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4637                 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4638                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4639                 break;
4640         default:
4641                 break;
4642         }
4643 }
4644
4645 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4646                                                      int me, int pipe,
4647                                                      enum amdgpu_interrupt_state state)
4648 {
4649         u32 mec_int_cntl, mec_int_cntl_reg;
4650
4651         /*
4652          * amdgpu controls only the first MEC. That's why this function only
4653          * handles the setting of interrupts for this specific MEC. All other
4654          * pipes' interrupts are set by amdkfd.
4655          */
4656
4657         if (me == 1) {
4658                 switch (pipe) {
4659                 case 0:
4660                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4661                         break;
4662                 case 1:
4663                         mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
4664                         break;
4665                 case 2:
4666                         mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
4667                         break;
4668                 case 3:
4669                         mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
4670                         break;
4671                 default:
4672                         DRM_DEBUG("invalid pipe %d\n", pipe);
4673                         return;
4674                 }
4675         } else {
4676                 DRM_DEBUG("invalid me %d\n", me);
4677                 return;
4678         }
4679
4680         switch (state) {
4681         case AMDGPU_IRQ_STATE_DISABLE:
4682                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4683                 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4684                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4685                 break;
4686         case AMDGPU_IRQ_STATE_ENABLE:
4687                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4688                 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4689                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4690                 break;
4691         default:
4692                 break;
4693         }
4694 }
4695
4696 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4697                                              struct amdgpu_irq_src *src,
4698                                              unsigned type,
4699                                              enum amdgpu_interrupt_state state)
4700 {
4701         u32 cp_int_cntl;
4702
4703         switch (state) {
4704         case AMDGPU_IRQ_STATE_DISABLE:
4705                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4706                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4707                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4708                 break;
4709         case AMDGPU_IRQ_STATE_ENABLE:
4710                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4711                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4712                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4713                 break;
4714         default:
4715                 break;
4716         }
4717
4718         return 0;
4719 }
4720
4721 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4722                                               struct amdgpu_irq_src *src,
4723                                               unsigned type,
4724                                               enum amdgpu_interrupt_state state)
4725 {
4726         u32 cp_int_cntl;
4727
4728         switch (state) {
4729         case AMDGPU_IRQ_STATE_DISABLE:
4730                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4731                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4732                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4733                 break;
4734         case AMDGPU_IRQ_STATE_ENABLE:
4735                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4736                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4737                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4738                 break;
4739         default:
4740                 break;
4741         }
4742
4743         return 0;
4744 }
4745
4746 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4747                                             struct amdgpu_irq_src *src,
4748                                             unsigned type,
4749                                             enum amdgpu_interrupt_state state)
4750 {
4751         switch (type) {
4752         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4753                 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4754                 break;
4755         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4756                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4757                 break;
4758         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4759                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4760                 break;
4761         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4762                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4763                 break;
4764         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4765                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4766                 break;
4767         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4768                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4769                 break;
4770         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4771                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4772                 break;
4773         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4774                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4775                 break;
4776         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4777                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4778                 break;
4779         default:
4780                 break;
4781         }
4782         return 0;
4783 }
4784
4785 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4786                             struct amdgpu_irq_src *source,
4787                             struct amdgpu_iv_entry *entry)
4788 {
4789         u8 me_id, pipe_id;
4790         struct amdgpu_ring *ring;
4791         int i;
4792
4793         DRM_DEBUG("IH: CP EOP\n");
4794         me_id = (entry->ring_id & 0x0c) >> 2;
4795         pipe_id = (entry->ring_id & 0x03) >> 0;
4796         switch (me_id) {
4797         case 0:
4798                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4799                 break;
4800         case 1:
4801         case 2:
4802                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4803                         ring = &adev->gfx.compute_ring[i];
4804                         if ((ring->me == me_id) && (ring->pipe == pipe_id))
4805                                 amdgpu_fence_process(ring);
4806                 }
4807                 break;
4808         }
4809         return 0;
4810 }
4811
4812 static void gfx_v7_0_fault(struct amdgpu_device *adev,
4813                            struct amdgpu_iv_entry *entry)
4814 {
4815         struct amdgpu_ring *ring;
4816         u8 me_id, pipe_id;
4817         int i;
4818
4819         me_id = (entry->ring_id & 0x0c) >> 2;
4820         pipe_id = (entry->ring_id & 0x03) >> 0;
4821         switch (me_id) {
4822         case 0:
4823                 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
4824                 break;
4825         case 1:
4826         case 2:
4827                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4828                         ring = &adev->gfx.compute_ring[i];
4829                         if ((ring->me == me_id) && (ring->pipe == pipe_id))
4830                                 drm_sched_fault(&ring->sched);
4831                 }
4832                 break;
4833         }
4834 }
4835
4836 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
4837                                  struct amdgpu_irq_src *source,
4838                                  struct amdgpu_iv_entry *entry)
4839 {
4840         DRM_ERROR("Illegal register access in command stream\n");
4841         gfx_v7_0_fault(adev, entry);
4842         return 0;
4843 }
4844
4845 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
4846                                   struct amdgpu_irq_src *source,
4847                                   struct amdgpu_iv_entry *entry)
4848 {
4849         DRM_ERROR("Illegal instruction in command stream\n");
4850         // XXX soft reset the gfx block only
4851         gfx_v7_0_fault(adev, entry);
4852         return 0;
4853 }
4854
4855 static int gfx_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
4856                                           enum amd_clockgating_state state)
4857 {
4858         bool gate = false;
4859         struct amdgpu_device *adev = ip_block->adev;
4860
4861         if (state == AMD_CG_STATE_GATE)
4862                 gate = true;
4863
4864         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4865         /* order matters! */
4866         if (gate) {
4867                 gfx_v7_0_enable_mgcg(adev, true);
4868                 gfx_v7_0_enable_cgcg(adev, true);
4869         } else {
4870                 gfx_v7_0_enable_cgcg(adev, false);
4871                 gfx_v7_0_enable_mgcg(adev, false);
4872         }
4873         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4874
4875         return 0;
4876 }
4877
4878 static int gfx_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
4879                                           enum amd_powergating_state state)
4880 {
4881         bool gate = false;
4882         struct amdgpu_device *adev = ip_block->adev;
4883
4884         if (state == AMD_PG_STATE_GATE)
4885                 gate = true;
4886
4887         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4888                               AMD_PG_SUPPORT_GFX_SMG |
4889                               AMD_PG_SUPPORT_GFX_DMG |
4890                               AMD_PG_SUPPORT_CP |
4891                               AMD_PG_SUPPORT_GDS |
4892                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4893                 gfx_v7_0_update_gfx_pg(adev, gate);
4894                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4895                         gfx_v7_0_enable_cp_pg(adev, gate);
4896                         gfx_v7_0_enable_gds_pg(adev, gate);
4897                 }
4898         }
4899
4900         return 0;
4901 }
4902
4903 static void gfx_v7_0_emit_mem_sync(struct amdgpu_ring *ring)
4904 {
4905         amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
4906         amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
4907                           PACKET3_TC_ACTION_ENA |
4908                           PACKET3_SH_KCACHE_ACTION_ENA |
4909                           PACKET3_SH_ICACHE_ACTION_ENA);  /* CP_COHER_CNTL */
4910         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
4911         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE */
4912         amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
4913 }
4914
4915 static void gfx_v7_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
4916 {
4917         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
4918         amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
4919                           PACKET3_TC_ACTION_ENA |
4920                           PACKET3_SH_KCACHE_ACTION_ENA |
4921                           PACKET3_SH_ICACHE_ACTION_ENA);  /* CP_COHER_CNTL */
4922         amdgpu_ring_write(ring, 0xffffffff);    /* CP_COHER_SIZE */
4923         amdgpu_ring_write(ring, 0xff);          /* CP_COHER_SIZE_HI */
4924         amdgpu_ring_write(ring, 0);             /* CP_COHER_BASE */
4925         amdgpu_ring_write(ring, 0);             /* CP_COHER_BASE_HI */
4926         amdgpu_ring_write(ring, 0x0000000A);    /* poll interval */
4927 }
4928
4929 static void gfx_v7_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
4930                                   int mem_space, int opt, uint32_t addr0,
4931                                   uint32_t addr1, uint32_t ref, uint32_t mask,
4932                                   uint32_t inv)
4933 {
4934         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4935         amdgpu_ring_write(ring,
4936                           /* memory (1) or register (0) */
4937                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
4938                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
4939                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
4940                            WAIT_REG_MEM_ENGINE(eng_sel)));
4941
4942         if (mem_space)
4943                 BUG_ON(addr0 & 0x3); /* Dword align */
4944         amdgpu_ring_write(ring, addr0);
4945         amdgpu_ring_write(ring, addr1);
4946         amdgpu_ring_write(ring, ref);
4947         amdgpu_ring_write(ring, mask);
4948         amdgpu_ring_write(ring, inv); /* poll interval */
4949 }
4950
4951 static void gfx_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4952                                         uint32_t val, uint32_t mask)
4953 {
4954         gfx_v7_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4955 }
4956
4957 static int gfx_v7_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
4958 {
4959         struct amdgpu_device *adev = ring->adev;
4960         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
4961         struct amdgpu_ring *kiq_ring = &kiq->ring;
4962         unsigned long flags;
4963         u32 tmp;
4964         int r;
4965
4966         if (amdgpu_sriov_vf(adev))
4967                 return -EINVAL;
4968
4969         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4970                 return -EINVAL;
4971
4972         spin_lock_irqsave(&kiq->ring_lock, flags);
4973
4974         if (amdgpu_ring_alloc(kiq_ring, 5)) {
4975                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
4976                 return -ENOMEM;
4977         }
4978
4979         tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
4980         gfx_v7_0_ring_emit_wreg(kiq_ring, mmCP_VMID_RESET, tmp);
4981         amdgpu_ring_commit(kiq_ring);
4982
4983         spin_unlock_irqrestore(&kiq->ring_lock, flags);
4984
4985         r = amdgpu_ring_test_ring(kiq_ring);
4986         if (r)
4987                 return r;
4988
4989         if (amdgpu_ring_alloc(ring, 7 + 12 + 5))
4990                 return -ENOMEM;
4991         gfx_v7_0_ring_emit_fence_gfx(ring, ring->fence_drv.gpu_addr,
4992                                      ring->fence_drv.sync_seq, AMDGPU_FENCE_FLAG_EXEC);
4993         gfx_v7_0_ring_emit_reg_wait(ring, mmCP_VMID_RESET, 0, 0xffff);
4994         gfx_v7_0_ring_emit_wreg(ring, mmCP_VMID_RESET, 0);
4995
4996         return amdgpu_ring_test_ring(ring);
4997 }
4998
4999 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5000         .name = "gfx_v7_0",
5001         .early_init = gfx_v7_0_early_init,
5002         .late_init = gfx_v7_0_late_init,
5003         .sw_init = gfx_v7_0_sw_init,
5004         .sw_fini = gfx_v7_0_sw_fini,
5005         .hw_init = gfx_v7_0_hw_init,
5006         .hw_fini = gfx_v7_0_hw_fini,
5007         .suspend = gfx_v7_0_suspend,
5008         .resume = gfx_v7_0_resume,
5009         .is_idle = gfx_v7_0_is_idle,
5010         .wait_for_idle = gfx_v7_0_wait_for_idle,
5011         .soft_reset = gfx_v7_0_soft_reset,
5012         .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5013         .set_powergating_state = gfx_v7_0_set_powergating_state,
5014 };
5015
5016 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5017         .type = AMDGPU_RING_TYPE_GFX,
5018         .align_mask = 0xff,
5019         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5020         .support_64bit_ptrs = false,
5021         .get_rptr = gfx_v7_0_ring_get_rptr,
5022         .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5023         .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5024         .emit_frame_size =
5025                 20 + /* gfx_v7_0_ring_emit_gds_switch */
5026                 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5027                 5 + /* hdp invalidate */
5028                 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5029                 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5030                 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
5031                 3 + 4 + /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5032                 5, /* SURFACE_SYNC */
5033         .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
5034         .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
5035         .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
5036         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5037         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5038         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5039         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5040         .test_ring = gfx_v7_0_ring_test_ring,
5041         .test_ib = gfx_v7_0_ring_test_ib,
5042         .insert_nop = amdgpu_ring_insert_nop,
5043         .pad_ib = amdgpu_ring_generic_pad_ib,
5044         .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
5045         .emit_wreg = gfx_v7_0_ring_emit_wreg,
5046         .soft_recovery = gfx_v7_0_ring_soft_recovery,
5047         .emit_mem_sync = gfx_v7_0_emit_mem_sync,
5048         .reset = gfx_v7_0_reset_kgq,
5049 };
5050
5051 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5052         .type = AMDGPU_RING_TYPE_COMPUTE,
5053         .align_mask = 0xff,
5054         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5055         .support_64bit_ptrs = false,
5056         .get_rptr = gfx_v7_0_ring_get_rptr,
5057         .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5058         .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5059         .emit_frame_size =
5060                 20 + /* gfx_v7_0_ring_emit_gds_switch */
5061                 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5062                 5 + /* hdp invalidate */
5063                 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
5064                 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */
5065                 7 + 7 + 7 + /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5066                 7, /* gfx_v7_0_emit_mem_sync_compute */
5067         .emit_ib_size = 7, /* gfx_v7_0_ring_emit_ib_compute */
5068         .emit_ib = gfx_v7_0_ring_emit_ib_compute,
5069         .emit_fence = gfx_v7_0_ring_emit_fence_compute,
5070         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5071         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5072         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5073         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5074         .test_ring = gfx_v7_0_ring_test_ring,
5075         .test_ib = gfx_v7_0_ring_test_ib,
5076         .insert_nop = amdgpu_ring_insert_nop,
5077         .pad_ib = amdgpu_ring_generic_pad_ib,
5078         .emit_wreg = gfx_v7_0_ring_emit_wreg,
5079         .soft_recovery = gfx_v7_0_ring_soft_recovery,
5080         .emit_mem_sync = gfx_v7_0_emit_mem_sync_compute,
5081 };
5082
5083 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5084 {
5085         int i;
5086
5087         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5088                 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5089         for (i = 0; i < adev->gfx.num_compute_rings; i++)
5090                 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5091 }
5092
5093 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5094         .set = gfx_v7_0_set_eop_interrupt_state,
5095         .process = gfx_v7_0_eop_irq,
5096 };
5097
5098 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5099         .set = gfx_v7_0_set_priv_reg_fault_state,
5100         .process = gfx_v7_0_priv_reg_irq,
5101 };
5102
5103 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5104         .set = gfx_v7_0_set_priv_inst_fault_state,
5105         .process = gfx_v7_0_priv_inst_irq,
5106 };
5107
5108 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5109 {
5110         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5111         adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5112
5113         adev->gfx.priv_reg_irq.num_types = 1;
5114         adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5115
5116         adev->gfx.priv_inst_irq.num_types = 1;
5117         adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5118 }
5119
5120 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5121 {
5122         /* init asci gds info */
5123         adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);
5124         adev->gds.gws_size = 64;
5125         adev->gds.oa_size = 16;
5126         adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
5127 }
5128
5129
5130 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5131 {
5132         int i, j, k, counter, active_cu_number = 0;
5133         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5134         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5135         unsigned disable_masks[4 * 2];
5136         u32 ao_cu_num;
5137
5138         if (adev->flags & AMD_IS_APU)
5139                 ao_cu_num = 2;
5140         else
5141                 ao_cu_num = adev->gfx.config.max_cu_per_sh;
5142
5143         memset(cu_info, 0, sizeof(*cu_info));
5144
5145         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5146
5147         mutex_lock(&adev->grbm_idx_mutex);
5148         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5149                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5150                         mask = 1;
5151                         ao_bitmap = 0;
5152                         counter = 0;
5153                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5154                         if (i < 4 && j < 2)
5155                                 gfx_v7_0_set_user_cu_inactive_bitmap(
5156                                         adev, disable_masks[i * 2 + j]);
5157                         bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5158                         cu_info->bitmap[0][i][j] = bitmap;
5159
5160                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5161                                 if (bitmap & mask) {
5162                                         if (counter < ao_cu_num)
5163                                                 ao_bitmap |= mask;
5164                                         counter++;
5165                                 }
5166                                 mask <<= 1;
5167                         }
5168                         active_cu_number += counter;
5169                         if (i < 2 && j < 2)
5170                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5171                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5172                 }
5173         }
5174         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5175         mutex_unlock(&adev->grbm_idx_mutex);
5176
5177         cu_info->number = active_cu_number;
5178         cu_info->ao_cu_mask = ao_cu_mask;
5179         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5180         cu_info->max_waves_per_simd = 10;
5181         cu_info->max_scratch_slots_per_cu = 32;
5182         cu_info->wave_front_size = 64;
5183         cu_info->lds_size = 64;
5184 }
5185
5186 const struct amdgpu_ip_block_version gfx_v7_1_ip_block = {
5187         .type = AMD_IP_BLOCK_TYPE_GFX,
5188         .major = 7,
5189         .minor = 1,
5190         .rev = 0,
5191         .funcs = &gfx_v7_0_ip_funcs,
5192 };
5193
5194 const struct amdgpu_ip_block_version gfx_v7_2_ip_block = {
5195         .type = AMD_IP_BLOCK_TYPE_GFX,
5196         .major = 7,
5197         .minor = 2,
5198         .rev = 0,
5199         .funcs = &gfx_v7_0_ip_funcs,
5200 };
5201
5202 const struct amdgpu_ip_block_version gfx_v7_3_ip_block = {
5203         .type = AMD_IP_BLOCK_TYPE_GFX,
5204         .major = 7,
5205         .minor = 3,
5206         .rev = 0,
5207         .funcs = &gfx_v7_0_ip_funcs,
5208 };