drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DAL_DCHUBBUB_H__
  27 #define __DAL_DCHUBBUB_H__
  28
  29 /**
  30  * DOC: overview
  31  *
  32  * There is only one common DCHUBBUB. It contains the common request and return
  33  * blocks for the Data Fabric Interface that are not clock/power gated.
  34  */
  35
  36 #include "dc/dc_hw_types.h"
  37
  38 enum dcc_control {
  39         dcc_control__256_256_xxx,
  40         dcc_control__128_128_xxx,
  41         dcc_control__256_64_64,
  42         dcc_control__256_128_128,
  43         dcc_control__256_256,
  44         dcc_control__256_128,
  45         dcc_control__256_64,
  46
  47 };
  48
  49 enum segment_order {
  50         segment_order__na,
  51         segment_order__contiguous,
  52         segment_order__non_contiguous,
  53 };
  54
  55 struct dcn_hubbub_wm_set {
  56         uint32_t wm_set;
  57         uint32_t data_urgent;
  58         uint32_t pte_meta_urgent;
  59         uint32_t sr_enter;
  60         uint32_t sr_exit;
  61         uint32_t dram_clk_change;
  62         uint32_t usr_retrain;
  63         uint32_t fclk_pstate_change;
  64         uint32_t sr_enter_exit_Z8;
  65         uint32_t sr_enter_Z8;
  66 };
  67
  68 struct dcn_hubbub_wm {
  69         struct dcn_hubbub_wm_set sets[4];
  70 };
  71
  72 enum dcn_hubbub_page_table_depth {
  73         DCN_PAGE_TABLE_DEPTH_1_LEVEL,
  74         DCN_PAGE_TABLE_DEPTH_2_LEVEL,
  75         DCN_PAGE_TABLE_DEPTH_3_LEVEL,
  76         DCN_PAGE_TABLE_DEPTH_4_LEVEL
  77 };
  78
  79 enum dcn_hubbub_page_table_block_size {
  80         DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0,
  81         DCN_PAGE_TABLE_BLOCK_SIZE_8KB = 1,
  82         DCN_PAGE_TABLE_BLOCK_SIZE_16KB = 2,
  83         DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3,
  84         DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4,
  85         DCN_PAGE_TABLE_BLOCK_SIZE_128KB = 5,
  86         DCN_PAGE_TABLE_BLOCK_SIZE_256KB = 6,
  87         DCN_PAGE_TABLE_BLOCK_SIZE_512KB = 7,
  88         DCN_PAGE_TABLE_BLOCK_SIZE_1024KB = 8,
  89         DCN_PAGE_TABLE_BLOCK_SIZE_2048KB = 9
  90 };
  91
  92 struct dcn_hubbub_phys_addr_config {
  93         struct {
  94                 uint64_t fb_top;
  95                 uint64_t fb_offset;
  96                 uint64_t fb_base;
  97                 uint64_t agp_top;
  98                 uint64_t agp_bot;
  99                 uint64_t agp_base;
 100         } system_aperture;
 101
 102         struct {
 103                 uint64_t page_table_start_addr;
 104                 uint64_t page_table_end_addr;
 105                 uint64_t page_table_base_addr;
 106         } gart_config;
 107
 108         uint64_t page_table_default_page_addr;
 109 };
 110
 111 struct dcn_hubbub_virt_addr_config {
 112         uint64_t                                page_table_start_addr;
 113         uint64_t                                page_table_end_addr;
 114         enum dcn_hubbub_page_table_block_size   page_table_block_size;
 115         enum dcn_hubbub_page_table_depth        page_table_depth;
 116         uint64_t                                page_table_base_addr;
 117 };
 118
 119 struct hubbub_addr_config {
 120         struct dcn_hubbub_phys_addr_config pa_config;
 121         struct dcn_hubbub_virt_addr_config va_config;
 122         struct {
 123                 uint64_t aperture_check_fault;
 124                 uint64_t generic_fault;
 125         } default_addrs;
 126 };
 127
 128 struct dcn_hubbub_state {
 129         uint32_t vm_fault_addr_msb;
 130         uint32_t vm_fault_addr_lsb;
 131         uint32_t vm_error_status;
 132         uint32_t vm_error_vmid;
 133         uint32_t vm_error_pipe;
 134         uint32_t vm_error_mode;
 135         uint32_t test_debug_data;
 136         uint32_t watermark_change_cntl;
 137         uint32_t dram_state_cntl;
 138 };
 139
 140 struct hubbub_funcs {
 141         void (*update_dchub)(
 142                         struct hubbub *hubbub,
 143                         struct dchub_init_data *dh_data);
 144
 145         int (*init_dchub_sys_ctx)(
 146                         struct hubbub *hubbub,
 147                         struct dcn_hubbub_phys_addr_config *pa_config);
 148         void (*init_vm_ctx)(
 149                         struct hubbub *hubbub,
 150                         struct dcn_hubbub_virt_addr_config *va_config,
 151                         int vmid);
 152
 153         bool (*get_dcc_compression_cap)(struct hubbub *hubbub,
 154                         const struct dc_dcc_surface_param *input,
 155                         struct dc_surface_dcc_cap *output);
 156
 157         bool (*dcc_support_swizzle)(
 158                         enum swizzle_mode_values swizzle,
 159                         unsigned int bytes_per_element,
 160                         enum segment_order *segment_order_horz,
 161                         enum segment_order *segment_order_vert);
 162
 163         bool (*dcc_support_swizzle_addr3)(
 164                         enum swizzle_mode_addr3_values swizzle,
 165                         unsigned int plane_pitch,
 166                         unsigned int bytes_per_element,
 167                         enum segment_order *segment_order_horz,
 168                         enum segment_order *segment_order_vert);
 169
 170         bool (*dcc_support_pixel_format_plane0_plane1)(
 171                         enum surface_pixel_format format,
 172                         unsigned int *plane0_bpe,
 173                         unsigned int *plane1_bpe);
 174         bool (*dcc_support_pixel_format)(
 175                         enum surface_pixel_format format,
 176                         unsigned int *bytes_per_element);
 177
 178         void (*wm_read_state)(struct hubbub *hubbub,
 179                         struct dcn_hubbub_wm *wm);
 180
 181         void (*get_dchub_ref_freq)(struct hubbub *hubbub,
 182                         unsigned int dccg_ref_freq_inKhz,
 183                         unsigned int *dchub_ref_freq_inKhz);
 184
 185         bool (*program_watermarks)(
 186                         struct hubbub *hubbub,
 187                         union dcn_watermark_set *watermarks,
 188                         unsigned int refclk_mhz,
 189                         bool safe_to_lower);
 190
 191         bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub);
 192         void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
 193
 194         bool (*verify_allow_pstate_change_high)(struct hubbub *hubbub);
 195
 196         void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub);
 197
 198         void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub);
 199
 200         void (*hubbub_read_state)(struct hubbub *hubbub, struct dcn_hubbub_state *hubbub_state);
 201
 202         void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow);
 203
 204         void (*init_watermarks)(struct hubbub *hubbub);
 205
 206         /**
 207          * @program_det_size:
 208          *
 209          * DE-Tile buffers (DET) is a memory that is used to convert the tiled
 210          * data into linear, which the rest of the display can use to generate
 211          * the graphics output. One of the main features of this component is
 212          * that each pipe has a configurable DET buffer which means that when a
 213          * pipe is not enabled, the device can assign the memory to other
 214          * enabled pipes to try to be more efficient.
 215          *
 216          * DET logic is handled by dchubbub. Some ASICs provide a feature named
 217          * Configurable Return Buffer (CRB) segments which can be allocated to
 218          * compressed or detiled buffers.
 219          */
 220         void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte);
 221         void (*wait_for_det_apply)(struct hubbub *hubbub, int hubp_inst);
 222         void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase);
 223         void (*init_crb)(struct hubbub *hubbub);
 224         void (*force_usr_retraining_allow)(struct hubbub *hubbub, bool allow);
 225         void (*set_request_limit)(struct hubbub *hubbub, int memory_channel_count, int words_per_channel);
 226         void (*dchubbub_init)(struct hubbub *hubbub);
 227         void (*get_mall_en)(struct hubbub *hubbub, unsigned int *mall_in_use);
 228         void (*program_det_segments)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg);
 229         void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase);
 230 };
 231
 232 struct hubbub {
 233         const struct hubbub_funcs *funcs;
 234         struct dc_context *ctx;
 235         bool riommu_active;
 236 };
 237
 238 #endif