drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_drv.h>
  32 #include <drm/drm_fb_helper.h>
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "atom.h"
  36
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/slab.h>
  39 #include <linux/uaccess.h>
  40 #include <linux/pci.h>
  41 #include <linux/pm_runtime.h>
  42 #include "amdgpu_amdkfd.h"
  43 #include "amdgpu_gem.h"
  44 #include "amdgpu_display.h"
  45 #include "amdgpu_ras.h"
  46 #include "amd_pcie.h"
  47
  48 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  49 {
  50         struct amdgpu_gpu_instance *gpu_instance;
  51         int i;
  52
  53         mutex_lock(&mgpu_info.mutex);
  54
  55         for (i = 0; i < mgpu_info.num_gpu; i++) {
  56                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  57                 if (gpu_instance->adev == adev) {
  58                         mgpu_info.gpu_ins[i] =
  59                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  60                         mgpu_info.num_gpu--;
  61                         if (adev->flags & AMD_IS_APU)
  62                                 mgpu_info.num_apu--;
  63                         else
  64                                 mgpu_info.num_dgpu--;
  65                         break;
  66                 }
  67         }
  68
  69         mutex_unlock(&mgpu_info.mutex);
  70 }
  71
  72 /**
  73  * amdgpu_driver_unload_kms - Main unload function for KMS.
  74  *
  75  * @dev: drm dev pointer
  76  *
  77  * This is the main unload function for KMS (all asics).
  78  * Returns 0 on success.
  79  */
  80 void amdgpu_driver_unload_kms(struct drm_device *dev)
  81 {
  82         struct amdgpu_device *adev = drm_to_adev(dev);
  83
  84         if (adev == NULL)
  85                 return;
  86
  87         amdgpu_unregister_gpu_instance(adev);
  88
  89         if (adev->rmmio == NULL)
  90                 return;
  91
  92         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
  93                 DRM_WARN("smart shift update failed\n");
  94
  95         amdgpu_acpi_fini(adev);
  96         amdgpu_device_fini_hw(adev);
  97 }
  98
  99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 100 {
 101         struct amdgpu_gpu_instance *gpu_instance;
 102
 103         mutex_lock(&mgpu_info.mutex);
 104
 105         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 106                 DRM_ERROR("Cannot register more gpu instance\n");
 107                 mutex_unlock(&mgpu_info.mutex);
 108                 return;
 109         }
 110
 111         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 112         gpu_instance->adev = adev;
 113         gpu_instance->mgpu_fan_enabled = 0;
 114
 115         mgpu_info.num_gpu++;
 116         if (adev->flags & AMD_IS_APU)
 117                 mgpu_info.num_apu++;
 118         else
 119                 mgpu_info.num_dgpu++;
 120
 121         mutex_unlock(&mgpu_info.mutex);
 122 }
 123
 124 /**
 125  * amdgpu_driver_load_kms - Main load function for KMS.
 126  *
 127  * @adev: pointer to struct amdgpu_device
 128  * @flags: device flags
 129  *
 130  * This is the main load function for KMS (all asics).
 131  * Returns 0 on success, error on failure.
 132  */
 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 134 {
 135         struct drm_device *dev;
 136         int r, acpi_status;
 137
 138         dev = adev_to_drm(adev);
 139
 140         /* amdgpu_device_init should report only fatal error
 141          * like memory allocation failure or iomapping failure,
 142          * or memory manager initialization failure, it must
 143          * properly initialize the GPU MC controller and permit
 144          * VRAM allocation
 145          */
 146         r = amdgpu_device_init(adev, flags);
 147         if (r) {
 148                 dev_err(dev->dev, "Fatal error during GPU init\n");
 149                 goto out;
 150         }
 151
 152         adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
 153         if (amdgpu_device_supports_px(dev) &&
 154             (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */
 155                 adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
 156                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 157         } else if (amdgpu_device_supports_boco(dev) &&
 158                    (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */
 159                 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
 160                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 161         } else if (amdgpu_device_supports_baco(dev) &&
 162                    (amdgpu_runtime_pm != 0)) {
 163                 switch (adev->asic_type) {
 164                 case CHIP_VEGA20:
 165                 case CHIP_ARCTURUS:
 166                         /* enable BACO as runpm mode if runpm=1 */
 167                         if (amdgpu_runtime_pm > 0)
 168                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 169                         break;
 170                 case CHIP_VEGA10:
 171                         /* enable BACO as runpm mode if noretry=0 */
 172                         if (!adev->gmc.noretry)
 173                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 174                         break;
 175                 default:
 176                         /* enable BACO as runpm mode on CI+ */
 177                         adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 178                         break;
 179                 }
 180
 181                 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
 182                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 183         }
 184
 185         /* Call ACPI methods: require modeset init
 186          * but failure is not fatal
 187          */
 188
 189         acpi_status = amdgpu_acpi_init(adev);
 190         if (acpi_status)
 191                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 192
 193         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
 194                 DRM_WARN("smart shift update failed\n");
 195
 196 out:
 197         if (r)
 198                 amdgpu_driver_unload_kms(dev);
 199
 200         return r;
 201 }
 202
 203 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 204                                 struct drm_amdgpu_query_fw *query_fw,
 205                                 struct amdgpu_device *adev)
 206 {
 207         switch (query_fw->fw_type) {
 208         case AMDGPU_INFO_FW_VCE:
 209                 fw_info->ver = adev->vce.fw_version;
 210                 fw_info->feature = adev->vce.fb_version;
 211                 break;
 212         case AMDGPU_INFO_FW_UVD:
 213                 fw_info->ver = adev->uvd.fw_version;
 214                 fw_info->feature = 0;
 215                 break;
 216         case AMDGPU_INFO_FW_VCN:
 217                 fw_info->ver = adev->vcn.fw_version;
 218                 fw_info->feature = 0;
 219                 break;
 220         case AMDGPU_INFO_FW_GMC:
 221                 fw_info->ver = adev->gmc.fw_version;
 222                 fw_info->feature = 0;
 223                 break;
 224         case AMDGPU_INFO_FW_GFX_ME:
 225                 fw_info->ver = adev->gfx.me_fw_version;
 226                 fw_info->feature = adev->gfx.me_feature_version;
 227                 break;
 228         case AMDGPU_INFO_FW_GFX_PFP:
 229                 fw_info->ver = adev->gfx.pfp_fw_version;
 230                 fw_info->feature = adev->gfx.pfp_feature_version;
 231                 break;
 232         case AMDGPU_INFO_FW_GFX_CE:
 233                 fw_info->ver = adev->gfx.ce_fw_version;
 234                 fw_info->feature = adev->gfx.ce_feature_version;
 235                 break;
 236         case AMDGPU_INFO_FW_GFX_RLC:
 237                 fw_info->ver = adev->gfx.rlc_fw_version;
 238                 fw_info->feature = adev->gfx.rlc_feature_version;
 239                 break;
 240         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 241                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 242                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 243                 break;
 244         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 245                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 246                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 247                 break;
 248         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 249                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 250                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 251                 break;
 252         case AMDGPU_INFO_FW_GFX_RLCP:
 253                 fw_info->ver = adev->gfx.rlcp_ucode_version;
 254                 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
 255                 break;
 256         case AMDGPU_INFO_FW_GFX_RLCV:
 257                 fw_info->ver = adev->gfx.rlcv_ucode_version;
 258                 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
 259                 break;
 260         case AMDGPU_INFO_FW_GFX_MEC:
 261                 if (query_fw->index == 0) {
 262                         fw_info->ver = adev->gfx.mec_fw_version;
 263                         fw_info->feature = adev->gfx.mec_feature_version;
 264                 } else if (query_fw->index == 1) {
 265                         fw_info->ver = adev->gfx.mec2_fw_version;
 266                         fw_info->feature = adev->gfx.mec2_feature_version;
 267                 } else
 268                         return -EINVAL;
 269                 break;
 270         case AMDGPU_INFO_FW_SMC:
 271                 fw_info->ver = adev->pm.fw_version;
 272                 fw_info->feature = 0;
 273                 break;
 274         case AMDGPU_INFO_FW_TA:
 275                 switch (query_fw->index) {
 276                 case TA_FW_TYPE_PSP_XGMI:
 277                         fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
 278                         fw_info->feature = adev->psp.xgmi_context.context
 279                                                    .bin_desc.feature_version;
 280                         break;
 281                 case TA_FW_TYPE_PSP_RAS:
 282                         fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
 283                         fw_info->feature = adev->psp.ras_context.context
 284                                                    .bin_desc.feature_version;
 285                         break;
 286                 case TA_FW_TYPE_PSP_HDCP:
 287                         fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
 288                         fw_info->feature = adev->psp.hdcp_context.context
 289                                                    .bin_desc.feature_version;
 290                         break;
 291                 case TA_FW_TYPE_PSP_DTM:
 292                         fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
 293                         fw_info->feature = adev->psp.dtm_context.context
 294                                                    .bin_desc.feature_version;
 295                         break;
 296                 case TA_FW_TYPE_PSP_RAP:
 297                         fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
 298                         fw_info->feature = adev->psp.rap_context.context
 299                                                    .bin_desc.feature_version;
 300                         break;
 301                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 302                         fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
 303                         fw_info->feature =
 304                                 adev->psp.securedisplay_context.context.bin_desc
 305                                         .feature_version;
 306                         break;
 307                 default:
 308                         return -EINVAL;
 309                 }
 310                 break;
 311         case AMDGPU_INFO_FW_SDMA:
 312                 if (query_fw->index >= adev->sdma.num_instances)
 313                         return -EINVAL;
 314                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 315                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 316                 break;
 317         case AMDGPU_INFO_FW_SOS:
 318                 fw_info->ver = adev->psp.sos.fw_version;
 319                 fw_info->feature = adev->psp.sos.feature_version;
 320                 break;
 321         case AMDGPU_INFO_FW_ASD:
 322                 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
 323                 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
 324                 break;
 325         case AMDGPU_INFO_FW_DMCU:
 326                 fw_info->ver = adev->dm.dmcu_fw_version;
 327                 fw_info->feature = 0;
 328                 break;
 329         case AMDGPU_INFO_FW_DMCUB:
 330                 fw_info->ver = adev->dm.dmcub_fw_version;
 331                 fw_info->feature = 0;
 332                 break;
 333         case AMDGPU_INFO_FW_TOC:
 334                 fw_info->ver = adev->psp.toc.fw_version;
 335                 fw_info->feature = adev->psp.toc.feature_version;
 336                 break;
 337         case AMDGPU_INFO_FW_CAP:
 338                 fw_info->ver = adev->psp.cap_fw_version;
 339                 fw_info->feature = adev->psp.cap_feature_version;
 340                 break;
 341         case AMDGPU_INFO_FW_MES_KIQ:
 342                 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
 343                 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK)
 344                                         >> AMDGPU_MES_FEAT_VERSION_SHIFT;
 345                 break;
 346         case AMDGPU_INFO_FW_MES:
 347                 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
 348                 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK)
 349                                         >> AMDGPU_MES_FEAT_VERSION_SHIFT;
 350                 break;
 351         case AMDGPU_INFO_FW_IMU:
 352                 fw_info->ver = adev->gfx.imu_fw_version;
 353                 fw_info->feature = 0;
 354                 break;
 355         default:
 356                 return -EINVAL;
 357         }
 358         return 0;
 359 }
 360
 361 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 362                              struct drm_amdgpu_info *info,
 363                              struct drm_amdgpu_info_hw_ip *result)
 364 {
 365         uint32_t ib_start_alignment = 0;
 366         uint32_t ib_size_alignment = 0;
 367         enum amd_ip_block_type type;
 368         unsigned int num_rings = 0;
 369         unsigned int i, j;
 370
 371         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 372                 return -EINVAL;
 373
 374         switch (info->query_hw_ip.type) {
 375         case AMDGPU_HW_IP_GFX:
 376                 type = AMD_IP_BLOCK_TYPE_GFX;
 377                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 378                         if (adev->gfx.gfx_ring[i].sched.ready)
 379                                 ++num_rings;
 380                 ib_start_alignment = 32;
 381                 ib_size_alignment = 32;
 382                 break;
 383         case AMDGPU_HW_IP_COMPUTE:
 384                 type = AMD_IP_BLOCK_TYPE_GFX;
 385                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 386                         if (adev->gfx.compute_ring[i].sched.ready)
 387                                 ++num_rings;
 388                 ib_start_alignment = 32;
 389                 ib_size_alignment = 32;
 390                 break;
 391         case AMDGPU_HW_IP_DMA:
 392                 type = AMD_IP_BLOCK_TYPE_SDMA;
 393                 for (i = 0; i < adev->sdma.num_instances; i++)
 394                         if (adev->sdma.instance[i].ring.sched.ready)
 395                                 ++num_rings;
 396                 ib_start_alignment = 256;
 397                 ib_size_alignment = 4;
 398                 break;
 399         case AMDGPU_HW_IP_UVD:
 400                 type = AMD_IP_BLOCK_TYPE_UVD;
 401                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 402                         if (adev->uvd.harvest_config & (1 << i))
 403                                 continue;
 404
 405                         if (adev->uvd.inst[i].ring.sched.ready)
 406                                 ++num_rings;
 407                 }
 408                 ib_start_alignment = 64;
 409                 ib_size_alignment = 64;
 410                 break;
 411         case AMDGPU_HW_IP_VCE:
 412                 type = AMD_IP_BLOCK_TYPE_VCE;
 413                 for (i = 0; i < adev->vce.num_rings; i++)
 414                         if (adev->vce.ring[i].sched.ready)
 415                                 ++num_rings;
 416                 ib_start_alignment = 4;
 417                 ib_size_alignment = 1;
 418                 break;
 419         case AMDGPU_HW_IP_UVD_ENC:
 420                 type = AMD_IP_BLOCK_TYPE_UVD;
 421                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 422                         if (adev->uvd.harvest_config & (1 << i))
 423                                 continue;
 424
 425                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 426                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 427                                         ++num_rings;
 428                 }
 429                 ib_start_alignment = 64;
 430                 ib_size_alignment = 64;
 431                 break;
 432         case AMDGPU_HW_IP_VCN_DEC:
 433                 type = AMD_IP_BLOCK_TYPE_VCN;
 434                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 435                         if (adev->vcn.harvest_config & (1 << i))
 436                                 continue;
 437
 438                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 439                                 ++num_rings;
 440                 }
 441                 ib_start_alignment = 16;
 442                 ib_size_alignment = 16;
 443                 break;
 444         case AMDGPU_HW_IP_VCN_ENC:
 445                 type = AMD_IP_BLOCK_TYPE_VCN;
 446                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 447                         if (adev->vcn.harvest_config & (1 << i))
 448                                 continue;
 449
 450                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 451                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 452                                         ++num_rings;
 453                 }
 454                 ib_start_alignment = 64;
 455                 ib_size_alignment = 1;
 456                 break;
 457         case AMDGPU_HW_IP_VCN_JPEG:
 458                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 459                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 460
 461                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 462                         if (adev->jpeg.harvest_config & (1 << i))
 463                                 continue;
 464
 465                         for (j = 0; j < adev->jpeg.num_jpeg_rings; j++)
 466                                 if (adev->jpeg.inst[i].ring_dec[j].sched.ready)
 467                                         ++num_rings;
 468                 }
 469                 ib_start_alignment = 16;
 470                 ib_size_alignment = 16;
 471                 break;
 472         default:
 473                 return -EINVAL;
 474         }
 475
 476         for (i = 0; i < adev->num_ip_blocks; i++)
 477                 if (adev->ip_blocks[i].version->type == type &&
 478                     adev->ip_blocks[i].status.valid)
 479                         break;
 480
 481         if (i == adev->num_ip_blocks)
 482                 return 0;
 483
 484         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 485                         num_rings);
 486
 487         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 488         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 489
 490         if (adev->asic_type >= CHIP_VEGA10) {
 491                 switch (type) {
 492                 case AMD_IP_BLOCK_TYPE_GFX:
 493                         result->ip_discovery_version = adev->ip_versions[GC_HWIP][0];
 494                         break;
 495                 case AMD_IP_BLOCK_TYPE_SDMA:
 496                         result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0];
 497                         break;
 498                 case AMD_IP_BLOCK_TYPE_UVD:
 499                 case AMD_IP_BLOCK_TYPE_VCN:
 500                 case AMD_IP_BLOCK_TYPE_JPEG:
 501                         result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0];
 502                         break;
 503                 case AMD_IP_BLOCK_TYPE_VCE:
 504                         result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0];
 505                         break;
 506                 default:
 507                         result->ip_discovery_version = 0;
 508                         break;
 509                 }
 510         } else {
 511                 result->ip_discovery_version = 0;
 512         }
 513         result->capabilities_flags = 0;
 514         result->available_rings = (1 << num_rings) - 1;
 515         result->ib_start_alignment = ib_start_alignment;
 516         result->ib_size_alignment = ib_size_alignment;
 517         return 0;
 518 }
 519
 520 /*
 521  * Userspace get information ioctl
 522  */
 523 /**
 524  * amdgpu_info_ioctl - answer a device specific request.
 525  *
 526  * @dev: drm device pointer
 527  * @data: request object
 528  * @filp: drm filp
 529  *
 530  * This function is used to pass device specific parameters to the userspace
 531  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 532  * etc. (all asics).
 533  * Returns 0 on success, -EINVAL on failure.
 534  */
 535 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 536 {
 537         struct amdgpu_device *adev = drm_to_adev(dev);
 538         struct drm_amdgpu_info *info = data;
 539         struct amdgpu_mode_info *minfo = &adev->mode_info;
 540         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 541         uint32_t size = info->return_size;
 542         struct drm_crtc *crtc;
 543         uint32_t ui32 = 0;
 544         uint64_t ui64 = 0;
 545         int i, found;
 546         int ui32_size = sizeof(ui32);
 547
 548         if (!info->return_size || !info->return_pointer)
 549                 return -EINVAL;
 550
 551         switch (info->query) {
 552         case AMDGPU_INFO_ACCEL_WORKING:
 553                 ui32 = adev->accel_working;
 554                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 555         case AMDGPU_INFO_CRTC_FROM_ID:
 556                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 557                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 558                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 559                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 560                                 ui32 = amdgpu_crtc->crtc_id;
 561                                 found = 1;
 562                                 break;
 563                         }
 564                 }
 565                 if (!found) {
 566                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 567                         return -EINVAL;
 568                 }
 569                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 570         case AMDGPU_INFO_HW_IP_INFO: {
 571                 struct drm_amdgpu_info_hw_ip ip = {};
 572                 int ret;
 573
 574                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 575                 if (ret)
 576                         return ret;
 577
 578                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 579                 return ret ? -EFAULT : 0;
 580         }
 581         case AMDGPU_INFO_HW_IP_COUNT: {
 582                 enum amd_ip_block_type type;
 583                 uint32_t count = 0;
 584
 585                 switch (info->query_hw_ip.type) {
 586                 case AMDGPU_HW_IP_GFX:
 587                         type = AMD_IP_BLOCK_TYPE_GFX;
 588                         break;
 589                 case AMDGPU_HW_IP_COMPUTE:
 590                         type = AMD_IP_BLOCK_TYPE_GFX;
 591                         break;
 592                 case AMDGPU_HW_IP_DMA:
 593                         type = AMD_IP_BLOCK_TYPE_SDMA;
 594                         break;
 595                 case AMDGPU_HW_IP_UVD:
 596                         type = AMD_IP_BLOCK_TYPE_UVD;
 597                         break;
 598                 case AMDGPU_HW_IP_VCE:
 599                         type = AMD_IP_BLOCK_TYPE_VCE;
 600                         break;
 601                 case AMDGPU_HW_IP_UVD_ENC:
 602                         type = AMD_IP_BLOCK_TYPE_UVD;
 603                         break;
 604                 case AMDGPU_HW_IP_VCN_DEC:
 605                 case AMDGPU_HW_IP_VCN_ENC:
 606                         type = AMD_IP_BLOCK_TYPE_VCN;
 607                         break;
 608                 case AMDGPU_HW_IP_VCN_JPEG:
 609                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 610                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 611                         break;
 612                 default:
 613                         return -EINVAL;
 614                 }
 615
 616                 for (i = 0; i < adev->num_ip_blocks; i++)
 617                         if (adev->ip_blocks[i].version->type == type &&
 618                             adev->ip_blocks[i].status.valid &&
 619                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 620                                 count++;
 621
 622                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 623         }
 624         case AMDGPU_INFO_TIMESTAMP:
 625                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 626                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 627         case AMDGPU_INFO_FW_VERSION: {
 628                 struct drm_amdgpu_info_firmware fw_info;
 629                 int ret;
 630
 631                 /* We only support one instance of each IP block right now. */
 632                 if (info->query_fw.ip_instance != 0)
 633                         return -EINVAL;
 634
 635                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 636                 if (ret)
 637                         return ret;
 638
 639                 return copy_to_user(out, &fw_info,
 640                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 641         }
 642         case AMDGPU_INFO_NUM_BYTES_MOVED:
 643                 ui64 = atomic64_read(&adev->num_bytes_moved);
 644                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 645         case AMDGPU_INFO_NUM_EVICTIONS:
 646                 ui64 = atomic64_read(&adev->num_evictions);
 647                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 648         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 649                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 650                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 651         case AMDGPU_INFO_VRAM_USAGE:
 652                 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 653                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 654         case AMDGPU_INFO_VIS_VRAM_USAGE:
 655                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 656                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 657         case AMDGPU_INFO_GTT_USAGE:
 658                 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
 659                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 660         case AMDGPU_INFO_GDS_CONFIG: {
 661                 struct drm_amdgpu_info_gds gds_info;
 662
 663                 memset(&gds_info, 0, sizeof(gds_info));
 664                 gds_info.compute_partition_size = adev->gds.gds_size;
 665                 gds_info.gds_total_size = adev->gds.gds_size;
 666                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 667                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 668                 return copy_to_user(out, &gds_info,
 669                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 670         }
 671         case AMDGPU_INFO_VRAM_GTT: {
 672                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 673
 674                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 675                         atomic64_read(&adev->vram_pin_size) -
 676                         AMDGPU_VM_RESERVED_VRAM;
 677                 vram_gtt.vram_cpu_accessible_size =
 678                         min(adev->gmc.visible_vram_size -
 679                             atomic64_read(&adev->visible_pin_size),
 680                             vram_gtt.vram_size);
 681                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 682                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 683                 return copy_to_user(out, &vram_gtt,
 684                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 685         }
 686         case AMDGPU_INFO_MEMORY: {
 687                 struct drm_amdgpu_memory_info mem;
 688                 struct ttm_resource_manager *gtt_man =
 689                         &adev->mman.gtt_mgr.manager;
 690                 struct ttm_resource_manager *vram_man =
 691                         &adev->mman.vram_mgr.manager;
 692
 693                 memset(&mem, 0, sizeof(mem));
 694                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 695                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 696                         atomic64_read(&adev->vram_pin_size) -
 697                         AMDGPU_VM_RESERVED_VRAM;
 698                 mem.vram.heap_usage =
 699                         ttm_resource_manager_usage(vram_man);
 700                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 701
 702                 mem.cpu_accessible_vram.total_heap_size =
 703                         adev->gmc.visible_vram_size;
 704                 mem.cpu_accessible_vram.usable_heap_size =
 705                         min(adev->gmc.visible_vram_size -
 706                             atomic64_read(&adev->visible_pin_size),
 707                             mem.vram.usable_heap_size);
 708                 mem.cpu_accessible_vram.heap_usage =
 709                         amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 710                 mem.cpu_accessible_vram.max_allocation =
 711                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 712
 713                 mem.gtt.total_heap_size = gtt_man->size;
 714                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 715                         atomic64_read(&adev->gart_pin_size);
 716                 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
 717                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 718
 719                 return copy_to_user(out, &mem,
 720                                     min((size_t)size, sizeof(mem)))
 721                                     ? -EFAULT : 0;
 722         }
 723         case AMDGPU_INFO_READ_MMR_REG: {
 724                 unsigned n, alloc_size;
 725                 uint32_t *regs;
 726                 unsigned se_num = (info->read_mmr_reg.instance >>
 727                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 728                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 729                 unsigned sh_num = (info->read_mmr_reg.instance >>
 730                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 731                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 732
 733                 /* set full masks if the userspace set all bits
 734                  * in the bitfields */
 735                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 736                         se_num = 0xffffffff;
 737                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 738                         return -EINVAL;
 739                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 740                         sh_num = 0xffffffff;
 741                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 742                         return -EINVAL;
 743
 744                 if (info->read_mmr_reg.count > 128)
 745                         return -EINVAL;
 746
 747                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 748                 if (!regs)
 749                         return -ENOMEM;
 750                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 751
 752                 amdgpu_gfx_off_ctrl(adev, false);
 753                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 754                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 755                                                       info->read_mmr_reg.dword_offset + i,
 756                                                       &regs[i])) {
 757                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 758                                               info->read_mmr_reg.dword_offset + i);
 759                                 kfree(regs);
 760                                 amdgpu_gfx_off_ctrl(adev, true);
 761                                 return -EFAULT;
 762                         }
 763                 }
 764                 amdgpu_gfx_off_ctrl(adev, true);
 765                 n = copy_to_user(out, regs, min(size, alloc_size));
 766                 kfree(regs);
 767                 return n ? -EFAULT : 0;
 768         }
 769         case AMDGPU_INFO_DEV_INFO: {
 770                 struct drm_amdgpu_info_device *dev_info;
 771                 uint64_t vm_size;
 772                 uint32_t pcie_gen_mask;
 773                 int ret;
 774
 775                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 776                 if (!dev_info)
 777                         return -ENOMEM;
 778
 779                 dev_info->device_id = adev->pdev->device;
 780                 dev_info->chip_rev = adev->rev_id;
 781                 dev_info->external_rev = adev->external_rev_id;
 782                 dev_info->pci_rev = adev->pdev->revision;
 783                 dev_info->family = adev->family;
 784                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 785                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 786                 /* return all clocks in KHz */
 787                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 788                 if (adev->pm.dpm_enabled) {
 789                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 790                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 791                         dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;
 792                         dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;
 793                 } else {
 794                         dev_info->max_engine_clock =
 795                                 dev_info->min_engine_clock =
 796                                         adev->clock.default_sclk * 10;
 797                         dev_info->max_memory_clock =
 798                                 dev_info->min_memory_clock =
 799                                         adev->clock.default_mclk * 10;
 800                 }
 801                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 802                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 803                         adev->gfx.config.max_shader_engines;
 804                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 805                 dev_info->ids_flags = 0;
 806                 if (adev->flags & AMD_IS_APU)
 807                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 808                 if (amdgpu_mcbp)
 809                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 810                 if (amdgpu_is_tmz(adev))
 811                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 812                 if (adev->gfx.config.ta_cntl2_truncate_coord_mode)
 813                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;
 814
 815                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 816                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 817
 818                 /* Older VCE FW versions are buggy and can handle only 40bits */
 819                 if (adev->vce.fw_version &&
 820                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 821                         vm_size = min(vm_size, 1ULL << 40);
 822
 823                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 824                 dev_info->virtual_address_max =
 825                         min(vm_size, AMDGPU_GMC_HOLE_START);
 826
 827                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 828                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 829                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 830                 }
 831                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 832                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 833                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 834                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 835                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 836                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 837                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 838                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 839                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 840                        sizeof(adev->gfx.cu_info.bitmap));
 841                 dev_info->vram_type = adev->gmc.vram_type;
 842                 dev_info->vram_bit_width = adev->gmc.vram_width;
 843                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 844                 dev_info->gc_double_offchip_lds_buf =
 845                         adev->gfx.config.double_offchip_lds_buf;
 846                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 847                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 848                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 849                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 850                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 851                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 852                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 853
 854                 if (adev->family >= AMDGPU_FAMILY_NV)
 855                         dev_info->pa_sc_tile_steering_override =
 856                                 adev->gfx.config.pa_sc_tile_steering_override;
 857
 858                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 859
 860                 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */
 861                 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16);
 862                 dev_info->pcie_gen = fls(pcie_gen_mask);
 863                 dev_info->pcie_num_lanes =
 864                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :
 865                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
 866                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :
 867                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :
 868                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
 869                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
 870
 871                 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
 872                 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;
 873                 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
 874                 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
 875                 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *
 876                                             adev->gfx.config.gc_gl1c_per_sa;
 877                 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
 878                 dev_info->mall_size = adev->gmc.mall_size;
 879
 880
 881                 if (adev->gfx.funcs->get_gfx_shadow_info) {
 882                         struct amdgpu_gfx_shadow_info shadow_info;
 883
 884                         ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info);
 885                         if (!ret) {
 886                                 dev_info->shadow_size = shadow_info.shadow_size;
 887                                 dev_info->shadow_alignment = shadow_info.shadow_alignment;
 888                                 dev_info->csa_size = shadow_info.csa_size;
 889                                 dev_info->csa_alignment = shadow_info.csa_alignment;
 890                         }
 891                 }
 892
 893                 ret = copy_to_user(out, dev_info,
 894                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 895                 kfree(dev_info);
 896                 return ret;
 897         }
 898         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 899                 unsigned i;
 900                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 901                 struct amd_vce_state *vce_state;
 902
 903                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 904                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 905                         if (vce_state) {
 906                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 907                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 908                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 909                                 vce_clk_table.num_valid_entries++;
 910                         }
 911                 }
 912
 913                 return copy_to_user(out, &vce_clk_table,
 914                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 915         }
 916         case AMDGPU_INFO_VBIOS: {
 917                 uint32_t bios_size = adev->bios_size;
 918
 919                 switch (info->vbios_info.type) {
 920                 case AMDGPU_INFO_VBIOS_SIZE:
 921                         return copy_to_user(out, &bios_size,
 922                                         min((size_t)size, sizeof(bios_size)))
 923                                         ? -EFAULT : 0;
 924                 case AMDGPU_INFO_VBIOS_IMAGE: {
 925                         uint8_t *bios;
 926                         uint32_t bios_offset = info->vbios_info.offset;
 927
 928                         if (bios_offset >= bios_size)
 929                                 return -EINVAL;
 930
 931                         bios = adev->bios + bios_offset;
 932                         return copy_to_user(out, bios,
 933                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 934                                         ? -EFAULT : 0;
 935                 }
 936                 case AMDGPU_INFO_VBIOS_INFO: {
 937                         struct drm_amdgpu_info_vbios vbios_info = {};
 938                         struct atom_context *atom_context;
 939
 940                         atom_context = adev->mode_info.atom_context;
 941                         memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
 942                         memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
 943                         vbios_info.version = atom_context->version;
 944                         memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
 945                                                 sizeof(atom_context->vbios_ver_str));
 946                         memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
 947
 948                         return copy_to_user(out, &vbios_info,
 949                                                 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
 950                 }
 951                 default:
 952                         DRM_DEBUG_KMS("Invalid request %d\n",
 953                                         info->vbios_info.type);
 954                         return -EINVAL;
 955                 }
 956         }
 957         case AMDGPU_INFO_NUM_HANDLES: {
 958                 struct drm_amdgpu_info_num_handles handle;
 959
 960                 switch (info->query_hw_ip.type) {
 961                 case AMDGPU_HW_IP_UVD:
 962                         /* Starting Polaris, we support unlimited UVD handles */
 963                         if (adev->asic_type < CHIP_POLARIS10) {
 964                                 handle.uvd_max_handles = adev->uvd.max_handles;
 965                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 966
 967                                 return copy_to_user(out, &handle,
 968                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 969                         } else {
 970                                 return -ENODATA;
 971                         }
 972
 973                         break;
 974                 default:
 975                         return -EINVAL;
 976                 }
 977         }
 978         case AMDGPU_INFO_SENSOR: {
 979                 if (!adev->pm.dpm_enabled)
 980                         return -ENOENT;
 981
 982                 switch (info->sensor_info.type) {
 983                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 984                         /* get sclk in Mhz */
 985                         if (amdgpu_dpm_read_sensor(adev,
 986                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 987                                                    (void *)&ui32, &ui32_size)) {
 988                                 return -EINVAL;
 989                         }
 990                         ui32 /= 100;
 991                         break;
 992                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 993                         /* get mclk in Mhz */
 994                         if (amdgpu_dpm_read_sensor(adev,
 995                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 996                                                    (void *)&ui32, &ui32_size)) {
 997                                 return -EINVAL;
 998                         }
 999                         ui32 /= 100;
1000                         break;
1001                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
1002                         /* get temperature in millidegrees C */
1003                         if (amdgpu_dpm_read_sensor(adev,
1004                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
1005                                                    (void *)&ui32, &ui32_size)) {
1006                                 return -EINVAL;
1007                         }
1008                         break;
1009                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
1010                         /* get GPU load */
1011                         if (amdgpu_dpm_read_sensor(adev,
1012                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
1013                                                    (void *)&ui32, &ui32_size)) {
1014                                 return -EINVAL;
1015                         }
1016                         break;
1017                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
1018                         /* get average GPU power */
1019                         if (amdgpu_dpm_read_sensor(adev,
1020                                                    AMDGPU_PP_SENSOR_GPU_POWER,
1021                                                    (void *)&ui32, &ui32_size)) {
1022                                 return -EINVAL;
1023                         }
1024                         ui32 >>= 8;
1025                         break;
1026                 case AMDGPU_INFO_SENSOR_VDDNB:
1027                         /* get VDDNB in millivolts */
1028                         if (amdgpu_dpm_read_sensor(adev,
1029                                                    AMDGPU_PP_SENSOR_VDDNB,
1030                                                    (void *)&ui32, &ui32_size)) {
1031                                 return -EINVAL;
1032                         }
1033                         break;
1034                 case AMDGPU_INFO_SENSOR_VDDGFX:
1035                         /* get VDDGFX in millivolts */
1036                         if (amdgpu_dpm_read_sensor(adev,
1037                                                    AMDGPU_PP_SENSOR_VDDGFX,
1038                                                    (void *)&ui32, &ui32_size)) {
1039                                 return -EINVAL;
1040                         }
1041                         break;
1042                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1043                         /* get stable pstate sclk in Mhz */
1044                         if (amdgpu_dpm_read_sensor(adev,
1045                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1046                                                    (void *)&ui32, &ui32_size)) {
1047                                 return -EINVAL;
1048                         }
1049                         ui32 /= 100;
1050                         break;
1051                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1052                         /* get stable pstate mclk in Mhz */
1053                         if (amdgpu_dpm_read_sensor(adev,
1054                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1055                                                    (void *)&ui32, &ui32_size)) {
1056                                 return -EINVAL;
1057                         }
1058                         ui32 /= 100;
1059                         break;
1060                 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
1061                         /* get peak pstate sclk in Mhz */
1062                         if (amdgpu_dpm_read_sensor(adev,
1063                                                    AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
1064                                                    (void *)&ui32, &ui32_size)) {
1065                                 return -EINVAL;
1066                         }
1067                         ui32 /= 100;
1068                         break;
1069                 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
1070                         /* get peak pstate mclk in Mhz */
1071                         if (amdgpu_dpm_read_sensor(adev,
1072                                                    AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
1073                                                    (void *)&ui32, &ui32_size)) {
1074                                 return -EINVAL;
1075                         }
1076                         ui32 /= 100;
1077                         break;
1078                 default:
1079                         DRM_DEBUG_KMS("Invalid request %d\n",
1080                                       info->sensor_info.type);
1081                         return -EINVAL;
1082                 }
1083                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1084         }
1085         case AMDGPU_INFO_VRAM_LOST_COUNTER:
1086                 ui32 = atomic_read(&adev->vram_lost_counter);
1087                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1088         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1089                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1090                 uint64_t ras_mask;
1091
1092                 if (!ras)
1093                         return -EINVAL;
1094                 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1095
1096                 return copy_to_user(out, &ras_mask,
1097                                 min_t(u64, size, sizeof(ras_mask))) ?
1098                         -EFAULT : 0;
1099         }
1100         case AMDGPU_INFO_VIDEO_CAPS: {
1101                 const struct amdgpu_video_codecs *codecs;
1102                 struct drm_amdgpu_info_video_caps *caps;
1103                 int r;
1104
1105                 switch (info->video_cap.type) {
1106                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1107                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1108                         if (r)
1109                                 return -EINVAL;
1110                         break;
1111                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1112                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1113                         if (r)
1114                                 return -EINVAL;
1115                         break;
1116                 default:
1117                         DRM_DEBUG_KMS("Invalid request %d\n",
1118                                       info->video_cap.type);
1119                         return -EINVAL;
1120                 }
1121
1122                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1123                 if (!caps)
1124                         return -ENOMEM;
1125
1126                 for (i = 0; i < codecs->codec_count; i++) {
1127                         int idx = codecs->codec_array[i].codec_type;
1128
1129                         switch (idx) {
1130                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1131                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1132                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1133                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1134                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1135                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1136                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1137                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1138                                 caps->codec_info[idx].valid = 1;
1139                                 caps->codec_info[idx].max_width =
1140                                         codecs->codec_array[i].max_width;
1141                                 caps->codec_info[idx].max_height =
1142                                         codecs->codec_array[i].max_height;
1143                                 caps->codec_info[idx].max_pixels_per_frame =
1144                                         codecs->codec_array[i].max_pixels_per_frame;
1145                                 caps->codec_info[idx].max_level =
1146                                         codecs->codec_array[i].max_level;
1147                                 break;
1148                         default:
1149                                 break;
1150                         }
1151                 }
1152                 r = copy_to_user(out, caps,
1153                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1154                 kfree(caps);
1155                 return r;
1156         }
1157         case AMDGPU_INFO_MAX_IBS: {
1158                 uint32_t max_ibs[AMDGPU_HW_IP_NUM];
1159
1160                 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
1161                         max_ibs[i] = amdgpu_ring_max_ibs(i);
1162
1163                 return copy_to_user(out, max_ibs,
1164                                     min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0;
1165         }
1166         default:
1167                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1168                 return -EINVAL;
1169         }
1170         return 0;
1171 }
1172
1173
1174 /*
1175  * Outdated mess for old drm with Xorg being in charge (void function now).
1176  */
1177 /**
1178  * amdgpu_driver_lastclose_kms - drm callback for last close
1179  *
1180  * @dev: drm dev pointer
1181  *
1182  * Switch vga_switcheroo state after last close (all asics).
1183  */
1184 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1185 {
1186         drm_fb_helper_lastclose(dev);
1187         vga_switcheroo_process_delayed_switch();
1188 }
1189
1190 /**
1191  * amdgpu_driver_open_kms - drm callback for open
1192  *
1193  * @dev: drm dev pointer
1194  * @file_priv: drm file
1195  *
1196  * On device open, init vm on cayman+ (all asics).
1197  * Returns 0 on success, error on failure.
1198  */
1199 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1200 {
1201         struct amdgpu_device *adev = drm_to_adev(dev);
1202         struct amdgpu_fpriv *fpriv;
1203         int r, pasid;
1204
1205         /* Ensure IB tests are run on ring */
1206         flush_delayed_work(&adev->delayed_init_work);
1207
1208
1209         if (amdgpu_ras_intr_triggered()) {
1210                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1211                 return -EHWPOISON;
1212         }
1213
1214         file_priv->driver_priv = NULL;
1215
1216         r = pm_runtime_get_sync(dev->dev);
1217         if (r < 0)
1218                 goto pm_put;
1219
1220         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1221         if (unlikely(!fpriv)) {
1222                 r = -ENOMEM;
1223                 goto out_suspend;
1224         }
1225
1226         pasid = amdgpu_pasid_alloc(16);
1227         if (pasid < 0) {
1228                 dev_warn(adev->dev, "No more PASIDs available!");
1229                 pasid = 0;
1230         }
1231
1232         r = amdgpu_vm_init(adev, &fpriv->vm);
1233         if (r)
1234                 goto error_pasid;
1235
1236         r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1237         if (r)
1238                 goto error_vm;
1239
1240         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1241         if (!fpriv->prt_va) {
1242                 r = -ENOMEM;
1243                 goto error_vm;
1244         }
1245
1246         if (amdgpu_mcbp) {
1247                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1248
1249                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1250                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1251                 if (r)
1252                         goto error_vm;
1253         }
1254
1255         mutex_init(&fpriv->bo_list_lock);
1256         idr_init_base(&fpriv->bo_list_handles, 1);
1257
1258         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1259
1260         file_priv->driver_priv = fpriv;
1261         goto out_suspend;
1262
1263 error_vm:
1264         amdgpu_vm_fini(adev, &fpriv->vm);
1265
1266 error_pasid:
1267         if (pasid) {
1268                 amdgpu_pasid_free(pasid);
1269                 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1270         }
1271
1272         kfree(fpriv);
1273
1274 out_suspend:
1275         pm_runtime_mark_last_busy(dev->dev);
1276 pm_put:
1277         pm_runtime_put_autosuspend(dev->dev);
1278
1279         return r;
1280 }
1281
1282 /**
1283  * amdgpu_driver_postclose_kms - drm callback for post close
1284  *
1285  * @dev: drm dev pointer
1286  * @file_priv: drm file
1287  *
1288  * On device post close, tear down vm on cayman+ (all asics).
1289  */
1290 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1291                                  struct drm_file *file_priv)
1292 {
1293         struct amdgpu_device *adev = drm_to_adev(dev);
1294         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1295         struct amdgpu_bo_list *list;
1296         struct amdgpu_bo *pd;
1297         u32 pasid;
1298         int handle;
1299
1300         if (!fpriv)
1301                 return;
1302
1303         pm_runtime_get_sync(dev->dev);
1304
1305         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1306                 amdgpu_uvd_free_handles(adev, file_priv);
1307         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1308                 amdgpu_vce_free_handles(adev, file_priv);
1309
1310         if (amdgpu_mcbp) {
1311                 /* TODO: how to handle reserve failure */
1312                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1313                 amdgpu_vm_bo_del(adev, fpriv->csa_va);
1314                 fpriv->csa_va = NULL;
1315                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1316         }
1317
1318         pasid = fpriv->vm.pasid;
1319         pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1320         if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1321                 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1322                 amdgpu_bo_unreserve(pd);
1323         }
1324
1325         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1326         amdgpu_vm_fini(adev, &fpriv->vm);
1327
1328         if (pasid)
1329                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1330         amdgpu_bo_unref(&pd);
1331
1332         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1333                 amdgpu_bo_list_put(list);
1334
1335         idr_destroy(&fpriv->bo_list_handles);
1336         mutex_destroy(&fpriv->bo_list_lock);
1337
1338         kfree(fpriv);
1339         file_priv->driver_priv = NULL;
1340
1341         pm_runtime_mark_last_busy(dev->dev);
1342         pm_runtime_put_autosuspend(dev->dev);
1343 }
1344
1345
1346 void amdgpu_driver_release_kms(struct drm_device *dev)
1347 {
1348         struct amdgpu_device *adev = drm_to_adev(dev);
1349
1350         amdgpu_device_fini_sw(adev);
1351         pci_set_drvdata(adev->pdev, NULL);
1352 }
1353
1354 /*
1355  * VBlank related functions.
1356  */
1357 /**
1358  * amdgpu_get_vblank_counter_kms - get frame count
1359  *
1360  * @crtc: crtc to get the frame count from
1361  *
1362  * Gets the frame count on the requested crtc (all asics).
1363  * Returns frame count on success, -EINVAL on failure.
1364  */
1365 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1366 {
1367         struct drm_device *dev = crtc->dev;
1368         unsigned int pipe = crtc->index;
1369         struct amdgpu_device *adev = drm_to_adev(dev);
1370         int vpos, hpos, stat;
1371         u32 count;
1372
1373         if (pipe >= adev->mode_info.num_crtc) {
1374                 DRM_ERROR("Invalid crtc %u\n", pipe);
1375                 return -EINVAL;
1376         }
1377
1378         /* The hw increments its frame counter at start of vsync, not at start
1379          * of vblank, as is required by DRM core vblank counter handling.
1380          * Cook the hw count here to make it appear to the caller as if it
1381          * incremented at start of vblank. We measure distance to start of
1382          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1383          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1384          * result by 1 to give the proper appearance to caller.
1385          */
1386         if (adev->mode_info.crtcs[pipe]) {
1387                 /* Repeat readout if needed to provide stable result if
1388                  * we cross start of vsync during the queries.
1389                  */
1390                 do {
1391                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1392                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1393                          * vpos as distance to start of vblank, instead of
1394                          * regular vertical scanout pos.
1395                          */
1396                         stat = amdgpu_display_get_crtc_scanoutpos(
1397                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1398                                 &vpos, &hpos, NULL, NULL,
1399                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1400                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1401
1402                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1403                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1404                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1405                 } else {
1406                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1407                                       pipe, vpos);
1408
1409                         /* Bump counter if we are at >= leading edge of vblank,
1410                          * but before vsync where vpos would turn negative and
1411                          * the hw counter really increments.
1412                          */
1413                         if (vpos >= 0)
1414                                 count++;
1415                 }
1416         } else {
1417                 /* Fallback to use value as is. */
1418                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1419                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1420         }
1421
1422         return count;
1423 }
1424
1425 /**
1426  * amdgpu_enable_vblank_kms - enable vblank interrupt
1427  *
1428  * @crtc: crtc to enable vblank interrupt for
1429  *
1430  * Enable the interrupt on the requested crtc (all asics).
1431  * Returns 0 on success, -EINVAL on failure.
1432  */
1433 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1434 {
1435         struct drm_device *dev = crtc->dev;
1436         unsigned int pipe = crtc->index;
1437         struct amdgpu_device *adev = drm_to_adev(dev);
1438         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1439
1440         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1441 }
1442
1443 /**
1444  * amdgpu_disable_vblank_kms - disable vblank interrupt
1445  *
1446  * @crtc: crtc to disable vblank interrupt for
1447  *
1448  * Disable the interrupt on the requested crtc (all asics).
1449  */
1450 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1451 {
1452         struct drm_device *dev = crtc->dev;
1453         unsigned int pipe = crtc->index;
1454         struct amdgpu_device *adev = drm_to_adev(dev);
1455         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1456
1457         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1458 }
1459
1460 /*
1461  * Debugfs info
1462  */
1463 #if defined(CONFIG_DEBUG_FS)
1464
1465 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1466 {
1467         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1468         struct drm_amdgpu_info_firmware fw_info;
1469         struct drm_amdgpu_query_fw query_fw;
1470         struct atom_context *ctx = adev->mode_info.atom_context;
1471         uint8_t smu_program, smu_major, smu_minor, smu_debug;
1472         int ret, i;
1473
1474         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1475 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type
1476                 TA_FW_NAME(XGMI),
1477                 TA_FW_NAME(RAS),
1478                 TA_FW_NAME(HDCP),
1479                 TA_FW_NAME(DTM),
1480                 TA_FW_NAME(RAP),
1481                 TA_FW_NAME(SECUREDISPLAY),
1482 #undef TA_FW_NAME
1483         };
1484
1485         /* VCE */
1486         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1487         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1488         if (ret)
1489                 return ret;
1490         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1491                    fw_info.feature, fw_info.ver);
1492
1493         /* UVD */
1494         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1495         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1496         if (ret)
1497                 return ret;
1498         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1499                    fw_info.feature, fw_info.ver);
1500
1501         /* GMC */
1502         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1503         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1504         if (ret)
1505                 return ret;
1506         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1507                    fw_info.feature, fw_info.ver);
1508
1509         /* ME */
1510         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1511         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1512         if (ret)
1513                 return ret;
1514         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1515                    fw_info.feature, fw_info.ver);
1516
1517         /* PFP */
1518         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1519         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1520         if (ret)
1521                 return ret;
1522         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1523                    fw_info.feature, fw_info.ver);
1524
1525         /* CE */
1526         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1527         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1528         if (ret)
1529                 return ret;
1530         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1531                    fw_info.feature, fw_info.ver);
1532
1533         /* RLC */
1534         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1535         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1536         if (ret)
1537                 return ret;
1538         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1539                    fw_info.feature, fw_info.ver);
1540
1541         /* RLC SAVE RESTORE LIST CNTL */
1542         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1543         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1544         if (ret)
1545                 return ret;
1546         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1547                    fw_info.feature, fw_info.ver);
1548
1549         /* RLC SAVE RESTORE LIST GPM MEM */
1550         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1551         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1552         if (ret)
1553                 return ret;
1554         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1555                    fw_info.feature, fw_info.ver);
1556
1557         /* RLC SAVE RESTORE LIST SRM MEM */
1558         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1559         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1560         if (ret)
1561                 return ret;
1562         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1563                    fw_info.feature, fw_info.ver);
1564
1565         /* RLCP */
1566         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1567         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1568         if (ret)
1569                 return ret;
1570         seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1571                    fw_info.feature, fw_info.ver);
1572
1573         /* RLCV */
1574         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1575         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1576         if (ret)
1577                 return ret;
1578         seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1579                    fw_info.feature, fw_info.ver);
1580
1581         /* MEC */
1582         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1583         query_fw.index = 0;
1584         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1585         if (ret)
1586                 return ret;
1587         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1588                    fw_info.feature, fw_info.ver);
1589
1590         /* MEC2 */
1591         if (adev->gfx.mec2_fw) {
1592                 query_fw.index = 1;
1593                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1594                 if (ret)
1595                         return ret;
1596                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1597                            fw_info.feature, fw_info.ver);
1598         }
1599
1600         /* IMU */
1601         query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1602         query_fw.index = 0;
1603         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1604         if (ret)
1605                 return ret;
1606         seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1607                    fw_info.feature, fw_info.ver);
1608
1609         /* PSP SOS */
1610         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1611         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1612         if (ret)
1613                 return ret;
1614         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1615                    fw_info.feature, fw_info.ver);
1616
1617
1618         /* PSP ASD */
1619         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1620         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1621         if (ret)
1622                 return ret;
1623         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1624                    fw_info.feature, fw_info.ver);
1625
1626         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1627         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1628                 query_fw.index = i;
1629                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1630                 if (ret)
1631                         continue;
1632
1633                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1634                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1635         }
1636
1637         /* SMC */
1638         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1639         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1640         if (ret)
1641                 return ret;
1642         smu_program = (fw_info.ver >> 24) & 0xff;
1643         smu_major = (fw_info.ver >> 16) & 0xff;
1644         smu_minor = (fw_info.ver >> 8) & 0xff;
1645         smu_debug = (fw_info.ver >> 0) & 0xff;
1646         seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1647                    fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1648
1649         /* SDMA */
1650         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1651         for (i = 0; i < adev->sdma.num_instances; i++) {
1652                 query_fw.index = i;
1653                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1654                 if (ret)
1655                         return ret;
1656                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1657                            i, fw_info.feature, fw_info.ver);
1658         }
1659
1660         /* VCN */
1661         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1662         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1663         if (ret)
1664                 return ret;
1665         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1666                    fw_info.feature, fw_info.ver);
1667
1668         /* DMCU */
1669         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1670         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1671         if (ret)
1672                 return ret;
1673         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1674                    fw_info.feature, fw_info.ver);
1675
1676         /* DMCUB */
1677         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1678         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1679         if (ret)
1680                 return ret;
1681         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1682                    fw_info.feature, fw_info.ver);
1683
1684         /* TOC */
1685         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1686         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1687         if (ret)
1688                 return ret;
1689         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1690                    fw_info.feature, fw_info.ver);
1691
1692         /* CAP */
1693         if (adev->psp.cap_fw) {
1694                 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1695                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1696                 if (ret)
1697                         return ret;
1698                 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1699                                 fw_info.feature, fw_info.ver);
1700         }
1701
1702         /* MES_KIQ */
1703         query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1704         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1705         if (ret)
1706                 return ret;
1707         seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1708                    fw_info.feature, fw_info.ver);
1709
1710         /* MES */
1711         query_fw.fw_type = AMDGPU_INFO_FW_MES;
1712         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1713         if (ret)
1714                 return ret;
1715         seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1716                    fw_info.feature, fw_info.ver);
1717
1718         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1719
1720         return 0;
1721 }
1722
1723 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1724
1725 #endif
1726
1727 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1728 {
1729 #if defined(CONFIG_DEBUG_FS)
1730         struct drm_minor *minor = adev_to_drm(adev)->primary;
1731         struct dentry *root = minor->debugfs_root;
1732
1733         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1734                             adev, &amdgpu_debugfs_firmware_info_fops);
1735
1736 #endif
1737 }