drivers/net/dsa/qca/qca8k.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2009 Felix Fietkau <[email protected]>
   4  * Copyright (C) 2011-2012 Gabor Juhos <[email protected]>
   5  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #ifndef __QCA8K_H
   9 #define __QCA8K_H
  10
  11 #include <linux/delay.h>
  12 #include <linux/regmap.h>
  13 #include <linux/gpio.h>
  14 #include <linux/dsa/tag_qca.h>
  15
  16 #define QCA8K_ETHERNET_MDIO_PRIORITY                    7
  17 #define QCA8K_ETHERNET_PHY_PRIORITY                     6
  18 #define QCA8K_ETHERNET_TIMEOUT                          5
  19
  20 #define QCA8K_NUM_PORTS                                 7
  21 #define QCA8K_NUM_CPU_PORTS                             2
  22 #define QCA8K_MAX_MTU                                   9000
  23 #define QCA8K_NUM_LAGS                                  4
  24 #define QCA8K_NUM_PORTS_FOR_LAG                         4
  25
  26 #define PHY_ID_QCA8327                                  0x004dd034
  27 #define QCA8K_ID_QCA8327                                0x12
  28 #define PHY_ID_QCA8337                                  0x004dd036
  29 #define QCA8K_ID_QCA8337                                0x13
  30
  31 #define QCA8K_QCA832X_MIB_COUNT                         39
  32 #define QCA8K_QCA833X_MIB_COUNT                         41
  33
  34 #define QCA8K_BUSY_WAIT_TIMEOUT                         2000
  35
  36 #define QCA8K_NUM_FDB_RECORDS                           2048
  37
  38 #define QCA8K_PORT_VID_DEF                              1
  39
  40 /* Global control registers */
  41 #define QCA8K_REG_MASK_CTRL                             0x000
  42 #define   QCA8K_MASK_CTRL_REV_ID_MASK                   GENMASK(7, 0)
  43 #define   QCA8K_MASK_CTRL_REV_ID(x)                     FIELD_GET(QCA8K_MASK_CTRL_REV_ID_MASK, x)
  44 #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK                GENMASK(15, 8)
  45 #define   QCA8K_MASK_CTRL_DEVICE_ID(x)                  FIELD_GET(QCA8K_MASK_CTRL_DEVICE_ID_MASK, x)
  46 #define QCA8K_REG_PORT0_PAD_CTRL                        0x004
  47 #define   QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN             BIT(31)
  48 #define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE      BIT(19)
  49 #define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE      BIT(18)
  50 #define QCA8K_REG_PORT5_PAD_CTRL                        0x008
  51 #define QCA8K_REG_PORT6_PAD_CTRL                        0x00c
  52 #define   QCA8K_PORT_PAD_RGMII_EN                       BIT(26)
  53 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK            GENMASK(23, 22)
  54 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)              FIELD_PREP(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, x)
  55 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK            GENMASK(21, 20)
  56 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)              FIELD_PREP(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, x)
  57 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY_EN              BIT(25)
  58 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN              BIT(24)
  59 #define   QCA8K_PORT_PAD_SGMII_EN                       BIT(7)
  60 #define QCA8K_REG_PWS                                   0x010
  61 #define   QCA8K_PWS_POWER_ON_SEL                        BIT(31)
  62 /* This reg is only valid for QCA832x and toggle the package
  63  * type from 176 pin (by default) to 148 pin used on QCA8327
  64  */
  65 #define   QCA8327_PWS_PACKAGE148_EN                     BIT(30)
  66 #define   QCA8K_PWS_LED_OPEN_EN_CSR                     BIT(24)
  67 #define   QCA8K_PWS_SERDES_AEN_DIS                      BIT(7)
  68 #define QCA8K_REG_MODULE_EN                             0x030
  69 #define   QCA8K_MODULE_EN_MIB                           BIT(0)
  70 #define QCA8K_REG_MIB                                   0x034
  71 #define   QCA8K_MIB_FUNC                                GENMASK(26, 24)
  72 #define   QCA8K_MIB_CPU_KEEP                            BIT(20)
  73 #define   QCA8K_MIB_BUSY                                BIT(17)
  74 #define QCA8K_MDIO_MASTER_CTRL                          0x3c
  75 #define   QCA8K_MDIO_MASTER_BUSY                        BIT(31)
  76 #define   QCA8K_MDIO_MASTER_EN                          BIT(30)
  77 #define   QCA8K_MDIO_MASTER_READ                        BIT(27)
  78 #define   QCA8K_MDIO_MASTER_WRITE                       0
  79 #define   QCA8K_MDIO_MASTER_SUP_PRE                     BIT(26)
  80 #define   QCA8K_MDIO_MASTER_PHY_ADDR_MASK               GENMASK(25, 21)
  81 #define   QCA8K_MDIO_MASTER_PHY_ADDR(x)                 FIELD_PREP(QCA8K_MDIO_MASTER_PHY_ADDR_MASK, x)
  82 #define   QCA8K_MDIO_MASTER_REG_ADDR_MASK               GENMASK(20, 16)
  83 #define   QCA8K_MDIO_MASTER_REG_ADDR(x)                 FIELD_PREP(QCA8K_MDIO_MASTER_REG_ADDR_MASK, x)
  84 #define   QCA8K_MDIO_MASTER_DATA_MASK                   GENMASK(15, 0)
  85 #define   QCA8K_MDIO_MASTER_DATA(x)                     FIELD_PREP(QCA8K_MDIO_MASTER_DATA_MASK, x)
  86 #define   QCA8K_MDIO_MASTER_MAX_PORTS                   5
  87 #define   QCA8K_MDIO_MASTER_MAX_REG                     32
  88 #define QCA8K_GOL_MAC_ADDR0                             0x60
  89 #define QCA8K_GOL_MAC_ADDR1                             0x64
  90 #define QCA8K_MAX_FRAME_SIZE                            0x78
  91 #define QCA8K_REG_PORT_STATUS(_i)                       (0x07c + (_i) * 4)
  92 #define   QCA8K_PORT_STATUS_SPEED                       GENMASK(1, 0)
  93 #define   QCA8K_PORT_STATUS_SPEED_10                    0
  94 #define   QCA8K_PORT_STATUS_SPEED_100                   0x1
  95 #define   QCA8K_PORT_STATUS_SPEED_1000                  0x2
  96 #define   QCA8K_PORT_STATUS_TXMAC                       BIT(2)
  97 #define   QCA8K_PORT_STATUS_RXMAC                       BIT(3)
  98 #define   QCA8K_PORT_STATUS_TXFLOW                      BIT(4)
  99 #define   QCA8K_PORT_STATUS_RXFLOW                      BIT(5)
 100 #define   QCA8K_PORT_STATUS_DUPLEX                      BIT(6)
 101 #define   QCA8K_PORT_STATUS_LINK_UP                     BIT(8)
 102 #define   QCA8K_PORT_STATUS_LINK_AUTO                   BIT(9)
 103 #define   QCA8K_PORT_STATUS_LINK_PAUSE                  BIT(10)
 104 #define   QCA8K_PORT_STATUS_FLOW_AUTO                   BIT(12)
 105 #define QCA8K_REG_PORT_HDR_CTRL(_i)                     (0x9c + (_i * 4))
 106 #define   QCA8K_PORT_HDR_CTRL_RX_MASK                   GENMASK(3, 2)
 107 #define   QCA8K_PORT_HDR_CTRL_TX_MASK                   GENMASK(1, 0)
 108 #define   QCA8K_PORT_HDR_CTRL_ALL                       2
 109 #define   QCA8K_PORT_HDR_CTRL_MGMT                      1
 110 #define   QCA8K_PORT_HDR_CTRL_NONE                      0
 111 #define QCA8K_REG_SGMII_CTRL                            0x0e0
 112 #define   QCA8K_SGMII_EN_PLL                            BIT(1)
 113 #define   QCA8K_SGMII_EN_RX                             BIT(2)
 114 #define   QCA8K_SGMII_EN_TX                             BIT(3)
 115 #define   QCA8K_SGMII_EN_SD                             BIT(4)
 116 #define   QCA8K_SGMII_CLK125M_DELAY                     BIT(7)
 117 #define   QCA8K_SGMII_MODE_CTRL_MASK                    GENMASK(23, 22)
 118 #define   QCA8K_SGMII_MODE_CTRL(x)                      FIELD_PREP(QCA8K_SGMII_MODE_CTRL_MASK, x)
 119 #define   QCA8K_SGMII_MODE_CTRL_BASEX                   QCA8K_SGMII_MODE_CTRL(0x0)
 120 #define   QCA8K_SGMII_MODE_CTRL_PHY                     QCA8K_SGMII_MODE_CTRL(0x1)
 121 #define   QCA8K_SGMII_MODE_CTRL_MAC                     QCA8K_SGMII_MODE_CTRL(0x2)
 122
 123 /* MAC_PWR_SEL registers */
 124 #define QCA8K_REG_MAC_PWR_SEL                           0x0e4
 125 #define   QCA8K_MAC_PWR_RGMII1_1_8V                     BIT(18)
 126 #define   QCA8K_MAC_PWR_RGMII0_1_8V                     BIT(19)
 127
 128 /* EEE control registers */
 129 #define QCA8K_REG_EEE_CTRL                              0x100
 130 #define  QCA8K_REG_EEE_CTRL_LPI_EN(_i)                  ((_i + 1) * 2)
 131
 132 /* TRUNK_HASH_EN registers */
 133 #define QCA8K_TRUNK_HASH_EN_CTRL                        0x270
 134 #define   QCA8K_TRUNK_HASH_SIP_EN                       BIT(3)
 135 #define   QCA8K_TRUNK_HASH_DIP_EN                       BIT(2)
 136 #define   QCA8K_TRUNK_HASH_SA_EN                        BIT(1)
 137 #define   QCA8K_TRUNK_HASH_DA_EN                        BIT(0)
 138 #define   QCA8K_TRUNK_HASH_MASK                         GENMASK(3, 0)
 139
 140 /* ACL registers */
 141 #define QCA8K_REG_PORT_VLAN_CTRL0(_i)                   (0x420 + (_i * 8))
 142 #define   QCA8K_PORT_VLAN_CVID_MASK                     GENMASK(27, 16)
 143 #define   QCA8K_PORT_VLAN_CVID(x)                       FIELD_PREP(QCA8K_PORT_VLAN_CVID_MASK, x)
 144 #define   QCA8K_PORT_VLAN_SVID_MASK                     GENMASK(11, 0)
 145 #define   QCA8K_PORT_VLAN_SVID(x)                       FIELD_PREP(QCA8K_PORT_VLAN_SVID_MASK, x)
 146 #define QCA8K_REG_PORT_VLAN_CTRL1(_i)                   (0x424 + (_i * 8))
 147 #define QCA8K_REG_IPV4_PRI_BASE_ADDR                    0x470
 148 #define QCA8K_REG_IPV4_PRI_ADDR_MASK                    0x474
 149
 150 /* Lookup registers */
 151 #define QCA8K_ATU_TABLE_SIZE                            3 /* 12 bytes wide table / sizeof(u32) */
 152
 153 #define QCA8K_REG_ATU_DATA0                             0x600
 154 #define   QCA8K_ATU_ADDR2_MASK                          GENMASK(31, 24)
 155 #define   QCA8K_ATU_ADDR3_MASK                          GENMASK(23, 16)
 156 #define   QCA8K_ATU_ADDR4_MASK                          GENMASK(15, 8)
 157 #define   QCA8K_ATU_ADDR5_MASK                          GENMASK(7, 0)
 158 #define QCA8K_REG_ATU_DATA1                             0x604
 159 #define   QCA8K_ATU_PORT_MASK                           GENMASK(22, 16)
 160 #define   QCA8K_ATU_ADDR0_MASK                          GENMASK(15, 8)
 161 #define   QCA8K_ATU_ADDR1_MASK                          GENMASK(7, 0)
 162 #define QCA8K_REG_ATU_DATA2                             0x608
 163 #define   QCA8K_ATU_VID_MASK                            GENMASK(19, 8)
 164 #define   QCA8K_ATU_STATUS_MASK                         GENMASK(3, 0)
 165 #define   QCA8K_ATU_STATUS_STATIC                       0xf
 166 #define QCA8K_REG_ATU_FUNC                              0x60c
 167 #define   QCA8K_ATU_FUNC_BUSY                           BIT(31)
 168 #define   QCA8K_ATU_FUNC_PORT_EN                        BIT(14)
 169 #define   QCA8K_ATU_FUNC_MULTI_EN                       BIT(13)
 170 #define   QCA8K_ATU_FUNC_FULL                           BIT(12)
 171 #define   QCA8K_ATU_FUNC_PORT_MASK                      GENMASK(11, 8)
 172 #define QCA8K_REG_VTU_FUNC0                             0x610
 173 #define   QCA8K_VTU_FUNC0_VALID                         BIT(20)
 174 #define   QCA8K_VTU_FUNC0_IVL_EN                        BIT(19)
 175 /*        QCA8K_VTU_FUNC0_EG_MODE_MASK                  GENMASK(17, 4)
 176  *          It does contain VLAN_MODE for each port [5:4] for port0,
 177  *          [7:6] for port1 ... [17:16] for port6. Use virtual port
 178  *          define to handle this.
 179  */
 180 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i)        (4 + (_i) * 2)
 181 #define   QCA8K_VTU_FUNC0_EG_MODE_MASK                  GENMASK(1, 0)
 182 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i)         (GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 183 #define   QCA8K_VTU_FUNC0_EG_MODE_UNMOD                 FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x0)
 184 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i)        (QCA8K_VTU_FUNC0_EG_MODE_UNMOD << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 185 #define   QCA8K_VTU_FUNC0_EG_MODE_UNTAG                 FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x1)
 186 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i)        (QCA8K_VTU_FUNC0_EG_MODE_UNTAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 187 #define   QCA8K_VTU_FUNC0_EG_MODE_TAG                   FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x2)
 188 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i)          (QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 189 #define   QCA8K_VTU_FUNC0_EG_MODE_NOT                   FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x3)
 190 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i)          (QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 191 #define QCA8K_REG_VTU_FUNC1                             0x614
 192 #define   QCA8K_VTU_FUNC1_BUSY                          BIT(31)
 193 #define   QCA8K_VTU_FUNC1_VID_MASK                      GENMASK(27, 16)
 194 #define   QCA8K_VTU_FUNC1_FULL                          BIT(4)
 195 #define QCA8K_REG_ATU_CTRL                              0x618
 196 #define   QCA8K_ATU_AGE_TIME_MASK                       GENMASK(15, 0)
 197 #define   QCA8K_ATU_AGE_TIME(x)                         FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))
 198 #define QCA8K_REG_GLOBAL_FW_CTRL0                       0x620
 199 #define   QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN             BIT(10)
 200 #define   QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM         GENMASK(7, 4)
 201 #define QCA8K_REG_GLOBAL_FW_CTRL1                       0x624
 202 #define   QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK            GENMASK(30, 24)
 203 #define   QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK              GENMASK(22, 16)
 204 #define   QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK              GENMASK(14, 8)
 205 #define   QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK              GENMASK(6, 0)
 206 #define QCA8K_PORT_LOOKUP_CTRL(_i)                      (0x660 + (_i) * 0xc)
 207 #define   QCA8K_PORT_LOOKUP_MEMBER                      GENMASK(6, 0)
 208 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_MASK              GENMASK(9, 8)
 209 #define   QCA8K_PORT_LOOKUP_VLAN_MODE(x)                FIELD_PREP(QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, x)
 210 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_NONE              QCA8K_PORT_LOOKUP_VLAN_MODE(0x0)
 211 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK          QCA8K_PORT_LOOKUP_VLAN_MODE(0x1)
 212 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK             QCA8K_PORT_LOOKUP_VLAN_MODE(0x2)
 213 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE            QCA8K_PORT_LOOKUP_VLAN_MODE(0x3)
 214 #define   QCA8K_PORT_LOOKUP_STATE_MASK                  GENMASK(18, 16)
 215 #define   QCA8K_PORT_LOOKUP_STATE(x)                    FIELD_PREP(QCA8K_PORT_LOOKUP_STATE_MASK, x)
 216 #define   QCA8K_PORT_LOOKUP_STATE_DISABLED              QCA8K_PORT_LOOKUP_STATE(0x0)
 217 #define   QCA8K_PORT_LOOKUP_STATE_BLOCKING              QCA8K_PORT_LOOKUP_STATE(0x1)
 218 #define   QCA8K_PORT_LOOKUP_STATE_LISTENING             QCA8K_PORT_LOOKUP_STATE(0x2)
 219 #define   QCA8K_PORT_LOOKUP_STATE_LEARNING              QCA8K_PORT_LOOKUP_STATE(0x3)
 220 #define   QCA8K_PORT_LOOKUP_STATE_FORWARD               QCA8K_PORT_LOOKUP_STATE(0x4)
 221 #define   QCA8K_PORT_LOOKUP_LEARN                       BIT(20)
 222 #define   QCA8K_PORT_LOOKUP_ING_MIRROR_EN               BIT(25)
 223
 224 #define QCA8K_REG_GOL_TRUNK_CTRL0                       0x700
 225 /* 4 max trunk first
 226  * first 6 bit for member bitmap
 227  * 7th bit is to enable trunk port
 228  */
 229 #define QCA8K_REG_GOL_TRUNK_SHIFT(_i)                   ((_i) * 8)
 230 #define QCA8K_REG_GOL_TRUNK_EN_MASK                     BIT(7)
 231 #define QCA8K_REG_GOL_TRUNK_EN(_i)                      (QCA8K_REG_GOL_TRUNK_EN_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
 232 #define QCA8K_REG_GOL_TRUNK_MEMBER_MASK                 GENMASK(6, 0)
 233 #define QCA8K_REG_GOL_TRUNK_MEMBER(_i)                  (QCA8K_REG_GOL_TRUNK_MEMBER_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
 234 /* 0x704 for TRUNK 0-1 --- 0x708 for TRUNK 2-3 */
 235 #define QCA8K_REG_GOL_TRUNK_CTRL(_i)                    (0x704 + (((_i) / 2) * 4))
 236 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK              GENMASK(3, 0)
 237 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK           BIT(3)
 238 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK         GENMASK(2, 0)
 239 #define QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i)                (((_i) / 2) * 16)
 240 #define QCA8K_REG_GOL_MEM_ID_SHIFT(_i)                  ((_i) * 4)
 241 /* Complex shift: FIRST shift for port THEN shift for trunk */
 242 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j)     (QCA8K_REG_GOL_MEM_ID_SHIFT(_j) + QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i))
 243 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(_i, _j)        (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
 244 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(_i, _j)      (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
 245
 246 #define QCA8K_REG_GLOBAL_FC_THRESH                      0x800
 247 #define   QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK            GENMASK(24, 16)
 248 #define   QCA8K_GLOBAL_FC_GOL_XON_THRES(x)              FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)
 249 #define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK           GENMASK(8, 0)
 250 #define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x)             FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, x)
 251
 252 #define QCA8K_REG_PORT_HOL_CTRL0(_i)                    (0x970 + (_i) * 0x8)
 253 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK         GENMASK(3, 0)
 254 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI0(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK, x)
 255 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK         GENMASK(7, 4)
 256 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI1(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK, x)
 257 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK         GENMASK(11, 8)
 258 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI2(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK, x)
 259 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK         GENMASK(15, 12)
 260 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI3(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK, x)
 261 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK         GENMASK(19, 16)
 262 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI4(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK, x)
 263 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK         GENMASK(23, 20)
 264 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI5(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK, x)
 265 #define   QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK         GENMASK(29, 24)
 266 #define   QCA8K_PORT_HOL_CTRL0_EG_PORT(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK, x)
 267
 268 #define QCA8K_REG_PORT_HOL_CTRL1(_i)                    (0x974 + (_i) * 0x8)
 269 #define   QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK             GENMASK(3, 0)
 270 #define   QCA8K_PORT_HOL_CTRL1_ING(x)                   FIELD_PREP(QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK, x)
 271 #define   QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN            BIT(6)
 272 #define   QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN           BIT(7)
 273 #define   QCA8K_PORT_HOL_CTRL1_WRED_EN                  BIT(8)
 274 #define   QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN             BIT(16)
 275
 276 /* Pkt edit registers */
 277 #define QCA8K_EGREES_VLAN_PORT_SHIFT(_i)                (16 * ((_i) % 2))
 278 #define QCA8K_EGREES_VLAN_PORT_MASK(_i)                 (GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
 279 #define QCA8K_EGREES_VLAN_PORT(_i, x)                   ((x) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
 280 #define QCA8K_EGRESS_VLAN(x)                            (0x0c70 + (4 * (x / 2)))
 281
 282 /* L3 registers */
 283 #define QCA8K_HROUTER_CONTROL                           0xe00
 284 #define   QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M          GENMASK(17, 16)
 285 #define   QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S          16
 286 #define   QCA8K_HROUTER_CONTROL_ARP_AGE_MODE            1
 287 #define QCA8K_HROUTER_PBASED_CONTROL1                   0xe08
 288 #define QCA8K_HROUTER_PBASED_CONTROL2                   0xe0c
 289 #define QCA8K_HNAT_CONTROL                              0xe38
 290
 291 /* MIB registers */
 292 #define QCA8K_PORT_MIB_COUNTER(_i)                      (0x1000 + (_i) * 0x100)
 293
 294 /* QCA specific MII registers */
 295 #define MII_ATH_MMD_ADDR                                0x0d
 296 #define MII_ATH_MMD_DATA                                0x0e
 297
 298 enum {
 299         QCA8K_PORT_SPEED_10M = 0,
 300         QCA8K_PORT_SPEED_100M = 1,
 301         QCA8K_PORT_SPEED_1000M = 2,
 302         QCA8K_PORT_SPEED_ERR = 3,
 303 };
 304
 305 enum qca8k_fdb_cmd {
 306         QCA8K_FDB_FLUSH = 1,
 307         QCA8K_FDB_LOAD = 2,
 308         QCA8K_FDB_PURGE = 3,
 309         QCA8K_FDB_FLUSH_PORT = 5,
 310         QCA8K_FDB_NEXT = 6,
 311         QCA8K_FDB_SEARCH = 7,
 312 };
 313
 314 enum qca8k_vlan_cmd {
 315         QCA8K_VLAN_FLUSH = 1,
 316         QCA8K_VLAN_LOAD = 2,
 317         QCA8K_VLAN_PURGE = 3,
 318         QCA8K_VLAN_REMOVE_PORT = 4,
 319         QCA8K_VLAN_NEXT = 5,
 320         QCA8K_VLAN_READ = 6,
 321 };
 322
 323 enum qca8k_mid_cmd {
 324         QCA8K_MIB_FLUSH = 1,
 325         QCA8K_MIB_FLUSH_PORT = 2,
 326         QCA8K_MIB_CAST = 3,
 327 };
 328
 329 struct qca8k_priv;
 330
 331 struct qca8k_info_ops {
 332         int (*autocast_mib)(struct dsa_switch *ds, int port, u64 *data);
 333 };
 334
 335 struct qca8k_match_data {
 336         u8 id;
 337         bool reduced_package;
 338         u8 mib_count;
 339         const struct qca8k_info_ops *ops;
 340 };
 341
 342 enum {
 343         QCA8K_CPU_PORT0,
 344         QCA8K_CPU_PORT6,
 345 };
 346
 347 struct qca8k_mgmt_eth_data {
 348         struct completion rw_done;
 349         struct mutex mutex; /* Enforce one mdio read/write at time */
 350         bool ack;
 351         u32 seq;
 352         u32 data[4];
 353 };
 354
 355 struct qca8k_mib_eth_data {
 356         struct completion rw_done;
 357         struct mutex mutex; /* Process one command at time */
 358         refcount_t port_parsed; /* Counter to track parsed port */
 359         u8 req_port;
 360         u64 *data; /* pointer to ethtool data */
 361 };
 362
 363 struct qca8k_ports_config {
 364         bool sgmii_rx_clk_falling_edge;
 365         bool sgmii_tx_clk_falling_edge;
 366         bool sgmii_enable_pll;
 367         u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
 368         u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
 369 };
 370
 371 struct qca8k_mdio_cache {
 372 /* The 32bit switch registers are accessed indirectly. To achieve this we need
 373  * to set the page of the register. Track the last page that was set to reduce
 374  * mdio writes
 375  */
 376         u16 page;
 377 };
 378
 379 struct qca8k_pcs {
 380         struct phylink_pcs pcs;
 381         struct qca8k_priv *priv;
 382         int port;
 383 };
 384
 385 struct qca8k_priv {
 386         u8 switch_id;
 387         u8 switch_revision;
 388         u8 mirror_rx;
 389         u8 mirror_tx;
 390         u8 lag_hash_mode;
 391         /* Each bit correspond to a port. This switch can support a max of 7 port.
 392          * Bit 1: port enabled. Bit 0: port disabled.
 393          */
 394         u8 port_enabled_map;
 395         struct qca8k_ports_config ports_config;
 396         struct regmap *regmap;
 397         struct mii_bus *bus;
 398         struct dsa_switch *ds;
 399         struct mutex reg_mutex;
 400         struct device *dev;
 401         struct gpio_desc *reset_gpio;
 402         struct net_device *mgmt_master; /* Track if mdio/mib Ethernet is available */
 403         struct qca8k_mgmt_eth_data mgmt_eth_data;
 404         struct qca8k_mib_eth_data mib_eth_data;
 405         struct qca8k_mdio_cache mdio_cache;
 406         struct qca8k_pcs pcs_port_0;
 407         struct qca8k_pcs pcs_port_6;
 408         const struct qca8k_match_data *info;
 409 };
 410
 411 struct qca8k_mib_desc {
 412         unsigned int size;
 413         unsigned int offset;
 414         const char *name;
 415 };
 416
 417 struct qca8k_fdb {
 418         u16 vid;
 419         u8 port_mask;
 420         u8 aging;
 421         u8 mac[6];
 422 };
 423
 424 /* Common setup function */
 425 extern const struct qca8k_mib_desc ar8327_mib[];
 426 extern const struct regmap_access_table qca8k_readable_table;
 427 int qca8k_mib_init(struct qca8k_priv *priv);
 428 void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable);
 429 int qca8k_read_switch_id(struct qca8k_priv *priv);
 430
 431 /* Common read/write/rmw function */
 432 int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val);
 433 int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val);
 434 int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val);
 435
 436 /* Common ops function */
 437 void qca8k_fdb_flush(struct qca8k_priv *priv);
 438
 439 /* Common ethtool stats function */
 440 void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data);
 441 void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
 442                              uint64_t *data);
 443 int qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset);
 444
 445 /* Common eee function */
 446 int qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee);
 447 int qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e);
 448
 449 /* Common bridge function */
 450 void qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
 451 int qca8k_port_bridge_join(struct dsa_switch *ds, int port,
 452                            struct dsa_bridge bridge,
 453                            bool *tx_fwd_offload,
 454                            struct netlink_ext_ack *extack);
 455 void qca8k_port_bridge_leave(struct dsa_switch *ds, int port,
 456                              struct dsa_bridge bridge);
 457
 458 /* Common port enable/disable function */
 459 int qca8k_port_enable(struct dsa_switch *ds, int port,
 460                       struct phy_device *phy);
 461 void qca8k_port_disable(struct dsa_switch *ds, int port);
 462
 463 /* Common MTU function */
 464 int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu);
 465 int qca8k_port_max_mtu(struct dsa_switch *ds, int port);
 466
 467 /* Common fast age function */
 468 void qca8k_port_fast_age(struct dsa_switch *ds, int port);
 469 int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs);
 470
 471 /* Common FDB function */
 472 int qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
 473                           u16 port_mask, u16 vid);
 474 int qca8k_port_fdb_add(struct dsa_switch *ds, int port,
 475                        const unsigned char *addr, u16 vid,
 476                        struct dsa_db db);
 477 int qca8k_port_fdb_del(struct dsa_switch *ds, int port,
 478                        const unsigned char *addr, u16 vid,
 479                        struct dsa_db db);
 480 int qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
 481                         dsa_fdb_dump_cb_t *cb, void *data);
 482
 483 /* Common MDB function */
 484 int qca8k_port_mdb_add(struct dsa_switch *ds, int port,
 485                        const struct switchdev_obj_port_mdb *mdb,
 486                        struct dsa_db db);
 487 int qca8k_port_mdb_del(struct dsa_switch *ds, int port,
 488                        const struct switchdev_obj_port_mdb *mdb,
 489                        struct dsa_db db);
 490
 491 /* Common port mirror function */
 492 int qca8k_port_mirror_add(struct dsa_switch *ds, int port,
 493                           struct dsa_mall_mirror_tc_entry *mirror,
 494                           bool ingress, struct netlink_ext_ack *extack);
 495 void qca8k_port_mirror_del(struct dsa_switch *ds, int port,
 496                            struct dsa_mall_mirror_tc_entry *mirror);
 497
 498 /* Common port VLAN function */
 499 int qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
 500                               struct netlink_ext_ack *extack);
 501 int qca8k_port_vlan_add(struct dsa_switch *ds, int port,
 502                         const struct switchdev_obj_port_vlan *vlan,
 503                         struct netlink_ext_ack *extack);
 504 int qca8k_port_vlan_del(struct dsa_switch *ds, int port,
 505                         const struct switchdev_obj_port_vlan *vlan);
 506
 507 /* Common port LAG function */
 508 int qca8k_port_lag_join(struct dsa_switch *ds, int port, struct dsa_lag lag,
 509                         struct netdev_lag_upper_info *info,
 510                         struct netlink_ext_ack *extack);
 511 int qca8k_port_lag_leave(struct dsa_switch *ds, int port,
 512                          struct dsa_lag lag);
 513
 514 #endif /* __QCA8K_H */