drivers/net/dsa/qca/qca8k.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2009 Felix Fietkau <[email protected]>
   4  * Copyright (C) 2011-2012 Gabor Juhos <[email protected]>
   5  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #ifndef __QCA8K_H
   9 #define __QCA8K_H
  10
  11 #include <linux/delay.h>
  12 #include <linux/regmap.h>
  13 #include <linux/gpio.h>
  14 #include <linux/leds.h>
  15 #include <linux/dsa/tag_qca.h>
  16
  17 #define QCA8K_ETHERNET_MDIO_PRIORITY                    7
  18 #define QCA8K_ETHERNET_PHY_PRIORITY                     6
  19 #define QCA8K_ETHERNET_TIMEOUT                          msecs_to_jiffies(5)
  20
  21 #define QCA8K_NUM_PORTS                                 7
  22 #define QCA8K_NUM_CPU_PORTS                             2
  23 #define QCA8K_MAX_MTU                                   9000
  24 #define QCA8K_NUM_LAGS                                  4
  25 #define QCA8K_NUM_PORTS_FOR_LAG                         4
  26
  27 #define PHY_ID_QCA8327                                  0x004dd034
  28 #define QCA8K_ID_QCA8327                                0x12
  29 #define PHY_ID_QCA8337                                  0x004dd036
  30 #define QCA8K_ID_QCA8337                                0x13
  31
  32 #define QCA8K_QCA832X_MIB_COUNT                         39
  33 #define QCA8K_QCA833X_MIB_COUNT                         41
  34
  35 #define QCA8K_BUSY_WAIT_TIMEOUT                         2000
  36
  37 #define QCA8K_NUM_FDB_RECORDS                           2048
  38
  39 #define QCA8K_PORT_VID_DEF                              1
  40
  41 /* Global control registers */
  42 #define QCA8K_REG_MASK_CTRL                             0x000
  43 #define   QCA8K_MASK_CTRL_REV_ID_MASK                   GENMASK(7, 0)
  44 #define   QCA8K_MASK_CTRL_REV_ID(x)                     FIELD_GET(QCA8K_MASK_CTRL_REV_ID_MASK, x)
  45 #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK                GENMASK(15, 8)
  46 #define   QCA8K_MASK_CTRL_DEVICE_ID(x)                  FIELD_GET(QCA8K_MASK_CTRL_DEVICE_ID_MASK, x)
  47 #define QCA8K_REG_PORT0_PAD_CTRL                        0x004
  48 #define   QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN             BIT(31)
  49 #define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE      BIT(19)
  50 #define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE      BIT(18)
  51 #define QCA8K_REG_PORT5_PAD_CTRL                        0x008
  52 #define QCA8K_REG_PORT6_PAD_CTRL                        0x00c
  53 #define   QCA8K_PORT_PAD_RGMII_EN                       BIT(26)
  54 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK            GENMASK(23, 22)
  55 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)              FIELD_PREP(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, x)
  56 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK            GENMASK(21, 20)
  57 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)              FIELD_PREP(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, x)
  58 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY_EN              BIT(25)
  59 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN              BIT(24)
  60 #define   QCA8K_PORT_PAD_SGMII_EN                       BIT(7)
  61 #define QCA8K_REG_PWS                                   0x010
  62 #define   QCA8K_PWS_POWER_ON_SEL                        BIT(31)
  63 /* This reg is only valid for QCA832x and toggle the package
  64  * type from 176 pin (by default) to 148 pin used on QCA8327
  65  */
  66 #define   QCA8327_PWS_PACKAGE148_EN                     BIT(30)
  67 #define   QCA8K_PWS_LED_OPEN_EN_CSR                     BIT(24)
  68 #define   QCA8K_PWS_SERDES_AEN_DIS                      BIT(7)
  69 #define QCA8K_REG_MODULE_EN                             0x030
  70 #define   QCA8K_MODULE_EN_MIB                           BIT(0)
  71 #define QCA8K_REG_MIB                                   0x034
  72 #define   QCA8K_MIB_FUNC                                GENMASK(26, 24)
  73 #define   QCA8K_MIB_CPU_KEEP                            BIT(20)
  74 #define   QCA8K_MIB_BUSY                                BIT(17)
  75 #define QCA8K_MDIO_MASTER_CTRL                          0x3c
  76 #define   QCA8K_MDIO_MASTER_BUSY                        BIT(31)
  77 #define   QCA8K_MDIO_MASTER_EN                          BIT(30)
  78 #define   QCA8K_MDIO_MASTER_READ                        BIT(27)
  79 #define   QCA8K_MDIO_MASTER_WRITE                       0
  80 #define   QCA8K_MDIO_MASTER_SUP_PRE                     BIT(26)
  81 #define   QCA8K_MDIO_MASTER_PHY_ADDR_MASK               GENMASK(25, 21)
  82 #define   QCA8K_MDIO_MASTER_PHY_ADDR(x)                 FIELD_PREP(QCA8K_MDIO_MASTER_PHY_ADDR_MASK, x)
  83 #define   QCA8K_MDIO_MASTER_REG_ADDR_MASK               GENMASK(20, 16)
  84 #define   QCA8K_MDIO_MASTER_REG_ADDR(x)                 FIELD_PREP(QCA8K_MDIO_MASTER_REG_ADDR_MASK, x)
  85 #define   QCA8K_MDIO_MASTER_DATA_MASK                   GENMASK(15, 0)
  86 #define   QCA8K_MDIO_MASTER_DATA(x)                     FIELD_PREP(QCA8K_MDIO_MASTER_DATA_MASK, x)
  87 #define   QCA8K_MDIO_MASTER_MAX_PORTS                   5
  88 #define   QCA8K_MDIO_MASTER_MAX_REG                     32
  89
  90 /* LED control register */
  91 #define QCA8K_LED_PORT_COUNT                            3
  92 #define QCA8K_LED_COUNT                                 ((QCA8K_NUM_PORTS - QCA8K_NUM_CPU_PORTS) * QCA8K_LED_PORT_COUNT)
  93 #define QCA8K_LED_RULE_COUNT                            6
  94 #define QCA8K_LED_RULE_MAX                              11
  95 #define QCA8K_LED_PORT_INDEX(_phy, _led)                (((_phy) * QCA8K_LED_PORT_COUNT) + (_led))
  96
  97 #define QCA8K_LED_PHY123_PATTERN_EN_SHIFT(_phy, _led)   ((((_phy) - 1) * 6) + 8 + (2 * (_led)))
  98 #define QCA8K_LED_PHY123_PATTERN_EN_MASK                GENMASK(1, 0)
  99
 100 #define QCA8K_LED_PHY0123_CONTROL_RULE_SHIFT            0
 101 #define QCA8K_LED_PHY4_CONTROL_RULE_SHIFT               16
 102
 103 #define QCA8K_LED_CTRL_REG(_i)                          (0x050 + (_i) * 4)
 104 #define QCA8K_LED_CTRL0_REG                             0x50
 105 #define QCA8K_LED_CTRL1_REG                             0x54
 106 #define QCA8K_LED_CTRL2_REG                             0x58
 107 #define QCA8K_LED_CTRL3_REG                             0x5C
 108 #define   QCA8K_LED_CTRL_SHIFT(_i)                      (((_i) % 2) * 16)
 109 #define   QCA8K_LED_CTRL_MASK                           GENMASK(15, 0)
 110 #define QCA8K_LED_RULE_MASK                             GENMASK(13, 0)
 111 #define QCA8K_LED_BLINK_FREQ_MASK                       GENMASK(1, 0)
 112 #define QCA8K_LED_BLINK_FREQ_SHITF                      0
 113 #define   QCA8K_LED_BLINK_2HZ                           0
 114 #define   QCA8K_LED_BLINK_4HZ                           1
 115 #define   QCA8K_LED_BLINK_8HZ                           2
 116 #define   QCA8K_LED_BLINK_AUTO                          3
 117 #define QCA8K_LED_LINKUP_OVER_MASK                      BIT(2)
 118 #define QCA8K_LED_TX_BLINK_MASK                         BIT(4)
 119 #define QCA8K_LED_RX_BLINK_MASK                         BIT(5)
 120 #define QCA8K_LED_COL_BLINK_MASK                        BIT(7)
 121 #define QCA8K_LED_LINK_10M_EN_MASK                      BIT(8)
 122 #define QCA8K_LED_LINK_100M_EN_MASK                     BIT(9)
 123 #define QCA8K_LED_LINK_1000M_EN_MASK                    BIT(10)
 124 #define QCA8K_LED_POWER_ON_LIGHT_MASK                   BIT(11)
 125 #define QCA8K_LED_HALF_DUPLEX_MASK                      BIT(12)
 126 #define QCA8K_LED_FULL_DUPLEX_MASK                      BIT(13)
 127 #define QCA8K_LED_PATTERN_EN_MASK                       GENMASK(15, 14)
 128 #define QCA8K_LED_PATTERN_EN_SHIFT                      14
 129 #define   QCA8K_LED_ALWAYS_OFF                          0
 130 #define   QCA8K_LED_ALWAYS_BLINK_4HZ                    1
 131 #define   QCA8K_LED_ALWAYS_ON                           2
 132 #define   QCA8K_LED_RULE_CONTROLLED                     3
 133
 134 #define QCA8K_GOL_MAC_ADDR0                             0x60
 135 #define QCA8K_GOL_MAC_ADDR1                             0x64
 136 #define QCA8K_MAX_FRAME_SIZE                            0x78
 137 #define QCA8K_REG_PORT_STATUS(_i)                       (0x07c + (_i) * 4)
 138 #define   QCA8K_PORT_STATUS_SPEED                       GENMASK(1, 0)
 139 #define   QCA8K_PORT_STATUS_SPEED_10                    0
 140 #define   QCA8K_PORT_STATUS_SPEED_100                   0x1
 141 #define   QCA8K_PORT_STATUS_SPEED_1000                  0x2
 142 #define   QCA8K_PORT_STATUS_TXMAC                       BIT(2)
 143 #define   QCA8K_PORT_STATUS_RXMAC                       BIT(3)
 144 #define   QCA8K_PORT_STATUS_TXFLOW                      BIT(4)
 145 #define   QCA8K_PORT_STATUS_RXFLOW                      BIT(5)
 146 #define   QCA8K_PORT_STATUS_DUPLEX                      BIT(6)
 147 #define   QCA8K_PORT_STATUS_LINK_UP                     BIT(8)
 148 #define   QCA8K_PORT_STATUS_LINK_AUTO                   BIT(9)
 149 #define   QCA8K_PORT_STATUS_LINK_PAUSE                  BIT(10)
 150 #define   QCA8K_PORT_STATUS_FLOW_AUTO                   BIT(12)
 151 #define QCA8K_REG_PORT_HDR_CTRL(_i)                     (0x9c + (_i * 4))
 152 #define   QCA8K_PORT_HDR_CTRL_RX_MASK                   GENMASK(3, 2)
 153 #define   QCA8K_PORT_HDR_CTRL_TX_MASK                   GENMASK(1, 0)
 154 #define   QCA8K_PORT_HDR_CTRL_ALL                       2
 155 #define   QCA8K_PORT_HDR_CTRL_MGMT                      1
 156 #define   QCA8K_PORT_HDR_CTRL_NONE                      0
 157 #define QCA8K_REG_SGMII_CTRL                            0x0e0
 158 #define   QCA8K_SGMII_EN_PLL                            BIT(1)
 159 #define   QCA8K_SGMII_EN_RX                             BIT(2)
 160 #define   QCA8K_SGMII_EN_TX                             BIT(3)
 161 #define   QCA8K_SGMII_EN_SD                             BIT(4)
 162 #define   QCA8K_SGMII_CLK125M_DELAY                     BIT(7)
 163 #define   QCA8K_SGMII_MODE_CTRL_MASK                    GENMASK(23, 22)
 164 #define   QCA8K_SGMII_MODE_CTRL(x)                      FIELD_PREP(QCA8K_SGMII_MODE_CTRL_MASK, x)
 165 #define   QCA8K_SGMII_MODE_CTRL_BASEX                   QCA8K_SGMII_MODE_CTRL(0x0)
 166 #define   QCA8K_SGMII_MODE_CTRL_PHY                     QCA8K_SGMII_MODE_CTRL(0x1)
 167 #define   QCA8K_SGMII_MODE_CTRL_MAC                     QCA8K_SGMII_MODE_CTRL(0x2)
 168
 169 /* MAC_PWR_SEL registers */
 170 #define QCA8K_REG_MAC_PWR_SEL                           0x0e4
 171 #define   QCA8K_MAC_PWR_RGMII1_1_8V                     BIT(18)
 172 #define   QCA8K_MAC_PWR_RGMII0_1_8V                     BIT(19)
 173
 174 /* EEE control registers */
 175 #define QCA8K_REG_EEE_CTRL                              0x100
 176 #define  QCA8K_REG_EEE_CTRL_LPI_EN(_i)                  ((_i + 1) * 2)
 177
 178 /* TRUNK_HASH_EN registers */
 179 #define QCA8K_TRUNK_HASH_EN_CTRL                        0x270
 180 #define   QCA8K_TRUNK_HASH_SIP_EN                       BIT(3)
 181 #define   QCA8K_TRUNK_HASH_DIP_EN                       BIT(2)
 182 #define   QCA8K_TRUNK_HASH_SA_EN                        BIT(1)
 183 #define   QCA8K_TRUNK_HASH_DA_EN                        BIT(0)
 184 #define   QCA8K_TRUNK_HASH_MASK                         GENMASK(3, 0)
 185
 186 /* ACL registers */
 187 #define QCA8K_REG_PORT_VLAN_CTRL0(_i)                   (0x420 + (_i * 8))
 188 #define   QCA8K_PORT_VLAN_CVID_MASK                     GENMASK(27, 16)
 189 #define   QCA8K_PORT_VLAN_CVID(x)                       FIELD_PREP(QCA8K_PORT_VLAN_CVID_MASK, x)
 190 #define   QCA8K_PORT_VLAN_SVID_MASK                     GENMASK(11, 0)
 191 #define   QCA8K_PORT_VLAN_SVID(x)                       FIELD_PREP(QCA8K_PORT_VLAN_SVID_MASK, x)
 192 #define QCA8K_REG_PORT_VLAN_CTRL1(_i)                   (0x424 + (_i * 8))
 193 #define QCA8K_REG_IPV4_PRI_BASE_ADDR                    0x470
 194 #define QCA8K_REG_IPV4_PRI_ADDR_MASK                    0x474
 195
 196 /* Lookup registers */
 197 #define QCA8K_ATU_TABLE_SIZE                            3 /* 12 bytes wide table / sizeof(u32) */
 198
 199 #define QCA8K_REG_ATU_DATA0                             0x600
 200 #define   QCA8K_ATU_ADDR2_MASK                          GENMASK(31, 24)
 201 #define   QCA8K_ATU_ADDR3_MASK                          GENMASK(23, 16)
 202 #define   QCA8K_ATU_ADDR4_MASK                          GENMASK(15, 8)
 203 #define   QCA8K_ATU_ADDR5_MASK                          GENMASK(7, 0)
 204 #define QCA8K_REG_ATU_DATA1                             0x604
 205 #define   QCA8K_ATU_PORT_MASK                           GENMASK(22, 16)
 206 #define   QCA8K_ATU_ADDR0_MASK                          GENMASK(15, 8)
 207 #define   QCA8K_ATU_ADDR1_MASK                          GENMASK(7, 0)
 208 #define QCA8K_REG_ATU_DATA2                             0x608
 209 #define   QCA8K_ATU_VID_MASK                            GENMASK(19, 8)
 210 #define   QCA8K_ATU_STATUS_MASK                         GENMASK(3, 0)
 211 #define   QCA8K_ATU_STATUS_STATIC                       0xf
 212 #define QCA8K_REG_ATU_FUNC                              0x60c
 213 #define   QCA8K_ATU_FUNC_BUSY                           BIT(31)
 214 #define   QCA8K_ATU_FUNC_PORT_EN                        BIT(14)
 215 #define   QCA8K_ATU_FUNC_MULTI_EN                       BIT(13)
 216 #define   QCA8K_ATU_FUNC_FULL                           BIT(12)
 217 #define   QCA8K_ATU_FUNC_PORT_MASK                      GENMASK(11, 8)
 218 #define QCA8K_REG_VTU_FUNC0                             0x610
 219 #define   QCA8K_VTU_FUNC0_VALID                         BIT(20)
 220 #define   QCA8K_VTU_FUNC0_IVL_EN                        BIT(19)
 221 /*        QCA8K_VTU_FUNC0_EG_MODE_MASK                  GENMASK(17, 4)
 222  *          It does contain VLAN_MODE for each port [5:4] for port0,
 223  *          [7:6] for port1 ... [17:16] for port6. Use virtual port
 224  *          define to handle this.
 225  */
 226 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i)        (4 + (_i) * 2)
 227 #define   QCA8K_VTU_FUNC0_EG_MODE_MASK                  GENMASK(1, 0)
 228 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i)         (GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 229 #define   QCA8K_VTU_FUNC0_EG_MODE_UNMOD                 FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x0)
 230 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i)        (QCA8K_VTU_FUNC0_EG_MODE_UNMOD << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 231 #define   QCA8K_VTU_FUNC0_EG_MODE_UNTAG                 FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x1)
 232 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i)        (QCA8K_VTU_FUNC0_EG_MODE_UNTAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 233 #define   QCA8K_VTU_FUNC0_EG_MODE_TAG                   FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x2)
 234 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i)          (QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 235 #define   QCA8K_VTU_FUNC0_EG_MODE_NOT                   FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x3)
 236 #define   QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i)          (QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
 237 #define QCA8K_REG_VTU_FUNC1                             0x614
 238 #define   QCA8K_VTU_FUNC1_BUSY                          BIT(31)
 239 #define   QCA8K_VTU_FUNC1_VID_MASK                      GENMASK(27, 16)
 240 #define   QCA8K_VTU_FUNC1_FULL                          BIT(4)
 241 #define QCA8K_REG_ATU_CTRL                              0x618
 242 #define   QCA8K_ATU_AGE_TIME_MASK                       GENMASK(15, 0)
 243 #define   QCA8K_ATU_AGE_TIME(x)                         FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))
 244 #define QCA8K_REG_GLOBAL_FW_CTRL0                       0x620
 245 #define   QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN             BIT(10)
 246 #define   QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM         GENMASK(7, 4)
 247 #define QCA8K_REG_GLOBAL_FW_CTRL1                       0x624
 248 #define   QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK            GENMASK(30, 24)
 249 #define   QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK              GENMASK(22, 16)
 250 #define   QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK              GENMASK(14, 8)
 251 #define   QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK              GENMASK(6, 0)
 252 #define QCA8K_PORT_LOOKUP_CTRL(_i)                      (0x660 + (_i) * 0xc)
 253 #define   QCA8K_PORT_LOOKUP_MEMBER                      GENMASK(6, 0)
 254 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_MASK              GENMASK(9, 8)
 255 #define   QCA8K_PORT_LOOKUP_VLAN_MODE(x)                FIELD_PREP(QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, x)
 256 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_NONE              QCA8K_PORT_LOOKUP_VLAN_MODE(0x0)
 257 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK          QCA8K_PORT_LOOKUP_VLAN_MODE(0x1)
 258 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK             QCA8K_PORT_LOOKUP_VLAN_MODE(0x2)
 259 #define   QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE            QCA8K_PORT_LOOKUP_VLAN_MODE(0x3)
 260 #define   QCA8K_PORT_LOOKUP_STATE_MASK                  GENMASK(18, 16)
 261 #define   QCA8K_PORT_LOOKUP_STATE(x)                    FIELD_PREP(QCA8K_PORT_LOOKUP_STATE_MASK, x)
 262 #define   QCA8K_PORT_LOOKUP_STATE_DISABLED              QCA8K_PORT_LOOKUP_STATE(0x0)
 263 #define   QCA8K_PORT_LOOKUP_STATE_BLOCKING              QCA8K_PORT_LOOKUP_STATE(0x1)
 264 #define   QCA8K_PORT_LOOKUP_STATE_LISTENING             QCA8K_PORT_LOOKUP_STATE(0x2)
 265 #define   QCA8K_PORT_LOOKUP_STATE_LEARNING              QCA8K_PORT_LOOKUP_STATE(0x3)
 266 #define   QCA8K_PORT_LOOKUP_STATE_FORWARD               QCA8K_PORT_LOOKUP_STATE(0x4)
 267 #define   QCA8K_PORT_LOOKUP_LEARN                       BIT(20)
 268 #define   QCA8K_PORT_LOOKUP_ING_MIRROR_EN               BIT(25)
 269
 270 #define QCA8K_REG_GOL_TRUNK_CTRL0                       0x700
 271 /* 4 max trunk first
 272  * first 6 bit for member bitmap
 273  * 7th bit is to enable trunk port
 274  */
 275 #define QCA8K_REG_GOL_TRUNK_SHIFT(_i)                   ((_i) * 8)
 276 #define QCA8K_REG_GOL_TRUNK_EN_MASK                     BIT(7)
 277 #define QCA8K_REG_GOL_TRUNK_EN(_i)                      (QCA8K_REG_GOL_TRUNK_EN_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
 278 #define QCA8K_REG_GOL_TRUNK_MEMBER_MASK                 GENMASK(6, 0)
 279 #define QCA8K_REG_GOL_TRUNK_MEMBER(_i)                  (QCA8K_REG_GOL_TRUNK_MEMBER_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
 280 /* 0x704 for TRUNK 0-1 --- 0x708 for TRUNK 2-3 */
 281 #define QCA8K_REG_GOL_TRUNK_CTRL(_i)                    (0x704 + (((_i) / 2) * 4))
 282 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK              GENMASK(3, 0)
 283 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK           BIT(3)
 284 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK         GENMASK(2, 0)
 285 #define QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i)                (((_i) / 2) * 16)
 286 #define QCA8K_REG_GOL_MEM_ID_SHIFT(_i)                  ((_i) * 4)
 287 /* Complex shift: FIRST shift for port THEN shift for trunk */
 288 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j)     (QCA8K_REG_GOL_MEM_ID_SHIFT(_j) + QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i))
 289 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(_i, _j)        (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
 290 #define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(_i, _j)      (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
 291
 292 #define QCA8K_REG_GLOBAL_FC_THRESH                      0x800
 293 #define   QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK            GENMASK(24, 16)
 294 #define   QCA8K_GLOBAL_FC_GOL_XON_THRES(x)              FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)
 295 #define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK           GENMASK(8, 0)
 296 #define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x)             FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, x)
 297
 298 #define QCA8K_REG_PORT_HOL_CTRL0(_i)                    (0x970 + (_i) * 0x8)
 299 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK         GENMASK(3, 0)
 300 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI0(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK, x)
 301 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK         GENMASK(7, 4)
 302 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI1(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK, x)
 303 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK         GENMASK(11, 8)
 304 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI2(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK, x)
 305 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK         GENMASK(15, 12)
 306 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI3(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK, x)
 307 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK         GENMASK(19, 16)
 308 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI4(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK, x)
 309 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK         GENMASK(23, 20)
 310 #define   QCA8K_PORT_HOL_CTRL0_EG_PRI5(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK, x)
 311 #define   QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK         GENMASK(29, 24)
 312 #define   QCA8K_PORT_HOL_CTRL0_EG_PORT(x)               FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK, x)
 313
 314 #define QCA8K_REG_PORT_HOL_CTRL1(_i)                    (0x974 + (_i) * 0x8)
 315 #define   QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK             GENMASK(3, 0)
 316 #define   QCA8K_PORT_HOL_CTRL1_ING(x)                   FIELD_PREP(QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK, x)
 317 #define   QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN            BIT(6)
 318 #define   QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN           BIT(7)
 319 #define   QCA8K_PORT_HOL_CTRL1_WRED_EN                  BIT(8)
 320 #define   QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN             BIT(16)
 321
 322 /* Pkt edit registers */
 323 #define QCA8K_EGREES_VLAN_PORT_SHIFT(_i)                (16 * ((_i) % 2))
 324 #define QCA8K_EGREES_VLAN_PORT_MASK(_i)                 (GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
 325 #define QCA8K_EGREES_VLAN_PORT(_i, x)                   ((x) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
 326 #define QCA8K_EGRESS_VLAN(x)                            (0x0c70 + (4 * (x / 2)))
 327
 328 /* L3 registers */
 329 #define QCA8K_HROUTER_CONTROL                           0xe00
 330 #define   QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M          GENMASK(17, 16)
 331 #define   QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S          16
 332 #define   QCA8K_HROUTER_CONTROL_ARP_AGE_MODE            1
 333 #define QCA8K_HROUTER_PBASED_CONTROL1                   0xe08
 334 #define QCA8K_HROUTER_PBASED_CONTROL2                   0xe0c
 335 #define QCA8K_HNAT_CONTROL                              0xe38
 336
 337 /* MIB registers */
 338 #define QCA8K_PORT_MIB_COUNTER(_i)                      (0x1000 + (_i) * 0x100)
 339
 340 /* QCA specific MII registers */
 341 #define MII_ATH_MMD_ADDR                                0x0d
 342 #define MII_ATH_MMD_DATA                                0x0e
 343
 344 enum {
 345         QCA8K_PORT_SPEED_10M = 0,
 346         QCA8K_PORT_SPEED_100M = 1,
 347         QCA8K_PORT_SPEED_1000M = 2,
 348         QCA8K_PORT_SPEED_ERR = 3,
 349 };
 350
 351 enum qca8k_fdb_cmd {
 352         QCA8K_FDB_FLUSH = 1,
 353         QCA8K_FDB_LOAD = 2,
 354         QCA8K_FDB_PURGE = 3,
 355         QCA8K_FDB_FLUSH_PORT = 5,
 356         QCA8K_FDB_NEXT = 6,
 357         QCA8K_FDB_SEARCH = 7,
 358 };
 359
 360 enum qca8k_vlan_cmd {
 361         QCA8K_VLAN_FLUSH = 1,
 362         QCA8K_VLAN_LOAD = 2,
 363         QCA8K_VLAN_PURGE = 3,
 364         QCA8K_VLAN_REMOVE_PORT = 4,
 365         QCA8K_VLAN_NEXT = 5,
 366         QCA8K_VLAN_READ = 6,
 367 };
 368
 369 enum qca8k_mid_cmd {
 370         QCA8K_MIB_FLUSH = 1,
 371         QCA8K_MIB_FLUSH_PORT = 2,
 372         QCA8K_MIB_CAST = 3,
 373 };
 374
 375 struct qca8k_priv;
 376
 377 struct qca8k_info_ops {
 378         int (*autocast_mib)(struct dsa_switch *ds, int port, u64 *data);
 379 };
 380
 381 struct qca8k_match_data {
 382         u8 id;
 383         bool reduced_package;
 384         u8 mib_count;
 385         const struct qca8k_info_ops *ops;
 386 };
 387
 388 enum {
 389         QCA8K_CPU_PORT0,
 390         QCA8K_CPU_PORT6,
 391 };
 392
 393 struct qca8k_mgmt_eth_data {
 394         struct completion rw_done;
 395         struct mutex mutex; /* Enforce one mdio read/write at time */
 396         bool ack;
 397         u32 seq;
 398         u32 data[4];
 399 };
 400
 401 struct qca8k_mib_eth_data {
 402         struct completion rw_done;
 403         struct mutex mutex; /* Process one command at time */
 404         refcount_t port_parsed; /* Counter to track parsed port */
 405         u8 req_port;
 406         u64 *data; /* pointer to ethtool data */
 407 };
 408
 409 struct qca8k_ports_config {
 410         bool sgmii_rx_clk_falling_edge;
 411         bool sgmii_tx_clk_falling_edge;
 412         bool sgmii_enable_pll;
 413         u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
 414         u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
 415 };
 416
 417 struct qca8k_mdio_cache {
 418 /* The 32bit switch registers are accessed indirectly. To achieve this we need
 419  * to set the page of the register. Track the last page that was set to reduce
 420  * mdio writes
 421  */
 422         u16 page;
 423 };
 424
 425 struct qca8k_pcs {
 426         struct phylink_pcs pcs;
 427         struct qca8k_priv *priv;
 428         int port;
 429 };
 430
 431 struct qca8k_led_pattern_en {
 432         u32 reg;
 433         u8 shift;
 434 };
 435
 436 struct qca8k_led {
 437         u8 port_num;
 438         u8 led_num;
 439         u16 old_rule;
 440         struct qca8k_priv *priv;
 441         struct led_classdev cdev;
 442 };
 443
 444 struct qca8k_priv {
 445         u8 switch_id;
 446         u8 switch_revision;
 447         u8 mirror_rx;
 448         u8 mirror_tx;
 449         u8 lag_hash_mode;
 450         /* Each bit correspond to a port. This switch can support a max of 7 port.
 451          * Bit 1: port enabled. Bit 0: port disabled.
 452          */
 453         u8 port_enabled_map;
 454         u8 port_isolated_map;
 455         struct qca8k_ports_config ports_config;
 456         struct regmap *regmap;
 457         struct mii_bus *bus;
 458         struct mii_bus *internal_mdio_bus;
 459         struct dsa_switch *ds;
 460         struct mutex reg_mutex;
 461         struct device *dev;
 462         struct gpio_desc *reset_gpio;
 463         struct net_device *mgmt_conduit; /* Track if mdio/mib Ethernet is available */
 464         struct qca8k_mgmt_eth_data mgmt_eth_data;
 465         struct qca8k_mib_eth_data mib_eth_data;
 466         struct qca8k_mdio_cache mdio_cache;
 467         struct qca8k_pcs pcs_port_0;
 468         struct qca8k_pcs pcs_port_6;
 469         const struct qca8k_match_data *info;
 470         struct qca8k_led ports_led[QCA8K_LED_COUNT];
 471 };
 472
 473 struct qca8k_mib_desc {
 474         unsigned int size;
 475         unsigned int offset;
 476         const char *name;
 477 };
 478
 479 struct qca8k_fdb {
 480         u16 vid;
 481         u8 port_mask;
 482         u8 aging;
 483         u8 mac[6];
 484 };
 485
 486 static inline u32 qca8k_port_to_phy(int port)
 487 {
 488         /* From Andrew Lunn:
 489          * Port 0 has no internal phy.
 490          * Port 1 has an internal PHY at MDIO address 0.
 491          * Port 2 has an internal PHY at MDIO address 1.
 492          * ...
 493          * Port 5 has an internal PHY at MDIO address 4.
 494          * Port 6 has no internal PHY.
 495          */
 496
 497         return port - 1;
 498 }
 499
 500 /* Common setup function */
 501 extern const struct qca8k_mib_desc ar8327_mib[];
 502 extern const struct regmap_access_table qca8k_readable_table;
 503 int qca8k_mib_init(struct qca8k_priv *priv);
 504 void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable);
 505 int qca8k_read_switch_id(struct qca8k_priv *priv);
 506
 507 /* Common read/write/rmw function */
 508 int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val);
 509 int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val);
 510 int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val);
 511
 512 /* Common ops function */
 513 void qca8k_fdb_flush(struct qca8k_priv *priv);
 514
 515 /* Common ethtool stats function */
 516 void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data);
 517 void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
 518                              uint64_t *data);
 519 int qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset);
 520
 521 /* Common eee function */
 522 int qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *eee);
 523
 524 /* Common bridge function */
 525 void qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
 526 int qca8k_port_pre_bridge_flags(struct dsa_switch *ds, int port,
 527                                 struct switchdev_brport_flags flags,
 528                                 struct netlink_ext_ack *extack);
 529 int qca8k_port_bridge_flags(struct dsa_switch *ds, int port,
 530                             struct switchdev_brport_flags flags,
 531                             struct netlink_ext_ack *extack);
 532 int qca8k_port_bridge_join(struct dsa_switch *ds, int port,
 533                            struct dsa_bridge bridge,
 534                            bool *tx_fwd_offload,
 535                            struct netlink_ext_ack *extack);
 536 void qca8k_port_bridge_leave(struct dsa_switch *ds, int port,
 537                              struct dsa_bridge bridge);
 538
 539 /* Common port enable/disable function */
 540 int qca8k_port_enable(struct dsa_switch *ds, int port,
 541                       struct phy_device *phy);
 542 void qca8k_port_disable(struct dsa_switch *ds, int port);
 543
 544 /* Common MTU function */
 545 int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu);
 546 int qca8k_port_max_mtu(struct dsa_switch *ds, int port);
 547
 548 /* Common fast age function */
 549 void qca8k_port_fast_age(struct dsa_switch *ds, int port);
 550 int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs);
 551
 552 /* Common FDB function */
 553 int qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
 554                           u16 port_mask, u16 vid);
 555 int qca8k_port_fdb_add(struct dsa_switch *ds, int port,
 556                        const unsigned char *addr, u16 vid,
 557                        struct dsa_db db);
 558 int qca8k_port_fdb_del(struct dsa_switch *ds, int port,
 559                        const unsigned char *addr, u16 vid,
 560                        struct dsa_db db);
 561 int qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
 562                         dsa_fdb_dump_cb_t *cb, void *data);
 563
 564 /* Common MDB function */
 565 int qca8k_port_mdb_add(struct dsa_switch *ds, int port,
 566                        const struct switchdev_obj_port_mdb *mdb,
 567                        struct dsa_db db);
 568 int qca8k_port_mdb_del(struct dsa_switch *ds, int port,
 569                        const struct switchdev_obj_port_mdb *mdb,
 570                        struct dsa_db db);
 571
 572 /* Common port mirror function */
 573 int qca8k_port_mirror_add(struct dsa_switch *ds, int port,
 574                           struct dsa_mall_mirror_tc_entry *mirror,
 575                           bool ingress, struct netlink_ext_ack *extack);
 576 void qca8k_port_mirror_del(struct dsa_switch *ds, int port,
 577                            struct dsa_mall_mirror_tc_entry *mirror);
 578
 579 /* Common port VLAN function */
 580 int qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
 581                               struct netlink_ext_ack *extack);
 582 int qca8k_port_vlan_add(struct dsa_switch *ds, int port,
 583                         const struct switchdev_obj_port_vlan *vlan,
 584                         struct netlink_ext_ack *extack);
 585 int qca8k_port_vlan_del(struct dsa_switch *ds, int port,
 586                         const struct switchdev_obj_port_vlan *vlan);
 587
 588 /* Common port LAG function */
 589 int qca8k_port_lag_join(struct dsa_switch *ds, int port, struct dsa_lag lag,
 590                         struct netdev_lag_upper_info *info,
 591                         struct netlink_ext_ack *extack);
 592 int qca8k_port_lag_leave(struct dsa_switch *ds, int port,
 593                          struct dsa_lag lag);
 594
 595 #endif /* __QCA8K_H */