drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_ih.h"
  27 #include "amdgpu_gfx.h"
  28 #include "cikd.h"
  29 #include "cik.h"
  30 #include "cik_structs.h"
  31 #include "atom.h"
  32 #include "amdgpu_ucode.h"
  33 #include "clearstate_ci.h"
  34
  35 #include "dce/dce_8_0_d.h"
  36 #include "dce/dce_8_0_sh_mask.h"
  37
  38 #include "bif/bif_4_1_d.h"
  39 #include "bif/bif_4_1_sh_mask.h"
  40
  41 #include "gca/gfx_7_0_d.h"
  42 #include "gca/gfx_7_2_enum.h"
  43 #include "gca/gfx_7_2_sh_mask.h"
  44
  45 #include "gmc/gmc_7_0_d.h"
  46 #include "gmc/gmc_7_0_sh_mask.h"
  47
  48 #include "oss/oss_2_0_d.h"
  49 #include "oss/oss_2_0_sh_mask.h"
  50
  51 #define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */
  52
  53 #define GFX7_NUM_GFX_RINGS     1
  54 #define GFX7_MEC_HPD_SIZE      2048
  55
  56 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  57 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  58 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
  59
  60 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
  61 MODULE_FIRMWARE("radeon/bonaire_me.bin");
  62 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
  63 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
  64 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
  65
  66 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
  67 MODULE_FIRMWARE("radeon/hawaii_me.bin");
  68 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
  69 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
  70 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
  71
  72 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
  73 MODULE_FIRMWARE("radeon/kaveri_me.bin");
  74 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
  75 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
  76 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
  77 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
  78
  79 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
  80 MODULE_FIRMWARE("radeon/kabini_me.bin");
  81 MODULE_FIRMWARE("radeon/kabini_ce.bin");
  82 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
  83 MODULE_FIRMWARE("radeon/kabini_mec.bin");
  84
  85 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
  86 MODULE_FIRMWARE("radeon/mullins_me.bin");
  87 MODULE_FIRMWARE("radeon/mullins_ce.bin");
  88 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
  89 MODULE_FIRMWARE("radeon/mullins_mec.bin");
  90
  91 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  92 {
  93         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  94         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  95         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  96         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  97         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
  98         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
  99         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
 100         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 101         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 102         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 103         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 104         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 105         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 106         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 107         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 108         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 109 };
 110
 111 static const u32 spectre_rlc_save_restore_register_list[] =
 112 {
 113         (0x0e00 << 16) | (0xc12c >> 2),
 114         0x00000000,
 115         (0x0e00 << 16) | (0xc140 >> 2),
 116         0x00000000,
 117         (0x0e00 << 16) | (0xc150 >> 2),
 118         0x00000000,
 119         (0x0e00 << 16) | (0xc15c >> 2),
 120         0x00000000,
 121         (0x0e00 << 16) | (0xc168 >> 2),
 122         0x00000000,
 123         (0x0e00 << 16) | (0xc170 >> 2),
 124         0x00000000,
 125         (0x0e00 << 16) | (0xc178 >> 2),
 126         0x00000000,
 127         (0x0e00 << 16) | (0xc204 >> 2),
 128         0x00000000,
 129         (0x0e00 << 16) | (0xc2b4 >> 2),
 130         0x00000000,
 131         (0x0e00 << 16) | (0xc2b8 >> 2),
 132         0x00000000,
 133         (0x0e00 << 16) | (0xc2bc >> 2),
 134         0x00000000,
 135         (0x0e00 << 16) | (0xc2c0 >> 2),
 136         0x00000000,
 137         (0x0e00 << 16) | (0x8228 >> 2),
 138         0x00000000,
 139         (0x0e00 << 16) | (0x829c >> 2),
 140         0x00000000,
 141         (0x0e00 << 16) | (0x869c >> 2),
 142         0x00000000,
 143         (0x0600 << 16) | (0x98f4 >> 2),
 144         0x00000000,
 145         (0x0e00 << 16) | (0x98f8 >> 2),
 146         0x00000000,
 147         (0x0e00 << 16) | (0x9900 >> 2),
 148         0x00000000,
 149         (0x0e00 << 16) | (0xc260 >> 2),
 150         0x00000000,
 151         (0x0e00 << 16) | (0x90e8 >> 2),
 152         0x00000000,
 153         (0x0e00 << 16) | (0x3c000 >> 2),
 154         0x00000000,
 155         (0x0e00 << 16) | (0x3c00c >> 2),
 156         0x00000000,
 157         (0x0e00 << 16) | (0x8c1c >> 2),
 158         0x00000000,
 159         (0x0e00 << 16) | (0x9700 >> 2),
 160         0x00000000,
 161         (0x0e00 << 16) | (0xcd20 >> 2),
 162         0x00000000,
 163         (0x4e00 << 16) | (0xcd20 >> 2),
 164         0x00000000,
 165         (0x5e00 << 16) | (0xcd20 >> 2),
 166         0x00000000,
 167         (0x6e00 << 16) | (0xcd20 >> 2),
 168         0x00000000,
 169         (0x7e00 << 16) | (0xcd20 >> 2),
 170         0x00000000,
 171         (0x8e00 << 16) | (0xcd20 >> 2),
 172         0x00000000,
 173         (0x9e00 << 16) | (0xcd20 >> 2),
 174         0x00000000,
 175         (0xae00 << 16) | (0xcd20 >> 2),
 176         0x00000000,
 177         (0xbe00 << 16) | (0xcd20 >> 2),
 178         0x00000000,
 179         (0x0e00 << 16) | (0x89bc >> 2),
 180         0x00000000,
 181         (0x0e00 << 16) | (0x8900 >> 2),
 182         0x00000000,
 183         0x3,
 184         (0x0e00 << 16) | (0xc130 >> 2),
 185         0x00000000,
 186         (0x0e00 << 16) | (0xc134 >> 2),
 187         0x00000000,
 188         (0x0e00 << 16) | (0xc1fc >> 2),
 189         0x00000000,
 190         (0x0e00 << 16) | (0xc208 >> 2),
 191         0x00000000,
 192         (0x0e00 << 16) | (0xc264 >> 2),
 193         0x00000000,
 194         (0x0e00 << 16) | (0xc268 >> 2),
 195         0x00000000,
 196         (0x0e00 << 16) | (0xc26c >> 2),
 197         0x00000000,
 198         (0x0e00 << 16) | (0xc270 >> 2),
 199         0x00000000,
 200         (0x0e00 << 16) | (0xc274 >> 2),
 201         0x00000000,
 202         (0x0e00 << 16) | (0xc278 >> 2),
 203         0x00000000,
 204         (0x0e00 << 16) | (0xc27c >> 2),
 205         0x00000000,
 206         (0x0e00 << 16) | (0xc280 >> 2),
 207         0x00000000,
 208         (0x0e00 << 16) | (0xc284 >> 2),
 209         0x00000000,
 210         (0x0e00 << 16) | (0xc288 >> 2),
 211         0x00000000,
 212         (0x0e00 << 16) | (0xc28c >> 2),
 213         0x00000000,
 214         (0x0e00 << 16) | (0xc290 >> 2),
 215         0x00000000,
 216         (0x0e00 << 16) | (0xc294 >> 2),
 217         0x00000000,
 218         (0x0e00 << 16) | (0xc298 >> 2),
 219         0x00000000,
 220         (0x0e00 << 16) | (0xc29c >> 2),
 221         0x00000000,
 222         (0x0e00 << 16) | (0xc2a0 >> 2),
 223         0x00000000,
 224         (0x0e00 << 16) | (0xc2a4 >> 2),
 225         0x00000000,
 226         (0x0e00 << 16) | (0xc2a8 >> 2),
 227         0x00000000,
 228         (0x0e00 << 16) | (0xc2ac  >> 2),
 229         0x00000000,
 230         (0x0e00 << 16) | (0xc2b0 >> 2),
 231         0x00000000,
 232         (0x0e00 << 16) | (0x301d0 >> 2),
 233         0x00000000,
 234         (0x0e00 << 16) | (0x30238 >> 2),
 235         0x00000000,
 236         (0x0e00 << 16) | (0x30250 >> 2),
 237         0x00000000,
 238         (0x0e00 << 16) | (0x30254 >> 2),
 239         0x00000000,
 240         (0x0e00 << 16) | (0x30258 >> 2),
 241         0x00000000,
 242         (0x0e00 << 16) | (0x3025c >> 2),
 243         0x00000000,
 244         (0x4e00 << 16) | (0xc900 >> 2),
 245         0x00000000,
 246         (0x5e00 << 16) | (0xc900 >> 2),
 247         0x00000000,
 248         (0x6e00 << 16) | (0xc900 >> 2),
 249         0x00000000,
 250         (0x7e00 << 16) | (0xc900 >> 2),
 251         0x00000000,
 252         (0x8e00 << 16) | (0xc900 >> 2),
 253         0x00000000,
 254         (0x9e00 << 16) | (0xc900 >> 2),
 255         0x00000000,
 256         (0xae00 << 16) | (0xc900 >> 2),
 257         0x00000000,
 258         (0xbe00 << 16) | (0xc900 >> 2),
 259         0x00000000,
 260         (0x4e00 << 16) | (0xc904 >> 2),
 261         0x00000000,
 262         (0x5e00 << 16) | (0xc904 >> 2),
 263         0x00000000,
 264         (0x6e00 << 16) | (0xc904 >> 2),
 265         0x00000000,
 266         (0x7e00 << 16) | (0xc904 >> 2),
 267         0x00000000,
 268         (0x8e00 << 16) | (0xc904 >> 2),
 269         0x00000000,
 270         (0x9e00 << 16) | (0xc904 >> 2),
 271         0x00000000,
 272         (0xae00 << 16) | (0xc904 >> 2),
 273         0x00000000,
 274         (0xbe00 << 16) | (0xc904 >> 2),
 275         0x00000000,
 276         (0x4e00 << 16) | (0xc908 >> 2),
 277         0x00000000,
 278         (0x5e00 << 16) | (0xc908 >> 2),
 279         0x00000000,
 280         (0x6e00 << 16) | (0xc908 >> 2),
 281         0x00000000,
 282         (0x7e00 << 16) | (0xc908 >> 2),
 283         0x00000000,
 284         (0x8e00 << 16) | (0xc908 >> 2),
 285         0x00000000,
 286         (0x9e00 << 16) | (0xc908 >> 2),
 287         0x00000000,
 288         (0xae00 << 16) | (0xc908 >> 2),
 289         0x00000000,
 290         (0xbe00 << 16) | (0xc908 >> 2),
 291         0x00000000,
 292         (0x4e00 << 16) | (0xc90c >> 2),
 293         0x00000000,
 294         (0x5e00 << 16) | (0xc90c >> 2),
 295         0x00000000,
 296         (0x6e00 << 16) | (0xc90c >> 2),
 297         0x00000000,
 298         (0x7e00 << 16) | (0xc90c >> 2),
 299         0x00000000,
 300         (0x8e00 << 16) | (0xc90c >> 2),
 301         0x00000000,
 302         (0x9e00 << 16) | (0xc90c >> 2),
 303         0x00000000,
 304         (0xae00 << 16) | (0xc90c >> 2),
 305         0x00000000,
 306         (0xbe00 << 16) | (0xc90c >> 2),
 307         0x00000000,
 308         (0x4e00 << 16) | (0xc910 >> 2),
 309         0x00000000,
 310         (0x5e00 << 16) | (0xc910 >> 2),
 311         0x00000000,
 312         (0x6e00 << 16) | (0xc910 >> 2),
 313         0x00000000,
 314         (0x7e00 << 16) | (0xc910 >> 2),
 315         0x00000000,
 316         (0x8e00 << 16) | (0xc910 >> 2),
 317         0x00000000,
 318         (0x9e00 << 16) | (0xc910 >> 2),
 319         0x00000000,
 320         (0xae00 << 16) | (0xc910 >> 2),
 321         0x00000000,
 322         (0xbe00 << 16) | (0xc910 >> 2),
 323         0x00000000,
 324         (0x0e00 << 16) | (0xc99c >> 2),
 325         0x00000000,
 326         (0x0e00 << 16) | (0x9834 >> 2),
 327         0x00000000,
 328         (0x0000 << 16) | (0x30f00 >> 2),
 329         0x00000000,
 330         (0x0001 << 16) | (0x30f00 >> 2),
 331         0x00000000,
 332         (0x0000 << 16) | (0x30f04 >> 2),
 333         0x00000000,
 334         (0x0001 << 16) | (0x30f04 >> 2),
 335         0x00000000,
 336         (0x0000 << 16) | (0x30f08 >> 2),
 337         0x00000000,
 338         (0x0001 << 16) | (0x30f08 >> 2),
 339         0x00000000,
 340         (0x0000 << 16) | (0x30f0c >> 2),
 341         0x00000000,
 342         (0x0001 << 16) | (0x30f0c >> 2),
 343         0x00000000,
 344         (0x0600 << 16) | (0x9b7c >> 2),
 345         0x00000000,
 346         (0x0e00 << 16) | (0x8a14 >> 2),
 347         0x00000000,
 348         (0x0e00 << 16) | (0x8a18 >> 2),
 349         0x00000000,
 350         (0x0600 << 16) | (0x30a00 >> 2),
 351         0x00000000,
 352         (0x0e00 << 16) | (0x8bf0 >> 2),
 353         0x00000000,
 354         (0x0e00 << 16) | (0x8bcc >> 2),
 355         0x00000000,
 356         (0x0e00 << 16) | (0x8b24 >> 2),
 357         0x00000000,
 358         (0x0e00 << 16) | (0x30a04 >> 2),
 359         0x00000000,
 360         (0x0600 << 16) | (0x30a10 >> 2),
 361         0x00000000,
 362         (0x0600 << 16) | (0x30a14 >> 2),
 363         0x00000000,
 364         (0x0600 << 16) | (0x30a18 >> 2),
 365         0x00000000,
 366         (0x0600 << 16) | (0x30a2c >> 2),
 367         0x00000000,
 368         (0x0e00 << 16) | (0xc700 >> 2),
 369         0x00000000,
 370         (0x0e00 << 16) | (0xc704 >> 2),
 371         0x00000000,
 372         (0x0e00 << 16) | (0xc708 >> 2),
 373         0x00000000,
 374         (0x0e00 << 16) | (0xc768 >> 2),
 375         0x00000000,
 376         (0x0400 << 16) | (0xc770 >> 2),
 377         0x00000000,
 378         (0x0400 << 16) | (0xc774 >> 2),
 379         0x00000000,
 380         (0x0400 << 16) | (0xc778 >> 2),
 381         0x00000000,
 382         (0x0400 << 16) | (0xc77c >> 2),
 383         0x00000000,
 384         (0x0400 << 16) | (0xc780 >> 2),
 385         0x00000000,
 386         (0x0400 << 16) | (0xc784 >> 2),
 387         0x00000000,
 388         (0x0400 << 16) | (0xc788 >> 2),
 389         0x00000000,
 390         (0x0400 << 16) | (0xc78c >> 2),
 391         0x00000000,
 392         (0x0400 << 16) | (0xc798 >> 2),
 393         0x00000000,
 394         (0x0400 << 16) | (0xc79c >> 2),
 395         0x00000000,
 396         (0x0400 << 16) | (0xc7a0 >> 2),
 397         0x00000000,
 398         (0x0400 << 16) | (0xc7a4 >> 2),
 399         0x00000000,
 400         (0x0400 << 16) | (0xc7a8 >> 2),
 401         0x00000000,
 402         (0x0400 << 16) | (0xc7ac >> 2),
 403         0x00000000,
 404         (0x0400 << 16) | (0xc7b0 >> 2),
 405         0x00000000,
 406         (0x0400 << 16) | (0xc7b4 >> 2),
 407         0x00000000,
 408         (0x0e00 << 16) | (0x9100 >> 2),
 409         0x00000000,
 410         (0x0e00 << 16) | (0x3c010 >> 2),
 411         0x00000000,
 412         (0x0e00 << 16) | (0x92a8 >> 2),
 413         0x00000000,
 414         (0x0e00 << 16) | (0x92ac >> 2),
 415         0x00000000,
 416         (0x0e00 << 16) | (0x92b4 >> 2),
 417         0x00000000,
 418         (0x0e00 << 16) | (0x92b8 >> 2),
 419         0x00000000,
 420         (0x0e00 << 16) | (0x92bc >> 2),
 421         0x00000000,
 422         (0x0e00 << 16) | (0x92c0 >> 2),
 423         0x00000000,
 424         (0x0e00 << 16) | (0x92c4 >> 2),
 425         0x00000000,
 426         (0x0e00 << 16) | (0x92c8 >> 2),
 427         0x00000000,
 428         (0x0e00 << 16) | (0x92cc >> 2),
 429         0x00000000,
 430         (0x0e00 << 16) | (0x92d0 >> 2),
 431         0x00000000,
 432         (0x0e00 << 16) | (0x8c00 >> 2),
 433         0x00000000,
 434         (0x0e00 << 16) | (0x8c04 >> 2),
 435         0x00000000,
 436         (0x0e00 << 16) | (0x8c20 >> 2),
 437         0x00000000,
 438         (0x0e00 << 16) | (0x8c38 >> 2),
 439         0x00000000,
 440         (0x0e00 << 16) | (0x8c3c >> 2),
 441         0x00000000,
 442         (0x0e00 << 16) | (0xae00 >> 2),
 443         0x00000000,
 444         (0x0e00 << 16) | (0x9604 >> 2),
 445         0x00000000,
 446         (0x0e00 << 16) | (0xac08 >> 2),
 447         0x00000000,
 448         (0x0e00 << 16) | (0xac0c >> 2),
 449         0x00000000,
 450         (0x0e00 << 16) | (0xac10 >> 2),
 451         0x00000000,
 452         (0x0e00 << 16) | (0xac14 >> 2),
 453         0x00000000,
 454         (0x0e00 << 16) | (0xac58 >> 2),
 455         0x00000000,
 456         (0x0e00 << 16) | (0xac68 >> 2),
 457         0x00000000,
 458         (0x0e00 << 16) | (0xac6c >> 2),
 459         0x00000000,
 460         (0x0e00 << 16) | (0xac70 >> 2),
 461         0x00000000,
 462         (0x0e00 << 16) | (0xac74 >> 2),
 463         0x00000000,
 464         (0x0e00 << 16) | (0xac78 >> 2),
 465         0x00000000,
 466         (0x0e00 << 16) | (0xac7c >> 2),
 467         0x00000000,
 468         (0x0e00 << 16) | (0xac80 >> 2),
 469         0x00000000,
 470         (0x0e00 << 16) | (0xac84 >> 2),
 471         0x00000000,
 472         (0x0e00 << 16) | (0xac88 >> 2),
 473         0x00000000,
 474         (0x0e00 << 16) | (0xac8c >> 2),
 475         0x00000000,
 476         (0x0e00 << 16) | (0x970c >> 2),
 477         0x00000000,
 478         (0x0e00 << 16) | (0x9714 >> 2),
 479         0x00000000,
 480         (0x0e00 << 16) | (0x9718 >> 2),
 481         0x00000000,
 482         (0x0e00 << 16) | (0x971c >> 2),
 483         0x00000000,
 484         (0x0e00 << 16) | (0x31068 >> 2),
 485         0x00000000,
 486         (0x4e00 << 16) | (0x31068 >> 2),
 487         0x00000000,
 488         (0x5e00 << 16) | (0x31068 >> 2),
 489         0x00000000,
 490         (0x6e00 << 16) | (0x31068 >> 2),
 491         0x00000000,
 492         (0x7e00 << 16) | (0x31068 >> 2),
 493         0x00000000,
 494         (0x8e00 << 16) | (0x31068 >> 2),
 495         0x00000000,
 496         (0x9e00 << 16) | (0x31068 >> 2),
 497         0x00000000,
 498         (0xae00 << 16) | (0x31068 >> 2),
 499         0x00000000,
 500         (0xbe00 << 16) | (0x31068 >> 2),
 501         0x00000000,
 502         (0x0e00 << 16) | (0xcd10 >> 2),
 503         0x00000000,
 504         (0x0e00 << 16) | (0xcd14 >> 2),
 505         0x00000000,
 506         (0x0e00 << 16) | (0x88b0 >> 2),
 507         0x00000000,
 508         (0x0e00 << 16) | (0x88b4 >> 2),
 509         0x00000000,
 510         (0x0e00 << 16) | (0x88b8 >> 2),
 511         0x00000000,
 512         (0x0e00 << 16) | (0x88bc >> 2),
 513         0x00000000,
 514         (0x0400 << 16) | (0x89c0 >> 2),
 515         0x00000000,
 516         (0x0e00 << 16) | (0x88c4 >> 2),
 517         0x00000000,
 518         (0x0e00 << 16) | (0x88c8 >> 2),
 519         0x00000000,
 520         (0x0e00 << 16) | (0x88d0 >> 2),
 521         0x00000000,
 522         (0x0e00 << 16) | (0x88d4 >> 2),
 523         0x00000000,
 524         (0x0e00 << 16) | (0x88d8 >> 2),
 525         0x00000000,
 526         (0x0e00 << 16) | (0x8980 >> 2),
 527         0x00000000,
 528         (0x0e00 << 16) | (0x30938 >> 2),
 529         0x00000000,
 530         (0x0e00 << 16) | (0x3093c >> 2),
 531         0x00000000,
 532         (0x0e00 << 16) | (0x30940 >> 2),
 533         0x00000000,
 534         (0x0e00 << 16) | (0x89a0 >> 2),
 535         0x00000000,
 536         (0x0e00 << 16) | (0x30900 >> 2),
 537         0x00000000,
 538         (0x0e00 << 16) | (0x30904 >> 2),
 539         0x00000000,
 540         (0x0e00 << 16) | (0x89b4 >> 2),
 541         0x00000000,
 542         (0x0e00 << 16) | (0x3c210 >> 2),
 543         0x00000000,
 544         (0x0e00 << 16) | (0x3c214 >> 2),
 545         0x00000000,
 546         (0x0e00 << 16) | (0x3c218 >> 2),
 547         0x00000000,
 548         (0x0e00 << 16) | (0x8904 >> 2),
 549         0x00000000,
 550         0x5,
 551         (0x0e00 << 16) | (0x8c28 >> 2),
 552         (0x0e00 << 16) | (0x8c2c >> 2),
 553         (0x0e00 << 16) | (0x8c30 >> 2),
 554         (0x0e00 << 16) | (0x8c34 >> 2),
 555         (0x0e00 << 16) | (0x9600 >> 2),
 556 };
 557
 558 static const u32 kalindi_rlc_save_restore_register_list[] =
 559 {
 560         (0x0e00 << 16) | (0xc12c >> 2),
 561         0x00000000,
 562         (0x0e00 << 16) | (0xc140 >> 2),
 563         0x00000000,
 564         (0x0e00 << 16) | (0xc150 >> 2),
 565         0x00000000,
 566         (0x0e00 << 16) | (0xc15c >> 2),
 567         0x00000000,
 568         (0x0e00 << 16) | (0xc168 >> 2),
 569         0x00000000,
 570         (0x0e00 << 16) | (0xc170 >> 2),
 571         0x00000000,
 572         (0x0e00 << 16) | (0xc204 >> 2),
 573         0x00000000,
 574         (0x0e00 << 16) | (0xc2b4 >> 2),
 575         0x00000000,
 576         (0x0e00 << 16) | (0xc2b8 >> 2),
 577         0x00000000,
 578         (0x0e00 << 16) | (0xc2bc >> 2),
 579         0x00000000,
 580         (0x0e00 << 16) | (0xc2c0 >> 2),
 581         0x00000000,
 582         (0x0e00 << 16) | (0x8228 >> 2),
 583         0x00000000,
 584         (0x0e00 << 16) | (0x829c >> 2),
 585         0x00000000,
 586         (0x0e00 << 16) | (0x869c >> 2),
 587         0x00000000,
 588         (0x0600 << 16) | (0x98f4 >> 2),
 589         0x00000000,
 590         (0x0e00 << 16) | (0x98f8 >> 2),
 591         0x00000000,
 592         (0x0e00 << 16) | (0x9900 >> 2),
 593         0x00000000,
 594         (0x0e00 << 16) | (0xc260 >> 2),
 595         0x00000000,
 596         (0x0e00 << 16) | (0x90e8 >> 2),
 597         0x00000000,
 598         (0x0e00 << 16) | (0x3c000 >> 2),
 599         0x00000000,
 600         (0x0e00 << 16) | (0x3c00c >> 2),
 601         0x00000000,
 602         (0x0e00 << 16) | (0x8c1c >> 2),
 603         0x00000000,
 604         (0x0e00 << 16) | (0x9700 >> 2),
 605         0x00000000,
 606         (0x0e00 << 16) | (0xcd20 >> 2),
 607         0x00000000,
 608         (0x4e00 << 16) | (0xcd20 >> 2),
 609         0x00000000,
 610         (0x5e00 << 16) | (0xcd20 >> 2),
 611         0x00000000,
 612         (0x6e00 << 16) | (0xcd20 >> 2),
 613         0x00000000,
 614         (0x7e00 << 16) | (0xcd20 >> 2),
 615         0x00000000,
 616         (0x0e00 << 16) | (0x89bc >> 2),
 617         0x00000000,
 618         (0x0e00 << 16) | (0x8900 >> 2),
 619         0x00000000,
 620         0x3,
 621         (0x0e00 << 16) | (0xc130 >> 2),
 622         0x00000000,
 623         (0x0e00 << 16) | (0xc134 >> 2),
 624         0x00000000,
 625         (0x0e00 << 16) | (0xc1fc >> 2),
 626         0x00000000,
 627         (0x0e00 << 16) | (0xc208 >> 2),
 628         0x00000000,
 629         (0x0e00 << 16) | (0xc264 >> 2),
 630         0x00000000,
 631         (0x0e00 << 16) | (0xc268 >> 2),
 632         0x00000000,
 633         (0x0e00 << 16) | (0xc26c >> 2),
 634         0x00000000,
 635         (0x0e00 << 16) | (0xc270 >> 2),
 636         0x00000000,
 637         (0x0e00 << 16) | (0xc274 >> 2),
 638         0x00000000,
 639         (0x0e00 << 16) | (0xc28c >> 2),
 640         0x00000000,
 641         (0x0e00 << 16) | (0xc290 >> 2),
 642         0x00000000,
 643         (0x0e00 << 16) | (0xc294 >> 2),
 644         0x00000000,
 645         (0x0e00 << 16) | (0xc298 >> 2),
 646         0x00000000,
 647         (0x0e00 << 16) | (0xc2a0 >> 2),
 648         0x00000000,
 649         (0x0e00 << 16) | (0xc2a4 >> 2),
 650         0x00000000,
 651         (0x0e00 << 16) | (0xc2a8 >> 2),
 652         0x00000000,
 653         (0x0e00 << 16) | (0xc2ac >> 2),
 654         0x00000000,
 655         (0x0e00 << 16) | (0x301d0 >> 2),
 656         0x00000000,
 657         (0x0e00 << 16) | (0x30238 >> 2),
 658         0x00000000,
 659         (0x0e00 << 16) | (0x30250 >> 2),
 660         0x00000000,
 661         (0x0e00 << 16) | (0x30254 >> 2),
 662         0x00000000,
 663         (0x0e00 << 16) | (0x30258 >> 2),
 664         0x00000000,
 665         (0x0e00 << 16) | (0x3025c >> 2),
 666         0x00000000,
 667         (0x4e00 << 16) | (0xc900 >> 2),
 668         0x00000000,
 669         (0x5e00 << 16) | (0xc900 >> 2),
 670         0x00000000,
 671         (0x6e00 << 16) | (0xc900 >> 2),
 672         0x00000000,
 673         (0x7e00 << 16) | (0xc900 >> 2),
 674         0x00000000,
 675         (0x4e00 << 16) | (0xc904 >> 2),
 676         0x00000000,
 677         (0x5e00 << 16) | (0xc904 >> 2),
 678         0x00000000,
 679         (0x6e00 << 16) | (0xc904 >> 2),
 680         0x00000000,
 681         (0x7e00 << 16) | (0xc904 >> 2),
 682         0x00000000,
 683         (0x4e00 << 16) | (0xc908 >> 2),
 684         0x00000000,
 685         (0x5e00 << 16) | (0xc908 >> 2),
 686         0x00000000,
 687         (0x6e00 << 16) | (0xc908 >> 2),
 688         0x00000000,
 689         (0x7e00 << 16) | (0xc908 >> 2),
 690         0x00000000,
 691         (0x4e00 << 16) | (0xc90c >> 2),
 692         0x00000000,
 693         (0x5e00 << 16) | (0xc90c >> 2),
 694         0x00000000,
 695         (0x6e00 << 16) | (0xc90c >> 2),
 696         0x00000000,
 697         (0x7e00 << 16) | (0xc90c >> 2),
 698         0x00000000,
 699         (0x4e00 << 16) | (0xc910 >> 2),
 700         0x00000000,
 701         (0x5e00 << 16) | (0xc910 >> 2),
 702         0x00000000,
 703         (0x6e00 << 16) | (0xc910 >> 2),
 704         0x00000000,
 705         (0x7e00 << 16) | (0xc910 >> 2),
 706         0x00000000,
 707         (0x0e00 << 16) | (0xc99c >> 2),
 708         0x00000000,
 709         (0x0e00 << 16) | (0x9834 >> 2),
 710         0x00000000,
 711         (0x0000 << 16) | (0x30f00 >> 2),
 712         0x00000000,
 713         (0x0000 << 16) | (0x30f04 >> 2),
 714         0x00000000,
 715         (0x0000 << 16) | (0x30f08 >> 2),
 716         0x00000000,
 717         (0x0000 << 16) | (0x30f0c >> 2),
 718         0x00000000,
 719         (0x0600 << 16) | (0x9b7c >> 2),
 720         0x00000000,
 721         (0x0e00 << 16) | (0x8a14 >> 2),
 722         0x00000000,
 723         (0x0e00 << 16) | (0x8a18 >> 2),
 724         0x00000000,
 725         (0x0600 << 16) | (0x30a00 >> 2),
 726         0x00000000,
 727         (0x0e00 << 16) | (0x8bf0 >> 2),
 728         0x00000000,
 729         (0x0e00 << 16) | (0x8bcc >> 2),
 730         0x00000000,
 731         (0x0e00 << 16) | (0x8b24 >> 2),
 732         0x00000000,
 733         (0x0e00 << 16) | (0x30a04 >> 2),
 734         0x00000000,
 735         (0x0600 << 16) | (0x30a10 >> 2),
 736         0x00000000,
 737         (0x0600 << 16) | (0x30a14 >> 2),
 738         0x00000000,
 739         (0x0600 << 16) | (0x30a18 >> 2),
 740         0x00000000,
 741         (0x0600 << 16) | (0x30a2c >> 2),
 742         0x00000000,
 743         (0x0e00 << 16) | (0xc700 >> 2),
 744         0x00000000,
 745         (0x0e00 << 16) | (0xc704 >> 2),
 746         0x00000000,
 747         (0x0e00 << 16) | (0xc708 >> 2),
 748         0x00000000,
 749         (0x0e00 << 16) | (0xc768 >> 2),
 750         0x00000000,
 751         (0x0400 << 16) | (0xc770 >> 2),
 752         0x00000000,
 753         (0x0400 << 16) | (0xc774 >> 2),
 754         0x00000000,
 755         (0x0400 << 16) | (0xc798 >> 2),
 756         0x00000000,
 757         (0x0400 << 16) | (0xc79c >> 2),
 758         0x00000000,
 759         (0x0e00 << 16) | (0x9100 >> 2),
 760         0x00000000,
 761         (0x0e00 << 16) | (0x3c010 >> 2),
 762         0x00000000,
 763         (0x0e00 << 16) | (0x8c00 >> 2),
 764         0x00000000,
 765         (0x0e00 << 16) | (0x8c04 >> 2),
 766         0x00000000,
 767         (0x0e00 << 16) | (0x8c20 >> 2),
 768         0x00000000,
 769         (0x0e00 << 16) | (0x8c38 >> 2),
 770         0x00000000,
 771         (0x0e00 << 16) | (0x8c3c >> 2),
 772         0x00000000,
 773         (0x0e00 << 16) | (0xae00 >> 2),
 774         0x00000000,
 775         (0x0e00 << 16) | (0x9604 >> 2),
 776         0x00000000,
 777         (0x0e00 << 16) | (0xac08 >> 2),
 778         0x00000000,
 779         (0x0e00 << 16) | (0xac0c >> 2),
 780         0x00000000,
 781         (0x0e00 << 16) | (0xac10 >> 2),
 782         0x00000000,
 783         (0x0e00 << 16) | (0xac14 >> 2),
 784         0x00000000,
 785         (0x0e00 << 16) | (0xac58 >> 2),
 786         0x00000000,
 787         (0x0e00 << 16) | (0xac68 >> 2),
 788         0x00000000,
 789         (0x0e00 << 16) | (0xac6c >> 2),
 790         0x00000000,
 791         (0x0e00 << 16) | (0xac70 >> 2),
 792         0x00000000,
 793         (0x0e00 << 16) | (0xac74 >> 2),
 794         0x00000000,
 795         (0x0e00 << 16) | (0xac78 >> 2),
 796         0x00000000,
 797         (0x0e00 << 16) | (0xac7c >> 2),
 798         0x00000000,
 799         (0x0e00 << 16) | (0xac80 >> 2),
 800         0x00000000,
 801         (0x0e00 << 16) | (0xac84 >> 2),
 802         0x00000000,
 803         (0x0e00 << 16) | (0xac88 >> 2),
 804         0x00000000,
 805         (0x0e00 << 16) | (0xac8c >> 2),
 806         0x00000000,
 807         (0x0e00 << 16) | (0x970c >> 2),
 808         0x00000000,
 809         (0x0e00 << 16) | (0x9714 >> 2),
 810         0x00000000,
 811         (0x0e00 << 16) | (0x9718 >> 2),
 812         0x00000000,
 813         (0x0e00 << 16) | (0x971c >> 2),
 814         0x00000000,
 815         (0x0e00 << 16) | (0x31068 >> 2),
 816         0x00000000,
 817         (0x4e00 << 16) | (0x31068 >> 2),
 818         0x00000000,
 819         (0x5e00 << 16) | (0x31068 >> 2),
 820         0x00000000,
 821         (0x6e00 << 16) | (0x31068 >> 2),
 822         0x00000000,
 823         (0x7e00 << 16) | (0x31068 >> 2),
 824         0x00000000,
 825         (0x0e00 << 16) | (0xcd10 >> 2),
 826         0x00000000,
 827         (0x0e00 << 16) | (0xcd14 >> 2),
 828         0x00000000,
 829         (0x0e00 << 16) | (0x88b0 >> 2),
 830         0x00000000,
 831         (0x0e00 << 16) | (0x88b4 >> 2),
 832         0x00000000,
 833         (0x0e00 << 16) | (0x88b8 >> 2),
 834         0x00000000,
 835         (0x0e00 << 16) | (0x88bc >> 2),
 836         0x00000000,
 837         (0x0400 << 16) | (0x89c0 >> 2),
 838         0x00000000,
 839         (0x0e00 << 16) | (0x88c4 >> 2),
 840         0x00000000,
 841         (0x0e00 << 16) | (0x88c8 >> 2),
 842         0x00000000,
 843         (0x0e00 << 16) | (0x88d0 >> 2),
 844         0x00000000,
 845         (0x0e00 << 16) | (0x88d4 >> 2),
 846         0x00000000,
 847         (0x0e00 << 16) | (0x88d8 >> 2),
 848         0x00000000,
 849         (0x0e00 << 16) | (0x8980 >> 2),
 850         0x00000000,
 851         (0x0e00 << 16) | (0x30938 >> 2),
 852         0x00000000,
 853         (0x0e00 << 16) | (0x3093c >> 2),
 854         0x00000000,
 855         (0x0e00 << 16) | (0x30940 >> 2),
 856         0x00000000,
 857         (0x0e00 << 16) | (0x89a0 >> 2),
 858         0x00000000,
 859         (0x0e00 << 16) | (0x30900 >> 2),
 860         0x00000000,
 861         (0x0e00 << 16) | (0x30904 >> 2),
 862         0x00000000,
 863         (0x0e00 << 16) | (0x89b4 >> 2),
 864         0x00000000,
 865         (0x0e00 << 16) | (0x3e1fc >> 2),
 866         0x00000000,
 867         (0x0e00 << 16) | (0x3c210 >> 2),
 868         0x00000000,
 869         (0x0e00 << 16) | (0x3c214 >> 2),
 870         0x00000000,
 871         (0x0e00 << 16) | (0x3c218 >> 2),
 872         0x00000000,
 873         (0x0e00 << 16) | (0x8904 >> 2),
 874         0x00000000,
 875         0x5,
 876         (0x0e00 << 16) | (0x8c28 >> 2),
 877         (0x0e00 << 16) | (0x8c2c >> 2),
 878         (0x0e00 << 16) | (0x8c30 >> 2),
 879         (0x0e00 << 16) | (0x8c34 >> 2),
 880         (0x0e00 << 16) | (0x9600 >> 2),
 881 };
 882
 883 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
 884 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
 885 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
 886 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
 887 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
 888
 889 /*
 890  * Core functions
 891  */
 892 /**
 893  * gfx_v7_0_init_microcode - load ucode images from disk
 894  *
 895  * @adev: amdgpu_device pointer
 896  *
 897  * Use the firmware interface to load the ucode images into
 898  * the driver (not loaded into hw).
 899  * Returns 0 on success, error on failure.
 900  */
 901 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
 902 {
 903         const char *chip_name;
 904         char fw_name[30];
 905         int err;
 906
 907         DRM_DEBUG("\n");
 908
 909         switch (adev->asic_type) {
 910         case CHIP_BONAIRE:
 911                 chip_name = "bonaire";
 912                 break;
 913         case CHIP_HAWAII:
 914                 chip_name = "hawaii";
 915                 break;
 916         case CHIP_KAVERI:
 917                 chip_name = "kaveri";
 918                 break;
 919         case CHIP_KABINI:
 920                 chip_name = "kabini";
 921                 break;
 922         case CHIP_MULLINS:
 923                 chip_name = "mullins";
 924                 break;
 925         default: BUG();
 926         }
 927
 928         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 929         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 930         if (err)
 931                 goto out;
 932         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 933         if (err)
 934                 goto out;
 935
 936         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 937         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 938         if (err)
 939                 goto out;
 940         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 941         if (err)
 942                 goto out;
 943
 944         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 945         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 946         if (err)
 947                 goto out;
 948         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 949         if (err)
 950                 goto out;
 951
 952         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
 953         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 954         if (err)
 955                 goto out;
 956         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 957         if (err)
 958                 goto out;
 959
 960         if (adev->asic_type == CHIP_KAVERI) {
 961                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
 962                 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 963                 if (err)
 964                         goto out;
 965                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 966                 if (err)
 967                         goto out;
 968         }
 969
 970         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
 971         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 972         if (err)
 973                 goto out;
 974         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 975
 976 out:
 977         if (err) {
 978                 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name);
 979                 release_firmware(adev->gfx.pfp_fw);
 980                 adev->gfx.pfp_fw = NULL;
 981                 release_firmware(adev->gfx.me_fw);
 982                 adev->gfx.me_fw = NULL;
 983                 release_firmware(adev->gfx.ce_fw);
 984                 adev->gfx.ce_fw = NULL;
 985                 release_firmware(adev->gfx.mec_fw);
 986                 adev->gfx.mec_fw = NULL;
 987                 release_firmware(adev->gfx.mec2_fw);
 988                 adev->gfx.mec2_fw = NULL;
 989                 release_firmware(adev->gfx.rlc_fw);
 990                 adev->gfx.rlc_fw = NULL;
 991         }
 992         return err;
 993 }
 994
 995 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
 996 {
 997         release_firmware(adev->gfx.pfp_fw);
 998         adev->gfx.pfp_fw = NULL;
 999         release_firmware(adev->gfx.me_fw);
1000         adev->gfx.me_fw = NULL;
1001         release_firmware(adev->gfx.ce_fw);
1002         adev->gfx.ce_fw = NULL;
1003         release_firmware(adev->gfx.mec_fw);
1004         adev->gfx.mec_fw = NULL;
1005         release_firmware(adev->gfx.mec2_fw);
1006         adev->gfx.mec2_fw = NULL;
1007         release_firmware(adev->gfx.rlc_fw);
1008         adev->gfx.rlc_fw = NULL;
1009 }
1010
1011 /**
1012  * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1013  *
1014  * @adev: amdgpu_device pointer
1015  *
1016  * Starting with SI, the tiling setup is done globally in a
1017  * set of 32 tiling modes.  Rather than selecting each set of
1018  * parameters per surface as on older asics, we just select
1019  * which index in the tiling table we want to use, and the
1020  * surface uses those parameters (CIK).
1021  */
1022 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1023 {
1024         const u32 num_tile_mode_states =
1025                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1026         const u32 num_secondary_tile_mode_states =
1027                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1028         u32 reg_offset, split_equal_to_row_size;
1029         uint32_t *tile, *macrotile;
1030
1031         tile = adev->gfx.config.tile_mode_array;
1032         macrotile = adev->gfx.config.macrotile_mode_array;
1033
1034         switch (adev->gfx.config.mem_row_size_in_kb) {
1035         case 1:
1036                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1037                 break;
1038         case 2:
1039         default:
1040                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1041                 break;
1042         case 4:
1043                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1044                 break;
1045         }
1046
1047         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1048                 tile[reg_offset] = 0;
1049         for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1050                 macrotile[reg_offset] = 0;
1051
1052         switch (adev->asic_type) {
1053         case CHIP_BONAIRE:
1054                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1055                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1056                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1057                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1058                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1059                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1060                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1061                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1062                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1063                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1064                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1065                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1066                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1067                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1068                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1069                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1070                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1072                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1073                            TILE_SPLIT(split_equal_to_row_size));
1074                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1075                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1076                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1077                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1078                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1079                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1080                            TILE_SPLIT(split_equal_to_row_size));
1081                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1082                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1083                            PIPE_CONFIG(ADDR_SURF_P4_16x16));
1084                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1085                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1086                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1087                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1088                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1089                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1090                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1091                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1092                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1093                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1094                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1095                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1096                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1097                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1098                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1099                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1100                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1101                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1102                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1103                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1104                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1105                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1106                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1107                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1108                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1109                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1110                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1111                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1112                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1113                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1114                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1115                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1116                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1117                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1118                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1119                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1120                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1121                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1122                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1123                 tile[21] =  (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1124                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1125                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1126                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1127                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1128                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1129                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1130                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1131                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1132                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1133                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1134                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1135                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1136                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1137                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1138                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1139                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1140                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1141                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1142                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1143                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1144                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1145                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1146                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1147                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1148                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1149                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1150                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1151                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1152                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1153                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1154                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1155                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1156
1157                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1158                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1159                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1160                                 NUM_BANKS(ADDR_SURF_16_BANK));
1161                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1162                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1163                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1164                                 NUM_BANKS(ADDR_SURF_16_BANK));
1165                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1166                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1167                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1168                                 NUM_BANKS(ADDR_SURF_16_BANK));
1169                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1171                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1172                                 NUM_BANKS(ADDR_SURF_16_BANK));
1173                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1174                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1175                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1176                                 NUM_BANKS(ADDR_SURF_16_BANK));
1177                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1178                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1179                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1180                                 NUM_BANKS(ADDR_SURF_8_BANK));
1181                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1182                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1183                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1184                                 NUM_BANKS(ADDR_SURF_4_BANK));
1185                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1186                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1187                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1188                                 NUM_BANKS(ADDR_SURF_16_BANK));
1189                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1190                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1191                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1192                                 NUM_BANKS(ADDR_SURF_16_BANK));
1193                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1194                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1195                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1196                                 NUM_BANKS(ADDR_SURF_16_BANK));
1197                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1198                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1199                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1200                                 NUM_BANKS(ADDR_SURF_16_BANK));
1201                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1202                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1203                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1204                                 NUM_BANKS(ADDR_SURF_16_BANK));
1205                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1206                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1207                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1208                                 NUM_BANKS(ADDR_SURF_8_BANK));
1209                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1210                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1211                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1212                                 NUM_BANKS(ADDR_SURF_4_BANK));
1213
1214                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1215                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1216                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1217                         if (reg_offset != 7)
1218                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1219                 break;
1220         case CHIP_HAWAII:
1221                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1222                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1223                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1224                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1225                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1226                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1227                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1228                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1229                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1230                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1231                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1232                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1233                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1234                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1235                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1236                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1237                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1238                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1239                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1240                            TILE_SPLIT(split_equal_to_row_size));
1241                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1242                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1243                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1244                            TILE_SPLIT(split_equal_to_row_size));
1245                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1246                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1247                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1248                            TILE_SPLIT(split_equal_to_row_size));
1249                 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1250                            PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1251                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1252                            TILE_SPLIT(split_equal_to_row_size));
1253                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1254                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1255                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1256                            PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1257                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1258                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1259                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1260                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1261                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1262                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1263                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1264                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1265                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1266                 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1267                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1268                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1269                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1270                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1271                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1272                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1273                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1274                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1275                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1276                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1277                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1278                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1279                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1280                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1281                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1282                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1283                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1284                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1285                 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1286                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1287                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1288                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1289                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1290                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1291                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1292                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1293                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1294                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1295                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1296                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1297                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1298                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1299                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1300                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1301                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1302                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1303                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1304                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1305                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1306                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1307                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1308                 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1309                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1310                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1311                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1312                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1313                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1314                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1315                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1316                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1317                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1318                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1319                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1320                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1321                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1322                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1323                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1324                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1325                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1326                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1327                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1328                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1329                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1330                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1331                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1332                             PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1333                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1334                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1335                 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1336                             PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1337                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1338                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1339
1340                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1341                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1342                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1343                                 NUM_BANKS(ADDR_SURF_16_BANK));
1344                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1345                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1346                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1347                                 NUM_BANKS(ADDR_SURF_16_BANK));
1348                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1349                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1350                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1351                                 NUM_BANKS(ADDR_SURF_16_BANK));
1352                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1353                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1354                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1355                                 NUM_BANKS(ADDR_SURF_16_BANK));
1356                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1357                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1358                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1359                                 NUM_BANKS(ADDR_SURF_8_BANK));
1360                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1361                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1362                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1363                                 NUM_BANKS(ADDR_SURF_4_BANK));
1364                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1365                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1366                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1367                                 NUM_BANKS(ADDR_SURF_4_BANK));
1368                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1369                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1370                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1371                                 NUM_BANKS(ADDR_SURF_16_BANK));
1372                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1373                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1374                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1375                                 NUM_BANKS(ADDR_SURF_16_BANK));
1376                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1377                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1378                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1379                                 NUM_BANKS(ADDR_SURF_16_BANK));
1380                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1381                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1382                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1383                                 NUM_BANKS(ADDR_SURF_8_BANK));
1384                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1385                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1386                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1387                                 NUM_BANKS(ADDR_SURF_16_BANK));
1388                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1389                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1390                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1391                                 NUM_BANKS(ADDR_SURF_8_BANK));
1392                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1393                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1394                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1395                                 NUM_BANKS(ADDR_SURF_4_BANK));
1396
1397                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1398                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1399                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1400                         if (reg_offset != 7)
1401                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1402                 break;
1403         case CHIP_KABINI:
1404         case CHIP_KAVERI:
1405         case CHIP_MULLINS:
1406         default:
1407                 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1408                            PIPE_CONFIG(ADDR_SURF_P2) |
1409                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1410                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1411                 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1412                            PIPE_CONFIG(ADDR_SURF_P2) |
1413                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1414                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1415                 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1416                            PIPE_CONFIG(ADDR_SURF_P2) |
1417                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1418                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1419                 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1420                            PIPE_CONFIG(ADDR_SURF_P2) |
1421                            TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1422                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1423                 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1424                            PIPE_CONFIG(ADDR_SURF_P2) |
1425                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1426                            TILE_SPLIT(split_equal_to_row_size));
1427                 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1428                            PIPE_CONFIG(ADDR_SURF_P2) |
1429                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1430                 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1431                            PIPE_CONFIG(ADDR_SURF_P2) |
1432                            MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1433                            TILE_SPLIT(split_equal_to_row_size));
1434                 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1435                 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1436                            PIPE_CONFIG(ADDR_SURF_P2));
1437                 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1438                            PIPE_CONFIG(ADDR_SURF_P2) |
1439                            MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1440                 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1441                             PIPE_CONFIG(ADDR_SURF_P2) |
1442                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1443                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1444                 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1445                             PIPE_CONFIG(ADDR_SURF_P2) |
1446                             MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1447                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1448                 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1449                 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1450                             PIPE_CONFIG(ADDR_SURF_P2) |
1451                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1452                 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1453                             PIPE_CONFIG(ADDR_SURF_P2) |
1454                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1455                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1456                 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1457                             PIPE_CONFIG(ADDR_SURF_P2) |
1458                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1459                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1460                 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1461                             PIPE_CONFIG(ADDR_SURF_P2) |
1462                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1463                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1464                 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1465                 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1466                             PIPE_CONFIG(ADDR_SURF_P2) |
1467                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1468                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1469                 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1470                             PIPE_CONFIG(ADDR_SURF_P2) |
1471                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1472                 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1473                             PIPE_CONFIG(ADDR_SURF_P2) |
1474                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1475                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1476                 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1477                             PIPE_CONFIG(ADDR_SURF_P2) |
1478                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1479                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1480                 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1481                             PIPE_CONFIG(ADDR_SURF_P2) |
1482                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1483                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1484                 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1485                 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1486                             PIPE_CONFIG(ADDR_SURF_P2) |
1487                             MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1488                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1489                 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1490                             PIPE_CONFIG(ADDR_SURF_P2) |
1491                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1492                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1493                 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1494                             PIPE_CONFIG(ADDR_SURF_P2) |
1495                             MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1496                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1497                 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1498                             PIPE_CONFIG(ADDR_SURF_P2) |
1499                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1500                 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1501                             PIPE_CONFIG(ADDR_SURF_P2) |
1502                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1503                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1504                 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1505                             PIPE_CONFIG(ADDR_SURF_P2) |
1506                             MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1507                             SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1508                 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1509
1510                 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1511                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1512                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1513                                 NUM_BANKS(ADDR_SURF_8_BANK));
1514                 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1515                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1516                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1517                                 NUM_BANKS(ADDR_SURF_8_BANK));
1518                 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1519                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1520                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1521                                 NUM_BANKS(ADDR_SURF_8_BANK));
1522                 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1523                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1524                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1525                                 NUM_BANKS(ADDR_SURF_8_BANK));
1526                 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1527                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1528                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1529                                 NUM_BANKS(ADDR_SURF_8_BANK));
1530                 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1531                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1532                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1533                                 NUM_BANKS(ADDR_SURF_8_BANK));
1534                 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1535                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1536                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1537                                 NUM_BANKS(ADDR_SURF_8_BANK));
1538                 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1539                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1540                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1541                                 NUM_BANKS(ADDR_SURF_16_BANK));
1542                 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1543                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1544                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1545                                 NUM_BANKS(ADDR_SURF_16_BANK));
1546                 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1547                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1548                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1549                                 NUM_BANKS(ADDR_SURF_16_BANK));
1550                 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1551                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1552                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1553                                 NUM_BANKS(ADDR_SURF_16_BANK));
1554                 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1555                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1556                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1557                                 NUM_BANKS(ADDR_SURF_16_BANK));
1558                 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1559                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1560                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1561                                 NUM_BANKS(ADDR_SURF_16_BANK));
1562                 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1563                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1564                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1565                                 NUM_BANKS(ADDR_SURF_8_BANK));
1566
1567                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1568                         WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1569                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1570                         if (reg_offset != 7)
1571                                 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1572                 break;
1573         }
1574 }
1575
1576 /**
1577  * gfx_v7_0_select_se_sh - select which SE, SH to address
1578  *
1579  * @adev: amdgpu_device pointer
1580  * @se_num: shader engine to address
1581  * @sh_num: sh block to address
1582  *
1583  * Select which SE, SH combinations to address. Certain
1584  * registers are instanced per SE or SH.  0xffffffff means
1585  * broadcast to all SEs or SHs (CIK).
1586  */
1587 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
1588                                   u32 se_num, u32 sh_num, u32 instance)
1589 {
1590         u32 data;
1591
1592         if (instance == 0xffffffff)
1593                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1594         else
1595                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1596
1597         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1598                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1599                         GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1600         else if (se_num == 0xffffffff)
1601                 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1602                         (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1603         else if (sh_num == 0xffffffff)
1604                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1605                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1606         else
1607                 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1608                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1609         WREG32(mmGRBM_GFX_INDEX, data);
1610 }
1611
1612 /**
1613  * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1614  *
1615  * @adev: amdgpu_device pointer
1616  *
1617  * Calculates the bitmask of enabled RBs (CIK).
1618  * Returns the enabled RB bitmask.
1619  */
1620 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1621 {
1622         u32 data, mask;
1623
1624         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1625         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1626
1627         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1628         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1629
1630         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1631                                          adev->gfx.config.max_sh_per_se);
1632
1633         return (~data) & mask;
1634 }
1635
1636 static void
1637 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1638 {
1639         switch (adev->asic_type) {
1640         case CHIP_BONAIRE:
1641                 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1642                           SE_XSEL(1) | SE_YSEL(1);
1643                 *rconf1 |= 0x0;
1644                 break;
1645         case CHIP_HAWAII:
1646                 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1647                           RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1648                           PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1649                           SE_YSEL(3);
1650                 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1651                            SE_PAIR_YSEL(2);
1652                 break;
1653         case CHIP_KAVERI:
1654                 *rconf |= RB_MAP_PKR0(2);
1655                 *rconf1 |= 0x0;
1656                 break;
1657         case CHIP_KABINI:
1658         case CHIP_MULLINS:
1659                 *rconf |= 0x0;
1660                 *rconf1 |= 0x0;
1661                 break;
1662         default:
1663                 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1664                 break;
1665         }
1666 }
1667
1668 static void
1669 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1670                                         u32 raster_config, u32 raster_config_1,
1671                                         unsigned rb_mask, unsigned num_rb)
1672 {
1673         unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1674         unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1675         unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1676         unsigned rb_per_se = num_rb / num_se;
1677         unsigned se_mask[4];
1678         unsigned se;
1679
1680         se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1681         se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1682         se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1683         se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1684
1685         WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1686         WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1687         WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1688
1689         if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1690                              (!se_mask[2] && !se_mask[3]))) {
1691                 raster_config_1 &= ~SE_PAIR_MAP_MASK;
1692
1693                 if (!se_mask[0] && !se_mask[1]) {
1694                         raster_config_1 |=
1695                                 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1696                 } else {
1697                         raster_config_1 |=
1698                                 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1699                 }
1700         }
1701
1702         for (se = 0; se < num_se; se++) {
1703                 unsigned raster_config_se = raster_config;
1704                 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1705                 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1706                 int idx = (se / 2) * 2;
1707
1708                 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1709                         raster_config_se &= ~SE_MAP_MASK;
1710
1711                         if (!se_mask[idx]) {
1712                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1713                         } else {
1714                                 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1715                         }
1716                 }
1717
1718                 pkr0_mask &= rb_mask;
1719                 pkr1_mask &= rb_mask;
1720                 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1721                         raster_config_se &= ~PKR_MAP_MASK;
1722
1723                         if (!pkr0_mask) {
1724                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1725                         } else {
1726                                 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1727                         }
1728                 }
1729
1730                 if (rb_per_se >= 2) {
1731                         unsigned rb0_mask = 1 << (se * rb_per_se);
1732                         unsigned rb1_mask = rb0_mask << 1;
1733
1734                         rb0_mask &= rb_mask;
1735                         rb1_mask &= rb_mask;
1736                         if (!rb0_mask || !rb1_mask) {
1737                                 raster_config_se &= ~RB_MAP_PKR0_MASK;
1738
1739                                 if (!rb0_mask) {
1740                                         raster_config_se |=
1741                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1742                                 } else {
1743                                         raster_config_se |=
1744                                                 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1745                                 }
1746                         }
1747
1748                         if (rb_per_se > 2) {
1749                                 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1750                                 rb1_mask = rb0_mask << 1;
1751                                 rb0_mask &= rb_mask;
1752                                 rb1_mask &= rb_mask;
1753                                 if (!rb0_mask || !rb1_mask) {
1754                                         raster_config_se &= ~RB_MAP_PKR1_MASK;
1755
1756                                         if (!rb0_mask) {
1757                                                 raster_config_se |=
1758                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1759                                         } else {
1760                                                 raster_config_se |=
1761                                                         RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1762                                         }
1763                                 }
1764                         }
1765                 }
1766
1767                 /* GRBM_GFX_INDEX has a different offset on CI+ */
1768                 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1769                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1770                 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1771         }
1772
1773         /* GRBM_GFX_INDEX has a different offset on CI+ */
1774         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1775 }
1776
1777 /**
1778  * gfx_v7_0_setup_rb - setup the RBs on the asic
1779  *
1780  * @adev: amdgpu_device pointer
1781  * @se_num: number of SEs (shader engines) for the asic
1782  * @sh_per_se: number of SH blocks per SE for the asic
1783  *
1784  * Configures per-SE/SH RB registers (CIK).
1785  */
1786 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1787 {
1788         int i, j;
1789         u32 data;
1790         u32 raster_config = 0, raster_config_1 = 0;
1791         u32 active_rbs = 0;
1792         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1793                                         adev->gfx.config.max_sh_per_se;
1794         unsigned num_rb_pipes;
1795
1796         mutex_lock(&adev->grbm_idx_mutex);
1797         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1798                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1799                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1800                         data = gfx_v7_0_get_rb_active_bitmap(adev);
1801                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1802                                                rb_bitmap_width_per_sh);
1803                 }
1804         }
1805         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1806
1807         adev->gfx.config.backend_enable_mask = active_rbs;
1808         adev->gfx.config.num_rbs = hweight32(active_rbs);
1809
1810         num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1811                              adev->gfx.config.max_shader_engines, 16);
1812
1813         gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1814
1815         if (!adev->gfx.config.backend_enable_mask ||
1816                         adev->gfx.config.num_rbs >= num_rb_pipes) {
1817                 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1818                 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1819         } else {
1820                 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1821                                                         adev->gfx.config.backend_enable_mask,
1822                                                         num_rb_pipes);
1823         }
1824
1825         /* cache the values for userspace */
1826         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1827                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1828                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1829                         adev->gfx.config.rb_config[i][j].rb_backend_disable =
1830                                 RREG32(mmCC_RB_BACKEND_DISABLE);
1831                         adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1832                                 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1833                         adev->gfx.config.rb_config[i][j].raster_config =
1834                                 RREG32(mmPA_SC_RASTER_CONFIG);
1835                         adev->gfx.config.rb_config[i][j].raster_config_1 =
1836                                 RREG32(mmPA_SC_RASTER_CONFIG_1);
1837                 }
1838         }
1839         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1840         mutex_unlock(&adev->grbm_idx_mutex);
1841 }
1842
1843 /**
1844  * gfx_v7_0_init_compute_vmid - gart enable
1845  *
1846  * @adev: amdgpu_device pointer
1847  *
1848  * Initialize compute vmid sh_mem registers
1849  *
1850  */
1851 #define DEFAULT_SH_MEM_BASES    (0x6000)
1852 #define FIRST_COMPUTE_VMID      (8)
1853 #define LAST_COMPUTE_VMID       (16)
1854 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1855 {
1856         int i;
1857         uint32_t sh_mem_config;
1858         uint32_t sh_mem_bases;
1859
1860         /*
1861          * Configure apertures:
1862          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1863          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1864          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1865         */
1866         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1867         sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1868                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1869         sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1870         mutex_lock(&adev->srbm_mutex);
1871         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1872                 cik_srbm_select(adev, 0, 0, 0, i);
1873                 /* CP and shaders */
1874                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1875                 WREG32(mmSH_MEM_APE1_BASE, 1);
1876                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1877                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1878         }
1879         cik_srbm_select(adev, 0, 0, 0, 0);
1880         mutex_unlock(&adev->srbm_mutex);
1881 }
1882
1883 static void gfx_v7_0_config_init(struct amdgpu_device *adev)
1884 {
1885         adev->gfx.config.double_offchip_lds_buf = 1;
1886 }
1887
1888 /**
1889  * gfx_v7_0_gpu_init - setup the 3D engine
1890  *
1891  * @adev: amdgpu_device pointer
1892  *
1893  * Configures the 3D engine and tiling configuration
1894  * registers so that the 3D engine is usable.
1895  */
1896 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1897 {
1898         u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
1899         u32 tmp;
1900         int i;
1901
1902         WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1903
1904         WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1905         WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1906         WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1907
1908         gfx_v7_0_tiling_mode_table_init(adev);
1909
1910         gfx_v7_0_setup_rb(adev);
1911         gfx_v7_0_get_cu_info(adev);
1912         gfx_v7_0_config_init(adev);
1913
1914         /* set HW defaults for 3D engine */
1915         WREG32(mmCP_MEQ_THRESHOLDS,
1916                (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1917                (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1918
1919         mutex_lock(&adev->grbm_idx_mutex);
1920         /*
1921          * making sure that the following register writes will be broadcasted
1922          * to all the shaders
1923          */
1924         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1925
1926         /* XXX SH_MEM regs */
1927         /* where to put LDS, scratch, GPUVM in FSA64 space */
1928         sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1929                                    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1930         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
1931                                    MTYPE_NC);
1932         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
1933                                    MTYPE_UC);
1934         sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
1935
1936         sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
1937                                    SWIZZLE_ENABLE, 1);
1938         sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1939                                    ELEMENT_SIZE, 1);
1940         sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1941                                    INDEX_STRIDE, 3);
1942         WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
1943
1944         mutex_lock(&adev->srbm_mutex);
1945         for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
1946                 if (i == 0)
1947                         sh_mem_base = 0;
1948                 else
1949                         sh_mem_base = adev->mc.shared_aperture_start >> 48;
1950                 cik_srbm_select(adev, 0, 0, 0, i);
1951                 /* CP and shaders */
1952                 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1953                 WREG32(mmSH_MEM_APE1_BASE, 1);
1954                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1955                 WREG32(mmSH_MEM_BASES, sh_mem_base);
1956         }
1957         cik_srbm_select(adev, 0, 0, 0, 0);
1958         mutex_unlock(&adev->srbm_mutex);
1959
1960         gfx_v7_0_init_compute_vmid(adev);
1961
1962         WREG32(mmSX_DEBUG_1, 0x20);
1963
1964         WREG32(mmTA_CNTL_AUX, 0x00010000);
1965
1966         tmp = RREG32(mmSPI_CONFIG_CNTL);
1967         tmp |= 0x03000000;
1968         WREG32(mmSPI_CONFIG_CNTL, tmp);
1969
1970         WREG32(mmSQ_CONFIG, 1);
1971
1972         WREG32(mmDB_DEBUG, 0);
1973
1974         tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1975         tmp |= 0x00000400;
1976         WREG32(mmDB_DEBUG2, tmp);
1977
1978         tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1979         tmp |= 0x00020200;
1980         WREG32(mmDB_DEBUG3, tmp);
1981
1982         tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1983         tmp |= 0x00018208;
1984         WREG32(mmCB_HW_CONTROL, tmp);
1985
1986         WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1987
1988         WREG32(mmPA_SC_FIFO_SIZE,
1989                 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1990                 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1991                 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1992                 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1993
1994         WREG32(mmVGT_NUM_INSTANCES, 1);
1995
1996         WREG32(mmCP_PERFMON_CNTL, 0);
1997
1998         WREG32(mmSQ_CONFIG, 0);
1999
2000         WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
2001                 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
2002                 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
2003
2004         WREG32(mmVGT_CACHE_INVALIDATION,
2005                 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
2006                 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
2007
2008         WREG32(mmVGT_GS_VERTEX_REUSE, 16);
2009         WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
2010
2011         WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
2012                         (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
2013         WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
2014
2015         tmp = RREG32(mmSPI_ARB_PRIORITY);
2016         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
2017         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
2018         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
2019         tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
2020         WREG32(mmSPI_ARB_PRIORITY, tmp);
2021
2022         mutex_unlock(&adev->grbm_idx_mutex);
2023
2024         udelay(50);
2025 }
2026
2027 /*
2028  * GPU scratch registers helpers function.
2029  */
2030 /**
2031  * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
2032  *
2033  * @adev: amdgpu_device pointer
2034  *
2035  * Set up the number and offset of the CP scratch registers.
2036  * NOTE: use of CP scratch registers is a legacy inferface and
2037  * is not used by default on newer asics (r6xx+).  On newer asics,
2038  * memory buffers are used for fences rather than scratch regs.
2039  */
2040 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
2041 {
2042         adev->gfx.scratch.num_reg = 8;
2043         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
2044         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
2045 }
2046
2047 /**
2048  * gfx_v7_0_ring_test_ring - basic gfx ring test
2049  *
2050  * @adev: amdgpu_device pointer
2051  * @ring: amdgpu_ring structure holding ring information
2052  *
2053  * Allocate a scratch register and write to it using the gfx ring (CIK).
2054  * Provides a basic gfx ring test to verify that the ring is working.
2055  * Used by gfx_v7_0_cp_gfx_resume();
2056  * Returns 0 on success, error on failure.
2057  */
2058 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2059 {
2060         struct amdgpu_device *adev = ring->adev;
2061         uint32_t scratch;
2062         uint32_t tmp = 0;
2063         unsigned i;
2064         int r;
2065
2066         r = amdgpu_gfx_scratch_get(adev, &scratch);
2067         if (r) {
2068                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
2069                 return r;
2070         }
2071         WREG32(scratch, 0xCAFEDEAD);
2072         r = amdgpu_ring_alloc(ring, 3);
2073         if (r) {
2074                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
2075                 amdgpu_gfx_scratch_free(adev, scratch);
2076                 return r;
2077         }
2078         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2079         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2080         amdgpu_ring_write(ring, 0xDEADBEEF);
2081         amdgpu_ring_commit(ring);
2082
2083         for (i = 0; i < adev->usec_timeout; i++) {
2084                 tmp = RREG32(scratch);
2085                 if (tmp == 0xDEADBEEF)
2086                         break;
2087                 DRM_UDELAY(1);
2088         }
2089         if (i < adev->usec_timeout) {
2090                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2091         } else {
2092                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2093                           ring->idx, scratch, tmp);
2094                 r = -EINVAL;
2095         }
2096         amdgpu_gfx_scratch_free(adev, scratch);
2097         return r;
2098 }
2099
2100 /**
2101  * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
2102  *
2103  * @adev: amdgpu_device pointer
2104  * @ridx: amdgpu ring index
2105  *
2106  * Emits an hdp flush on the cp.
2107  */
2108 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2109 {
2110         u32 ref_and_mask;
2111         int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
2112
2113         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2114                 switch (ring->me) {
2115                 case 1:
2116                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2117                         break;
2118                 case 2:
2119                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2120                         break;
2121                 default:
2122                         return;
2123                 }
2124         } else {
2125                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2126         }
2127
2128         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2129         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2130                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
2131                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
2132         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2133         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2134         amdgpu_ring_write(ring, ref_and_mask);
2135         amdgpu_ring_write(ring, ref_and_mask);
2136         amdgpu_ring_write(ring, 0x20); /* poll interval */
2137 }
2138
2139 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2140 {
2141         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2142         amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2143                 EVENT_INDEX(4));
2144
2145         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2146         amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2147                 EVENT_INDEX(0));
2148 }
2149
2150
2151 /**
2152  * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
2153  *
2154  * @adev: amdgpu_device pointer
2155  * @ridx: amdgpu ring index
2156  *
2157  * Emits an hdp invalidate on the cp.
2158  */
2159 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2160 {
2161         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2162         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2163                                  WRITE_DATA_DST_SEL(0) |
2164                                  WR_CONFIRM));
2165         amdgpu_ring_write(ring, mmHDP_DEBUG0);
2166         amdgpu_ring_write(ring, 0);
2167         amdgpu_ring_write(ring, 1);
2168 }
2169
2170 /**
2171  * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2172  *
2173  * @adev: amdgpu_device pointer
2174  * @fence: amdgpu fence object
2175  *
2176  * Emits a fence sequnce number on the gfx ring and flushes
2177  * GPU caches.
2178  */
2179 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2180                                          u64 seq, unsigned flags)
2181 {
2182         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2183         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2184         /* Workaround for cache flush problems. First send a dummy EOP
2185          * event down the pipe with seq one below.
2186          */
2187         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2188         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2189                                  EOP_TC_ACTION_EN |
2190                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2191                                  EVENT_INDEX(5)));
2192         amdgpu_ring_write(ring, addr & 0xfffffffc);
2193         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2194                                 DATA_SEL(1) | INT_SEL(0));
2195         amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2196         amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2197
2198         /* Then send the real EOP event down the pipe. */
2199         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2200         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2201                                  EOP_TC_ACTION_EN |
2202                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2203                                  EVENT_INDEX(5)));
2204         amdgpu_ring_write(ring, addr & 0xfffffffc);
2205         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2206                                 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2207         amdgpu_ring_write(ring, lower_32_bits(seq));
2208         amdgpu_ring_write(ring, upper_32_bits(seq));
2209 }
2210
2211 /**
2212  * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2213  *
2214  * @adev: amdgpu_device pointer
2215  * @fence: amdgpu fence object
2216  *
2217  * Emits a fence sequnce number on the compute ring and flushes
2218  * GPU caches.
2219  */
2220 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2221                                              u64 addr, u64 seq,
2222                                              unsigned flags)
2223 {
2224         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2225         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2226
2227         /* RELEASE_MEM - flush caches, send int */
2228         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2229         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2230                                  EOP_TC_ACTION_EN |
2231                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2232                                  EVENT_INDEX(5)));
2233         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2234         amdgpu_ring_write(ring, addr & 0xfffffffc);
2235         amdgpu_ring_write(ring, upper_32_bits(addr));
2236         amdgpu_ring_write(ring, lower_32_bits(seq));
2237         amdgpu_ring_write(ring, upper_32_bits(seq));
2238 }
2239
2240 /*
2241  * IB stuff
2242  */
2243 /**
2244  * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2245  *
2246  * @ring: amdgpu_ring structure holding ring information
2247  * @ib: amdgpu indirect buffer object
2248  *
2249  * Emits an DE (drawing engine) or CE (constant engine) IB
2250  * on the gfx ring.  IBs are usually generated by userspace
2251  * acceleration drivers and submitted to the kernel for
2252  * sheduling on the ring.  This function schedules the IB
2253  * on the gfx ring for execution by the GPU.
2254  */
2255 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2256                                       struct amdgpu_ib *ib,
2257                                       unsigned vmid, bool ctx_switch)
2258 {
2259         u32 header, control = 0;
2260
2261         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2262         if (ctx_switch) {
2263                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2264                 amdgpu_ring_write(ring, 0);
2265         }
2266
2267         if (ib->flags & AMDGPU_IB_FLAG_CE)
2268                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2269         else
2270                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2271
2272         control |= ib->length_dw | (vmid << 24);
2273
2274         amdgpu_ring_write(ring, header);
2275         amdgpu_ring_write(ring,
2276 #ifdef __BIG_ENDIAN
2277                           (2 << 0) |
2278 #endif
2279                           (ib->gpu_addr & 0xFFFFFFFC));
2280         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2281         amdgpu_ring_write(ring, control);
2282 }
2283
2284 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2285                                           struct amdgpu_ib *ib,
2286                                           unsigned vmid, bool ctx_switch)
2287 {
2288         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2289
2290         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2291         amdgpu_ring_write(ring,
2292 #ifdef __BIG_ENDIAN
2293                                           (2 << 0) |
2294 #endif
2295                                           (ib->gpu_addr & 0xFFFFFFFC));
2296         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2297         amdgpu_ring_write(ring, control);
2298 }
2299
2300 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2301 {
2302         uint32_t dw2 = 0;
2303
2304         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2305         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2306                 gfx_v7_0_ring_emit_vgt_flush(ring);
2307                 /* set load_global_config & load_global_uconfig */
2308                 dw2 |= 0x8001;
2309                 /* set load_cs_sh_regs */
2310                 dw2 |= 0x01000000;
2311                 /* set load_per_context_state & load_gfx_sh_regs */
2312                 dw2 |= 0x10002;
2313         }
2314
2315         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2316         amdgpu_ring_write(ring, dw2);
2317         amdgpu_ring_write(ring, 0);
2318 }
2319
2320 /**
2321  * gfx_v7_0_ring_test_ib - basic ring IB test
2322  *
2323  * @ring: amdgpu_ring structure holding ring information
2324  *
2325  * Allocate an IB and execute it on the gfx ring (CIK).
2326  * Provides a basic gfx ring test to verify that IBs are working.
2327  * Returns 0 on success, error on failure.
2328  */
2329 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
2330 {
2331         struct amdgpu_device *adev = ring->adev;
2332         struct amdgpu_ib ib;
2333         struct dma_fence *f = NULL;
2334         uint32_t scratch;
2335         uint32_t tmp = 0;
2336         long r;
2337
2338         r = amdgpu_gfx_scratch_get(adev, &scratch);
2339         if (r) {
2340                 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
2341                 return r;
2342         }
2343         WREG32(scratch, 0xCAFEDEAD);
2344         memset(&ib, 0, sizeof(ib));
2345         r = amdgpu_ib_get(adev, NULL, 256, &ib);
2346         if (r) {
2347                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
2348                 goto err1;
2349         }
2350         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2351         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2352         ib.ptr[2] = 0xDEADBEEF;
2353         ib.length_dw = 3;
2354
2355         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
2356         if (r)
2357                 goto err2;
2358
2359         r = dma_fence_wait_timeout(f, false, timeout);
2360         if (r == 0) {
2361                 DRM_ERROR("amdgpu: IB test timed out\n");
2362                 r = -ETIMEDOUT;
2363                 goto err2;
2364         } else if (r < 0) {
2365                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
2366                 goto err2;
2367         }
2368         tmp = RREG32(scratch);
2369         if (tmp == 0xDEADBEEF) {
2370                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
2371                 r = 0;
2372         } else {
2373                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2374                           scratch, tmp);
2375                 r = -EINVAL;
2376         }
2377
2378 err2:
2379         amdgpu_ib_free(adev, &ib, NULL);
2380         dma_fence_put(f);
2381 err1:
2382         amdgpu_gfx_scratch_free(adev, scratch);
2383         return r;
2384 }
2385
2386 /*
2387  * CP.
2388  * On CIK, gfx and compute now have independant command processors.
2389  *
2390  * GFX
2391  * Gfx consists of a single ring and can process both gfx jobs and
2392  * compute jobs.  The gfx CP consists of three microengines (ME):
2393  * PFP - Pre-Fetch Parser
2394  * ME - Micro Engine
2395  * CE - Constant Engine
2396  * The PFP and ME make up what is considered the Drawing Engine (DE).
2397  * The CE is an asynchronous engine used for updating buffer desciptors
2398  * used by the DE so that they can be loaded into cache in parallel
2399  * while the DE is processing state update packets.
2400  *
2401  * Compute
2402  * The compute CP consists of two microengines (ME):
2403  * MEC1 - Compute MicroEngine 1
2404  * MEC2 - Compute MicroEngine 2
2405  * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2406  * The queues are exposed to userspace and are programmed directly
2407  * by the compute runtime.
2408  */
2409 /**
2410  * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2411  *
2412  * @adev: amdgpu_device pointer
2413  * @enable: enable or disable the MEs
2414  *
2415  * Halts or unhalts the gfx MEs.
2416  */
2417 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2418 {
2419         int i;
2420
2421         if (enable) {
2422                 WREG32(mmCP_ME_CNTL, 0);
2423         } else {
2424                 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2425                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2426                         adev->gfx.gfx_ring[i].ready = false;
2427         }
2428         udelay(50);
2429 }
2430
2431 /**
2432  * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2433  *
2434  * @adev: amdgpu_device pointer
2435  *
2436  * Loads the gfx PFP, ME, and CE ucode.
2437  * Returns 0 for success, -EINVAL if the ucode is not available.
2438  */
2439 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2440 {
2441         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2442         const struct gfx_firmware_header_v1_0 *ce_hdr;
2443         const struct gfx_firmware_header_v1_0 *me_hdr;
2444         const __le32 *fw_data;
2445         unsigned i, fw_size;
2446
2447         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2448                 return -EINVAL;
2449
2450         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2451         ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2452         me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2453
2454         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2455         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2456         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2457         adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2458         adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2459         adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2460         adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2461         adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2462         adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2463
2464         gfx_v7_0_cp_gfx_enable(adev, false);
2465
2466         /* PFP */
2467         fw_data = (const __le32 *)
2468                 (adev->gfx.pfp_fw->data +
2469                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2470         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2471         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2472         for (i = 0; i < fw_size; i++)
2473                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2474         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2475
2476         /* CE */
2477         fw_data = (const __le32 *)
2478                 (adev->gfx.ce_fw->data +
2479                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2480         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2481         WREG32(mmCP_CE_UCODE_ADDR, 0);
2482         for (i = 0; i < fw_size; i++)
2483                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2484         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2485
2486         /* ME */
2487         fw_data = (const __le32 *)
2488                 (adev->gfx.me_fw->data +
2489                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2490         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2491         WREG32(mmCP_ME_RAM_WADDR, 0);
2492         for (i = 0; i < fw_size; i++)
2493                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2494         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2495
2496         return 0;
2497 }
2498
2499 /**
2500  * gfx_v7_0_cp_gfx_start - start the gfx ring
2501  *
2502  * @adev: amdgpu_device pointer
2503  *
2504  * Enables the ring and loads the clear state context and other
2505  * packets required to init the ring.
2506  * Returns 0 for success, error for failure.
2507  */
2508 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2509 {
2510         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2511         const struct cs_section_def *sect = NULL;
2512         const struct cs_extent_def *ext = NULL;
2513         int r, i;
2514
2515         /* init the CP */
2516         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2517         WREG32(mmCP_ENDIAN_SWAP, 0);
2518         WREG32(mmCP_DEVICE_ID, 1);
2519
2520         gfx_v7_0_cp_gfx_enable(adev, true);
2521
2522         r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2523         if (r) {
2524                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2525                 return r;
2526         }
2527
2528         /* init the CE partitions.  CE only used for gfx on CIK */
2529         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2530         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2531         amdgpu_ring_write(ring, 0x8000);
2532         amdgpu_ring_write(ring, 0x8000);
2533
2534         /* clear state buffer */
2535         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2536         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2537
2538         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2539         amdgpu_ring_write(ring, 0x80000000);
2540         amdgpu_ring_write(ring, 0x80000000);
2541
2542         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2543                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2544                         if (sect->id == SECT_CONTEXT) {
2545                                 amdgpu_ring_write(ring,
2546                                                   PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2547                                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2548                                 for (i = 0; i < ext->reg_count; i++)
2549                                         amdgpu_ring_write(ring, ext->extent[i]);
2550                         }
2551                 }
2552         }
2553
2554         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2555         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2556         amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
2557         amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
2558
2559         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2560         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2561
2562         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2563         amdgpu_ring_write(ring, 0);
2564
2565         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2566         amdgpu_ring_write(ring, 0x00000316);
2567         amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2568         amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2569
2570         amdgpu_ring_commit(ring);
2571
2572         return 0;
2573 }
2574
2575 /**
2576  * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2577  *
2578  * @adev: amdgpu_device pointer
2579  *
2580  * Program the location and size of the gfx ring buffer
2581  * and test it to make sure it's working.
2582  * Returns 0 for success, error for failure.
2583  */
2584 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2585 {
2586         struct amdgpu_ring *ring;
2587         u32 tmp;
2588         u32 rb_bufsz;
2589         u64 rb_addr, rptr_addr;
2590         int r;
2591
2592         WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2593         if (adev->asic_type != CHIP_HAWAII)
2594                 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2595
2596         /* Set the write pointer delay */
2597         WREG32(mmCP_RB_WPTR_DELAY, 0);
2598
2599         /* set the RB to use vmid 0 */
2600         WREG32(mmCP_RB_VMID, 0);
2601
2602         WREG32(mmSCRATCH_ADDR, 0);
2603
2604         /* ring 0 - compute and gfx */
2605         /* Set ring buffer size */
2606         ring = &adev->gfx.gfx_ring[0];
2607         rb_bufsz = order_base_2(ring->ring_size / 8);
2608         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2609 #ifdef __BIG_ENDIAN
2610         tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2611 #endif
2612         WREG32(mmCP_RB0_CNTL, tmp);
2613
2614         /* Initialize the ring buffer's read and write pointers */
2615         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2616         ring->wptr = 0;
2617         WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2618
2619         /* set the wb address wether it's enabled or not */
2620         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2621         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2622         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2623
2624         /* scratch register shadowing is no longer supported */
2625         WREG32(mmSCRATCH_UMSK, 0);
2626
2627         mdelay(1);
2628         WREG32(mmCP_RB0_CNTL, tmp);
2629
2630         rb_addr = ring->gpu_addr >> 8;
2631         WREG32(mmCP_RB0_BASE, rb_addr);
2632         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2633
2634         /* start the ring */
2635         gfx_v7_0_cp_gfx_start(adev);
2636         ring->ready = true;
2637         r = amdgpu_ring_test_ring(ring);
2638         if (r) {
2639                 ring->ready = false;
2640                 return r;
2641         }
2642
2643         return 0;
2644 }
2645
2646 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
2647 {
2648         return ring->adev->wb.wb[ring->rptr_offs];
2649 }
2650
2651 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2652 {
2653         struct amdgpu_device *adev = ring->adev;
2654
2655         return RREG32(mmCP_RB0_WPTR);
2656 }
2657
2658 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2659 {
2660         struct amdgpu_device *adev = ring->adev;
2661
2662         WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2663         (void)RREG32(mmCP_RB0_WPTR);
2664 }
2665
2666 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2667 {
2668         /* XXX check if swapping is necessary on BE */
2669         return ring->adev->wb.wb[ring->wptr_offs];
2670 }
2671
2672 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2673 {
2674         struct amdgpu_device *adev = ring->adev;
2675
2676         /* XXX check if swapping is necessary on BE */
2677         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2678         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2679 }
2680
2681 /**
2682  * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2683  *
2684  * @adev: amdgpu_device pointer
2685  * @enable: enable or disable the MEs
2686  *
2687  * Halts or unhalts the compute MEs.
2688  */
2689 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2690 {
2691         int i;
2692
2693         if (enable) {
2694                 WREG32(mmCP_MEC_CNTL, 0);
2695         } else {
2696                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2697                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2698                         adev->gfx.compute_ring[i].ready = false;
2699         }
2700         udelay(50);
2701 }
2702
2703 /**
2704  * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2705  *
2706  * @adev: amdgpu_device pointer
2707  *
2708  * Loads the compute MEC1&2 ucode.
2709  * Returns 0 for success, -EINVAL if the ucode is not available.
2710  */
2711 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2712 {
2713         const struct gfx_firmware_header_v1_0 *mec_hdr;
2714         const __le32 *fw_data;
2715         unsigned i, fw_size;
2716
2717         if (!adev->gfx.mec_fw)
2718                 return -EINVAL;
2719
2720         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2721         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2722         adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2723         adev->gfx.mec_feature_version = le32_to_cpu(
2724                                         mec_hdr->ucode_feature_version);
2725
2726         gfx_v7_0_cp_compute_enable(adev, false);
2727
2728         /* MEC1 */
2729         fw_data = (const __le32 *)
2730                 (adev->gfx.mec_fw->data +
2731                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2732         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2733         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2734         for (i = 0; i < fw_size; i++)
2735                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2736         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2737
2738         if (adev->asic_type == CHIP_KAVERI) {
2739                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2740
2741                 if (!adev->gfx.mec2_fw)
2742                         return -EINVAL;
2743
2744                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2745                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2746                 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2747                 adev->gfx.mec2_feature_version = le32_to_cpu(
2748                                 mec2_hdr->ucode_feature_version);
2749
2750                 /* MEC2 */
2751                 fw_data = (const __le32 *)
2752                         (adev->gfx.mec2_fw->data +
2753                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2754                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2755                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2756                 for (i = 0; i < fw_size; i++)
2757                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2758                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2759         }
2760
2761         return 0;
2762 }
2763
2764 /**
2765  * gfx_v7_0_cp_compute_fini - stop the compute queues
2766  *
2767  * @adev: amdgpu_device pointer
2768  *
2769  * Stop the compute queues and tear down the driver queue
2770  * info.
2771  */
2772 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2773 {
2774         int i;
2775
2776         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2777                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2778
2779                 amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL);
2780         }
2781 }
2782
2783 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2784 {
2785         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
2786 }
2787
2788 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2789 {
2790         int r;
2791         u32 *hpd;
2792         size_t mec_hpd_size;
2793
2794         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2795
2796         /* take ownership of the relevant compute queues */
2797         amdgpu_gfx_compute_queue_acquire(adev);
2798
2799         /* allocate space for ALL pipes (even the ones we don't own) */
2800         mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec
2801                 * GFX7_MEC_HPD_SIZE * 2;
2802
2803         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
2804                                       AMDGPU_GEM_DOMAIN_GTT,
2805                                       &adev->gfx.mec.hpd_eop_obj,
2806                                       &adev->gfx.mec.hpd_eop_gpu_addr,
2807                                       (void **)&hpd);
2808         if (r) {
2809                 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r);
2810                 gfx_v7_0_mec_fini(adev);
2811                 return r;
2812         }
2813
2814         /* clear memory.  Not sure if this is required or not */
2815         memset(hpd, 0, mec_hpd_size);
2816
2817         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2818         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2819
2820         return 0;
2821 }
2822
2823 struct hqd_registers
2824 {
2825         u32 cp_mqd_base_addr;
2826         u32 cp_mqd_base_addr_hi;
2827         u32 cp_hqd_active;
2828         u32 cp_hqd_vmid;
2829         u32 cp_hqd_persistent_state;
2830         u32 cp_hqd_pipe_priority;
2831         u32 cp_hqd_queue_priority;
2832         u32 cp_hqd_quantum;
2833         u32 cp_hqd_pq_base;
2834         u32 cp_hqd_pq_base_hi;
2835         u32 cp_hqd_pq_rptr;
2836         u32 cp_hqd_pq_rptr_report_addr;
2837         u32 cp_hqd_pq_rptr_report_addr_hi;
2838         u32 cp_hqd_pq_wptr_poll_addr;
2839         u32 cp_hqd_pq_wptr_poll_addr_hi;
2840         u32 cp_hqd_pq_doorbell_control;
2841         u32 cp_hqd_pq_wptr;
2842         u32 cp_hqd_pq_control;
2843         u32 cp_hqd_ib_base_addr;
2844         u32 cp_hqd_ib_base_addr_hi;
2845         u32 cp_hqd_ib_rptr;
2846         u32 cp_hqd_ib_control;
2847         u32 cp_hqd_iq_timer;
2848         u32 cp_hqd_iq_rptr;
2849         u32 cp_hqd_dequeue_request;
2850         u32 cp_hqd_dma_offload;
2851         u32 cp_hqd_sema_cmd;
2852         u32 cp_hqd_msg_type;
2853         u32 cp_hqd_atomic0_preop_lo;
2854         u32 cp_hqd_atomic0_preop_hi;
2855         u32 cp_hqd_atomic1_preop_lo;
2856         u32 cp_hqd_atomic1_preop_hi;
2857         u32 cp_hqd_hq_scheduler0;
2858         u32 cp_hqd_hq_scheduler1;
2859         u32 cp_mqd_control;
2860 };
2861
2862 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev,
2863                                        int mec, int pipe)
2864 {
2865         u64 eop_gpu_addr;
2866         u32 tmp;
2867         size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)
2868                             * GFX7_MEC_HPD_SIZE * 2;
2869
2870         mutex_lock(&adev->srbm_mutex);
2871         eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset;
2872
2873         cik_srbm_select(adev, mec + 1, pipe, 0, 0);
2874
2875         /* write the EOP addr */
2876         WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2877         WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2878
2879         /* set the VMID assigned */
2880         WREG32(mmCP_HPD_EOP_VMID, 0);
2881
2882         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2883         tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2884         tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2885         tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8);
2886         WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2887
2888         cik_srbm_select(adev, 0, 0, 0, 0);
2889         mutex_unlock(&adev->srbm_mutex);
2890 }
2891
2892 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev)
2893 {
2894         int i;
2895
2896         /* disable the queue if it's active */
2897         if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2898                 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2899                 for (i = 0; i < adev->usec_timeout; i++) {
2900                         if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2901                                 break;
2902                         udelay(1);
2903                 }
2904
2905                 if (i == adev->usec_timeout)
2906                         return -ETIMEDOUT;
2907
2908                 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
2909                 WREG32(mmCP_HQD_PQ_RPTR, 0);
2910                 WREG32(mmCP_HQD_PQ_WPTR, 0);
2911         }
2912
2913         return 0;
2914 }
2915
2916 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
2917                              struct cik_mqd *mqd,
2918                              uint64_t mqd_gpu_addr,
2919                              struct amdgpu_ring *ring)
2920 {
2921         u64 hqd_gpu_addr;
2922         u64 wb_gpu_addr;
2923
2924         /* init the mqd struct */
2925         memset(mqd, 0, sizeof(struct cik_mqd));
2926
2927         mqd->header = 0xC0310800;
2928         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2929         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2930         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2931         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2932
2933         /* enable doorbell? */
2934         mqd->cp_hqd_pq_doorbell_control =
2935                 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2936         if (ring->use_doorbell)
2937                 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2938         else
2939                 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2940
2941         /* set the pointer to the MQD */
2942         mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
2943         mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2944
2945         /* set MQD vmid to 0 */
2946         mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2947         mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2948
2949         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2950         hqd_gpu_addr = ring->gpu_addr >> 8;
2951         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2952         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2953
2954         /* set up the HQD, this is similar to CP_RB0_CNTL */
2955         mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2956         mqd->cp_hqd_pq_control &=
2957                 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2958                                 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2959
2960         mqd->cp_hqd_pq_control |=
2961                 order_base_2(ring->ring_size / 8);
2962         mqd->cp_hqd_pq_control |=
2963                 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2964 #ifdef __BIG_ENDIAN
2965         mqd->cp_hqd_pq_control |=
2966                 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
2967 #endif
2968         mqd->cp_hqd_pq_control &=
2969                 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2970                                 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2971                                 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2972         mqd->cp_hqd_pq_control |=
2973                 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2974                 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2975
2976         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2977         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2978         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2979         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2980
2981         /* set the wb address wether it's enabled or not */
2982         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2983         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2984         mqd->cp_hqd_pq_rptr_report_addr_hi =
2985                 upper_32_bits(wb_gpu_addr) & 0xffff;
2986
2987         /* enable the doorbell if requested */
2988         if (ring->use_doorbell) {
2989                 mqd->cp_hqd_pq_doorbell_control =
2990                         RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2991                 mqd->cp_hqd_pq_doorbell_control &=
2992                         ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2993                 mqd->cp_hqd_pq_doorbell_control |=
2994                         (ring->doorbell_index <<
2995                          CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2996                 mqd->cp_hqd_pq_doorbell_control |=
2997                         CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2998                 mqd->cp_hqd_pq_doorbell_control &=
2999                         ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
3000                                         CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
3001
3002         } else {
3003                 mqd->cp_hqd_pq_doorbell_control = 0;
3004         }
3005
3006         /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3007         ring->wptr = 0;
3008         mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
3009         mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3010
3011         /* set the vmid for the queue */
3012         mqd->cp_hqd_vmid = 0;
3013
3014         /* defaults */
3015         mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
3016         mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
3017         mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
3018         mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
3019         mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
3020         mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
3021         mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
3022         mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
3023         mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
3024         mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
3025         mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
3026         mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3027         mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
3028         mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
3029         mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
3030         mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
3031
3032         /* activate the queue */
3033         mqd->cp_hqd_active = 1;
3034 }
3035
3036 int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
3037 {
3038         uint32_t tmp;
3039         uint32_t mqd_reg;
3040         uint32_t *mqd_data;
3041
3042         /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */
3043         mqd_data = &mqd->cp_mqd_base_addr_lo;
3044
3045         /* disable wptr polling */
3046         tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3047         tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3048         WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3049
3050         /* program all HQD registers */
3051         for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++)
3052                 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
3053
3054         /* activate the HQD */
3055         for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
3056                 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
3057
3058         return 0;
3059 }
3060
3061 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id)
3062 {
3063         int r;
3064         u64 mqd_gpu_addr;
3065         struct cik_mqd *mqd;
3066         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
3067
3068         r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE,
3069                                       AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
3070                                       &mqd_gpu_addr, (void **)&mqd);
3071         if (r) {
3072                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3073                 return r;
3074         }
3075
3076         mutex_lock(&adev->srbm_mutex);
3077         cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3078
3079         gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring);
3080         gfx_v7_0_mqd_deactivate(adev);
3081         gfx_v7_0_mqd_commit(adev, mqd);
3082
3083         cik_srbm_select(adev, 0, 0, 0, 0);
3084         mutex_unlock(&adev->srbm_mutex);
3085
3086         amdgpu_bo_kunmap(ring->mqd_obj);
3087         amdgpu_bo_unreserve(ring->mqd_obj);
3088         return 0;
3089 }
3090
3091 /**
3092  * gfx_v7_0_cp_compute_resume - setup the compute queue registers
3093  *
3094  * @adev: amdgpu_device pointer
3095  *
3096  * Program the compute queues and test them to make sure they
3097  * are working.
3098  * Returns 0 for success, error for failure.
3099  */
3100 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
3101 {
3102         int r, i, j;
3103         u32 tmp;
3104         struct amdgpu_ring *ring;
3105
3106         /* fix up chicken bits */
3107         tmp = RREG32(mmCP_CPF_DEBUG);
3108         tmp |= (1 << 23);
3109         WREG32(mmCP_CPF_DEBUG, tmp);
3110
3111         /* init all pipes (even the ones we don't own) */
3112         for (i = 0; i < adev->gfx.mec.num_mec; i++)
3113                 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++)
3114                         gfx_v7_0_compute_pipe_init(adev, i, j);
3115
3116         /* init the queues */
3117         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3118                 r = gfx_v7_0_compute_queue_init(adev, i);
3119                 if (r) {
3120                         gfx_v7_0_cp_compute_fini(adev);
3121                         return r;
3122                 }
3123         }
3124
3125         gfx_v7_0_cp_compute_enable(adev, true);
3126
3127         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3128                 ring = &adev->gfx.compute_ring[i];
3129                 ring->ready = true;
3130                 r = amdgpu_ring_test_ring(ring);
3131                 if (r)
3132                         ring->ready = false;
3133         }
3134
3135         return 0;
3136 }
3137
3138 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3139 {
3140         gfx_v7_0_cp_gfx_enable(adev, enable);
3141         gfx_v7_0_cp_compute_enable(adev, enable);
3142 }
3143
3144 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3145 {
3146         int r;
3147
3148         r = gfx_v7_0_cp_gfx_load_microcode(adev);
3149         if (r)
3150                 return r;
3151         r = gfx_v7_0_cp_compute_load_microcode(adev);
3152         if (r)
3153                 return r;
3154
3155         return 0;
3156 }
3157
3158 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3159                                                bool enable)
3160 {
3161         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3162
3163         if (enable)
3164                 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3165                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3166         else
3167                 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3168                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3169         WREG32(mmCP_INT_CNTL_RING0, tmp);
3170 }
3171
3172 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3173 {
3174         int r;
3175
3176         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3177
3178         r = gfx_v7_0_cp_load_microcode(adev);
3179         if (r)
3180                 return r;
3181
3182         r = gfx_v7_0_cp_gfx_resume(adev);
3183         if (r)
3184                 return r;
3185         r = gfx_v7_0_cp_compute_resume(adev);
3186         if (r)
3187                 return r;
3188
3189         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3190
3191         return 0;
3192 }
3193
3194 /**
3195  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3196  *
3197  * @ring: the ring to emmit the commands to
3198  *
3199  * Sync the command pipeline with the PFP. E.g. wait for everything
3200  * to be completed.
3201  */
3202 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3203 {
3204         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3205         uint32_t seq = ring->fence_drv.sync_seq;
3206         uint64_t addr = ring->fence_drv.gpu_addr;
3207
3208         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3209         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3210                                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
3211                                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
3212         amdgpu_ring_write(ring, addr & 0xfffffffc);
3213         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3214         amdgpu_ring_write(ring, seq);
3215         amdgpu_ring_write(ring, 0xffffffff);
3216         amdgpu_ring_write(ring, 4); /* poll interval */
3217
3218         if (usepfp) {
3219                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3220                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3221                 amdgpu_ring_write(ring, 0);
3222                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3223                 amdgpu_ring_write(ring, 0);
3224         }
3225 }
3226
3227 /*
3228  * vm
3229  * VMID 0 is the physical GPU addresses as used by the kernel.
3230  * VMIDs 1-15 are used for userspace clients and are handled
3231  * by the amdgpu vm/hsa code.
3232  */
3233 /**
3234  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3235  *
3236  * @adev: amdgpu_device pointer
3237  *
3238  * Update the page table base and flush the VM TLB
3239  * using the CP (CIK).
3240  */
3241 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3242                                         unsigned vmid, uint64_t pd_addr)
3243 {
3244         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3245
3246         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3247         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3248                                  WRITE_DATA_DST_SEL(0)));
3249         if (vmid < 8) {
3250                 amdgpu_ring_write(ring,
3251                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
3252         } else {
3253                 amdgpu_ring_write(ring,
3254                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
3255         }
3256         amdgpu_ring_write(ring, 0);
3257         amdgpu_ring_write(ring, pd_addr >> 12);
3258
3259         /* bits 0-15 are the VM contexts0-15 */
3260         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3261         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3262                                  WRITE_DATA_DST_SEL(0)));
3263         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3264         amdgpu_ring_write(ring, 0);
3265         amdgpu_ring_write(ring, 1 << vmid);
3266
3267         /* wait for the invalidate to complete */
3268         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3269         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3270                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
3271                                  WAIT_REG_MEM_ENGINE(0))); /* me */
3272         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3273         amdgpu_ring_write(ring, 0);
3274         amdgpu_ring_write(ring, 0); /* ref */
3275         amdgpu_ring_write(ring, 0); /* mask */
3276         amdgpu_ring_write(ring, 0x20); /* poll interval */
3277
3278         /* compute doesn't have PFP */
3279         if (usepfp) {
3280                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3281                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3282                 amdgpu_ring_write(ring, 0x0);
3283
3284                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3285                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3286                 amdgpu_ring_write(ring, 0);
3287                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3288                 amdgpu_ring_write(ring, 0);
3289         }
3290 }
3291
3292 /*
3293  * RLC
3294  * The RLC is a multi-purpose microengine that handles a
3295  * variety of functions.
3296  */
3297 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3298 {
3299         amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
3300         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
3301         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
3302 }
3303
3304 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3305 {
3306         const u32 *src_ptr;
3307         volatile u32 *dst_ptr;
3308         u32 dws, i;
3309         const struct cs_section_def *cs_data;
3310         int r;
3311
3312         /* allocate rlc buffers */
3313         if (adev->flags & AMD_IS_APU) {
3314                 if (adev->asic_type == CHIP_KAVERI) {
3315                         adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3316                         adev->gfx.rlc.reg_list_size =
3317                                 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3318                 } else {
3319                         adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3320                         adev->gfx.rlc.reg_list_size =
3321                                 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3322                 }
3323         }
3324         adev->gfx.rlc.cs_data = ci_cs_data;
3325         adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3326         adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3327
3328         src_ptr = adev->gfx.rlc.reg_list;
3329         dws = adev->gfx.rlc.reg_list_size;
3330         dws += (5 * 16) + 48 + 48 + 64;
3331
3332         cs_data = adev->gfx.rlc.cs_data;
3333
3334         if (src_ptr) {
3335                 /* save restore block */
3336                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
3337                                               AMDGPU_GEM_DOMAIN_VRAM,
3338                                               &adev->gfx.rlc.save_restore_obj,
3339                                               &adev->gfx.rlc.save_restore_gpu_addr,
3340                                               (void **)&adev->gfx.rlc.sr_ptr);
3341                 if (r) {
3342                         dev_warn(adev->dev, "(%d) create, pin or map of RLC sr bo failed\n", r);
3343                         gfx_v7_0_rlc_fini(adev);
3344                         return r;
3345                 }
3346
3347                 /* write the sr buffer */
3348                 dst_ptr = adev->gfx.rlc.sr_ptr;
3349                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3350                         dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3351                 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3352                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3353         }
3354
3355         if (cs_data) {
3356                 /* clear state block */
3357                 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3358
3359                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
3360                                               AMDGPU_GEM_DOMAIN_VRAM,
3361                                               &adev->gfx.rlc.clear_state_obj,
3362                                               &adev->gfx.rlc.clear_state_gpu_addr,
3363                                               (void **)&adev->gfx.rlc.cs_ptr);
3364                 if (r) {
3365                         dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3366                         gfx_v7_0_rlc_fini(adev);
3367                         return r;
3368                 }
3369
3370                 /* set up the cs buffer */
3371                 dst_ptr = adev->gfx.rlc.cs_ptr;
3372                 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3373                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3374                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3375         }
3376
3377         if (adev->gfx.rlc.cp_table_size) {
3378
3379                 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
3380                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
3381                                               &adev->gfx.rlc.cp_table_obj,
3382                                               &adev->gfx.rlc.cp_table_gpu_addr,
3383                                               (void **)&adev->gfx.rlc.cp_table_ptr);
3384                 if (r) {
3385                         dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3386                         gfx_v7_0_rlc_fini(adev);
3387                         return r;
3388                 }
3389
3390                 gfx_v7_0_init_cp_pg_table(adev);
3391
3392                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3393                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3394
3395         }
3396
3397         return 0;
3398 }
3399
3400 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3401 {
3402         u32 tmp;
3403
3404         tmp = RREG32(mmRLC_LB_CNTL);
3405         if (enable)
3406                 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3407         else
3408                 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3409         WREG32(mmRLC_LB_CNTL, tmp);
3410 }
3411
3412 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3413 {
3414         u32 i, j, k;
3415         u32 mask;
3416
3417         mutex_lock(&adev->grbm_idx_mutex);
3418         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3419                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3420                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
3421                         for (k = 0; k < adev->usec_timeout; k++) {
3422                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3423                                         break;
3424                                 udelay(1);
3425                         }
3426                 }
3427         }
3428         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3429         mutex_unlock(&adev->grbm_idx_mutex);
3430
3431         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3432                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3433                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3434                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3435         for (k = 0; k < adev->usec_timeout; k++) {
3436                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3437                         break;
3438                 udelay(1);
3439         }
3440 }
3441
3442 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3443 {
3444         u32 tmp;
3445
3446         tmp = RREG32(mmRLC_CNTL);
3447         if (tmp != rlc)
3448                 WREG32(mmRLC_CNTL, rlc);
3449 }
3450
3451 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3452 {
3453         u32 data, orig;
3454
3455         orig = data = RREG32(mmRLC_CNTL);
3456
3457         if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3458                 u32 i;
3459
3460                 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3461                 WREG32(mmRLC_CNTL, data);
3462
3463                 for (i = 0; i < adev->usec_timeout; i++) {
3464                         if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3465                                 break;
3466                         udelay(1);
3467                 }
3468
3469                 gfx_v7_0_wait_for_rlc_serdes(adev);
3470         }
3471
3472         return orig;
3473 }
3474
3475 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3476 {
3477         u32 tmp, i, mask;
3478
3479         tmp = 0x1 | (1 << 1);
3480         WREG32(mmRLC_GPR_REG2, tmp);
3481
3482         mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3483                 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3484         for (i = 0; i < adev->usec_timeout; i++) {
3485                 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3486                         break;
3487                 udelay(1);
3488         }
3489
3490         for (i = 0; i < adev->usec_timeout; i++) {
3491                 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3492                         break;
3493                 udelay(1);
3494         }
3495 }
3496
3497 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3498 {
3499         u32 tmp;
3500
3501         tmp = 0x1 | (0 << 1);
3502         WREG32(mmRLC_GPR_REG2, tmp);
3503 }
3504
3505 /**
3506  * gfx_v7_0_rlc_stop - stop the RLC ME
3507  *
3508  * @adev: amdgpu_device pointer
3509  *
3510  * Halt the RLC ME (MicroEngine) (CIK).
3511  */
3512 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3513 {
3514         WREG32(mmRLC_CNTL, 0);
3515
3516         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3517
3518         gfx_v7_0_wait_for_rlc_serdes(adev);
3519 }
3520
3521 /**
3522  * gfx_v7_0_rlc_start - start the RLC ME
3523  *
3524  * @adev: amdgpu_device pointer
3525  *
3526  * Unhalt the RLC ME (MicroEngine) (CIK).
3527  */
3528 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3529 {
3530         WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3531
3532         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3533
3534         udelay(50);
3535 }
3536
3537 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3538 {
3539         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3540
3541         tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3542         WREG32(mmGRBM_SOFT_RESET, tmp);
3543         udelay(50);
3544         tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3545         WREG32(mmGRBM_SOFT_RESET, tmp);
3546         udelay(50);
3547 }
3548
3549 /**
3550  * gfx_v7_0_rlc_resume - setup the RLC hw
3551  *
3552  * @adev: amdgpu_device pointer
3553  *
3554  * Initialize the RLC registers, load the ucode,
3555  * and start the RLC (CIK).
3556  * Returns 0 for success, -EINVAL if the ucode is not available.
3557  */
3558 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3559 {
3560         const struct rlc_firmware_header_v1_0 *hdr;
3561         const __le32 *fw_data;
3562         unsigned i, fw_size;
3563         u32 tmp;
3564
3565         if (!adev->gfx.rlc_fw)
3566                 return -EINVAL;
3567
3568         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3569         amdgpu_ucode_print_rlc_hdr(&hdr->header);
3570         adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3571         adev->gfx.rlc_feature_version = le32_to_cpu(
3572                                         hdr->ucode_feature_version);
3573
3574         gfx_v7_0_rlc_stop(adev);
3575
3576         /* disable CG */
3577         tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3578         WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3579
3580         gfx_v7_0_rlc_reset(adev);
3581
3582         gfx_v7_0_init_pg(adev);
3583
3584         WREG32(mmRLC_LB_CNTR_INIT, 0);
3585         WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3586
3587         mutex_lock(&adev->grbm_idx_mutex);
3588         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3589         WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3590         WREG32(mmRLC_LB_PARAMS, 0x00600408);
3591         WREG32(mmRLC_LB_CNTL, 0x80000004);
3592         mutex_unlock(&adev->grbm_idx_mutex);
3593
3594         WREG32(mmRLC_MC_CNTL, 0);
3595         WREG32(mmRLC_UCODE_CNTL, 0);
3596
3597         fw_data = (const __le32 *)
3598                 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3599         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3600         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3601         for (i = 0; i < fw_size; i++)
3602                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3603         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3604
3605         /* XXX - find out what chips support lbpw */
3606         gfx_v7_0_enable_lbpw(adev, false);
3607
3608         if (adev->asic_type == CHIP_BONAIRE)
3609                 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3610
3611         gfx_v7_0_rlc_start(adev);
3612
3613         return 0;
3614 }
3615
3616 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3617 {
3618         u32 data, orig, tmp, tmp2;
3619
3620         orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3621
3622         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3623                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3624
3625                 tmp = gfx_v7_0_halt_rlc(adev);
3626
3627                 mutex_lock(&adev->grbm_idx_mutex);
3628                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3629                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3630                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3631                 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3632                         RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3633                         RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3634                 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3635                 mutex_unlock(&adev->grbm_idx_mutex);
3636
3637                 gfx_v7_0_update_rlc(adev, tmp);
3638
3639                 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3640                 if (orig != data)
3641                         WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3642
3643         } else {
3644                 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3645
3646                 RREG32(mmCB_CGTT_SCLK_CTRL);
3647                 RREG32(mmCB_CGTT_SCLK_CTRL);
3648                 RREG32(mmCB_CGTT_SCLK_CTRL);
3649                 RREG32(mmCB_CGTT_SCLK_CTRL);
3650
3651                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3652                 if (orig != data)
3653                         WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3654
3655                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3656         }
3657 }
3658
3659 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3660 {
3661         u32 data, orig, tmp = 0;
3662
3663         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3664                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3665                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3666                                 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3667                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3668                                 if (orig != data)
3669                                         WREG32(mmCP_MEM_SLP_CNTL, data);
3670                         }
3671                 }
3672
3673                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3674                 data |= 0x00000001;
3675                 data &= 0xfffffffd;
3676                 if (orig != data)
3677                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3678
3679                 tmp = gfx_v7_0_halt_rlc(adev);
3680
3681                 mutex_lock(&adev->grbm_idx_mutex);
3682                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3683                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3684                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3685                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3686                         RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3687                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3688                 mutex_unlock(&adev->grbm_idx_mutex);
3689
3690                 gfx_v7_0_update_rlc(adev, tmp);
3691
3692                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3693                         orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3694                         data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3695                         data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3696                         data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3697                         data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3698                         if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3699                             (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3700                                 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3701                         data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3702                         data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3703                         data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3704                         if (orig != data)
3705                                 WREG32(mmCGTS_SM_CTRL_REG, data);
3706                 }
3707         } else {
3708                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3709                 data |= 0x00000003;
3710                 if (orig != data)
3711                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3712
3713                 data = RREG32(mmRLC_MEM_SLP_CNTL);
3714                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3715                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3716                         WREG32(mmRLC_MEM_SLP_CNTL, data);
3717                 }
3718
3719                 data = RREG32(mmCP_MEM_SLP_CNTL);
3720                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3721                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3722                         WREG32(mmCP_MEM_SLP_CNTL, data);
3723                 }
3724
3725                 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3726                 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3727                 if (orig != data)
3728                         WREG32(mmCGTS_SM_CTRL_REG, data);
3729
3730                 tmp = gfx_v7_0_halt_rlc(adev);
3731
3732                 mutex_lock(&adev->grbm_idx_mutex);
3733                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3734                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3735                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3736                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3737                 WREG32(mmRLC_SERDES_WR_CTRL, data);
3738                 mutex_unlock(&adev->grbm_idx_mutex);
3739
3740                 gfx_v7_0_update_rlc(adev, tmp);
3741         }
3742 }
3743
3744 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3745                                bool enable)
3746 {
3747         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3748         /* order matters! */
3749         if (enable) {
3750                 gfx_v7_0_enable_mgcg(adev, true);
3751                 gfx_v7_0_enable_cgcg(adev, true);
3752         } else {
3753                 gfx_v7_0_enable_cgcg(adev, false);
3754                 gfx_v7_0_enable_mgcg(adev, false);
3755         }
3756         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3757 }
3758
3759 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3760                                                 bool enable)
3761 {
3762         u32 data, orig;
3763
3764         orig = data = RREG32(mmRLC_PG_CNTL);
3765         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3766                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3767         else
3768                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3769         if (orig != data)
3770                 WREG32(mmRLC_PG_CNTL, data);
3771 }
3772
3773 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3774                                                 bool enable)
3775 {
3776         u32 data, orig;
3777
3778         orig = data = RREG32(mmRLC_PG_CNTL);
3779         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3780                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3781         else
3782                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3783         if (orig != data)
3784                 WREG32(mmRLC_PG_CNTL, data);
3785 }
3786
3787 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3788 {
3789         u32 data, orig;
3790
3791         orig = data = RREG32(mmRLC_PG_CNTL);
3792         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3793                 data &= ~0x8000;
3794         else
3795                 data |= 0x8000;
3796         if (orig != data)
3797                 WREG32(mmRLC_PG_CNTL, data);
3798 }
3799
3800 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3801 {
3802         u32 data, orig;
3803
3804         orig = data = RREG32(mmRLC_PG_CNTL);
3805         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3806                 data &= ~0x2000;
3807         else
3808                 data |= 0x2000;
3809         if (orig != data)
3810                 WREG32(mmRLC_PG_CNTL, data);
3811 }
3812
3813 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3814 {
3815         const __le32 *fw_data;
3816         volatile u32 *dst_ptr;
3817         int me, i, max_me = 4;
3818         u32 bo_offset = 0;
3819         u32 table_offset, table_size;
3820
3821         if (adev->asic_type == CHIP_KAVERI)
3822                 max_me = 5;
3823
3824         if (adev->gfx.rlc.cp_table_ptr == NULL)
3825                 return;
3826
3827         /* write the cp table buffer */
3828         dst_ptr = adev->gfx.rlc.cp_table_ptr;
3829         for (me = 0; me < max_me; me++) {
3830                 if (me == 0) {
3831                         const struct gfx_firmware_header_v1_0 *hdr =
3832                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3833                         fw_data = (const __le32 *)
3834                                 (adev->gfx.ce_fw->data +
3835                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3836                         table_offset = le32_to_cpu(hdr->jt_offset);
3837                         table_size = le32_to_cpu(hdr->jt_size);
3838                 } else if (me == 1) {
3839                         const struct gfx_firmware_header_v1_0 *hdr =
3840                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3841                         fw_data = (const __le32 *)
3842                                 (adev->gfx.pfp_fw->data +
3843                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3844                         table_offset = le32_to_cpu(hdr->jt_offset);
3845                         table_size = le32_to_cpu(hdr->jt_size);
3846                 } else if (me == 2) {
3847                         const struct gfx_firmware_header_v1_0 *hdr =
3848                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3849                         fw_data = (const __le32 *)
3850                                 (adev->gfx.me_fw->data +
3851                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3852                         table_offset = le32_to_cpu(hdr->jt_offset);
3853                         table_size = le32_to_cpu(hdr->jt_size);
3854                 } else if (me == 3) {
3855                         const struct gfx_firmware_header_v1_0 *hdr =
3856                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3857                         fw_data = (const __le32 *)
3858                                 (adev->gfx.mec_fw->data +
3859                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3860                         table_offset = le32_to_cpu(hdr->jt_offset);
3861                         table_size = le32_to_cpu(hdr->jt_size);
3862                 } else {
3863                         const struct gfx_firmware_header_v1_0 *hdr =
3864                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3865                         fw_data = (const __le32 *)
3866                                 (adev->gfx.mec2_fw->data +
3867                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3868                         table_offset = le32_to_cpu(hdr->jt_offset);
3869                         table_size = le32_to_cpu(hdr->jt_size);
3870                 }
3871
3872                 for (i = 0; i < table_size; i ++) {
3873                         dst_ptr[bo_offset + i] =
3874                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3875                 }
3876
3877                 bo_offset += table_size;
3878         }
3879 }
3880
3881 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3882                                      bool enable)
3883 {
3884         u32 data, orig;
3885
3886         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3887                 orig = data = RREG32(mmRLC_PG_CNTL);
3888                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3889                 if (orig != data)
3890                         WREG32(mmRLC_PG_CNTL, data);
3891
3892                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3893                 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3894                 if (orig != data)
3895                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3896         } else {
3897                 orig = data = RREG32(mmRLC_PG_CNTL);
3898                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3899                 if (orig != data)
3900                         WREG32(mmRLC_PG_CNTL, data);
3901
3902                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3903                 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3904                 if (orig != data)
3905                         WREG32(mmRLC_AUTO_PG_CTRL, data);
3906
3907                 data = RREG32(mmDB_RENDER_CONTROL);
3908         }
3909 }
3910
3911 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
3912                                                  u32 bitmap)
3913 {
3914         u32 data;
3915
3916         if (!bitmap)
3917                 return;
3918
3919         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3920         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3921
3922         WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
3923 }
3924
3925 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3926 {
3927         u32 data, mask;
3928
3929         data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3930         data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
3931
3932         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3933         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3934
3935         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
3936
3937         return (~data) & mask;
3938 }
3939
3940 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3941 {
3942         u32 tmp;
3943
3944         WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
3945
3946         tmp = RREG32(mmRLC_MAX_PG_CU);
3947         tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3948         tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3949         WREG32(mmRLC_MAX_PG_CU, tmp);
3950 }
3951
3952 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3953                                             bool enable)
3954 {
3955         u32 data, orig;
3956
3957         orig = data = RREG32(mmRLC_PG_CNTL);
3958         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
3959                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3960         else
3961                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3962         if (orig != data)
3963                 WREG32(mmRLC_PG_CNTL, data);
3964 }
3965
3966 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3967                                              bool enable)
3968 {
3969         u32 data, orig;
3970
3971         orig = data = RREG32(mmRLC_PG_CNTL);
3972         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
3973                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3974         else
3975                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3976         if (orig != data)
3977                 WREG32(mmRLC_PG_CNTL, data);
3978 }
3979
3980 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3981 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
3982
3983 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3984 {
3985         u32 data, orig;
3986         u32 i;
3987
3988         if (adev->gfx.rlc.cs_data) {
3989                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3990                 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3991                 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3992                 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3993         } else {
3994                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3995                 for (i = 0; i < 3; i++)
3996                         WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3997         }
3998         if (adev->gfx.rlc.reg_list) {
3999                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
4000                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
4001                         WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
4002         }
4003
4004         orig = data = RREG32(mmRLC_PG_CNTL);
4005         data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
4006         if (orig != data)
4007                 WREG32(mmRLC_PG_CNTL, data);
4008
4009         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
4010         WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4011
4012         data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
4013         data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
4014         data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4015         WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
4016
4017         data = 0x10101010;
4018         WREG32(mmRLC_PG_DELAY, data);
4019
4020         data = RREG32(mmRLC_PG_DELAY_2);
4021         data &= ~0xff;
4022         data |= 0x3;
4023         WREG32(mmRLC_PG_DELAY_2, data);
4024
4025         data = RREG32(mmRLC_AUTO_PG_CTRL);
4026         data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
4027         data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
4028         WREG32(mmRLC_AUTO_PG_CTRL, data);
4029
4030 }
4031
4032 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
4033 {
4034         gfx_v7_0_enable_gfx_cgpg(adev, enable);
4035         gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
4036         gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
4037 }
4038
4039 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4040 {
4041         u32 count = 0;
4042         const struct cs_section_def *sect = NULL;
4043         const struct cs_extent_def *ext = NULL;
4044
4045         if (adev->gfx.rlc.cs_data == NULL)
4046                 return 0;
4047
4048         /* begin clear state */
4049         count += 2;
4050         /* context control state */
4051         count += 3;
4052
4053         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4054                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4055                         if (sect->id == SECT_CONTEXT)
4056                                 count += 2 + ext->reg_count;
4057                         else
4058                                 return 0;
4059                 }
4060         }
4061         /* pa_sc_raster_config/pa_sc_raster_config1 */
4062         count += 4;
4063         /* end clear state */
4064         count += 2;
4065         /* clear state */
4066         count += 2;
4067
4068         return count;
4069 }
4070
4071 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4072                                     volatile u32 *buffer)
4073 {
4074         u32 count = 0, i;
4075         const struct cs_section_def *sect = NULL;
4076         const struct cs_extent_def *ext = NULL;
4077
4078         if (adev->gfx.rlc.cs_data == NULL)
4079                 return;
4080         if (buffer == NULL)
4081                 return;
4082
4083         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4084         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4085
4086         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4087         buffer[count++] = cpu_to_le32(0x80000000);
4088         buffer[count++] = cpu_to_le32(0x80000000);
4089
4090         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4091                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4092                         if (sect->id == SECT_CONTEXT) {
4093                                 buffer[count++] =
4094                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4095                                 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4096                                 for (i = 0; i < ext->reg_count; i++)
4097                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4098                         } else {
4099                                 return;
4100                         }
4101                 }
4102         }
4103
4104         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4105         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4106         switch (adev->asic_type) {
4107         case CHIP_BONAIRE:
4108                 buffer[count++] = cpu_to_le32(0x16000012);
4109                 buffer[count++] = cpu_to_le32(0x00000000);
4110                 break;
4111         case CHIP_KAVERI:
4112                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4113                 buffer[count++] = cpu_to_le32(0x00000000);
4114                 break;
4115         case CHIP_KABINI:
4116         case CHIP_MULLINS:
4117                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4118                 buffer[count++] = cpu_to_le32(0x00000000);
4119                 break;
4120         case CHIP_HAWAII:
4121                 buffer[count++] = cpu_to_le32(0x3a00161a);
4122                 buffer[count++] = cpu_to_le32(0x0000002e);
4123                 break;
4124         default:
4125                 buffer[count++] = cpu_to_le32(0x00000000);
4126                 buffer[count++] = cpu_to_le32(0x00000000);
4127                 break;
4128         }
4129
4130         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4131         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4132
4133         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4134         buffer[count++] = cpu_to_le32(0);
4135 }
4136
4137 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4138 {
4139         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4140                               AMD_PG_SUPPORT_GFX_SMG |
4141                               AMD_PG_SUPPORT_GFX_DMG |
4142                               AMD_PG_SUPPORT_CP |
4143                               AMD_PG_SUPPORT_GDS |
4144                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4145                 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4146                 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4147                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4148                         gfx_v7_0_init_gfx_cgpg(adev);
4149                         gfx_v7_0_enable_cp_pg(adev, true);
4150                         gfx_v7_0_enable_gds_pg(adev, true);
4151                 }
4152                 gfx_v7_0_init_ao_cu_mask(adev);
4153                 gfx_v7_0_update_gfx_pg(adev, true);
4154         }
4155 }
4156
4157 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4158 {
4159         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4160                               AMD_PG_SUPPORT_GFX_SMG |
4161                               AMD_PG_SUPPORT_GFX_DMG |
4162                               AMD_PG_SUPPORT_CP |
4163                               AMD_PG_SUPPORT_GDS |
4164                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
4165                 gfx_v7_0_update_gfx_pg(adev, false);
4166                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4167                         gfx_v7_0_enable_cp_pg(adev, false);
4168                         gfx_v7_0_enable_gds_pg(adev, false);
4169                 }
4170         }
4171 }
4172
4173 /**
4174  * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4175  *
4176  * @adev: amdgpu_device pointer
4177  *
4178  * Fetches a GPU clock counter snapshot (SI).
4179  * Returns the 64 bit clock counter snapshot.
4180  */
4181 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4182 {
4183         uint64_t clock;
4184
4185         mutex_lock(&adev->gfx.gpu_clock_mutex);
4186         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4187         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4188                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4189         mutex_unlock(&adev->gfx.gpu_clock_mutex);
4190         return clock;
4191 }
4192
4193 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4194                                           uint32_t vmid,
4195                                           uint32_t gds_base, uint32_t gds_size,
4196                                           uint32_t gws_base, uint32_t gws_size,
4197                                           uint32_t oa_base, uint32_t oa_size)
4198 {
4199         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4200         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4201
4202         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4203         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4204
4205         oa_base = oa_base >> AMDGPU_OA_SHIFT;
4206         oa_size = oa_size >> AMDGPU_OA_SHIFT;
4207
4208         /* GDS Base */
4209         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4210         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4211                                 WRITE_DATA_DST_SEL(0)));
4212         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4213         amdgpu_ring_write(ring, 0);
4214         amdgpu_ring_write(ring, gds_base);
4215
4216         /* GDS Size */
4217         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4218         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4219                                 WRITE_DATA_DST_SEL(0)));
4220         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4221         amdgpu_ring_write(ring, 0);
4222         amdgpu_ring_write(ring, gds_size);
4223
4224         /* GWS */
4225         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4226         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4227                                 WRITE_DATA_DST_SEL(0)));
4228         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4229         amdgpu_ring_write(ring, 0);
4230         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4231
4232         /* OA */
4233         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4234         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4235                                 WRITE_DATA_DST_SEL(0)));
4236         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4237         amdgpu_ring_write(ring, 0);
4238         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4239 }
4240
4241 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4242 {
4243         WREG32(mmSQ_IND_INDEX,
4244                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4245                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4246                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
4247                 (SQ_IND_INDEX__FORCE_READ_MASK));
4248         return RREG32(mmSQ_IND_DATA);
4249 }
4250
4251 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4252                            uint32_t wave, uint32_t thread,
4253                            uint32_t regno, uint32_t num, uint32_t *out)
4254 {
4255         WREG32(mmSQ_IND_INDEX,
4256                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4257                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4258                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4259                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4260                 (SQ_IND_INDEX__FORCE_READ_MASK) |
4261                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4262         while (num--)
4263                 *(out++) = RREG32(mmSQ_IND_DATA);
4264 }
4265
4266 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4267 {
4268         /* type 0 wave data */
4269         dst[(*no_fields)++] = 0;
4270         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
4271         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
4272         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
4273         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
4274         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
4275         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
4276         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
4277         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
4278         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
4279         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
4280         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
4281         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
4282         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
4283         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
4284         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
4285         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
4286         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
4287         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
4288 }
4289
4290 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4291                                      uint32_t wave, uint32_t start,
4292                                      uint32_t size, uint32_t *dst)
4293 {
4294         wave_read_regs(
4295                 adev, simd, wave, 0,
4296                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4297 }
4298
4299 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4300         .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4301         .select_se_sh = &gfx_v7_0_select_se_sh,
4302         .read_wave_data = &gfx_v7_0_read_wave_data,
4303         .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4304 };
4305
4306 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4307         .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4308         .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode
4309 };
4310
4311 static int gfx_v7_0_early_init(void *handle)
4312 {
4313         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4314
4315         adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4316         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
4317         adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
4318         adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
4319         gfx_v7_0_set_ring_funcs(adev);
4320         gfx_v7_0_set_irq_funcs(adev);
4321         gfx_v7_0_set_gds_init(adev);
4322
4323         return 0;
4324 }
4325
4326 static int gfx_v7_0_late_init(void *handle)
4327 {
4328         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4329         int r;
4330
4331         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4332         if (r)
4333                 return r;
4334
4335         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4336         if (r)
4337                 return r;
4338
4339         return 0;
4340 }
4341
4342 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4343 {
4344         u32 gb_addr_config;
4345         u32 mc_shared_chmap, mc_arb_ramcfg;
4346         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4347         u32 tmp;
4348
4349         switch (adev->asic_type) {
4350         case CHIP_BONAIRE:
4351                 adev->gfx.config.max_shader_engines = 2;
4352                 adev->gfx.config.max_tile_pipes = 4;
4353                 adev->gfx.config.max_cu_per_sh = 7;
4354                 adev->gfx.config.max_sh_per_se = 1;
4355                 adev->gfx.config.max_backends_per_se = 2;
4356                 adev->gfx.config.max_texture_channel_caches = 4;
4357                 adev->gfx.config.max_gprs = 256;
4358                 adev->gfx.config.max_gs_threads = 32;
4359                 adev->gfx.config.max_hw_contexts = 8;
4360
4361                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4362                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4363                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4364                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4365                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4366                 break;
4367         case CHIP_HAWAII:
4368                 adev->gfx.config.max_shader_engines = 4;
4369                 adev->gfx.config.max_tile_pipes = 16;
4370                 adev->gfx.config.max_cu_per_sh = 11;
4371                 adev->gfx.config.max_sh_per_se = 1;
4372                 adev->gfx.config.max_backends_per_se = 4;
4373                 adev->gfx.config.max_texture_channel_caches = 16;
4374                 adev->gfx.config.max_gprs = 256;
4375                 adev->gfx.config.max_gs_threads = 32;
4376                 adev->gfx.config.max_hw_contexts = 8;
4377
4378                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4379                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4380                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4381                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4382                 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4383                 break;
4384         case CHIP_KAVERI:
4385                 adev->gfx.config.max_shader_engines = 1;
4386                 adev->gfx.config.max_tile_pipes = 4;
4387                 if ((adev->pdev->device == 0x1304) ||
4388                     (adev->pdev->device == 0x1305) ||
4389                     (adev->pdev->device == 0x130C) ||
4390                     (adev->pdev->device == 0x130F) ||
4391                     (adev->pdev->device == 0x1310) ||
4392                     (adev->pdev->device == 0x1311) ||
4393                     (adev->pdev->device == 0x131C)) {
4394                         adev->gfx.config.max_cu_per_sh = 8;
4395                         adev->gfx.config.max_backends_per_se = 2;
4396                 } else if ((adev->pdev->device == 0x1309) ||
4397                            (adev->pdev->device == 0x130A) ||
4398                            (adev->pdev->device == 0x130D) ||
4399                            (adev->pdev->device == 0x1313) ||
4400                            (adev->pdev->device == 0x131D)) {
4401                         adev->gfx.config.max_cu_per_sh = 6;
4402                         adev->gfx.config.max_backends_per_se = 2;
4403                 } else if ((adev->pdev->device == 0x1306) ||
4404                            (adev->pdev->device == 0x1307) ||
4405                            (adev->pdev->device == 0x130B) ||
4406                            (adev->pdev->device == 0x130E) ||
4407                            (adev->pdev->device == 0x1315) ||
4408                            (adev->pdev->device == 0x131B)) {
4409                         adev->gfx.config.max_cu_per_sh = 4;
4410                         adev->gfx.config.max_backends_per_se = 1;
4411                 } else {
4412                         adev->gfx.config.max_cu_per_sh = 3;
4413                         adev->gfx.config.max_backends_per_se = 1;
4414                 }
4415                 adev->gfx.config.max_sh_per_se = 1;
4416                 adev->gfx.config.max_texture_channel_caches = 4;
4417                 adev->gfx.config.max_gprs = 256;
4418                 adev->gfx.config.max_gs_threads = 16;
4419                 adev->gfx.config.max_hw_contexts = 8;
4420
4421                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4422                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4423                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4424                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4425                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4426                 break;
4427         case CHIP_KABINI:
4428         case CHIP_MULLINS:
4429         default:
4430                 adev->gfx.config.max_shader_engines = 1;
4431                 adev->gfx.config.max_tile_pipes = 2;
4432                 adev->gfx.config.max_cu_per_sh = 2;
4433                 adev->gfx.config.max_sh_per_se = 1;
4434                 adev->gfx.config.max_backends_per_se = 1;
4435                 adev->gfx.config.max_texture_channel_caches = 2;
4436                 adev->gfx.config.max_gprs = 256;
4437                 adev->gfx.config.max_gs_threads = 16;
4438                 adev->gfx.config.max_hw_contexts = 8;
4439
4440                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4441                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4442                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4443                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4444                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4445                 break;
4446         }
4447
4448         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4449         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4450         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4451
4452         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4453         adev->gfx.config.mem_max_burst_length_bytes = 256;
4454         if (adev->flags & AMD_IS_APU) {
4455                 /* Get memory bank mapping mode. */
4456                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4457                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4458                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4459
4460                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4461                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4462                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4463
4464                 /* Validate settings in case only one DIMM installed. */
4465                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4466                         dimm00_addr_map = 0;
4467                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4468                         dimm01_addr_map = 0;
4469                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4470                         dimm10_addr_map = 0;
4471                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4472                         dimm11_addr_map = 0;
4473
4474                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4475                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4476                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4477                         adev->gfx.config.mem_row_size_in_kb = 2;
4478                 else
4479                         adev->gfx.config.mem_row_size_in_kb = 1;
4480         } else {
4481                 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4482                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4483                 if (adev->gfx.config.mem_row_size_in_kb > 4)
4484                         adev->gfx.config.mem_row_size_in_kb = 4;
4485         }
4486         /* XXX use MC settings? */
4487         adev->gfx.config.shader_engine_tile_size = 32;
4488         adev->gfx.config.num_gpus = 1;
4489         adev->gfx.config.multi_gpu_tile_size = 64;
4490
4491         /* fix up row size */
4492         gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4493         switch (adev->gfx.config.mem_row_size_in_kb) {
4494         case 1:
4495         default:
4496                 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4497                 break;
4498         case 2:
4499                 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4500                 break;
4501         case 4:
4502                 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4503                 break;
4504         }
4505         adev->gfx.config.gb_addr_config = gb_addr_config;
4506 }
4507
4508 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4509                                         int mec, int pipe, int queue)
4510 {
4511         int r;
4512         unsigned irq_type;
4513         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
4514
4515         /* mec0 is me1 */
4516         ring->me = mec + 1;
4517         ring->pipe = pipe;
4518         ring->queue = queue;
4519
4520         ring->ring_obj = NULL;
4521         ring->use_doorbell = true;
4522         ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
4523         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4524
4525         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4526                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4527                 + ring->pipe;
4528
4529         /* type-2 packets are deprecated on MEC, use type-3 instead */
4530         r = amdgpu_ring_init(adev, ring, 1024,
4531                         &adev->gfx.eop_irq, irq_type);
4532         if (r)
4533                 return r;
4534
4535
4536         return 0;
4537 }
4538
4539 static int gfx_v7_0_sw_init(void *handle)
4540 {
4541         struct amdgpu_ring *ring;
4542         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4543         int i, j, k, r, ring_id;
4544
4545         switch (adev->asic_type) {
4546         case CHIP_KAVERI:
4547                 adev->gfx.mec.num_mec = 2;
4548                 break;
4549         case CHIP_BONAIRE:
4550         case CHIP_HAWAII:
4551         case CHIP_KABINI:
4552         case CHIP_MULLINS:
4553         default:
4554                 adev->gfx.mec.num_mec = 1;
4555                 break;
4556         }
4557         adev->gfx.mec.num_pipe_per_mec = 4;
4558         adev->gfx.mec.num_queue_per_pipe = 8;
4559
4560         /* EOP Event */
4561         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
4562         if (r)
4563                 return r;
4564
4565         /* Privileged reg */
4566         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184,
4567                               &adev->gfx.priv_reg_irq);
4568         if (r)
4569                 return r;
4570
4571         /* Privileged inst */
4572         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185,
4573                               &adev->gfx.priv_inst_irq);
4574         if (r)
4575                 return r;
4576
4577         gfx_v7_0_scratch_init(adev);
4578
4579         r = gfx_v7_0_init_microcode(adev);
4580         if (r) {
4581                 DRM_ERROR("Failed to load gfx firmware!\n");
4582                 return r;
4583         }
4584
4585         r = gfx_v7_0_rlc_init(adev);
4586         if (r) {
4587                 DRM_ERROR("Failed to init rlc BOs!\n");
4588                 return r;
4589         }
4590
4591         /* allocate mec buffers */
4592         r = gfx_v7_0_mec_init(adev);
4593         if (r) {
4594                 DRM_ERROR("Failed to init MEC BOs!\n");
4595                 return r;
4596         }
4597
4598         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4599                 ring = &adev->gfx.gfx_ring[i];
4600                 ring->ring_obj = NULL;
4601                 sprintf(ring->name, "gfx");
4602                 r = amdgpu_ring_init(adev, ring, 1024,
4603                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
4604                 if (r)
4605                         return r;
4606         }
4607
4608         /* set up the compute queues - allocate horizontally across pipes */
4609         ring_id = 0;
4610         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4611                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4612                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4613                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
4614                                         continue;
4615
4616                                 r = gfx_v7_0_compute_ring_init(adev,
4617                                                                 ring_id,
4618                                                                 i, k, j);
4619                                 if (r)
4620                                         return r;
4621
4622                                 ring_id++;
4623                         }
4624                 }
4625         }
4626
4627         /* reserve GDS, GWS and OA resource for gfx */
4628         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
4629                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
4630                                     &adev->gds.gds_gfx_bo, NULL, NULL);
4631         if (r)
4632                 return r;
4633
4634         r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
4635                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
4636                                     &adev->gds.gws_gfx_bo, NULL, NULL);
4637         if (r)
4638                 return r;
4639
4640         r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
4641                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
4642                                     &adev->gds.oa_gfx_bo, NULL, NULL);
4643         if (r)
4644                 return r;
4645
4646         adev->gfx.ce_ram_size = 0x8000;
4647
4648         gfx_v7_0_gpu_early_init(adev);
4649
4650         return r;
4651 }
4652
4653 static int gfx_v7_0_sw_fini(void *handle)
4654 {
4655         int i;
4656         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4657
4658         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
4659         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
4660         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
4661
4662         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4663                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4664         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4665                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4666
4667         gfx_v7_0_cp_compute_fini(adev);
4668         gfx_v7_0_rlc_fini(adev);
4669         gfx_v7_0_mec_fini(adev);
4670         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4671                                 &adev->gfx.rlc.clear_state_gpu_addr,
4672                                 (void **)&adev->gfx.rlc.cs_ptr);
4673         if (adev->gfx.rlc.cp_table_size) {
4674                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4675                                 &adev->gfx.rlc.cp_table_gpu_addr,
4676                                 (void **)&adev->gfx.rlc.cp_table_ptr);
4677         }
4678         gfx_v7_0_free_microcode(adev);
4679
4680         return 0;
4681 }
4682
4683 static int gfx_v7_0_hw_init(void *handle)
4684 {
4685         int r;
4686         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4687
4688         gfx_v7_0_gpu_init(adev);
4689
4690         /* init rlc */
4691         r = gfx_v7_0_rlc_resume(adev);
4692         if (r)
4693                 return r;
4694
4695         r = gfx_v7_0_cp_resume(adev);
4696         if (r)
4697                 return r;
4698
4699         return r;
4700 }
4701
4702 static int gfx_v7_0_hw_fini(void *handle)
4703 {
4704         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4705
4706         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4707         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4708         gfx_v7_0_cp_enable(adev, false);
4709         gfx_v7_0_rlc_stop(adev);
4710         gfx_v7_0_fini_pg(adev);
4711
4712         return 0;
4713 }
4714
4715 static int gfx_v7_0_suspend(void *handle)
4716 {
4717         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4718
4719         return gfx_v7_0_hw_fini(adev);
4720 }
4721
4722 static int gfx_v7_0_resume(void *handle)
4723 {
4724         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4725
4726         return gfx_v7_0_hw_init(adev);
4727 }
4728
4729 static bool gfx_v7_0_is_idle(void *handle)
4730 {
4731         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4732
4733         if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4734                 return false;
4735         else
4736                 return true;
4737 }
4738
4739 static int gfx_v7_0_wait_for_idle(void *handle)
4740 {
4741         unsigned i;
4742         u32 tmp;
4743         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4744
4745         for (i = 0; i < adev->usec_timeout; i++) {
4746                 /* read MC_STATUS */
4747                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4748
4749                 if (!tmp)
4750                         return 0;
4751                 udelay(1);
4752         }
4753         return -ETIMEDOUT;
4754 }
4755
4756 static int gfx_v7_0_soft_reset(void *handle)
4757 {
4758         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4759         u32 tmp;
4760         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4761
4762         /* GRBM_STATUS */
4763         tmp = RREG32(mmGRBM_STATUS);
4764         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4765                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4766                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4767                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4768                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4769                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4770                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4771                         GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4772
4773         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4774                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4775                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4776         }
4777
4778         /* GRBM_STATUS2 */
4779         tmp = RREG32(mmGRBM_STATUS2);
4780         if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4781                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4782
4783         /* SRBM_STATUS */
4784         tmp = RREG32(mmSRBM_STATUS);
4785         if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4786                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4787
4788         if (grbm_soft_reset || srbm_soft_reset) {
4789                 /* disable CG/PG */
4790                 gfx_v7_0_fini_pg(adev);
4791                 gfx_v7_0_update_cg(adev, false);
4792
4793                 /* stop the rlc */
4794                 gfx_v7_0_rlc_stop(adev);
4795
4796                 /* Disable GFX parsing/prefetching */
4797                 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4798
4799                 /* Disable MEC parsing/prefetching */
4800                 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4801
4802                 if (grbm_soft_reset) {
4803                         tmp = RREG32(mmGRBM_SOFT_RESET);
4804                         tmp |= grbm_soft_reset;
4805                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4806                         WREG32(mmGRBM_SOFT_RESET, tmp);
4807                         tmp = RREG32(mmGRBM_SOFT_RESET);
4808
4809                         udelay(50);
4810
4811                         tmp &= ~grbm_soft_reset;
4812                         WREG32(mmGRBM_SOFT_RESET, tmp);
4813                         tmp = RREG32(mmGRBM_SOFT_RESET);
4814                 }
4815
4816                 if (srbm_soft_reset) {
4817                         tmp = RREG32(mmSRBM_SOFT_RESET);
4818                         tmp |= srbm_soft_reset;
4819                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4820                         WREG32(mmSRBM_SOFT_RESET, tmp);
4821                         tmp = RREG32(mmSRBM_SOFT_RESET);
4822
4823                         udelay(50);
4824
4825                         tmp &= ~srbm_soft_reset;
4826                         WREG32(mmSRBM_SOFT_RESET, tmp);
4827                         tmp = RREG32(mmSRBM_SOFT_RESET);
4828                 }
4829                 /* Wait a little for things to settle down */
4830                 udelay(50);
4831         }
4832         return 0;
4833 }
4834
4835 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4836                                                  enum amdgpu_interrupt_state state)
4837 {
4838         u32 cp_int_cntl;
4839
4840         switch (state) {
4841         case AMDGPU_IRQ_STATE_DISABLE:
4842                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4843                 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4844                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4845                 break;
4846         case AMDGPU_IRQ_STATE_ENABLE:
4847                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4848                 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4849                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4850                 break;
4851         default:
4852                 break;
4853         }
4854 }
4855
4856 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4857                                                      int me, int pipe,
4858                                                      enum amdgpu_interrupt_state state)
4859 {
4860         u32 mec_int_cntl, mec_int_cntl_reg;
4861
4862         /*
4863          * amdgpu controls only the first MEC. That's why this function only
4864          * handles the setting of interrupts for this specific MEC. All other
4865          * pipes' interrupts are set by amdkfd.
4866          */
4867
4868         if (me == 1) {
4869                 switch (pipe) {
4870                 case 0:
4871                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4872                         break;
4873                 case 1:
4874                         mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
4875                         break;
4876                 case 2:
4877                         mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
4878                         break;
4879                 case 3:
4880                         mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
4881                         break;
4882                 default:
4883                         DRM_DEBUG("invalid pipe %d\n", pipe);
4884                         return;
4885                 }
4886         } else {
4887                 DRM_DEBUG("invalid me %d\n", me);
4888                 return;
4889         }
4890
4891         switch (state) {
4892         case AMDGPU_IRQ_STATE_DISABLE:
4893                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4894                 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4895                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4896                 break;
4897         case AMDGPU_IRQ_STATE_ENABLE:
4898                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4899                 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4900                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4901                 break;
4902         default:
4903                 break;
4904         }
4905 }
4906
4907 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4908                                              struct amdgpu_irq_src *src,
4909                                              unsigned type,
4910                                              enum amdgpu_interrupt_state state)
4911 {
4912         u32 cp_int_cntl;
4913
4914         switch (state) {
4915         case AMDGPU_IRQ_STATE_DISABLE:
4916                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4917                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4918                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4919                 break;
4920         case AMDGPU_IRQ_STATE_ENABLE:
4921                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4922                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4923                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4924                 break;
4925         default:
4926                 break;
4927         }
4928
4929         return 0;
4930 }
4931
4932 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4933                                               struct amdgpu_irq_src *src,
4934                                               unsigned type,
4935                                               enum amdgpu_interrupt_state state)
4936 {
4937         u32 cp_int_cntl;
4938
4939         switch (state) {
4940         case AMDGPU_IRQ_STATE_DISABLE:
4941                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4942                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4943                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4944                 break;
4945         case AMDGPU_IRQ_STATE_ENABLE:
4946                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4947                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4948                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4949                 break;
4950         default:
4951                 break;
4952         }
4953
4954         return 0;
4955 }
4956
4957 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4958                                             struct amdgpu_irq_src *src,
4959                                             unsigned type,
4960                                             enum amdgpu_interrupt_state state)
4961 {
4962         switch (type) {
4963         case AMDGPU_CP_IRQ_GFX_EOP:
4964                 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4965                 break;
4966         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4967                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4968                 break;
4969         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4970                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4971                 break;
4972         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4973                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4974                 break;
4975         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4976                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4977                 break;
4978         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4979                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4980                 break;
4981         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4982                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4983                 break;
4984         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4985                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4986                 break;
4987         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4988                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4989                 break;
4990         default:
4991                 break;
4992         }
4993         return 0;
4994 }
4995
4996 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4997                             struct amdgpu_irq_src *source,
4998                             struct amdgpu_iv_entry *entry)
4999 {
5000         u8 me_id, pipe_id;
5001         struct amdgpu_ring *ring;
5002         int i;
5003
5004         DRM_DEBUG("IH: CP EOP\n");
5005         me_id = (entry->ring_id & 0x0c) >> 2;
5006         pipe_id = (entry->ring_id & 0x03) >> 0;
5007         switch (me_id) {
5008         case 0:
5009                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5010                 break;
5011         case 1:
5012         case 2:
5013                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5014                         ring = &adev->gfx.compute_ring[i];
5015                         if ((ring->me == me_id) && (ring->pipe == pipe_id))
5016                                 amdgpu_fence_process(ring);
5017                 }
5018                 break;
5019         }
5020         return 0;
5021 }
5022
5023 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
5024                                  struct amdgpu_irq_src *source,
5025                                  struct amdgpu_iv_entry *entry)
5026 {
5027         DRM_ERROR("Illegal register access in command stream\n");
5028         schedule_work(&adev->reset_work);
5029         return 0;
5030 }
5031
5032 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5033                                   struct amdgpu_irq_src *source,
5034                                   struct amdgpu_iv_entry *entry)
5035 {
5036         DRM_ERROR("Illegal instruction in command stream\n");
5037         // XXX soft reset the gfx block only
5038         schedule_work(&adev->reset_work);
5039         return 0;
5040 }
5041
5042 static int gfx_v7_0_set_clockgating_state(void *handle,
5043                                           enum amd_clockgating_state state)
5044 {
5045         bool gate = false;
5046         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5047
5048         if (state == AMD_CG_STATE_GATE)
5049                 gate = true;
5050
5051         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
5052         /* order matters! */
5053         if (gate) {
5054                 gfx_v7_0_enable_mgcg(adev, true);
5055                 gfx_v7_0_enable_cgcg(adev, true);
5056         } else {
5057                 gfx_v7_0_enable_cgcg(adev, false);
5058                 gfx_v7_0_enable_mgcg(adev, false);
5059         }
5060         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5061
5062         return 0;
5063 }
5064
5065 static int gfx_v7_0_set_powergating_state(void *handle,
5066                                           enum amd_powergating_state state)
5067 {
5068         bool gate = false;
5069         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5070
5071         if (state == AMD_PG_STATE_GATE)
5072                 gate = true;
5073
5074         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
5075                               AMD_PG_SUPPORT_GFX_SMG |
5076                               AMD_PG_SUPPORT_GFX_DMG |
5077                               AMD_PG_SUPPORT_CP |
5078                               AMD_PG_SUPPORT_GDS |
5079                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
5080                 gfx_v7_0_update_gfx_pg(adev, gate);
5081                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
5082                         gfx_v7_0_enable_cp_pg(adev, gate);
5083                         gfx_v7_0_enable_gds_pg(adev, gate);
5084                 }
5085         }
5086
5087         return 0;
5088 }
5089
5090 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5091         .name = "gfx_v7_0",
5092         .early_init = gfx_v7_0_early_init,
5093         .late_init = gfx_v7_0_late_init,
5094         .sw_init = gfx_v7_0_sw_init,
5095         .sw_fini = gfx_v7_0_sw_fini,
5096         .hw_init = gfx_v7_0_hw_init,
5097         .hw_fini = gfx_v7_0_hw_fini,
5098         .suspend = gfx_v7_0_suspend,
5099         .resume = gfx_v7_0_resume,
5100         .is_idle = gfx_v7_0_is_idle,
5101         .wait_for_idle = gfx_v7_0_wait_for_idle,
5102         .soft_reset = gfx_v7_0_soft_reset,
5103         .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5104         .set_powergating_state = gfx_v7_0_set_powergating_state,
5105 };
5106
5107 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5108         .type = AMDGPU_RING_TYPE_GFX,
5109         .align_mask = 0xff,
5110         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5111         .support_64bit_ptrs = false,
5112         .get_rptr = gfx_v7_0_ring_get_rptr,
5113         .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5114         .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5115         .emit_frame_size =
5116                 20 + /* gfx_v7_0_ring_emit_gds_switch */
5117                 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5118                 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5119                 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5120                 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5121                 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
5122                 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5123         .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
5124         .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
5125         .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
5126         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5127         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5128         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5129         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5130         .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
5131         .test_ring = gfx_v7_0_ring_test_ring,
5132         .test_ib = gfx_v7_0_ring_test_ib,
5133         .insert_nop = amdgpu_ring_insert_nop,
5134         .pad_ib = amdgpu_ring_generic_pad_ib,
5135         .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
5136 };
5137
5138 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5139         .type = AMDGPU_RING_TYPE_COMPUTE,
5140         .align_mask = 0xff,
5141         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5142         .support_64bit_ptrs = false,
5143         .get_rptr = gfx_v7_0_ring_get_rptr,
5144         .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5145         .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5146         .emit_frame_size =
5147                 20 + /* gfx_v7_0_ring_emit_gds_switch */
5148                 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5149                 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5150                 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
5151                 17 + /* gfx_v7_0_ring_emit_vm_flush */
5152                 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5153         .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
5154         .emit_ib = gfx_v7_0_ring_emit_ib_compute,
5155         .emit_fence = gfx_v7_0_ring_emit_fence_compute,
5156         .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5157         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5158         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5159         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5160         .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
5161         .test_ring = gfx_v7_0_ring_test_ring,
5162         .test_ib = gfx_v7_0_ring_test_ib,
5163         .insert_nop = amdgpu_ring_insert_nop,
5164         .pad_ib = amdgpu_ring_generic_pad_ib,
5165 };
5166
5167 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5168 {
5169         int i;
5170
5171         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5172                 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5173         for (i = 0; i < adev->gfx.num_compute_rings; i++)
5174                 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5175 }
5176
5177 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5178         .set = gfx_v7_0_set_eop_interrupt_state,
5179         .process = gfx_v7_0_eop_irq,
5180 };
5181
5182 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5183         .set = gfx_v7_0_set_priv_reg_fault_state,
5184         .process = gfx_v7_0_priv_reg_irq,
5185 };
5186
5187 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5188         .set = gfx_v7_0_set_priv_inst_fault_state,
5189         .process = gfx_v7_0_priv_inst_irq,
5190 };
5191
5192 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5193 {
5194         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5195         adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5196
5197         adev->gfx.priv_reg_irq.num_types = 1;
5198         adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5199
5200         adev->gfx.priv_inst_irq.num_types = 1;
5201         adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5202 }
5203
5204 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5205 {
5206         /* init asci gds info */
5207         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5208         adev->gds.gws.total_size = 64;
5209         adev->gds.oa.total_size = 16;
5210
5211         if (adev->gds.mem.total_size == 64 * 1024) {
5212                 adev->gds.mem.gfx_partition_size = 4096;
5213                 adev->gds.mem.cs_partition_size = 4096;
5214
5215                 adev->gds.gws.gfx_partition_size = 4;
5216                 adev->gds.gws.cs_partition_size = 4;
5217
5218                 adev->gds.oa.gfx_partition_size = 4;
5219                 adev->gds.oa.cs_partition_size = 1;
5220         } else {
5221                 adev->gds.mem.gfx_partition_size = 1024;
5222                 adev->gds.mem.cs_partition_size = 1024;
5223
5224                 adev->gds.gws.gfx_partition_size = 16;
5225                 adev->gds.gws.cs_partition_size = 16;
5226
5227                 adev->gds.oa.gfx_partition_size = 4;
5228                 adev->gds.oa.cs_partition_size = 4;
5229         }
5230 }
5231
5232
5233 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5234 {
5235         int i, j, k, counter, active_cu_number = 0;
5236         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5237         struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5238         unsigned disable_masks[4 * 2];
5239         u32 ao_cu_num;
5240
5241         if (adev->flags & AMD_IS_APU)
5242                 ao_cu_num = 2;
5243         else
5244                 ao_cu_num = adev->gfx.config.max_cu_per_sh;
5245
5246         memset(cu_info, 0, sizeof(*cu_info));
5247
5248         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5249
5250         mutex_lock(&adev->grbm_idx_mutex);
5251         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5252                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5253                         mask = 1;
5254                         ao_bitmap = 0;
5255                         counter = 0;
5256                         gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
5257                         if (i < 4 && j < 2)
5258                                 gfx_v7_0_set_user_cu_inactive_bitmap(
5259                                         adev, disable_masks[i * 2 + j]);
5260                         bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5261                         cu_info->bitmap[i][j] = bitmap;
5262
5263                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
5264                                 if (bitmap & mask) {
5265                                         if (counter < ao_cu_num)
5266                                                 ao_bitmap |= mask;
5267                                         counter ++;
5268                                 }
5269                                 mask <<= 1;
5270                         }
5271                         active_cu_number += counter;
5272                         if (i < 2 && j < 2)
5273                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5274                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5275                 }
5276         }
5277         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5278         mutex_unlock(&adev->grbm_idx_mutex);
5279
5280         cu_info->number = active_cu_number;
5281         cu_info->ao_cu_mask = ao_cu_mask;
5282         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5283         cu_info->max_waves_per_simd = 10;
5284         cu_info->max_scratch_slots_per_cu = 32;
5285         cu_info->wave_front_size = 64;
5286         cu_info->lds_size = 64;
5287 }
5288
5289 const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
5290 {
5291         .type = AMD_IP_BLOCK_TYPE_GFX,
5292         .major = 7,
5293         .minor = 0,
5294         .rev = 0,
5295         .funcs = &gfx_v7_0_ip_funcs,
5296 };
5297
5298 const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
5299 {
5300         .type = AMD_IP_BLOCK_TYPE_GFX,
5301         .major = 7,
5302         .minor = 1,
5303         .rev = 0,
5304         .funcs = &gfx_v7_0_ip_funcs,
5305 };
5306
5307 const struct amdgpu_ip_block_version gfx_v7_2_ip_block =
5308 {
5309         .type = AMD_IP_BLOCK_TYPE_GFX,
5310         .major = 7,
5311         .minor = 2,
5312         .rev = 0,
5313         .funcs = &gfx_v7_0_ip_funcs,
5314 };
5315
5316 const struct amdgpu_ip_block_version gfx_v7_3_ip_block =
5317 {
5318         .type = AMD_IP_BLOCK_TYPE_GFX,
5319         .major = 7,
5320         .minor = 3,
5321         .rev = 0,
5322         .funcs = &gfx_v7_0_ip_funcs,
5323 };