drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "atom.h"
  34
  35 #include <linux/vga_switcheroo.h>
  36 #include <linux/slab.h>
  37 #include <linux/uaccess.h>
  38 #include <linux/pci.h>
  39 #include <linux/pm_runtime.h>
  40 #include "amdgpu_amdkfd.h"
  41 #include "amdgpu_gem.h"
  42 #include "amdgpu_display.h"
  43 #include "amdgpu_ras.h"
  44
  45 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  46 {
  47         struct amdgpu_gpu_instance *gpu_instance;
  48         int i;
  49
  50         mutex_lock(&mgpu_info.mutex);
  51
  52         for (i = 0; i < mgpu_info.num_gpu; i++) {
  53                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  54                 if (gpu_instance->adev == adev) {
  55                         mgpu_info.gpu_ins[i] =
  56                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  57                         mgpu_info.num_gpu--;
  58                         if (adev->flags & AMD_IS_APU)
  59                                 mgpu_info.num_apu--;
  60                         else
  61                                 mgpu_info.num_dgpu--;
  62                         break;
  63                 }
  64         }
  65
  66         mutex_unlock(&mgpu_info.mutex);
  67 }
  68
  69 /**
  70  * amdgpu_driver_unload_kms - Main unload function for KMS.
  71  *
  72  * @dev: drm dev pointer
  73  *
  74  * This is the main unload function for KMS (all asics).
  75  * Returns 0 on success.
  76  */
  77 void amdgpu_driver_unload_kms(struct drm_device *dev)
  78 {
  79         struct amdgpu_device *adev = drm_to_adev(dev);
  80
  81         if (adev == NULL)
  82                 return;
  83
  84         amdgpu_unregister_gpu_instance(adev);
  85
  86         if (adev->rmmio == NULL)
  87                 return;
  88
  89         if (adev->runpm) {
  90                 pm_runtime_get_sync(dev->dev);
  91                 pm_runtime_forbid(dev->dev);
  92         }
  93
  94         amdgpu_acpi_fini(adev);
  95         amdgpu_device_fini(adev);
  96 }
  97
  98 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
  99 {
 100         struct amdgpu_gpu_instance *gpu_instance;
 101
 102         mutex_lock(&mgpu_info.mutex);
 103
 104         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 105                 DRM_ERROR("Cannot register more gpu instance\n");
 106                 mutex_unlock(&mgpu_info.mutex);
 107                 return;
 108         }
 109
 110         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 111         gpu_instance->adev = adev;
 112         gpu_instance->mgpu_fan_enabled = 0;
 113
 114         mgpu_info.num_gpu++;
 115         if (adev->flags & AMD_IS_APU)
 116                 mgpu_info.num_apu++;
 117         else
 118                 mgpu_info.num_dgpu++;
 119
 120         mutex_unlock(&mgpu_info.mutex);
 121 }
 122
 123 /**
 124  * amdgpu_driver_load_kms - Main load function for KMS.
 125  *
 126  * @adev: pointer to struct amdgpu_device
 127  * @flags: device flags
 128  *
 129  * This is the main load function for KMS (all asics).
 130  * Returns 0 on success, error on failure.
 131  */
 132 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 133 {
 134         struct drm_device *dev;
 135         struct pci_dev *parent;
 136         int r, acpi_status;
 137
 138         dev = adev_to_drm(adev);
 139
 140         if (amdgpu_has_atpx() &&
 141             (amdgpu_is_atpx_hybrid() ||
 142              amdgpu_has_atpx_dgpu_power_cntl()) &&
 143             ((flags & AMD_IS_APU) == 0) &&
 144             !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
 145                 flags |= AMD_IS_PX;
 146
 147         parent = pci_upstream_bridge(adev->pdev);
 148         adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
 149
 150         /* amdgpu_device_init should report only fatal error
 151          * like memory allocation failure or iomapping failure,
 152          * or memory manager initialization failure, it must
 153          * properly initialize the GPU MC controller and permit
 154          * VRAM allocation
 155          */
 156         r = amdgpu_device_init(adev, flags);
 157         if (r) {
 158                 dev_err(dev->dev, "Fatal error during GPU init\n");
 159                 goto out;
 160         }
 161
 162         if (amdgpu_device_supports_atpx(dev) &&
 163             (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */
 164                 adev->runpm = true;
 165                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 166         } else if (amdgpu_device_supports_boco(dev) &&
 167                    (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
 168                 adev->runpm = true;
 169                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 170         } else if (amdgpu_device_supports_baco(dev) &&
 171                    (amdgpu_runtime_pm != 0)) {
 172                 switch (adev->asic_type) {
 173                 case CHIP_VEGA20:
 174                 case CHIP_ARCTURUS:
 175                         /* enable runpm if runpm=1 */
 176                         if (amdgpu_runtime_pm > 0)
 177                                 adev->runpm = true;
 178                         break;
 179                 case CHIP_VEGA10:
 180                         /* turn runpm on if noretry=0 */
 181                         if (!adev->gmc.noretry)
 182                                 adev->runpm = true;
 183                         break;
 184                 default:
 185                         /* enable runpm on CI+ */
 186                         adev->runpm = true;
 187                         break;
 188                 }
 189                 if (adev->runpm)
 190                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 191         }
 192
 193         /* Call ACPI methods: require modeset init
 194          * but failure is not fatal
 195          */
 196
 197         acpi_status = amdgpu_acpi_init(adev);
 198         if (acpi_status)
 199                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 200
 201         if (adev->runpm) {
 202                 /* only need to skip on ATPX */
 203                 if (amdgpu_device_supports_atpx(dev) &&
 204                     !amdgpu_is_atpx_hybrid())
 205                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 206                 /* we want direct complete for BOCO */
 207                 if ((amdgpu_device_supports_atpx(dev) &&
 208                     amdgpu_is_atpx_hybrid()) ||
 209                     amdgpu_device_supports_boco(dev))
 210                         dev_pm_set_driver_flags(dev->dev, DPM_FLAG_SMART_PREPARE |
 211                                                 DPM_FLAG_SMART_SUSPEND |
 212                                                 DPM_FLAG_MAY_SKIP_RESUME);
 213                 pm_runtime_use_autosuspend(dev->dev);
 214                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 215                 pm_runtime_allow(dev->dev);
 216                 pm_runtime_mark_last_busy(dev->dev);
 217                 pm_runtime_put_autosuspend(dev->dev);
 218         }
 219
 220 out:
 221         if (r) {
 222                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 223                 if (adev->rmmio && adev->runpm)
 224                         pm_runtime_put_noidle(dev->dev);
 225                 amdgpu_driver_unload_kms(dev);
 226         }
 227
 228         return r;
 229 }
 230
 231 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 232                                 struct drm_amdgpu_query_fw *query_fw,
 233                                 struct amdgpu_device *adev)
 234 {
 235         switch (query_fw->fw_type) {
 236         case AMDGPU_INFO_FW_VCE:
 237                 fw_info->ver = adev->vce.fw_version;
 238                 fw_info->feature = adev->vce.fb_version;
 239                 break;
 240         case AMDGPU_INFO_FW_UVD:
 241                 fw_info->ver = adev->uvd.fw_version;
 242                 fw_info->feature = 0;
 243                 break;
 244         case AMDGPU_INFO_FW_VCN:
 245                 fw_info->ver = adev->vcn.fw_version;
 246                 fw_info->feature = 0;
 247                 break;
 248         case AMDGPU_INFO_FW_GMC:
 249                 fw_info->ver = adev->gmc.fw_version;
 250                 fw_info->feature = 0;
 251                 break;
 252         case AMDGPU_INFO_FW_GFX_ME:
 253                 fw_info->ver = adev->gfx.me_fw_version;
 254                 fw_info->feature = adev->gfx.me_feature_version;
 255                 break;
 256         case AMDGPU_INFO_FW_GFX_PFP:
 257                 fw_info->ver = adev->gfx.pfp_fw_version;
 258                 fw_info->feature = adev->gfx.pfp_feature_version;
 259                 break;
 260         case AMDGPU_INFO_FW_GFX_CE:
 261                 fw_info->ver = adev->gfx.ce_fw_version;
 262                 fw_info->feature = adev->gfx.ce_feature_version;
 263                 break;
 264         case AMDGPU_INFO_FW_GFX_RLC:
 265                 fw_info->ver = adev->gfx.rlc_fw_version;
 266                 fw_info->feature = adev->gfx.rlc_feature_version;
 267                 break;
 268         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 269                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 270                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 271                 break;
 272         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 273                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 274                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 275                 break;
 276         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 277                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 278                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 279                 break;
 280         case AMDGPU_INFO_FW_GFX_MEC:
 281                 if (query_fw->index == 0) {
 282                         fw_info->ver = adev->gfx.mec_fw_version;
 283                         fw_info->feature = adev->gfx.mec_feature_version;
 284                 } else if (query_fw->index == 1) {
 285                         fw_info->ver = adev->gfx.mec2_fw_version;
 286                         fw_info->feature = adev->gfx.mec2_feature_version;
 287                 } else
 288                         return -EINVAL;
 289                 break;
 290         case AMDGPU_INFO_FW_SMC:
 291                 fw_info->ver = adev->pm.fw_version;
 292                 fw_info->feature = 0;
 293                 break;
 294         case AMDGPU_INFO_FW_TA:
 295                 switch (query_fw->index) {
 296                 case TA_FW_TYPE_PSP_XGMI:
 297                         fw_info->ver = adev->psp.ta_fw_version;
 298                         fw_info->feature = adev->psp.ta_xgmi_ucode_version;
 299                         break;
 300                 case TA_FW_TYPE_PSP_RAS:
 301                         fw_info->ver = adev->psp.ta_fw_version;
 302                         fw_info->feature = adev->psp.ta_ras_ucode_version;
 303                         break;
 304                 case TA_FW_TYPE_PSP_HDCP:
 305                         fw_info->ver = adev->psp.ta_fw_version;
 306                         fw_info->feature = adev->psp.ta_hdcp_ucode_version;
 307                         break;
 308                 case TA_FW_TYPE_PSP_DTM:
 309                         fw_info->ver = adev->psp.ta_fw_version;
 310                         fw_info->feature = adev->psp.ta_dtm_ucode_version;
 311                         break;
 312                 case TA_FW_TYPE_PSP_RAP:
 313                         fw_info->ver = adev->psp.ta_fw_version;
 314                         fw_info->feature = adev->psp.ta_rap_ucode_version;
 315                         break;
 316                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 317                         fw_info->ver = adev->psp.ta_fw_version;
 318                         fw_info->feature = adev->psp.ta_securedisplay_ucode_version;
 319                         break;
 320                 default:
 321                         return -EINVAL;
 322                 }
 323                 break;
 324         case AMDGPU_INFO_FW_SDMA:
 325                 if (query_fw->index >= adev->sdma.num_instances)
 326                         return -EINVAL;
 327                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 328                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 329                 break;
 330         case AMDGPU_INFO_FW_SOS:
 331                 fw_info->ver = adev->psp.sos_fw_version;
 332                 fw_info->feature = adev->psp.sos_feature_version;
 333                 break;
 334         case AMDGPU_INFO_FW_ASD:
 335                 fw_info->ver = adev->psp.asd_fw_version;
 336                 fw_info->feature = adev->psp.asd_feature_version;
 337                 break;
 338         case AMDGPU_INFO_FW_DMCU:
 339                 fw_info->ver = adev->dm.dmcu_fw_version;
 340                 fw_info->feature = 0;
 341                 break;
 342         case AMDGPU_INFO_FW_DMCUB:
 343                 fw_info->ver = adev->dm.dmcub_fw_version;
 344                 fw_info->feature = 0;
 345                 break;
 346         case AMDGPU_INFO_FW_TOC:
 347                 fw_info->ver = adev->psp.toc_fw_version;
 348                 fw_info->feature = adev->psp.toc_feature_version;
 349                 break;
 350         default:
 351                 return -EINVAL;
 352         }
 353         return 0;
 354 }
 355
 356 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 357                              struct drm_amdgpu_info *info,
 358                              struct drm_amdgpu_info_hw_ip *result)
 359 {
 360         uint32_t ib_start_alignment = 0;
 361         uint32_t ib_size_alignment = 0;
 362         enum amd_ip_block_type type;
 363         unsigned int num_rings = 0;
 364         unsigned int i, j;
 365
 366         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 367                 return -EINVAL;
 368
 369         switch (info->query_hw_ip.type) {
 370         case AMDGPU_HW_IP_GFX:
 371                 type = AMD_IP_BLOCK_TYPE_GFX;
 372                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 373                         if (adev->gfx.gfx_ring[i].sched.ready)
 374                                 ++num_rings;
 375                 ib_start_alignment = 32;
 376                 ib_size_alignment = 32;
 377                 break;
 378         case AMDGPU_HW_IP_COMPUTE:
 379                 type = AMD_IP_BLOCK_TYPE_GFX;
 380                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 381                         if (adev->gfx.compute_ring[i].sched.ready)
 382                                 ++num_rings;
 383                 ib_start_alignment = 32;
 384                 ib_size_alignment = 32;
 385                 break;
 386         case AMDGPU_HW_IP_DMA:
 387                 type = AMD_IP_BLOCK_TYPE_SDMA;
 388                 for (i = 0; i < adev->sdma.num_instances; i++)
 389                         if (adev->sdma.instance[i].ring.sched.ready)
 390                                 ++num_rings;
 391                 ib_start_alignment = 256;
 392                 ib_size_alignment = 4;
 393                 break;
 394         case AMDGPU_HW_IP_UVD:
 395                 type = AMD_IP_BLOCK_TYPE_UVD;
 396                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 397                         if (adev->uvd.harvest_config & (1 << i))
 398                                 continue;
 399
 400                         if (adev->uvd.inst[i].ring.sched.ready)
 401                                 ++num_rings;
 402                 }
 403                 ib_start_alignment = 64;
 404                 ib_size_alignment = 64;
 405                 break;
 406         case AMDGPU_HW_IP_VCE:
 407                 type = AMD_IP_BLOCK_TYPE_VCE;
 408                 for (i = 0; i < adev->vce.num_rings; i++)
 409                         if (adev->vce.ring[i].sched.ready)
 410                                 ++num_rings;
 411                 ib_start_alignment = 4;
 412                 ib_size_alignment = 1;
 413                 break;
 414         case AMDGPU_HW_IP_UVD_ENC:
 415                 type = AMD_IP_BLOCK_TYPE_UVD;
 416                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 417                         if (adev->uvd.harvest_config & (1 << i))
 418                                 continue;
 419
 420                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 421                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 422                                         ++num_rings;
 423                 }
 424                 ib_start_alignment = 64;
 425                 ib_size_alignment = 64;
 426                 break;
 427         case AMDGPU_HW_IP_VCN_DEC:
 428                 type = AMD_IP_BLOCK_TYPE_VCN;
 429                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 430                         if (adev->uvd.harvest_config & (1 << i))
 431                                 continue;
 432
 433                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 434                                 ++num_rings;
 435                 }
 436                 ib_start_alignment = 16;
 437                 ib_size_alignment = 16;
 438                 break;
 439         case AMDGPU_HW_IP_VCN_ENC:
 440                 type = AMD_IP_BLOCK_TYPE_VCN;
 441                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 442                         if (adev->uvd.harvest_config & (1 << i))
 443                                 continue;
 444
 445                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 446                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 447                                         ++num_rings;
 448                 }
 449                 ib_start_alignment = 64;
 450                 ib_size_alignment = 1;
 451                 break;
 452         case AMDGPU_HW_IP_VCN_JPEG:
 453                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 454                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 455
 456                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 457                         if (adev->jpeg.harvest_config & (1 << i))
 458                                 continue;
 459
 460                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 461                                 ++num_rings;
 462                 }
 463                 ib_start_alignment = 16;
 464                 ib_size_alignment = 16;
 465                 break;
 466         default:
 467                 return -EINVAL;
 468         }
 469
 470         for (i = 0; i < adev->num_ip_blocks; i++)
 471                 if (adev->ip_blocks[i].version->type == type &&
 472                     adev->ip_blocks[i].status.valid)
 473                         break;
 474
 475         if (i == adev->num_ip_blocks)
 476                 return 0;
 477
 478         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 479                         num_rings);
 480
 481         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 482         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 483         result->capabilities_flags = 0;
 484         result->available_rings = (1 << num_rings) - 1;
 485         result->ib_start_alignment = ib_start_alignment;
 486         result->ib_size_alignment = ib_size_alignment;
 487         return 0;
 488 }
 489
 490 /*
 491  * Userspace get information ioctl
 492  */
 493 /**
 494  * amdgpu_info_ioctl - answer a device specific request.
 495  *
 496  * @dev: drm device pointer
 497  * @data: request object
 498  * @filp: drm filp
 499  *
 500  * This function is used to pass device specific parameters to the userspace
 501  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 502  * etc. (all asics).
 503  * Returns 0 on success, -EINVAL on failure.
 504  */
 505 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 506 {
 507         struct amdgpu_device *adev = drm_to_adev(dev);
 508         struct drm_amdgpu_info *info = data;
 509         struct amdgpu_mode_info *minfo = &adev->mode_info;
 510         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 511         uint32_t size = info->return_size;
 512         struct drm_crtc *crtc;
 513         uint32_t ui32 = 0;
 514         uint64_t ui64 = 0;
 515         int i, found;
 516         int ui32_size = sizeof(ui32);
 517
 518         if (!info->return_size || !info->return_pointer)
 519                 return -EINVAL;
 520
 521         switch (info->query) {
 522         case AMDGPU_INFO_ACCEL_WORKING:
 523                 ui32 = adev->accel_working;
 524                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 525         case AMDGPU_INFO_CRTC_FROM_ID:
 526                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 527                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 528                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 529                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 530                                 ui32 = amdgpu_crtc->crtc_id;
 531                                 found = 1;
 532                                 break;
 533                         }
 534                 }
 535                 if (!found) {
 536                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 537                         return -EINVAL;
 538                 }
 539                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 540         case AMDGPU_INFO_HW_IP_INFO: {
 541                 struct drm_amdgpu_info_hw_ip ip = {};
 542                 int ret;
 543
 544                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 545                 if (ret)
 546                         return ret;
 547
 548                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 549                 return ret ? -EFAULT : 0;
 550         }
 551         case AMDGPU_INFO_HW_IP_COUNT: {
 552                 enum amd_ip_block_type type;
 553                 uint32_t count = 0;
 554
 555                 switch (info->query_hw_ip.type) {
 556                 case AMDGPU_HW_IP_GFX:
 557                         type = AMD_IP_BLOCK_TYPE_GFX;
 558                         break;
 559                 case AMDGPU_HW_IP_COMPUTE:
 560                         type = AMD_IP_BLOCK_TYPE_GFX;
 561                         break;
 562                 case AMDGPU_HW_IP_DMA:
 563                         type = AMD_IP_BLOCK_TYPE_SDMA;
 564                         break;
 565                 case AMDGPU_HW_IP_UVD:
 566                         type = AMD_IP_BLOCK_TYPE_UVD;
 567                         break;
 568                 case AMDGPU_HW_IP_VCE:
 569                         type = AMD_IP_BLOCK_TYPE_VCE;
 570                         break;
 571                 case AMDGPU_HW_IP_UVD_ENC:
 572                         type = AMD_IP_BLOCK_TYPE_UVD;
 573                         break;
 574                 case AMDGPU_HW_IP_VCN_DEC:
 575                 case AMDGPU_HW_IP_VCN_ENC:
 576                         type = AMD_IP_BLOCK_TYPE_VCN;
 577                         break;
 578                 case AMDGPU_HW_IP_VCN_JPEG:
 579                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 580                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 581                         break;
 582                 default:
 583                         return -EINVAL;
 584                 }
 585
 586                 for (i = 0; i < adev->num_ip_blocks; i++)
 587                         if (adev->ip_blocks[i].version->type == type &&
 588                             adev->ip_blocks[i].status.valid &&
 589                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 590                                 count++;
 591
 592                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 593         }
 594         case AMDGPU_INFO_TIMESTAMP:
 595                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 596                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 597         case AMDGPU_INFO_FW_VERSION: {
 598                 struct drm_amdgpu_info_firmware fw_info;
 599                 int ret;
 600
 601                 /* We only support one instance of each IP block right now. */
 602                 if (info->query_fw.ip_instance != 0)
 603                         return -EINVAL;
 604
 605                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 606                 if (ret)
 607                         return ret;
 608
 609                 return copy_to_user(out, &fw_info,
 610                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 611         }
 612         case AMDGPU_INFO_NUM_BYTES_MOVED:
 613                 ui64 = atomic64_read(&adev->num_bytes_moved);
 614                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 615         case AMDGPU_INFO_NUM_EVICTIONS:
 616                 ui64 = atomic64_read(&adev->num_evictions);
 617                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 618         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 619                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 620                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 621         case AMDGPU_INFO_VRAM_USAGE:
 622                 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 623                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 624         case AMDGPU_INFO_VIS_VRAM_USAGE:
 625                 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
 626                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 627         case AMDGPU_INFO_GTT_USAGE:
 628                 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
 629                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 630         case AMDGPU_INFO_GDS_CONFIG: {
 631                 struct drm_amdgpu_info_gds gds_info;
 632
 633                 memset(&gds_info, 0, sizeof(gds_info));
 634                 gds_info.compute_partition_size = adev->gds.gds_size;
 635                 gds_info.gds_total_size = adev->gds.gds_size;
 636                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 637                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 638                 return copy_to_user(out, &gds_info,
 639                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 640         }
 641         case AMDGPU_INFO_VRAM_GTT: {
 642                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 643
 644                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 645                         atomic64_read(&adev->vram_pin_size) -
 646                         AMDGPU_VM_RESERVED_VRAM;
 647                 vram_gtt.vram_cpu_accessible_size =
 648                         min(adev->gmc.visible_vram_size -
 649                             atomic64_read(&adev->visible_pin_size),
 650                             vram_gtt.vram_size);
 651                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 652                 vram_gtt.gtt_size *= PAGE_SIZE;
 653                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 654                 return copy_to_user(out, &vram_gtt,
 655                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 656         }
 657         case AMDGPU_INFO_MEMORY: {
 658                 struct drm_amdgpu_memory_info mem;
 659                 struct ttm_resource_manager *vram_man =
 660                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 661                 struct ttm_resource_manager *gtt_man =
 662                         ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
 663                 memset(&mem, 0, sizeof(mem));
 664                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 665                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 666                         atomic64_read(&adev->vram_pin_size) -
 667                         AMDGPU_VM_RESERVED_VRAM;
 668                 mem.vram.heap_usage =
 669                         amdgpu_vram_mgr_usage(vram_man);
 670                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 671
 672                 mem.cpu_accessible_vram.total_heap_size =
 673                         adev->gmc.visible_vram_size;
 674                 mem.cpu_accessible_vram.usable_heap_size =
 675                         min(adev->gmc.visible_vram_size -
 676                             atomic64_read(&adev->visible_pin_size),
 677                             mem.vram.usable_heap_size);
 678                 mem.cpu_accessible_vram.heap_usage =
 679                         amdgpu_vram_mgr_vis_usage(vram_man);
 680                 mem.cpu_accessible_vram.max_allocation =
 681                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 682
 683                 mem.gtt.total_heap_size = gtt_man->size;
 684                 mem.gtt.total_heap_size *= PAGE_SIZE;
 685                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 686                         atomic64_read(&adev->gart_pin_size);
 687                 mem.gtt.heap_usage =
 688                         amdgpu_gtt_mgr_usage(gtt_man);
 689                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 690
 691                 return copy_to_user(out, &mem,
 692                                     min((size_t)size, sizeof(mem)))
 693                                     ? -EFAULT : 0;
 694         }
 695         case AMDGPU_INFO_READ_MMR_REG: {
 696                 unsigned n, alloc_size;
 697                 uint32_t *regs;
 698                 unsigned se_num = (info->read_mmr_reg.instance >>
 699                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 700                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 701                 unsigned sh_num = (info->read_mmr_reg.instance >>
 702                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 703                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 704
 705                 /* set full masks if the userspace set all bits
 706                  * in the bitfields */
 707                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 708                         se_num = 0xffffffff;
 709                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 710                         return -EINVAL;
 711                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 712                         sh_num = 0xffffffff;
 713                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 714                         return -EINVAL;
 715
 716                 if (info->read_mmr_reg.count > 128)
 717                         return -EINVAL;
 718
 719                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 720                 if (!regs)
 721                         return -ENOMEM;
 722                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 723
 724                 amdgpu_gfx_off_ctrl(adev, false);
 725                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 726                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 727                                                       info->read_mmr_reg.dword_offset + i,
 728                                                       &regs[i])) {
 729                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 730                                               info->read_mmr_reg.dword_offset + i);
 731                                 kfree(regs);
 732                                 amdgpu_gfx_off_ctrl(adev, true);
 733                                 return -EFAULT;
 734                         }
 735                 }
 736                 amdgpu_gfx_off_ctrl(adev, true);
 737                 n = copy_to_user(out, regs, min(size, alloc_size));
 738                 kfree(regs);
 739                 return n ? -EFAULT : 0;
 740         }
 741         case AMDGPU_INFO_DEV_INFO: {
 742                 struct drm_amdgpu_info_device *dev_info;
 743                 uint64_t vm_size;
 744                 int ret;
 745
 746                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 747                 if (!dev_info)
 748                         return -ENOMEM;
 749
 750                 dev_info->device_id = adev->pdev->device;
 751                 dev_info->chip_rev = adev->rev_id;
 752                 dev_info->external_rev = adev->external_rev_id;
 753                 dev_info->pci_rev = adev->pdev->revision;
 754                 dev_info->family = adev->family;
 755                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 756                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 757                 /* return all clocks in KHz */
 758                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 759                 if (adev->pm.dpm_enabled) {
 760                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 761                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 762                 } else {
 763                         dev_info->max_engine_clock = adev->clock.default_sclk * 10;
 764                         dev_info->max_memory_clock = adev->clock.default_mclk * 10;
 765                 }
 766                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 767                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 768                         adev->gfx.config.max_shader_engines;
 769                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 770                 dev_info->_pad = 0;
 771                 dev_info->ids_flags = 0;
 772                 if (adev->flags & AMD_IS_APU)
 773                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 774                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 775                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 776                 if (amdgpu_is_tmz(adev))
 777                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 778
 779                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 780                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 781
 782                 /* Older VCE FW versions are buggy and can handle only 40bits */
 783                 if (adev->vce.fw_version &&
 784                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 785                         vm_size = min(vm_size, 1ULL << 40);
 786
 787                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 788                 dev_info->virtual_address_max =
 789                         min(vm_size, AMDGPU_GMC_HOLE_START);
 790
 791                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 792                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 793                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 794                 }
 795                 dev_info->virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 796                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 797                 dev_info->gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 798                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 799                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 800                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 801                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 802                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 803                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 804                        sizeof(adev->gfx.cu_info.bitmap));
 805                 dev_info->vram_type = adev->gmc.vram_type;
 806                 dev_info->vram_bit_width = adev->gmc.vram_width;
 807                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 808                 dev_info->gc_double_offchip_lds_buf =
 809                         adev->gfx.config.double_offchip_lds_buf;
 810                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 811                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 812                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 813                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 814                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 815                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 816                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 817
 818                 if (adev->family >= AMDGPU_FAMILY_NV)
 819                         dev_info->pa_sc_tile_steering_override =
 820                                 adev->gfx.config.pa_sc_tile_steering_override;
 821
 822                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 823
 824                 ret = copy_to_user(out, dev_info,
 825                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 826                 kfree(dev_info);
 827                 return ret;
 828         }
 829         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 830                 unsigned i;
 831                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 832                 struct amd_vce_state *vce_state;
 833
 834                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 835                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 836                         if (vce_state) {
 837                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 838                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 839                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 840                                 vce_clk_table.num_valid_entries++;
 841                         }
 842                 }
 843
 844                 return copy_to_user(out, &vce_clk_table,
 845                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 846         }
 847         case AMDGPU_INFO_VBIOS: {
 848                 uint32_t bios_size = adev->bios_size;
 849
 850                 switch (info->vbios_info.type) {
 851                 case AMDGPU_INFO_VBIOS_SIZE:
 852                         return copy_to_user(out, &bios_size,
 853                                         min((size_t)size, sizeof(bios_size)))
 854                                         ? -EFAULT : 0;
 855                 case AMDGPU_INFO_VBIOS_IMAGE: {
 856                         uint8_t *bios;
 857                         uint32_t bios_offset = info->vbios_info.offset;
 858
 859                         if (bios_offset >= bios_size)
 860                                 return -EINVAL;
 861
 862                         bios = adev->bios + bios_offset;
 863                         return copy_to_user(out, bios,
 864                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 865                                         ? -EFAULT : 0;
 866                 }
 867                 default:
 868                         DRM_DEBUG_KMS("Invalid request %d\n",
 869                                         info->vbios_info.type);
 870                         return -EINVAL;
 871                 }
 872         }
 873         case AMDGPU_INFO_NUM_HANDLES: {
 874                 struct drm_amdgpu_info_num_handles handle;
 875
 876                 switch (info->query_hw_ip.type) {
 877                 case AMDGPU_HW_IP_UVD:
 878                         /* Starting Polaris, we support unlimited UVD handles */
 879                         if (adev->asic_type < CHIP_POLARIS10) {
 880                                 handle.uvd_max_handles = adev->uvd.max_handles;
 881                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 882
 883                                 return copy_to_user(out, &handle,
 884                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 885                         } else {
 886                                 return -ENODATA;
 887                         }
 888
 889                         break;
 890                 default:
 891                         return -EINVAL;
 892                 }
 893         }
 894         case AMDGPU_INFO_SENSOR: {
 895                 if (!adev->pm.dpm_enabled)
 896                         return -ENOENT;
 897
 898                 switch (info->sensor_info.type) {
 899                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 900                         /* get sclk in Mhz */
 901                         if (amdgpu_dpm_read_sensor(adev,
 902                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 903                                                    (void *)&ui32, &ui32_size)) {
 904                                 return -EINVAL;
 905                         }
 906                         ui32 /= 100;
 907                         break;
 908                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 909                         /* get mclk in Mhz */
 910                         if (amdgpu_dpm_read_sensor(adev,
 911                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 912                                                    (void *)&ui32, &ui32_size)) {
 913                                 return -EINVAL;
 914                         }
 915                         ui32 /= 100;
 916                         break;
 917                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 918                         /* get temperature in millidegrees C */
 919                         if (amdgpu_dpm_read_sensor(adev,
 920                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 921                                                    (void *)&ui32, &ui32_size)) {
 922                                 return -EINVAL;
 923                         }
 924                         break;
 925                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 926                         /* get GPU load */
 927                         if (amdgpu_dpm_read_sensor(adev,
 928                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 929                                                    (void *)&ui32, &ui32_size)) {
 930                                 return -EINVAL;
 931                         }
 932                         break;
 933                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 934                         /* get average GPU power */
 935                         if (amdgpu_dpm_read_sensor(adev,
 936                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 937                                                    (void *)&ui32, &ui32_size)) {
 938                                 return -EINVAL;
 939                         }
 940                         ui32 >>= 8;
 941                         break;
 942                 case AMDGPU_INFO_SENSOR_VDDNB:
 943                         /* get VDDNB in millivolts */
 944                         if (amdgpu_dpm_read_sensor(adev,
 945                                                    AMDGPU_PP_SENSOR_VDDNB,
 946                                                    (void *)&ui32, &ui32_size)) {
 947                                 return -EINVAL;
 948                         }
 949                         break;
 950                 case AMDGPU_INFO_SENSOR_VDDGFX:
 951                         /* get VDDGFX in millivolts */
 952                         if (amdgpu_dpm_read_sensor(adev,
 953                                                    AMDGPU_PP_SENSOR_VDDGFX,
 954                                                    (void *)&ui32, &ui32_size)) {
 955                                 return -EINVAL;
 956                         }
 957                         break;
 958                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 959                         /* get stable pstate sclk in Mhz */
 960                         if (amdgpu_dpm_read_sensor(adev,
 961                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 962                                                    (void *)&ui32, &ui32_size)) {
 963                                 return -EINVAL;
 964                         }
 965                         ui32 /= 100;
 966                         break;
 967                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 968                         /* get stable pstate mclk in Mhz */
 969                         if (amdgpu_dpm_read_sensor(adev,
 970                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 971                                                    (void *)&ui32, &ui32_size)) {
 972                                 return -EINVAL;
 973                         }
 974                         ui32 /= 100;
 975                         break;
 976                 default:
 977                         DRM_DEBUG_KMS("Invalid request %d\n",
 978                                       info->sensor_info.type);
 979                         return -EINVAL;
 980                 }
 981                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 982         }
 983         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 984                 ui32 = atomic_read(&adev->vram_lost_counter);
 985                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 986         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
 987                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 988                 uint64_t ras_mask;
 989
 990                 if (!ras)
 991                         return -EINVAL;
 992                 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
 993
 994                 return copy_to_user(out, &ras_mask,
 995                                 min_t(u64, size, sizeof(ras_mask))) ?
 996                         -EFAULT : 0;
 997         }
 998         case AMDGPU_INFO_VIDEO_CAPS: {
 999                 const struct amdgpu_video_codecs *codecs;
1000                 struct drm_amdgpu_info_video_caps *caps;
1001                 int r;
1002
1003                 switch (info->video_cap.type) {
1004                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1005                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1006                         if (r)
1007                                 return -EINVAL;
1008                         break;
1009                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1010                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1011                         if (r)
1012                                 return -EINVAL;
1013                         break;
1014                 default:
1015                         DRM_DEBUG_KMS("Invalid request %d\n",
1016                                       info->video_cap.type);
1017                         return -EINVAL;
1018                 }
1019
1020                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1021                 if (!caps)
1022                         return -ENOMEM;
1023
1024                 for (i = 0; i < codecs->codec_count; i++) {
1025                         int idx = codecs->codec_array[i].codec_type;
1026
1027                         switch (idx) {
1028                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1029                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1030                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1031                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1032                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1033                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1034                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1035                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1036                                 caps->codec_info[idx].valid = 1;
1037                                 caps->codec_info[idx].max_width =
1038                                         codecs->codec_array[i].max_width;
1039                                 caps->codec_info[idx].max_height =
1040                                         codecs->codec_array[i].max_height;
1041                                 caps->codec_info[idx].max_pixels_per_frame =
1042                                         codecs->codec_array[i].max_pixels_per_frame;
1043                                 caps->codec_info[idx].max_level =
1044                                         codecs->codec_array[i].max_level;
1045                                 break;
1046                         default:
1047                                 break;
1048                         }
1049                 }
1050                 r = copy_to_user(out, caps,
1051                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1052                 kfree(caps);
1053                 return r;
1054         }
1055         default:
1056                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1057                 return -EINVAL;
1058         }
1059         return 0;
1060 }
1061
1062
1063 /*
1064  * Outdated mess for old drm with Xorg being in charge (void function now).
1065  */
1066 /**
1067  * amdgpu_driver_lastclose_kms - drm callback for last close
1068  *
1069  * @dev: drm dev pointer
1070  *
1071  * Switch vga_switcheroo state after last close (all asics).
1072  */
1073 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1074 {
1075         drm_fb_helper_lastclose(dev);
1076         vga_switcheroo_process_delayed_switch();
1077 }
1078
1079 /**
1080  * amdgpu_driver_open_kms - drm callback for open
1081  *
1082  * @dev: drm dev pointer
1083  * @file_priv: drm file
1084  *
1085  * On device open, init vm on cayman+ (all asics).
1086  * Returns 0 on success, error on failure.
1087  */
1088 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1089 {
1090         struct amdgpu_device *adev = drm_to_adev(dev);
1091         struct amdgpu_fpriv *fpriv;
1092         int r, pasid;
1093
1094         /* Ensure IB tests are run on ring */
1095         flush_delayed_work(&adev->delayed_init_work);
1096
1097
1098         if (amdgpu_ras_intr_triggered()) {
1099                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1100                 return -EHWPOISON;
1101         }
1102
1103         file_priv->driver_priv = NULL;
1104
1105         r = pm_runtime_get_sync(dev->dev);
1106         if (r < 0)
1107                 goto pm_put;
1108
1109         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1110         if (unlikely(!fpriv)) {
1111                 r = -ENOMEM;
1112                 goto out_suspend;
1113         }
1114
1115         pasid = amdgpu_pasid_alloc(16);
1116         if (pasid < 0) {
1117                 dev_warn(adev->dev, "No more PASIDs available!");
1118                 pasid = 0;
1119         }
1120         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
1121         if (r)
1122                 goto error_pasid;
1123
1124         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1125         if (!fpriv->prt_va) {
1126                 r = -ENOMEM;
1127                 goto error_vm;
1128         }
1129
1130         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1131                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1132
1133                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1134                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1135                 if (r)
1136                         goto error_vm;
1137         }
1138
1139         mutex_init(&fpriv->bo_list_lock);
1140         idr_init(&fpriv->bo_list_handles);
1141
1142         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1143
1144         file_priv->driver_priv = fpriv;
1145         goto out_suspend;
1146
1147 error_vm:
1148         amdgpu_vm_fini(adev, &fpriv->vm);
1149
1150 error_pasid:
1151         if (pasid)
1152                 amdgpu_pasid_free(pasid);
1153
1154         kfree(fpriv);
1155
1156 out_suspend:
1157         pm_runtime_mark_last_busy(dev->dev);
1158 pm_put:
1159         pm_runtime_put_autosuspend(dev->dev);
1160
1161         return r;
1162 }
1163
1164 /**
1165  * amdgpu_driver_postclose_kms - drm callback for post close
1166  *
1167  * @dev: drm dev pointer
1168  * @file_priv: drm file
1169  *
1170  * On device post close, tear down vm on cayman+ (all asics).
1171  */
1172 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1173                                  struct drm_file *file_priv)
1174 {
1175         struct amdgpu_device *adev = drm_to_adev(dev);
1176         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1177         struct amdgpu_bo_list *list;
1178         struct amdgpu_bo *pd;
1179         u32 pasid;
1180         int handle;
1181
1182         if (!fpriv)
1183                 return;
1184
1185         pm_runtime_get_sync(dev->dev);
1186
1187         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1188                 amdgpu_uvd_free_handles(adev, file_priv);
1189         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1190                 amdgpu_vce_free_handles(adev, file_priv);
1191
1192         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1193
1194         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1195                 /* TODO: how to handle reserve failure */
1196                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1197                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1198                 fpriv->csa_va = NULL;
1199                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1200         }
1201
1202         pasid = fpriv->vm.pasid;
1203         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1204
1205         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1206         amdgpu_vm_fini(adev, &fpriv->vm);
1207
1208         if (pasid)
1209                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1210         amdgpu_bo_unref(&pd);
1211
1212         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1213                 amdgpu_bo_list_put(list);
1214
1215         idr_destroy(&fpriv->bo_list_handles);
1216         mutex_destroy(&fpriv->bo_list_lock);
1217
1218         kfree(fpriv);
1219         file_priv->driver_priv = NULL;
1220
1221         pm_runtime_mark_last_busy(dev->dev);
1222         pm_runtime_put_autosuspend(dev->dev);
1223 }
1224
1225 /*
1226  * VBlank related functions.
1227  */
1228 /**
1229  * amdgpu_get_vblank_counter_kms - get frame count
1230  *
1231  * @crtc: crtc to get the frame count from
1232  *
1233  * Gets the frame count on the requested crtc (all asics).
1234  * Returns frame count on success, -EINVAL on failure.
1235  */
1236 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1237 {
1238         struct drm_device *dev = crtc->dev;
1239         unsigned int pipe = crtc->index;
1240         struct amdgpu_device *adev = drm_to_adev(dev);
1241         int vpos, hpos, stat;
1242         u32 count;
1243
1244         if (pipe >= adev->mode_info.num_crtc) {
1245                 DRM_ERROR("Invalid crtc %u\n", pipe);
1246                 return -EINVAL;
1247         }
1248
1249         /* The hw increments its frame counter at start of vsync, not at start
1250          * of vblank, as is required by DRM core vblank counter handling.
1251          * Cook the hw count here to make it appear to the caller as if it
1252          * incremented at start of vblank. We measure distance to start of
1253          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1254          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1255          * result by 1 to give the proper appearance to caller.
1256          */
1257         if (adev->mode_info.crtcs[pipe]) {
1258                 /* Repeat readout if needed to provide stable result if
1259                  * we cross start of vsync during the queries.
1260                  */
1261                 do {
1262                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1263                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1264                          * vpos as distance to start of vblank, instead of
1265                          * regular vertical scanout pos.
1266                          */
1267                         stat = amdgpu_display_get_crtc_scanoutpos(
1268                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1269                                 &vpos, &hpos, NULL, NULL,
1270                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1271                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1272
1273                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1274                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1275                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1276                 } else {
1277                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1278                                       pipe, vpos);
1279
1280                         /* Bump counter if we are at >= leading edge of vblank,
1281                          * but before vsync where vpos would turn negative and
1282                          * the hw counter really increments.
1283                          */
1284                         if (vpos >= 0)
1285                                 count++;
1286                 }
1287         } else {
1288                 /* Fallback to use value as is. */
1289                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1290                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1291         }
1292
1293         return count;
1294 }
1295
1296 /**
1297  * amdgpu_enable_vblank_kms - enable vblank interrupt
1298  *
1299  * @crtc: crtc to enable vblank interrupt for
1300  *
1301  * Enable the interrupt on the requested crtc (all asics).
1302  * Returns 0 on success, -EINVAL on failure.
1303  */
1304 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1305 {
1306         struct drm_device *dev = crtc->dev;
1307         unsigned int pipe = crtc->index;
1308         struct amdgpu_device *adev = drm_to_adev(dev);
1309         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1310
1311         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1312 }
1313
1314 /**
1315  * amdgpu_disable_vblank_kms - disable vblank interrupt
1316  *
1317  * @crtc: crtc to disable vblank interrupt for
1318  *
1319  * Disable the interrupt on the requested crtc (all asics).
1320  */
1321 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1322 {
1323         struct drm_device *dev = crtc->dev;
1324         unsigned int pipe = crtc->index;
1325         struct amdgpu_device *adev = drm_to_adev(dev);
1326         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1327
1328         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1329 }
1330
1331 /*
1332  * Debugfs info
1333  */
1334 #if defined(CONFIG_DEBUG_FS)
1335
1336 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1337 {
1338         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1339         struct drm_amdgpu_info_firmware fw_info;
1340         struct drm_amdgpu_query_fw query_fw;
1341         struct atom_context *ctx = adev->mode_info.atom_context;
1342         int ret, i;
1343
1344         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1345 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1346                 TA_FW_NAME(XGMI),
1347                 TA_FW_NAME(RAS),
1348                 TA_FW_NAME(HDCP),
1349                 TA_FW_NAME(DTM),
1350                 TA_FW_NAME(RAP),
1351                 TA_FW_NAME(SECUREDISPLAY),
1352 #undef TA_FW_NAME
1353         };
1354
1355         /* VCE */
1356         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1357         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1358         if (ret)
1359                 return ret;
1360         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1361                    fw_info.feature, fw_info.ver);
1362
1363         /* UVD */
1364         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1365         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1366         if (ret)
1367                 return ret;
1368         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1369                    fw_info.feature, fw_info.ver);
1370
1371         /* GMC */
1372         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1373         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1374         if (ret)
1375                 return ret;
1376         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1377                    fw_info.feature, fw_info.ver);
1378
1379         /* ME */
1380         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1381         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1382         if (ret)
1383                 return ret;
1384         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1385                    fw_info.feature, fw_info.ver);
1386
1387         /* PFP */
1388         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1389         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1390         if (ret)
1391                 return ret;
1392         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1393                    fw_info.feature, fw_info.ver);
1394
1395         /* CE */
1396         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1397         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1398         if (ret)
1399                 return ret;
1400         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1401                    fw_info.feature, fw_info.ver);
1402
1403         /* RLC */
1404         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1405         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1406         if (ret)
1407                 return ret;
1408         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1409                    fw_info.feature, fw_info.ver);
1410
1411         /* RLC SAVE RESTORE LIST CNTL */
1412         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1413         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1414         if (ret)
1415                 return ret;
1416         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1417                    fw_info.feature, fw_info.ver);
1418
1419         /* RLC SAVE RESTORE LIST GPM MEM */
1420         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1421         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1422         if (ret)
1423                 return ret;
1424         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1425                    fw_info.feature, fw_info.ver);
1426
1427         /* RLC SAVE RESTORE LIST SRM MEM */
1428         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1429         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1430         if (ret)
1431                 return ret;
1432         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1433                    fw_info.feature, fw_info.ver);
1434
1435         /* MEC */
1436         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1437         query_fw.index = 0;
1438         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1439         if (ret)
1440                 return ret;
1441         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1442                    fw_info.feature, fw_info.ver);
1443
1444         /* MEC2 */
1445         if (adev->gfx.mec2_fw) {
1446                 query_fw.index = 1;
1447                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1448                 if (ret)
1449                         return ret;
1450                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1451                            fw_info.feature, fw_info.ver);
1452         }
1453
1454         /* PSP SOS */
1455         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1456         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1457         if (ret)
1458                 return ret;
1459         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1460                    fw_info.feature, fw_info.ver);
1461
1462
1463         /* PSP ASD */
1464         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1465         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1466         if (ret)
1467                 return ret;
1468         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1469                    fw_info.feature, fw_info.ver);
1470
1471         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1472         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1473                 query_fw.index = i;
1474                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1475                 if (ret)
1476                         continue;
1477
1478                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1479                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1480         }
1481
1482         /* SMC */
1483         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1484         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1485         if (ret)
1486                 return ret;
1487         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1488                    fw_info.feature, fw_info.ver);
1489
1490         /* SDMA */
1491         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1492         for (i = 0; i < adev->sdma.num_instances; i++) {
1493                 query_fw.index = i;
1494                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1495                 if (ret)
1496                         return ret;
1497                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1498                            i, fw_info.feature, fw_info.ver);
1499         }
1500
1501         /* VCN */
1502         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1503         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1504         if (ret)
1505                 return ret;
1506         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1507                    fw_info.feature, fw_info.ver);
1508
1509         /* DMCU */
1510         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1511         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1512         if (ret)
1513                 return ret;
1514         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1515                    fw_info.feature, fw_info.ver);
1516
1517         /* DMCUB */
1518         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1519         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1520         if (ret)
1521                 return ret;
1522         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1523                    fw_info.feature, fw_info.ver);
1524
1525         /* TOC */
1526         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1527         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1528         if (ret)
1529                 return ret;
1530         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1531                    fw_info.feature, fw_info.ver);
1532
1533         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1534
1535         return 0;
1536 }
1537
1538 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1539
1540 #endif
1541
1542 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1543 {
1544 #if defined(CONFIG_DEBUG_FS)
1545         struct drm_minor *minor = adev_to_drm(adev)->primary;
1546         struct dentry *root = minor->debugfs_root;
1547
1548         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1549                             adev, &amdgpu_debugfs_firmware_info_fops);
1550
1551 #endif
1552 }