drivers/phy/mediatek/phy-mtk-tphy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  * Author: Chunfeng Yun <[email protected]>
   5  *
   6  */
   7
   8 #include <dt-bindings/phy/phy.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/mfd/syscon.h>
  13 #include <linux/module.h>
  14 #include <linux/nvmem-consumer.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_device.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regmap.h>
  20
  21 #include "phy-mtk-io.h"
  22
  23 /* version V1 sub-banks offset base address */
  24 /* banks shared by multiple phys */
  25 #define SSUSB_SIFSLV_V1_SPLLC           0x000   /* shared by u3 phys */
  26 #define SSUSB_SIFSLV_V1_U2FREQ          0x100   /* shared by u2 phys */
  27 #define SSUSB_SIFSLV_V1_CHIP            0x300   /* shared by u3 phys */
  28 /* u2 phy bank */
  29 #define SSUSB_SIFSLV_V1_U2PHY_COM       0x000
  30 /* u3/pcie/sata phy banks */
  31 #define SSUSB_SIFSLV_V1_U3PHYD          0x000
  32 #define SSUSB_SIFSLV_V1_U3PHYA          0x200
  33
  34 /* version V2/V3 sub-banks offset base address */
  35 /* V3: U2FREQ is not used anymore, but reserved */
  36 /* u2 phy banks */
  37 #define SSUSB_SIFSLV_V2_MISC            0x000
  38 #define SSUSB_SIFSLV_V2_U2FREQ          0x100
  39 #define SSUSB_SIFSLV_V2_U2PHY_COM       0x300
  40 /* u3/pcie/sata phy banks */
  41 #define SSUSB_SIFSLV_V2_SPLLC           0x000
  42 #define SSUSB_SIFSLV_V2_CHIP            0x100
  43 #define SSUSB_SIFSLV_V2_U3PHYD          0x200
  44 #define SSUSB_SIFSLV_V2_U3PHYA          0x400
  45
  46 #define U3P_MISC_REG1           0x04
  47 #define MR1_EFUSE_AUTO_LOAD_DIS         BIT(6)
  48
  49 #define U3P_USBPHYACR0          0x000
  50 #define PA0_RG_U2PLL_FORCE_ON           BIT(15)
  51 #define PA0_USB20_PLL_PREDIV            GENMASK(7, 6)
  52 #define PA0_USB20_PLL_PREDIV_VAL(x)     ((0x3 & (x)) << 6)
  53 #define PA0_RG_USB20_INTR_EN            BIT(5)
  54
  55 #define U3P_USBPHYACR1          0x004
  56 #define PA1_RG_INTR_CAL         GENMASK(23, 19)
  57 #define PA1_RG_INTR_CAL_VAL(x)  ((0x1f & (x)) << 19)
  58 #define PA1_RG_VRT_SEL                  GENMASK(14, 12)
  59 #define PA1_RG_VRT_SEL_VAL(x)   ((0x7 & (x)) << 12)
  60 #define PA1_RG_TERM_SEL         GENMASK(10, 8)
  61 #define PA1_RG_TERM_SEL_VAL(x)  ((0x7 & (x)) << 8)
  62
  63 #define U3P_USBPHYACR2          0x008
  64 #define PA2_RG_U2PLL_BW                 GENMASK(21, 19)
  65 #define PA2_RG_U2PLL_BW_VAL(x)          ((0x7 & (x)) << 19)
  66 #define PA2_RG_SIF_U2PLL_FORCE_EN       BIT(18)
  67
  68 #define U3P_USBPHYACR5          0x014
  69 #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
  70 #define PA5_RG_U2_HSTX_SRCTRL           GENMASK(14, 12)
  71 #define PA5_RG_U2_HSTX_SRCTRL_VAL(x)    ((0x7 & (x)) << 12)
  72 #define PA5_RG_U2_HS_100U_U3_EN BIT(11)
  73
  74 #define U3P_USBPHYACR6          0x018
  75 #define PA6_RG_U2_BC11_SW_EN            BIT(23)
  76 #define PA6_RG_U2_OTG_VBUSCMP_EN        BIT(20)
  77 #define PA6_RG_U2_DISCTH                GENMASK(7, 4)
  78 #define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4)
  79 #define PA6_RG_U2_SQTH          GENMASK(3, 0)
  80 #define PA6_RG_U2_SQTH_VAL(x)   (0xf & (x))
  81
  82 #define U3P_U2PHYACR4           0x020
  83 #define P2C_RG_USB20_GPIO_CTL           BIT(9)
  84 #define P2C_USB20_GPIO_MODE             BIT(8)
  85 #define P2C_U2_GPIO_CTR_MSK     (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
  86
  87 #define U3P_U2PHYA_RESV         0x030
  88 #define P2R_RG_U2PLL_FBDIV_26M          0x1bb13b
  89 #define P2R_RG_U2PLL_FBDIV_48M          0x3c0000
  90
  91 #define U3P_U2PHYA_RESV1        0x044
  92 #define P2R_RG_U2PLL_REFCLK_SEL BIT(5)
  93 #define P2R_RG_U2PLL_FRA_EN             BIT(3)
  94
  95 #define U3D_U2PHYDCR0           0x060
  96 #define P2C_RG_SIF_U2PLL_FORCE_ON       BIT(24)
  97
  98 #define U3P_U2PHYDTM0           0x068
  99 #define P2C_FORCE_UART_EN               BIT(26)
 100 #define P2C_FORCE_DATAIN                BIT(23)
 101 #define P2C_FORCE_DM_PULLDOWN           BIT(21)
 102 #define P2C_FORCE_DP_PULLDOWN           BIT(20)
 103 #define P2C_FORCE_XCVRSEL               BIT(19)
 104 #define P2C_FORCE_SUSPENDM              BIT(18)
 105 #define P2C_FORCE_TERMSEL               BIT(17)
 106 #define P2C_RG_DATAIN                   GENMASK(13, 10)
 107 #define P2C_RG_DATAIN_VAL(x)            ((0xf & (x)) << 10)
 108 #define P2C_RG_DMPULLDOWN               BIT(7)
 109 #define P2C_RG_DPPULLDOWN               BIT(6)
 110 #define P2C_RG_XCVRSEL                  GENMASK(5, 4)
 111 #define P2C_RG_XCVRSEL_VAL(x)           ((0x3 & (x)) << 4)
 112 #define P2C_RG_SUSPENDM                 BIT(3)
 113 #define P2C_RG_TERMSEL                  BIT(2)
 114 #define P2C_DTM0_PART_MASK \
 115                 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
 116                 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
 117                 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
 118                 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
 119
 120 #define U3P_U2PHYDTM1           0x06C
 121 #define P2C_RG_UART_EN                  BIT(16)
 122 #define P2C_FORCE_IDDIG         BIT(9)
 123 #define P2C_RG_VBUSVALID                BIT(5)
 124 #define P2C_RG_SESSEND                  BIT(4)
 125 #define P2C_RG_AVALID                   BIT(2)
 126 #define P2C_RG_IDDIG                    BIT(1)
 127
 128 #define U3P_U2PHYBC12C          0x080
 129 #define P2C_RG_CHGDT_EN         BIT(0)
 130
 131 #define U3P_U3_CHIP_GPIO_CTLD           0x0c
 132 #define P3C_REG_IP_SW_RST               BIT(31)
 133 #define P3C_MCU_BUS_CK_GATE_EN          BIT(30)
 134 #define P3C_FORCE_IP_SW_RST             BIT(29)
 135
 136 #define U3P_U3_CHIP_GPIO_CTLE           0x10
 137 #define P3C_RG_SWRST_U3_PHYD            BIT(25)
 138 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN   BIT(24)
 139
 140 #define U3P_U3_PHYA_REG0        0x000
 141 #define P3A_RG_IEXT_INTR                GENMASK(15, 10)
 142 #define P3A_RG_IEXT_INTR_VAL(x)         ((0x3f & (x)) << 10)
 143 #define P3A_RG_CLKDRV_OFF               GENMASK(3, 2)
 144 #define P3A_RG_CLKDRV_OFF_VAL(x)        ((0x3 & (x)) << 2)
 145
 146 #define U3P_U3_PHYA_REG1        0x004
 147 #define P3A_RG_CLKDRV_AMP               GENMASK(31, 29)
 148 #define P3A_RG_CLKDRV_AMP_VAL(x)        ((0x7 & (x)) << 29)
 149
 150 #define U3P_U3_PHYA_REG6        0x018
 151 #define P3A_RG_TX_EIDLE_CM              GENMASK(31, 28)
 152 #define P3A_RG_TX_EIDLE_CM_VAL(x)       ((0xf & (x)) << 28)
 153
 154 #define U3P_U3_PHYA_REG9        0x024
 155 #define P3A_RG_RX_DAC_MUX               GENMASK(5, 1)
 156 #define P3A_RG_RX_DAC_MUX_VAL(x)        ((0x1f & (x)) << 1)
 157
 158 #define U3P_U3_PHYA_DA_REG0     0x100
 159 #define P3A_RG_XTAL_EXT_PE2H            GENMASK(17, 16)
 160 #define P3A_RG_XTAL_EXT_PE2H_VAL(x)     ((0x3 & (x)) << 16)
 161 #define P3A_RG_XTAL_EXT_PE1H            GENMASK(13, 12)
 162 #define P3A_RG_XTAL_EXT_PE1H_VAL(x)     ((0x3 & (x)) << 12)
 163 #define P3A_RG_XTAL_EXT_EN_U3           GENMASK(11, 10)
 164 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x)    ((0x3 & (x)) << 10)
 165
 166 #define U3P_U3_PHYA_DA_REG4     0x108
 167 #define P3A_RG_PLL_DIVEN_PE2H           GENMASK(21, 19)
 168 #define P3A_RG_PLL_BC_PE2H              GENMASK(7, 6)
 169 #define P3A_RG_PLL_BC_PE2H_VAL(x)       ((0x3 & (x)) << 6)
 170
 171 #define U3P_U3_PHYA_DA_REG5     0x10c
 172 #define P3A_RG_PLL_BR_PE2H              GENMASK(29, 28)
 173 #define P3A_RG_PLL_BR_PE2H_VAL(x)       ((0x3 & (x)) << 28)
 174 #define P3A_RG_PLL_IC_PE2H              GENMASK(15, 12)
 175 #define P3A_RG_PLL_IC_PE2H_VAL(x)       ((0xf & (x)) << 12)
 176
 177 #define U3P_U3_PHYA_DA_REG6     0x110
 178 #define P3A_RG_PLL_IR_PE2H              GENMASK(19, 16)
 179 #define P3A_RG_PLL_IR_PE2H_VAL(x)       ((0xf & (x)) << 16)
 180
 181 #define U3P_U3_PHYA_DA_REG7     0x114
 182 #define P3A_RG_PLL_BP_PE2H              GENMASK(19, 16)
 183 #define P3A_RG_PLL_BP_PE2H_VAL(x)       ((0xf & (x)) << 16)
 184
 185 #define U3P_U3_PHYA_DA_REG20    0x13c
 186 #define P3A_RG_PLL_DELTA1_PE2H          GENMASK(31, 16)
 187 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x)   ((0xffff & (x)) << 16)
 188
 189 #define U3P_U3_PHYA_DA_REG25    0x148
 190 #define P3A_RG_PLL_DELTA_PE2H           GENMASK(15, 0)
 191 #define P3A_RG_PLL_DELTA_PE2H_VAL(x)    (0xffff & (x))
 192
 193 #define U3P_U3_PHYD_LFPS1               0x00c
 194 #define P3D_RG_FWAKE_TH         GENMASK(21, 16)
 195 #define P3D_RG_FWAKE_TH_VAL(x)  ((0x3f & (x)) << 16)
 196
 197 #define U3P_U3_PHYD_IMPCAL0             0x010
 198 #define P3D_RG_FORCE_TX_IMPEL           BIT(31)
 199 #define P3D_RG_TX_IMPEL                 GENMASK(28, 24)
 200 #define P3D_RG_TX_IMPEL_VAL(x)          ((0x1f & (x)) << 24)
 201
 202 #define U3P_U3_PHYD_IMPCAL1             0x014
 203 #define P3D_RG_FORCE_RX_IMPEL           BIT(31)
 204 #define P3D_RG_RX_IMPEL                 GENMASK(28, 24)
 205 #define P3D_RG_RX_IMPEL_VAL(x)          ((0x1f & (x)) << 24)
 206
 207 #define U3P_U3_PHYD_RSV                 0x054
 208 #define P3D_RG_EFUSE_AUTO_LOAD_DIS      BIT(12)
 209
 210 #define U3P_U3_PHYD_CDR1                0x05c
 211 #define P3D_RG_CDR_BIR_LTD1             GENMASK(28, 24)
 212 #define P3D_RG_CDR_BIR_LTD1_VAL(x)      ((0x1f & (x)) << 24)
 213 #define P3D_RG_CDR_BIR_LTD0             GENMASK(12, 8)
 214 #define P3D_RG_CDR_BIR_LTD0_VAL(x)      ((0x1f & (x)) << 8)
 215
 216 #define U3P_U3_PHYD_RXDET1              0x128
 217 #define P3D_RG_RXDET_STB2_SET           GENMASK(17, 9)
 218 #define P3D_RG_RXDET_STB2_SET_VAL(x)    ((0x1ff & (x)) << 9)
 219
 220 #define U3P_U3_PHYD_RXDET2              0x12c
 221 #define P3D_RG_RXDET_STB2_SET_P3        GENMASK(8, 0)
 222 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
 223
 224 #define U3P_SPLLC_XTALCTL3              0x018
 225 #define XC3_RG_U3_XTAL_RX_PWD           BIT(9)
 226 #define XC3_RG_U3_FRC_XTAL_RX_PWD       BIT(8)
 227
 228 #define U3P_U2FREQ_FMCR0        0x00
 229 #define P2F_RG_MONCLK_SEL       GENMASK(27, 26)
 230 #define P2F_RG_MONCLK_SEL_VAL(x)        ((0x3 & (x)) << 26)
 231 #define P2F_RG_FREQDET_EN       BIT(24)
 232 #define P2F_RG_CYCLECNT         GENMASK(23, 0)
 233 #define P2F_RG_CYCLECNT_VAL(x)  ((P2F_RG_CYCLECNT) & (x))
 234
 235 #define U3P_U2FREQ_VALUE        0x0c
 236
 237 #define U3P_U2FREQ_FMMONR1      0x10
 238 #define P2F_USB_FM_VALID        BIT(0)
 239 #define P2F_RG_FRCK_EN          BIT(8)
 240
 241 #define U3P_REF_CLK             26      /* MHZ */
 242 #define U3P_SLEW_RATE_COEF      28
 243 #define U3P_SR_COEF_DIVISOR     1000
 244 #define U3P_FM_DET_CYCLE_CNT    1024
 245
 246 /* SATA register setting */
 247 #define PHYD_CTRL_SIGNAL_MODE4          0x1c
 248 /* CDR Charge Pump P-path current adjustment */
 249 #define RG_CDR_BICLTD1_GEN1_MSK         GENMASK(23, 20)
 250 #define RG_CDR_BICLTD1_GEN1_VAL(x)      ((0xf & (x)) << 20)
 251 #define RG_CDR_BICLTD0_GEN1_MSK         GENMASK(11, 8)
 252 #define RG_CDR_BICLTD0_GEN1_VAL(x)      ((0xf & (x)) << 8)
 253
 254 #define PHYD_DESIGN_OPTION2             0x24
 255 /* Symbol lock count selection */
 256 #define RG_LOCK_CNT_SEL_MSK             GENMASK(5, 4)
 257 #define RG_LOCK_CNT_SEL_VAL(x)          ((0x3 & (x)) << 4)
 258
 259 #define PHYD_DESIGN_OPTION9     0x40
 260 /* COMWAK GAP width window */
 261 #define RG_TG_MAX_MSK           GENMASK(20, 16)
 262 #define RG_TG_MAX_VAL(x)        ((0x1f & (x)) << 16)
 263 /* COMINIT GAP width window */
 264 #define RG_T2_MAX_MSK           GENMASK(13, 8)
 265 #define RG_T2_MAX_VAL(x)        ((0x3f & (x)) << 8)
 266 /* COMWAK GAP width window */
 267 #define RG_TG_MIN_MSK           GENMASK(7, 5)
 268 #define RG_TG_MIN_VAL(x)        ((0x7 & (x)) << 5)
 269 /* COMINIT GAP width window */
 270 #define RG_T2_MIN_MSK           GENMASK(4, 0)
 271 #define RG_T2_MIN_VAL(x)        (0x1f & (x))
 272
 273 #define ANA_RG_CTRL_SIGNAL1             0x4c
 274 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
 275 #define RG_IDRV_0DB_GEN1_MSK            GENMASK(13, 8)
 276 #define RG_IDRV_0DB_GEN1_VAL(x)         ((0x3f & (x)) << 8)
 277
 278 #define ANA_RG_CTRL_SIGNAL4             0x58
 279 #define RG_CDR_BICLTR_GEN1_MSK          GENMASK(23, 20)
 280 #define RG_CDR_BICLTR_GEN1_VAL(x)       ((0xf & (x)) << 20)
 281 /* Loop filter R1 resistance adjustment for Gen1 speed */
 282 #define RG_CDR_BR_GEN2_MSK              GENMASK(10, 8)
 283 #define RG_CDR_BR_GEN2_VAL(x)           ((0x7 & (x)) << 8)
 284
 285 #define ANA_RG_CTRL_SIGNAL6             0x60
 286 /* I-path capacitance adjustment for Gen1 */
 287 #define RG_CDR_BC_GEN1_MSK              GENMASK(28, 24)
 288 #define RG_CDR_BC_GEN1_VAL(x)           ((0x1f & (x)) << 24)
 289 #define RG_CDR_BIRLTR_GEN1_MSK          GENMASK(4, 0)
 290 #define RG_CDR_BIRLTR_GEN1_VAL(x)       (0x1f & (x))
 291
 292 #define ANA_EQ_EYE_CTRL_SIGNAL1         0x6c
 293 /* RX Gen1 LEQ tuning step */
 294 #define RG_EQ_DLEQ_LFI_GEN1_MSK         GENMASK(11, 8)
 295 #define RG_EQ_DLEQ_LFI_GEN1_VAL(x)      ((0xf & (x)) << 8)
 296
 297 #define ANA_EQ_EYE_CTRL_SIGNAL4         0xd8
 298 #define RG_CDR_BIRLTD0_GEN1_MSK         GENMASK(20, 16)
 299 #define RG_CDR_BIRLTD0_GEN1_VAL(x)      ((0x1f & (x)) << 16)
 300
 301 #define ANA_EQ_EYE_CTRL_SIGNAL5         0xdc
 302 #define RG_CDR_BIRLTD0_GEN3_MSK         GENMASK(4, 0)
 303 #define RG_CDR_BIRLTD0_GEN3_VAL(x)      (0x1f & (x))
 304
 305 /* PHY switch between pcie/usb3/sgmii/sata */
 306 #define USB_PHY_SWITCH_CTRL     0x0
 307 #define RG_PHY_SW_TYPE          GENMASK(3, 0)
 308 #define RG_PHY_SW_PCIE          0x0
 309 #define RG_PHY_SW_USB3          0x1
 310 #define RG_PHY_SW_SGMII         0x2
 311 #define RG_PHY_SW_SATA          0x3
 312
 313 #define TPHY_CLKS_CNT   2
 314
 315 enum mtk_phy_version {
 316         MTK_PHY_V1 = 1,
 317         MTK_PHY_V2,
 318         MTK_PHY_V3,
 319 };
 320
 321 struct mtk_phy_pdata {
 322         /* avoid RX sensitivity level degradation only for mt8173 */
 323         bool avoid_rx_sen_degradation;
 324         /*
 325          * workaround only for mt8195, HW fix it for others of V3,
 326          * u2phy should use integer mode instead of fractional mode of
 327          * 48M PLL, fix it by switching PLL to 26M from default 48M
 328          */
 329         bool sw_pll_48m_to_26m;
 330         /*
 331          * Some SoCs (e.g. mt8195) drop a bit when use auto load efuse,
 332          * support sw way, also support it for v2/v3 optionally.
 333          */
 334         bool sw_efuse_supported;
 335         enum mtk_phy_version version;
 336 };
 337
 338 struct u2phy_banks {
 339         void __iomem *misc;
 340         void __iomem *fmreg;
 341         void __iomem *com;
 342 };
 343
 344 struct u3phy_banks {
 345         void __iomem *spllc;
 346         void __iomem *chip;
 347         void __iomem *phyd; /* include u3phyd_bank2 */
 348         void __iomem *phya; /* include u3phya_da */
 349 };
 350
 351 struct mtk_phy_instance {
 352         struct phy *phy;
 353         void __iomem *port_base;
 354         union {
 355                 struct u2phy_banks u2_banks;
 356                 struct u3phy_banks u3_banks;
 357         };
 358         struct clk_bulk_data clks[TPHY_CLKS_CNT];
 359         u32 index;
 360         u32 type;
 361         struct regmap *type_sw;
 362         u32 type_sw_reg;
 363         u32 type_sw_index;
 364         u32 efuse_sw_en;
 365         u32 efuse_intr;
 366         u32 efuse_tx_imp;
 367         u32 efuse_rx_imp;
 368         int eye_src;
 369         int eye_vrt;
 370         int eye_term;
 371         int intr;
 372         int discth;
 373         bool bc12_en;
 374 };
 375
 376 struct mtk_tphy {
 377         struct device *dev;
 378         void __iomem *sif_base; /* only shared sif */
 379         const struct mtk_phy_pdata *pdata;
 380         struct mtk_phy_instance **phys;
 381         int nphys;
 382         int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
 383         int src_coef; /* coefficient for slew rate calibrate */
 384 };
 385
 386 static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
 387         struct mtk_phy_instance *instance)
 388 {
 389         struct u2phy_banks *u2_banks = &instance->u2_banks;
 390         void __iomem *fmreg = u2_banks->fmreg;
 391         void __iomem *com = u2_banks->com;
 392         int calibration_val;
 393         int fm_out;
 394         u32 tmp;
 395
 396         /* HW V3 doesn't support slew rate cal anymore */
 397         if (tphy->pdata->version == MTK_PHY_V3)
 398                 return;
 399
 400         /* use force value */
 401         if (instance->eye_src)
 402                 return;
 403
 404         /* enable USB ring oscillator */
 405         mtk_phy_set_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN);
 406         udelay(1);
 407
 408         /*enable free run clock */
 409         mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
 410
 411         /* set cycle count as 1024, and select u2 channel */
 412         tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
 413         tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
 414         tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
 415         if (tphy->pdata->version == MTK_PHY_V1)
 416                 tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
 417
 418         writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
 419
 420         /* enable frequency meter */
 421         mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
 422
 423         /* ignore return value */
 424         readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp,
 425                            (tmp & P2F_USB_FM_VALID), 10, 200);
 426
 427         fm_out = readl(fmreg + U3P_U2FREQ_VALUE);
 428
 429         /* disable frequency meter */
 430         mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
 431
 432         /*disable free run clock */
 433         mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
 434
 435         if (fm_out) {
 436                 /* ( 1024 / FM_OUT ) x reference clock frequency x coef */
 437                 tmp = tphy->src_ref_clk * tphy->src_coef;
 438                 tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out;
 439                 calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
 440         } else {
 441                 /* if FM detection fail, set default value */
 442                 calibration_val = 4;
 443         }
 444         dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
 445                 instance->index, fm_out, calibration_val,
 446                 tphy->src_ref_clk, tphy->src_coef);
 447
 448         /* set HS slew rate */
 449         mtk_phy_update_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
 450                             PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val));
 451
 452         /* disable USB ring oscillator */
 453         mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN);
 454 }
 455
 456 static void u3_phy_instance_init(struct mtk_tphy *tphy,
 457         struct mtk_phy_instance *instance)
 458 {
 459         struct u3phy_banks *u3_banks = &instance->u3_banks;
 460
 461         /* gating PCIe Analog XTAL clock */
 462         mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
 463                          XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
 464
 465         /* gating XSQ */
 466         mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
 467                             P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
 468
 469         mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_REG9,
 470                             P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
 471
 472         mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_REG6,
 473                             P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
 474
 475         mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1,
 476                             P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
 477                             P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3));
 478
 479         mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_LFPS1,
 480                             P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34));
 481
 482         mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
 483                             P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));
 484
 485         mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
 486                             P3D_RG_RXDET_STB2_SET_P3, P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
 487
 488         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 489 }
 490
 491 static void u2_phy_pll_26m_set(struct mtk_tphy *tphy,
 492         struct mtk_phy_instance *instance)
 493 {
 494         struct u2phy_banks *u2_banks = &instance->u2_banks;
 495         void __iomem *com = u2_banks->com;
 496
 497         if (!tphy->pdata->sw_pll_48m_to_26m)
 498                 return;
 499
 500         mtk_phy_update_bits(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV,
 501                             PA0_USB20_PLL_PREDIV_VAL(0));
 502
 503         mtk_phy_update_bits(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW,
 504                             PA2_RG_U2PLL_BW_VAL(3));
 505
 506         writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV);
 507
 508         mtk_phy_set_bits(com + U3P_U2PHYA_RESV1,
 509                          P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL);
 510 }
 511
 512 static void u2_phy_instance_init(struct mtk_tphy *tphy,
 513         struct mtk_phy_instance *instance)
 514 {
 515         struct u2phy_banks *u2_banks = &instance->u2_banks;
 516         void __iomem *com = u2_banks->com;
 517         u32 index = instance->index;
 518
 519         /* switch to USB function, and enable usb pll */
 520         mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
 521
 522         mtk_phy_update_bits(com + U3P_U2PHYDTM0, P2C_RG_XCVRSEL | P2C_RG_DATAIN,
 523                             P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0));
 524
 525         mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
 526
 527         mtk_phy_set_bits(com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
 528
 529         /* disable switch 100uA current to SSUSB */
 530         mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
 531
 532         if (!index)
 533                 mtk_phy_clear_bits(com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
 534
 535         if (tphy->pdata->avoid_rx_sen_degradation) {
 536                 if (!index) {
 537                         mtk_phy_set_bits(com + U3P_USBPHYACR2, PA2_RG_SIF_U2PLL_FORCE_EN);
 538
 539                         mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
 540                 } else {
 541                         mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
 542
 543                         mtk_phy_set_bits(com + U3P_U2PHYDTM0,
 544                                          P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
 545                 }
 546         }
 547
 548         /* DP/DM BC1.1 path Disable */
 549         mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN);
 550
 551         mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2));
 552
 553         /* Workaround only for mt8195, HW fix it for others (V3) */
 554         u2_phy_pll_26m_set(tphy, instance);
 555
 556         dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
 557 }
 558
 559 static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
 560         struct mtk_phy_instance *instance)
 561 {
 562         struct u2phy_banks *u2_banks = &instance->u2_banks;
 563         void __iomem *com = u2_banks->com;
 564         u32 index = instance->index;
 565
 566         mtk_phy_clear_bits(com + U3P_U2PHYDTM0,
 567                            P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
 568
 569         /* OTG Enable */
 570         mtk_phy_set_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
 571
 572         mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
 573
 574         mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND);
 575
 576         if (tphy->pdata->avoid_rx_sen_degradation && index) {
 577                 mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
 578
 579                 mtk_phy_set_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
 580         }
 581         dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
 582 }
 583
 584 static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
 585         struct mtk_phy_instance *instance)
 586 {
 587         struct u2phy_banks *u2_banks = &instance->u2_banks;
 588         void __iomem *com = u2_banks->com;
 589         u32 index = instance->index;
 590
 591         mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_RG_XCVRSEL | P2C_RG_DATAIN);
 592
 593         /* OTG Disable */
 594         mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
 595
 596         mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
 597
 598         mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND);
 599
 600         if (tphy->pdata->avoid_rx_sen_degradation && index) {
 601                 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
 602
 603                 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
 604         }
 605
 606         dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
 607 }
 608
 609 static void u2_phy_instance_exit(struct mtk_tphy *tphy,
 610         struct mtk_phy_instance *instance)
 611 {
 612         struct u2phy_banks *u2_banks = &instance->u2_banks;
 613         void __iomem *com = u2_banks->com;
 614         u32 index = instance->index;
 615
 616         if (tphy->pdata->avoid_rx_sen_degradation && index) {
 617                 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
 618
 619                 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM);
 620         }
 621 }
 622
 623 static void u2_phy_instance_set_mode(struct mtk_tphy *tphy,
 624                                      struct mtk_phy_instance *instance,
 625                                      enum phy_mode mode)
 626 {
 627         struct u2phy_banks *u2_banks = &instance->u2_banks;
 628         u32 tmp;
 629
 630         tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
 631         switch (mode) {
 632         case PHY_MODE_USB_DEVICE:
 633                 tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
 634                 break;
 635         case PHY_MODE_USB_HOST:
 636                 tmp |= P2C_FORCE_IDDIG;
 637                 tmp &= ~P2C_RG_IDDIG;
 638                 break;
 639         case PHY_MODE_USB_OTG:
 640                 tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
 641                 break;
 642         default:
 643                 return;
 644         }
 645         writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
 646 }
 647
 648 static void pcie_phy_instance_init(struct mtk_tphy *tphy,
 649         struct mtk_phy_instance *instance)
 650 {
 651         struct u3phy_banks *u3_banks = &instance->u3_banks;
 652         void __iomem *phya = u3_banks->phya;
 653
 654         if (tphy->pdata->version != MTK_PHY_V1)
 655                 return;
 656
 657         mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0,
 658                             P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
 659                             P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2));
 660
 661         /* ref clk drive */
 662         mtk_phy_update_bits(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
 663                             P3A_RG_CLKDRV_AMP_VAL(0x4));
 664
 665         mtk_phy_update_bits(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
 666                             P3A_RG_CLKDRV_OFF_VAL(0x1));
 667
 668         /* SSC delta -5000ppm */
 669         mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H,
 670                             P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));
 671
 672         mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H,
 673                             P3A_RG_PLL_DELTA_PE2H_VAL(0x36));
 674
 675         /* change pll BW 0.6M */
 676         mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG5,
 677                             P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
 678                             P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1));
 679
 680         mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG4,
 681                             P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
 682                             P3A_RG_PLL_BC_PE2H_VAL(0x3));
 683
 684         mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H,
 685                             P3A_RG_PLL_IR_PE2H_VAL(0x2));
 686
 687         mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H,
 688                             P3A_RG_PLL_BP_PE2H_VAL(0xa));
 689
 690         /* Tx Detect Rx Timing: 10us -> 5us */
 691         mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
 692                             P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));
 693
 694         mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
 695                             P3D_RG_RXDET_STB2_SET_P3, P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
 696
 697         /* wait for PCIe subsys register to active */
 698         usleep_range(2500, 3000);
 699         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 700 }
 701
 702 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
 703         struct mtk_phy_instance *instance)
 704 {
 705         struct u3phy_banks *bank = &instance->u3_banks;
 706
 707         mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
 708                            P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 709
 710         mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
 711                            P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
 712 }
 713
 714 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
 715         struct mtk_phy_instance *instance)
 716
 717 {
 718         struct u3phy_banks *bank = &instance->u3_banks;
 719
 720         mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
 721                          P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 722
 723         mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
 724                          P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
 725 }
 726
 727 static void sata_phy_instance_init(struct mtk_tphy *tphy,
 728         struct mtk_phy_instance *instance)
 729 {
 730         struct u3phy_banks *u3_banks = &instance->u3_banks;
 731         void __iomem *phyd = u3_banks->phyd;
 732
 733         /* charge current adjustment */
 734         mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL6,
 735                             RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK,
 736                             RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a));
 737
 738         mtk_phy_update_bits(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK,
 739                             RG_CDR_BIRLTD0_GEN1_VAL(0x18));
 740
 741         mtk_phy_update_bits(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK,
 742                             RG_CDR_BIRLTD0_GEN3_VAL(0x06));
 743
 744         mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL4,
 745                             RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK,
 746                             RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07));
 747
 748         mtk_phy_update_bits(phyd + PHYD_CTRL_SIGNAL_MODE4,
 749                             RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK,
 750                             RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02));
 751
 752         mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK,
 753                             RG_LOCK_CNT_SEL_VAL(0x02));
 754
 755         mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9,
 756                             RG_T2_MIN_MSK | RG_TG_MIN_MSK,
 757                             RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04));
 758
 759         mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9,
 760                             RG_T2_MAX_MSK | RG_TG_MAX_MSK,
 761                             RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e));
 762
 763         mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK,
 764                             RG_IDRV_0DB_GEN1_VAL(0x20));
 765
 766         mtk_phy_update_bits(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK,
 767                             RG_EQ_DLEQ_LFI_GEN1_VAL(0x03));
 768
 769         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 770 }
 771
 772 static void phy_v1_banks_init(struct mtk_tphy *tphy,
 773                               struct mtk_phy_instance *instance)
 774 {
 775         struct u2phy_banks *u2_banks = &instance->u2_banks;
 776         struct u3phy_banks *u3_banks = &instance->u3_banks;
 777
 778         switch (instance->type) {
 779         case PHY_TYPE_USB2:
 780                 u2_banks->misc = NULL;
 781                 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
 782                 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
 783                 break;
 784         case PHY_TYPE_USB3:
 785         case PHY_TYPE_PCIE:
 786                 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
 787                 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
 788                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
 789                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
 790                 break;
 791         case PHY_TYPE_SATA:
 792                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
 793                 break;
 794         default:
 795                 dev_err(tphy->dev, "incompatible PHY type\n");
 796                 return;
 797         }
 798 }
 799
 800 static void phy_v2_banks_init(struct mtk_tphy *tphy,
 801                               struct mtk_phy_instance *instance)
 802 {
 803         struct u2phy_banks *u2_banks = &instance->u2_banks;
 804         struct u3phy_banks *u3_banks = &instance->u3_banks;
 805
 806         switch (instance->type) {
 807         case PHY_TYPE_USB2:
 808                 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
 809                 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
 810                 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
 811                 break;
 812         case PHY_TYPE_USB3:
 813         case PHY_TYPE_PCIE:
 814                 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
 815                 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
 816                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
 817                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
 818                 break;
 819         default:
 820                 dev_err(tphy->dev, "incompatible PHY type\n");
 821                 return;
 822         }
 823 }
 824
 825 static void phy_parse_property(struct mtk_tphy *tphy,
 826                                 struct mtk_phy_instance *instance)
 827 {
 828         struct device *dev = &instance->phy->dev;
 829
 830         if (instance->type != PHY_TYPE_USB2)
 831                 return;
 832
 833         instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");
 834         device_property_read_u32(dev, "mediatek,eye-src",
 835                                  &instance->eye_src);
 836         device_property_read_u32(dev, "mediatek,eye-vrt",
 837                                  &instance->eye_vrt);
 838         device_property_read_u32(dev, "mediatek,eye-term",
 839                                  &instance->eye_term);
 840         device_property_read_u32(dev, "mediatek,intr",
 841                                  &instance->intr);
 842         device_property_read_u32(dev, "mediatek,discth",
 843                                  &instance->discth);
 844         dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n",
 845                 instance->bc12_en, instance->eye_src,
 846                 instance->eye_vrt, instance->eye_term,
 847                 instance->intr, instance->discth);
 848 }
 849
 850 static void u2_phy_props_set(struct mtk_tphy *tphy,
 851                              struct mtk_phy_instance *instance)
 852 {
 853         struct u2phy_banks *u2_banks = &instance->u2_banks;
 854         void __iomem *com = u2_banks->com;
 855
 856         if (instance->bc12_en) /* BC1.2 path Enable */
 857                 mtk_phy_set_bits(com + U3P_U2PHYBC12C, P2C_RG_CHGDT_EN);
 858
 859         if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src)
 860                 mtk_phy_update_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
 861                                     PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src));
 862
 863         if (instance->eye_vrt)
 864                 mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL,
 865                                     PA1_RG_VRT_SEL_VAL(instance->eye_vrt));
 866
 867         if (instance->eye_term)
 868                 mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL,
 869                                     PA1_RG_TERM_SEL_VAL(instance->eye_term));
 870
 871         if (instance->intr)
 872                 mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
 873                                     PA1_RG_INTR_CAL_VAL(instance->intr));
 874
 875         if (instance->discth)
 876                 mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH,
 877                                     PA6_RG_U2_DISCTH_VAL(instance->discth));
 878 }
 879
 880 /* type switch for usb3/pcie/sgmii/sata */
 881 static int phy_type_syscon_get(struct mtk_phy_instance *instance,
 882                                struct device_node *dn)
 883 {
 884         struct of_phandle_args args;
 885         int ret;
 886
 887         /* type switch function is optional */
 888         if (!of_property_read_bool(dn, "mediatek,syscon-type"))
 889                 return 0;
 890
 891         ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",
 892                                                2, 0, &args);
 893         if (ret)
 894                 return ret;
 895
 896         instance->type_sw_reg = args.args[0];
 897         instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
 898         instance->type_sw = syscon_node_to_regmap(args.np);
 899         of_node_put(args.np);
 900         dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
 901                  instance->type_sw_reg, instance->type_sw_index);
 902
 903         return PTR_ERR_OR_ZERO(instance->type_sw);
 904 }
 905
 906 static int phy_type_set(struct mtk_phy_instance *instance)
 907 {
 908         int type;
 909         u32 mask;
 910
 911         if (!instance->type_sw)
 912                 return 0;
 913
 914         switch (instance->type) {
 915         case PHY_TYPE_USB3:
 916                 type = RG_PHY_SW_USB3;
 917                 break;
 918         case PHY_TYPE_PCIE:
 919                 type = RG_PHY_SW_PCIE;
 920                 break;
 921         case PHY_TYPE_SGMII:
 922                 type = RG_PHY_SW_SGMII;
 923                 break;
 924         case PHY_TYPE_SATA:
 925                 type = RG_PHY_SW_SATA;
 926                 break;
 927         case PHY_TYPE_USB2:
 928         default:
 929                 return 0;
 930         }
 931
 932         mask = RG_PHY_SW_TYPE << (instance->type_sw_index * BITS_PER_BYTE);
 933         regmap_update_bits(instance->type_sw, instance->type_sw_reg, mask, type);
 934
 935         return 0;
 936 }
 937
 938 static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instance)
 939 {
 940         struct device *dev = &instance->phy->dev;
 941         int ret = 0;
 942
 943         /* tphy v1 doesn't support sw efuse, skip it */
 944         if (!tphy->pdata->sw_efuse_supported) {
 945                 instance->efuse_sw_en = 0;
 946                 return 0;
 947         }
 948
 949         /* software efuse is optional */
 950         instance->efuse_sw_en = device_property_read_bool(dev, "nvmem-cells");
 951         if (!instance->efuse_sw_en)
 952                 return 0;
 953
 954         switch (instance->type) {
 955         case PHY_TYPE_USB2:
 956                 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
 957                 if (ret) {
 958                         dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
 959                         break;
 960                 }
 961
 962                 /* no efuse, ignore it */
 963                 if (!instance->efuse_intr) {
 964                         dev_warn(dev, "no u2 intr efuse, but dts enable it\n");
 965                         instance->efuse_sw_en = 0;
 966                         break;
 967                 }
 968
 969                 dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr);
 970                 break;
 971
 972         case PHY_TYPE_USB3:
 973         case PHY_TYPE_PCIE:
 974                 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
 975                 if (ret) {
 976                         dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
 977                         break;
 978                 }
 979
 980                 ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp);
 981                 if (ret) {
 982                         dev_err(dev, "fail to get u3 rx_imp efuse, %d\n", ret);
 983                         break;
 984                 }
 985
 986                 ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp);
 987                 if (ret) {
 988                         dev_err(dev, "fail to get u3 tx_imp efuse, %d\n", ret);
 989                         break;
 990                 }
 991
 992                 /* no efuse, ignore it */
 993                 if (!instance->efuse_intr &&
 994                     !instance->efuse_rx_imp &&
 995                     !instance->efuse_rx_imp) {
 996                         dev_warn(dev, "no u3 intr efuse, but dts enable it\n");
 997                         instance->efuse_sw_en = 0;
 998                         break;
 999                 }
1000
1001                 dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",
1002                         instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);
1003                 break;
1004         default:
1005                 dev_err(dev, "no sw efuse for type %d\n", instance->type);
1006                 ret = -EINVAL;
1007         }
1008
1009         return ret;
1010 }
1011
1012 static void phy_efuse_set(struct mtk_phy_instance *instance)
1013 {
1014         struct device *dev = &instance->phy->dev;
1015         struct u2phy_banks *u2_banks = &instance->u2_banks;
1016         struct u3phy_banks *u3_banks = &instance->u3_banks;
1017
1018         if (!instance->efuse_sw_en)
1019                 return;
1020
1021         switch (instance->type) {
1022         case PHY_TYPE_USB2:
1023                 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS);
1024
1025                 mtk_phy_update_bits(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
1026                                     PA1_RG_INTR_CAL_VAL(instance->efuse_intr));
1027                 break;
1028         case PHY_TYPE_USB3:
1029         case PHY_TYPE_PCIE:
1030                 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS);
1031
1032                 mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL,
1033                                     P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp));
1034                 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL);
1035
1036                 mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL,
1037                                     P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp));
1038                 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL);
1039
1040                 mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR,
1041                                     P3A_RG_IEXT_INTR_VAL(instance->efuse_intr));
1042                 break;
1043         default:
1044                 dev_warn(dev, "no sw efuse for type %d\n", instance->type);
1045                 break;
1046         }
1047 }
1048
1049 static int mtk_phy_init(struct phy *phy)
1050 {
1051         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1052         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1053         int ret;
1054
1055         ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks);
1056         if (ret)
1057                 return ret;
1058
1059         phy_efuse_set(instance);
1060
1061         switch (instance->type) {
1062         case PHY_TYPE_USB2:
1063                 u2_phy_instance_init(tphy, instance);
1064                 u2_phy_props_set(tphy, instance);
1065                 break;
1066         case PHY_TYPE_USB3:
1067                 u3_phy_instance_init(tphy, instance);
1068                 break;
1069         case PHY_TYPE_PCIE:
1070                 pcie_phy_instance_init(tphy, instance);
1071                 break;
1072         case PHY_TYPE_SATA:
1073                 sata_phy_instance_init(tphy, instance);
1074                 break;
1075         case PHY_TYPE_SGMII:
1076                 /* nothing to do, only used to set type */
1077                 break;
1078         default:
1079                 dev_err(tphy->dev, "incompatible PHY type\n");
1080                 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);
1081                 return -EINVAL;
1082         }
1083
1084         return 0;
1085 }
1086
1087 static int mtk_phy_power_on(struct phy *phy)
1088 {
1089         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1090         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1091
1092         if (instance->type == PHY_TYPE_USB2) {
1093                 u2_phy_instance_power_on(tphy, instance);
1094                 hs_slew_rate_calibrate(tphy, instance);
1095         } else if (instance->type == PHY_TYPE_PCIE) {
1096                 pcie_phy_instance_power_on(tphy, instance);
1097         }
1098
1099         return 0;
1100 }
1101
1102 static int mtk_phy_power_off(struct phy *phy)
1103 {
1104         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1105         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1106
1107         if (instance->type == PHY_TYPE_USB2)
1108                 u2_phy_instance_power_off(tphy, instance);
1109         else if (instance->type == PHY_TYPE_PCIE)
1110                 pcie_phy_instance_power_off(tphy, instance);
1111
1112         return 0;
1113 }
1114
1115 static int mtk_phy_exit(struct phy *phy)
1116 {
1117         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1118         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1119
1120         if (instance->type == PHY_TYPE_USB2)
1121                 u2_phy_instance_exit(tphy, instance);
1122
1123         clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);
1124         return 0;
1125 }
1126
1127 static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1128 {
1129         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1130         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1131
1132         if (instance->type == PHY_TYPE_USB2)
1133                 u2_phy_instance_set_mode(tphy, instance, mode);
1134
1135         return 0;
1136 }
1137
1138 static struct phy *mtk_phy_xlate(struct device *dev,
1139                                         struct of_phandle_args *args)
1140 {
1141         struct mtk_tphy *tphy = dev_get_drvdata(dev);
1142         struct mtk_phy_instance *instance = NULL;
1143         struct device_node *phy_np = args->np;
1144         int index;
1145         int ret;
1146
1147         if (args->args_count != 1) {
1148                 dev_err(dev, "invalid number of cells in 'phy' property\n");
1149                 return ERR_PTR(-EINVAL);
1150         }
1151
1152         for (index = 0; index < tphy->nphys; index++)
1153                 if (phy_np == tphy->phys[index]->phy->dev.of_node) {
1154                         instance = tphy->phys[index];
1155                         break;
1156                 }
1157
1158         if (!instance) {
1159                 dev_err(dev, "failed to find appropriate phy\n");
1160                 return ERR_PTR(-EINVAL);
1161         }
1162
1163         instance->type = args->args[0];
1164         if (!(instance->type == PHY_TYPE_USB2 ||
1165               instance->type == PHY_TYPE_USB3 ||
1166               instance->type == PHY_TYPE_PCIE ||
1167               instance->type == PHY_TYPE_SATA ||
1168               instance->type == PHY_TYPE_SGMII)) {
1169                 dev_err(dev, "unsupported device type: %d\n", instance->type);
1170                 return ERR_PTR(-EINVAL);
1171         }
1172
1173         switch (tphy->pdata->version) {
1174         case MTK_PHY_V1:
1175                 phy_v1_banks_init(tphy, instance);
1176                 break;
1177         case MTK_PHY_V2:
1178         case MTK_PHY_V3:
1179                 phy_v2_banks_init(tphy, instance);
1180                 break;
1181         default:
1182                 dev_err(dev, "phy version is not supported\n");
1183                 return ERR_PTR(-EINVAL);
1184         }
1185
1186         ret = phy_efuse_get(tphy, instance);
1187         if (ret)
1188                 return ERR_PTR(ret);
1189
1190         phy_parse_property(tphy, instance);
1191         phy_type_set(instance);
1192
1193         return instance->phy;
1194 }
1195
1196 static const struct phy_ops mtk_tphy_ops = {
1197         .init           = mtk_phy_init,
1198         .exit           = mtk_phy_exit,
1199         .power_on       = mtk_phy_power_on,
1200         .power_off      = mtk_phy_power_off,
1201         .set_mode       = mtk_phy_set_mode,
1202         .owner          = THIS_MODULE,
1203 };
1204
1205 static const struct mtk_phy_pdata tphy_v1_pdata = {
1206         .avoid_rx_sen_degradation = false,
1207         .version = MTK_PHY_V1,
1208 };
1209
1210 static const struct mtk_phy_pdata tphy_v2_pdata = {
1211         .avoid_rx_sen_degradation = false,
1212         .sw_efuse_supported = true,
1213         .version = MTK_PHY_V2,
1214 };
1215
1216 static const struct mtk_phy_pdata tphy_v3_pdata = {
1217         .sw_efuse_supported = true,
1218         .version = MTK_PHY_V3,
1219 };
1220
1221 static const struct mtk_phy_pdata mt8173_pdata = {
1222         .avoid_rx_sen_degradation = true,
1223         .version = MTK_PHY_V1,
1224 };
1225
1226 static const struct mtk_phy_pdata mt8195_pdata = {
1227         .sw_pll_48m_to_26m = true,
1228         .sw_efuse_supported = true,
1229         .version = MTK_PHY_V3,
1230 };
1231
1232 static const struct of_device_id mtk_tphy_id_table[] = {
1233         { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
1234         { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
1235         { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
1236         { .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata },
1237         { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
1238         { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
1239         { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
1240         { },
1241 };
1242 MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
1243
1244 static int mtk_tphy_probe(struct platform_device *pdev)
1245 {
1246         struct device *dev = &pdev->dev;
1247         struct device_node *np = dev->of_node;
1248         struct device_node *child_np;
1249         struct phy_provider *provider;
1250         struct resource *sif_res;
1251         struct mtk_tphy *tphy;
1252         struct resource res;
1253         int port, retval;
1254
1255         tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL);
1256         if (!tphy)
1257                 return -ENOMEM;
1258
1259         tphy->pdata = of_device_get_match_data(dev);
1260         if (!tphy->pdata)
1261                 return -EINVAL;
1262
1263         tphy->nphys = of_get_child_count(np);
1264         tphy->phys = devm_kcalloc(dev, tphy->nphys,
1265                                        sizeof(*tphy->phys), GFP_KERNEL);
1266         if (!tphy->phys)
1267                 return -ENOMEM;
1268
1269         tphy->dev = dev;
1270         platform_set_drvdata(pdev, tphy);
1271
1272         sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1273         /* SATA phy of V1 needn't it if not shared with PCIe or USB */
1274         if (sif_res && tphy->pdata->version == MTK_PHY_V1) {
1275                 /* get banks shared by multiple phys */
1276                 tphy->sif_base = devm_ioremap_resource(dev, sif_res);
1277                 if (IS_ERR(tphy->sif_base)) {
1278                         dev_err(dev, "failed to remap sif regs\n");
1279                         return PTR_ERR(tphy->sif_base);
1280                 }
1281         }
1282
1283         if (tphy->pdata->version < MTK_PHY_V3) {
1284                 tphy->src_ref_clk = U3P_REF_CLK;
1285                 tphy->src_coef = U3P_SLEW_RATE_COEF;
1286                 /* update parameters of slew rate calibrate if exist */
1287                 device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
1288                                          &tphy->src_ref_clk);
1289                 device_property_read_u32(dev, "mediatek,src-coef",
1290                                          &tphy->src_coef);
1291         }
1292
1293         port = 0;
1294         for_each_child_of_node(np, child_np) {
1295                 struct mtk_phy_instance *instance;
1296                 struct clk_bulk_data *clks;
1297                 struct device *subdev;
1298                 struct phy *phy;
1299
1300                 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
1301                 if (!instance) {
1302                         retval = -ENOMEM;
1303                         goto put_child;
1304                 }
1305
1306                 tphy->phys[port] = instance;
1307
1308                 phy = devm_phy_create(dev, child_np, &mtk_tphy_ops);
1309                 if (IS_ERR(phy)) {
1310                         dev_err(dev, "failed to create phy\n");
1311                         retval = PTR_ERR(phy);
1312                         goto put_child;
1313                 }
1314
1315                 subdev = &phy->dev;
1316                 retval = of_address_to_resource(child_np, 0, &res);
1317                 if (retval) {
1318                         dev_err(subdev, "failed to get address resource(id-%d)\n",
1319                                 port);
1320                         goto put_child;
1321                 }
1322
1323                 instance->port_base = devm_ioremap_resource(subdev, &res);
1324                 if (IS_ERR(instance->port_base)) {
1325                         retval = PTR_ERR(instance->port_base);
1326                         goto put_child;
1327                 }
1328
1329                 instance->phy = phy;
1330                 instance->index = port;
1331                 phy_set_drvdata(phy, instance);
1332                 port++;
1333
1334                 clks = instance->clks;
1335                 clks[0].id = "ref";     /* digital (& analog) clock */
1336                 clks[1].id = "da_ref";  /* analog clock */
1337                 retval = devm_clk_bulk_get_optional(subdev, TPHY_CLKS_CNT, clks);
1338                 if (retval)
1339                         goto put_child;
1340
1341                 retval = phy_type_syscon_get(instance, child_np);
1342                 if (retval)
1343                         goto put_child;
1344         }
1345
1346         provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
1347
1348         return PTR_ERR_OR_ZERO(provider);
1349 put_child:
1350         of_node_put(child_np);
1351         return retval;
1352 }
1353
1354 static struct platform_driver mtk_tphy_driver = {
1355         .probe          = mtk_tphy_probe,
1356         .driver         = {
1357                 .name   = "mtk-tphy",
1358                 .of_match_table = mtk_tphy_id_table,
1359         },
1360 };
1361
1362 module_platform_driver(mtk_tphy_driver);
1363
1364 MODULE_AUTHOR("Chunfeng Yun <[email protected]>");
1365 MODULE_DESCRIPTION("MediaTek T-PHY driver");
1366 MODULE_LICENSE("GPL v2");