drivers/phy/mediatek/phy-mtk-tphy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  * Author: Chunfeng Yun <[email protected]>
   5  *
   6  */
   7
   8 #include <dt-bindings/phy/phy.h>
   9 #include <linux/clk.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/delay.h>
  12 #include <linux/iopoll.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/module.h>
  15 #include <linux/nvmem-consumer.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/phy/phy.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/regmap.h>
  21
  22 #include "phy-mtk-io.h"
  23
  24 /* version V1 sub-banks offset base address */
  25 /* banks shared by multiple phys */
  26 #define SSUSB_SIFSLV_V1_SPLLC           0x000   /* shared by u3 phys */
  27 #define SSUSB_SIFSLV_V1_U2FREQ          0x100   /* shared by u2 phys */
  28 #define SSUSB_SIFSLV_V1_CHIP            0x300   /* shared by u3 phys */
  29 /* u2 phy bank */
  30 #define SSUSB_SIFSLV_V1_U2PHY_COM       0x000
  31 /* u3/pcie/sata phy banks */
  32 #define SSUSB_SIFSLV_V1_U3PHYD          0x000
  33 #define SSUSB_SIFSLV_V1_U3PHYA          0x200
  34
  35 /* version V2/V3 sub-banks offset base address */
  36 /* V3: U2FREQ is not used anymore, but reserved */
  37 /* u2 phy banks */
  38 #define SSUSB_SIFSLV_V2_MISC            0x000
  39 #define SSUSB_SIFSLV_V2_U2FREQ          0x100
  40 #define SSUSB_SIFSLV_V2_U2PHY_COM       0x300
  41 /* u3/pcie/sata phy banks */
  42 #define SSUSB_SIFSLV_V2_SPLLC           0x000
  43 #define SSUSB_SIFSLV_V2_CHIP            0x100
  44 #define SSUSB_SIFSLV_V2_U3PHYD          0x200
  45 #define SSUSB_SIFSLV_V2_U3PHYA          0x400
  46
  47 #define U3P_MISC_REG1           0x04
  48 #define MR1_EFUSE_AUTO_LOAD_DIS         BIT(6)
  49
  50 #define U3P_USBPHYACR0          0x000
  51 #define PA0_RG_U2PLL_FORCE_ON           BIT(15)
  52 #define PA0_USB20_PLL_PREDIV            GENMASK(7, 6)
  53 #define PA0_RG_USB20_INTR_EN            BIT(5)
  54
  55 #define U3P_USBPHYACR1          0x004
  56 #define PA1_RG_INTR_CAL         GENMASK(23, 19)
  57 #define PA1_RG_VRT_SEL                  GENMASK(14, 12)
  58 #define PA1_RG_TERM_SEL         GENMASK(10, 8)
  59
  60 #define U3P_USBPHYACR2          0x008
  61 #define PA2_RG_U2PLL_BW                 GENMASK(21, 19)
  62 #define PA2_RG_SIF_U2PLL_FORCE_EN       BIT(18)
  63
  64 #define U3P_USBPHYACR5          0x014
  65 #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
  66 #define PA5_RG_U2_HSTX_SRCTRL           GENMASK(14, 12)
  67 #define PA5_RG_U2_HS_100U_U3_EN BIT(11)
  68
  69 #define U3P_USBPHYACR6          0x018
  70 #define PA6_RG_U2_PRE_EMP               GENMASK(31, 30)
  71 #define PA6_RG_U2_BC11_SW_EN            BIT(23)
  72 #define PA6_RG_U2_OTG_VBUSCMP_EN        BIT(20)
  73 #define PA6_RG_U2_DISCTH                GENMASK(7, 4)
  74 #define PA6_RG_U2_SQTH          GENMASK(3, 0)
  75
  76 #define U3P_U2PHYACR4           0x020
  77 #define P2C_RG_USB20_GPIO_CTL           BIT(9)
  78 #define P2C_USB20_GPIO_MODE             BIT(8)
  79 #define P2C_U2_GPIO_CTR_MSK     (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
  80
  81 #define U3P_U2PHYA_RESV         0x030
  82 #define P2R_RG_U2PLL_FBDIV_26M          0x1bb13b
  83 #define P2R_RG_U2PLL_FBDIV_48M          0x3c0000
  84
  85 #define U3P_U2PHYA_RESV1        0x044
  86 #define P2R_RG_U2PLL_REFCLK_SEL BIT(5)
  87 #define P2R_RG_U2PLL_FRA_EN             BIT(3)
  88
  89 #define U3D_U2PHYDCR0           0x060
  90 #define P2C_RG_SIF_U2PLL_FORCE_ON       BIT(24)
  91
  92 #define U3P_U2PHYDTM0           0x068
  93 #define P2C_FORCE_UART_EN               BIT(26)
  94 #define P2C_FORCE_DATAIN                BIT(23)
  95 #define P2C_FORCE_DM_PULLDOWN           BIT(21)
  96 #define P2C_FORCE_DP_PULLDOWN           BIT(20)
  97 #define P2C_FORCE_XCVRSEL               BIT(19)
  98 #define P2C_FORCE_SUSPENDM              BIT(18)
  99 #define P2C_FORCE_TERMSEL               BIT(17)
 100 #define P2C_RG_DATAIN                   GENMASK(13, 10)
 101 #define P2C_RG_DMPULLDOWN               BIT(7)
 102 #define P2C_RG_DPPULLDOWN               BIT(6)
 103 #define P2C_RG_XCVRSEL                  GENMASK(5, 4)
 104 #define P2C_RG_SUSPENDM                 BIT(3)
 105 #define P2C_RG_TERMSEL                  BIT(2)
 106 #define P2C_DTM0_PART_MASK \
 107                 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
 108                 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
 109                 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
 110                 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
 111
 112 #define U3P_U2PHYDTM1           0x06C
 113 #define P2C_RG_UART_EN                  BIT(16)
 114 #define P2C_FORCE_IDDIG         BIT(9)
 115 #define P2C_RG_VBUSVALID                BIT(5)
 116 #define P2C_RG_SESSEND                  BIT(4)
 117 #define P2C_RG_AVALID                   BIT(2)
 118 #define P2C_RG_IDDIG                    BIT(1)
 119
 120 #define U3P_U2PHYBC12C          0x080
 121 #define P2C_RG_CHGDT_EN         BIT(0)
 122
 123 #define U3P_U3_CHIP_GPIO_CTLD           0x0c
 124 #define P3C_REG_IP_SW_RST               BIT(31)
 125 #define P3C_MCU_BUS_CK_GATE_EN          BIT(30)
 126 #define P3C_FORCE_IP_SW_RST             BIT(29)
 127
 128 #define U3P_U3_CHIP_GPIO_CTLE           0x10
 129 #define P3C_RG_SWRST_U3_PHYD            BIT(25)
 130 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN   BIT(24)
 131
 132 #define U3P_U3_PHYA_REG0        0x000
 133 #define P3A_RG_IEXT_INTR                GENMASK(15, 10)
 134 #define P3A_RG_CLKDRV_OFF               GENMASK(3, 2)
 135
 136 #define U3P_U3_PHYA_REG1        0x004
 137 #define P3A_RG_CLKDRV_AMP               GENMASK(31, 29)
 138
 139 #define U3P_U3_PHYA_REG6        0x018
 140 #define P3A_RG_TX_EIDLE_CM              GENMASK(31, 28)
 141
 142 #define U3P_U3_PHYA_REG9        0x024
 143 #define P3A_RG_RX_DAC_MUX               GENMASK(5, 1)
 144
 145 #define U3P_U3_PHYA_DA_REG0     0x100
 146 #define P3A_RG_XTAL_EXT_PE2H            GENMASK(17, 16)
 147 #define P3A_RG_XTAL_EXT_PE1H            GENMASK(13, 12)
 148 #define P3A_RG_XTAL_EXT_EN_U3           GENMASK(11, 10)
 149
 150 #define U3P_U3_PHYA_DA_REG4     0x108
 151 #define P3A_RG_PLL_DIVEN_PE2H           GENMASK(21, 19)
 152 #define P3A_RG_PLL_BC_PE2H              GENMASK(7, 6)
 153
 154 #define U3P_U3_PHYA_DA_REG5     0x10c
 155 #define P3A_RG_PLL_BR_PE2H              GENMASK(29, 28)
 156 #define P3A_RG_PLL_IC_PE2H              GENMASK(15, 12)
 157
 158 #define U3P_U3_PHYA_DA_REG6     0x110
 159 #define P3A_RG_PLL_IR_PE2H              GENMASK(19, 16)
 160
 161 #define U3P_U3_PHYA_DA_REG7     0x114
 162 #define P3A_RG_PLL_BP_PE2H              GENMASK(19, 16)
 163
 164 #define U3P_U3_PHYA_DA_REG20    0x13c
 165 #define P3A_RG_PLL_DELTA1_PE2H          GENMASK(31, 16)
 166
 167 #define U3P_U3_PHYA_DA_REG25    0x148
 168 #define P3A_RG_PLL_DELTA_PE2H           GENMASK(15, 0)
 169
 170 #define U3P_U3_PHYD_LFPS1               0x00c
 171 #define P3D_RG_FWAKE_TH         GENMASK(21, 16)
 172
 173 #define U3P_U3_PHYD_IMPCAL0             0x010
 174 #define P3D_RG_FORCE_TX_IMPEL           BIT(31)
 175 #define P3D_RG_TX_IMPEL                 GENMASK(28, 24)
 176
 177 #define U3P_U3_PHYD_IMPCAL1             0x014
 178 #define P3D_RG_FORCE_RX_IMPEL           BIT(31)
 179 #define P3D_RG_RX_IMPEL                 GENMASK(28, 24)
 180
 181 #define U3P_U3_PHYD_RSV                 0x054
 182 #define P3D_RG_EFUSE_AUTO_LOAD_DIS      BIT(12)
 183
 184 #define U3P_U3_PHYD_CDR1                0x05c
 185 #define P3D_RG_CDR_BIR_LTD1             GENMASK(28, 24)
 186 #define P3D_RG_CDR_BIR_LTD0             GENMASK(12, 8)
 187
 188 #define U3P_U3_PHYD_TOP1                0x100
 189 #define P3D_RG_PHY_MODE                 GENMASK(2, 1)
 190 #define P3D_RG_FORCE_PHY_MODE           BIT(0)
 191
 192 #define U3P_U3_PHYD_RXDET1              0x128
 193 #define P3D_RG_RXDET_STB2_SET           GENMASK(17, 9)
 194
 195 #define U3P_U3_PHYD_RXDET2              0x12c
 196 #define P3D_RG_RXDET_STB2_SET_P3        GENMASK(8, 0)
 197
 198 #define U3P_SPLLC_XTALCTL3              0x018
 199 #define XC3_RG_U3_XTAL_RX_PWD           BIT(9)
 200 #define XC3_RG_U3_FRC_XTAL_RX_PWD       BIT(8)
 201
 202 #define U3P_U2FREQ_FMCR0        0x00
 203 #define P2F_RG_MONCLK_SEL       GENMASK(27, 26)
 204 #define P2F_RG_FREQDET_EN       BIT(24)
 205 #define P2F_RG_CYCLECNT         GENMASK(23, 0)
 206
 207 #define U3P_U2FREQ_VALUE        0x0c
 208
 209 #define U3P_U2FREQ_FMMONR1      0x10
 210 #define P2F_USB_FM_VALID        BIT(0)
 211 #define P2F_RG_FRCK_EN          BIT(8)
 212
 213 #define U3P_REF_CLK             26      /* MHZ */
 214 #define U3P_SLEW_RATE_COEF      28
 215 #define U3P_SR_COEF_DIVISOR     1000
 216 #define U3P_FM_DET_CYCLE_CNT    1024
 217
 218 /* SATA register setting */
 219 #define PHYD_CTRL_SIGNAL_MODE4          0x1c
 220 /* CDR Charge Pump P-path current adjustment */
 221 #define RG_CDR_BICLTD1_GEN1_MSK         GENMASK(23, 20)
 222 #define RG_CDR_BICLTD0_GEN1_MSK         GENMASK(11, 8)
 223
 224 #define PHYD_DESIGN_OPTION2             0x24
 225 /* Symbol lock count selection */
 226 #define RG_LOCK_CNT_SEL_MSK             GENMASK(5, 4)
 227
 228 #define PHYD_DESIGN_OPTION9     0x40
 229 /* COMWAK GAP width window */
 230 #define RG_TG_MAX_MSK           GENMASK(20, 16)
 231 /* COMINIT GAP width window */
 232 #define RG_T2_MAX_MSK           GENMASK(13, 8)
 233 /* COMWAK GAP width window */
 234 #define RG_TG_MIN_MSK           GENMASK(7, 5)
 235 /* COMINIT GAP width window */
 236 #define RG_T2_MIN_MSK           GENMASK(4, 0)
 237
 238 #define ANA_RG_CTRL_SIGNAL1             0x4c
 239 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
 240 #define RG_IDRV_0DB_GEN1_MSK            GENMASK(13, 8)
 241
 242 #define ANA_RG_CTRL_SIGNAL4             0x58
 243 #define RG_CDR_BICLTR_GEN1_MSK          GENMASK(23, 20)
 244 /* Loop filter R1 resistance adjustment for Gen1 speed */
 245 #define RG_CDR_BR_GEN2_MSK              GENMASK(10, 8)
 246
 247 #define ANA_RG_CTRL_SIGNAL6             0x60
 248 /* I-path capacitance adjustment for Gen1 */
 249 #define RG_CDR_BC_GEN1_MSK              GENMASK(28, 24)
 250 #define RG_CDR_BIRLTR_GEN1_MSK          GENMASK(4, 0)
 251
 252 #define ANA_EQ_EYE_CTRL_SIGNAL1         0x6c
 253 /* RX Gen1 LEQ tuning step */
 254 #define RG_EQ_DLEQ_LFI_GEN1_MSK         GENMASK(11, 8)
 255
 256 #define ANA_EQ_EYE_CTRL_SIGNAL4         0xd8
 257 #define RG_CDR_BIRLTD0_GEN1_MSK         GENMASK(20, 16)
 258
 259 #define ANA_EQ_EYE_CTRL_SIGNAL5         0xdc
 260 #define RG_CDR_BIRLTD0_GEN3_MSK         GENMASK(4, 0)
 261
 262 /* PHY switch between pcie/usb3/sgmii/sata */
 263 #define USB_PHY_SWITCH_CTRL     0x0
 264 #define RG_PHY_SW_TYPE          GENMASK(3, 0)
 265 #define RG_PHY_SW_PCIE          0x0
 266 #define RG_PHY_SW_USB3          0x1
 267 #define RG_PHY_SW_SGMII         0x2
 268 #define RG_PHY_SW_SATA          0x3
 269
 270 #define TPHY_CLKS_CNT   2
 271
 272 #define USER_BUF_LEN(count) min_t(size_t, 8, (count))
 273
 274 enum mtk_phy_version {
 275         MTK_PHY_V1 = 1,
 276         MTK_PHY_V2,
 277         MTK_PHY_V3,
 278 };
 279
 280 struct mtk_phy_pdata {
 281         /* avoid RX sensitivity level degradation only for mt8173 */
 282         bool avoid_rx_sen_degradation;
 283         /*
 284          * workaround only for mt8195, HW fix it for others of V3,
 285          * u2phy should use integer mode instead of fractional mode of
 286          * 48M PLL, fix it by switching PLL to 26M from default 48M
 287          */
 288         bool sw_pll_48m_to_26m;
 289         /*
 290          * Some SoCs (e.g. mt8195) drop a bit when use auto load efuse,
 291          * support sw way, also support it for v2/v3 optionally.
 292          */
 293         bool sw_efuse_supported;
 294         enum mtk_phy_version version;
 295 };
 296
 297 struct u2phy_banks {
 298         void __iomem *misc;
 299         void __iomem *fmreg;
 300         void __iomem *com;
 301 };
 302
 303 struct u3phy_banks {
 304         void __iomem *spllc;
 305         void __iomem *chip;
 306         void __iomem *phyd; /* include u3phyd_bank2 */
 307         void __iomem *phya; /* include u3phya_da */
 308 };
 309
 310 struct mtk_phy_instance {
 311         struct phy *phy;
 312         void __iomem *port_base;
 313         union {
 314                 struct u2phy_banks u2_banks;
 315                 struct u3phy_banks u3_banks;
 316         };
 317         struct clk_bulk_data clks[TPHY_CLKS_CNT];
 318         u32 index;
 319         u32 type;
 320         struct regmap *type_sw;
 321         u32 type_sw_reg;
 322         u32 type_sw_index;
 323         u32 efuse_sw_en;
 324         u32 efuse_intr;
 325         u32 efuse_tx_imp;
 326         u32 efuse_rx_imp;
 327         int eye_src;
 328         int eye_vrt;
 329         int eye_term;
 330         int intr;
 331         int discth;
 332         int pre_emphasis;
 333         bool bc12_en;
 334         bool type_force_mode;
 335 };
 336
 337 struct mtk_tphy {
 338         struct device *dev;
 339         void __iomem *sif_base; /* only shared sif */
 340         const struct mtk_phy_pdata *pdata;
 341         struct mtk_phy_instance **phys;
 342         int nphys;
 343         int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
 344         int src_coef; /* coefficient for slew rate calibrate */
 345 };
 346
 347 #if IS_ENABLED(CONFIG_DEBUG_FS)
 348
 349 enum u2_phy_params {
 350         U2P_EYE_VRT = 0,
 351         U2P_EYE_TERM,
 352         U2P_EFUSE_EN,
 353         U2P_EFUSE_INTR,
 354         U2P_DISCTH,
 355         U2P_PRE_EMPHASIS,
 356 };
 357
 358 enum u3_phy_params {
 359         U3P_EFUSE_EN = 0,
 360         U3P_EFUSE_INTR,
 361         U3P_EFUSE_TX_IMP,
 362         U3P_EFUSE_RX_IMP,
 363 };
 364
 365 static const char *const u2_phy_files[] = {
 366         [U2P_EYE_VRT] = "vrt",
 367         [U2P_EYE_TERM] = "term",
 368         [U2P_EFUSE_EN] = "efuse",
 369         [U2P_EFUSE_INTR] = "intr",
 370         [U2P_DISCTH] = "discth",
 371         [U2P_PRE_EMPHASIS] = "preemph",
 372 };
 373
 374 static const char *const u3_phy_files[] = {
 375         [U3P_EFUSE_EN] = "efuse",
 376         [U3P_EFUSE_INTR] = "intr",
 377         [U3P_EFUSE_TX_IMP] = "tx-imp",
 378         [U3P_EFUSE_RX_IMP] = "rx-imp",
 379 };
 380
 381 static int u2_phy_params_show(struct seq_file *sf, void *unused)
 382 {
 383         struct mtk_phy_instance *inst = sf->private;
 384         struct u2phy_banks *u2_banks = &inst->u2_banks;
 385         void __iomem *com = u2_banks->com;
 386         u32 max = 0;
 387         u32 tmp = 0;
 388         u32 val = 0;
 389         int ret = debugfs_get_aux_num(sf->file);
 390
 391         switch (ret) {
 392         case U2P_EYE_VRT:
 393                 tmp = readl(com + U3P_USBPHYACR1);
 394                 val = FIELD_GET(PA1_RG_VRT_SEL, tmp);
 395                 max = FIELD_MAX(PA1_RG_VRT_SEL);
 396                 break;
 397
 398         case U2P_EYE_TERM:
 399                 tmp = readl(com + U3P_USBPHYACR1);
 400                 val = FIELD_GET(PA1_RG_TERM_SEL, tmp);
 401                 max = FIELD_MAX(PA1_RG_TERM_SEL);
 402                 break;
 403
 404         case U2P_EFUSE_EN:
 405                 if (u2_banks->misc) {
 406                         tmp = readl(u2_banks->misc + U3P_MISC_REG1);
 407                         max = 1;
 408                 }
 409
 410                 val = !!(tmp & MR1_EFUSE_AUTO_LOAD_DIS);
 411                 break;
 412
 413         case U2P_EFUSE_INTR:
 414                 tmp = readl(com + U3P_USBPHYACR1);
 415                 val = FIELD_GET(PA1_RG_INTR_CAL, tmp);
 416                 max = FIELD_MAX(PA1_RG_INTR_CAL);
 417                 break;
 418
 419         case U2P_DISCTH:
 420                 tmp = readl(com + U3P_USBPHYACR6);
 421                 val = FIELD_GET(PA6_RG_U2_DISCTH, tmp);
 422                 max = FIELD_MAX(PA6_RG_U2_DISCTH);
 423                 break;
 424
 425         case U2P_PRE_EMPHASIS:
 426                 tmp = readl(com + U3P_USBPHYACR6);
 427                 val = FIELD_GET(PA6_RG_U2_PRE_EMP, tmp);
 428                 max = FIELD_MAX(PA6_RG_U2_PRE_EMP);
 429                 break;
 430
 431         default:
 432                 seq_printf(sf, "invalid, %d\n", ret);
 433                 break;
 434         }
 435
 436         seq_printf(sf, "%s : %d [0, %d]\n", u2_phy_files[ret], val, max);
 437
 438         return 0;
 439 }
 440
 441 static int u2_phy_params_open(struct inode *inode, struct file *file)
 442 {
 443         return single_open(file, u2_phy_params_show, inode->i_private);
 444 }
 445
 446 static ssize_t u2_phy_params_write(struct file *file, const char __user *ubuf,
 447                                    size_t count, loff_t *ppos)
 448 {
 449         struct seq_file *sf = file->private_data;
 450         struct mtk_phy_instance *inst = sf->private;
 451         struct u2phy_banks *u2_banks = &inst->u2_banks;
 452         void __iomem *com = u2_banks->com;
 453         ssize_t rc;
 454         u32 val;
 455         int ret = debugfs_get_aux_num(file);
 456
 457         rc = kstrtouint_from_user(ubuf, USER_BUF_LEN(count), 0, &val);
 458         if (rc)
 459                 return rc;
 460
 461         switch (ret) {
 462         case U2P_EYE_VRT:
 463                 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, val);
 464                 break;
 465
 466         case U2P_EYE_TERM:
 467                 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, val);
 468                 break;
 469
 470         case U2P_EFUSE_EN:
 471                 if (u2_banks->misc)
 472                         mtk_phy_update_field(u2_banks->misc + U3P_MISC_REG1,
 473                                              MR1_EFUSE_AUTO_LOAD_DIS, !!val);
 474                 break;
 475
 476         case U2P_EFUSE_INTR:
 477                 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, val);
 478                 break;
 479
 480         case U2P_DISCTH:
 481                 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, val);
 482                 break;
 483
 484         case U2P_PRE_EMPHASIS:
 485                 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, val);
 486                 break;
 487
 488         default:
 489                 break;
 490         }
 491
 492         return count;
 493 }
 494
 495 static const struct file_operations u2_phy_fops = {
 496         .open = u2_phy_params_open,
 497         .write = u2_phy_params_write,
 498         .read = seq_read,
 499         .llseek = seq_lseek,
 500         .release = single_release,
 501 };
 502
 503 static void u2_phy_dbgfs_files_create(struct mtk_phy_instance *inst)
 504 {
 505         u32 count = ARRAY_SIZE(u2_phy_files);
 506         int i;
 507
 508         for (i = 0; i < count; i++)
 509                 debugfs_create_file_aux_num(u2_phy_files[i], 0644, inst->phy->debugfs,
 510                                     inst, i,  &u2_phy_fops);
 511 }
 512
 513 static int u3_phy_params_show(struct seq_file *sf, void *unused)
 514 {
 515         struct mtk_phy_instance *inst = sf->private;
 516         struct u3phy_banks *u3_banks = &inst->u3_banks;
 517         u32 val = 0;
 518         u32 max = 0;
 519         u32 tmp;
 520         int ret = debugfs_get_aux_num(sf->file);
 521
 522         switch (ret) {
 523         case U3P_EFUSE_EN:
 524                 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
 525                 val = !!(tmp & P3D_RG_EFUSE_AUTO_LOAD_DIS);
 526                 max = 1;
 527                 break;
 528
 529         case U3P_EFUSE_INTR:
 530                 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
 531                 val = FIELD_GET(P3A_RG_IEXT_INTR, tmp);
 532                 max = FIELD_MAX(P3A_RG_IEXT_INTR);
 533                 break;
 534
 535         case U3P_EFUSE_TX_IMP:
 536                 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0);
 537                 val = FIELD_GET(P3D_RG_TX_IMPEL, tmp);
 538                 max = FIELD_MAX(P3D_RG_TX_IMPEL);
 539                 break;
 540
 541         case U3P_EFUSE_RX_IMP:
 542                 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1);
 543                 val = FIELD_GET(P3D_RG_RX_IMPEL, tmp);
 544                 max = FIELD_MAX(P3D_RG_RX_IMPEL);
 545                 break;
 546
 547         default:
 548                 seq_printf(sf, "invalid, %d\n", ret);
 549                 break;
 550         }
 551
 552         seq_printf(sf, "%s : %d [0, %d]\n", u3_phy_files[ret], val, max);
 553
 554         return 0;
 555 }
 556
 557 static int u3_phy_params_open(struct inode *inode, struct file *file)
 558 {
 559         return single_open(file, u3_phy_params_show, inode->i_private);
 560 }
 561
 562 static ssize_t u3_phy_params_write(struct file *file, const char __user *ubuf,
 563                                    size_t count, loff_t *ppos)
 564 {
 565         struct seq_file *sf = file->private_data;
 566         struct mtk_phy_instance *inst = sf->private;
 567         struct u3phy_banks *u3_banks = &inst->u3_banks;
 568         void __iomem *phyd = u3_banks->phyd;
 569         ssize_t rc;
 570         u32 val;
 571         int ret = debugfs_get_aux_num(sf->file);
 572
 573         rc = kstrtouint_from_user(ubuf, USER_BUF_LEN(count), 0, &val);
 574         if (rc)
 575                 return rc;
 576
 577         switch (ret) {
 578         case U3P_EFUSE_EN:
 579                 mtk_phy_update_field(phyd + U3P_U3_PHYD_RSV,
 580                                      P3D_RG_EFUSE_AUTO_LOAD_DIS, !!val);
 581                 break;
 582
 583         case U3P_EFUSE_INTR:
 584                 mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0,
 585                                      P3A_RG_IEXT_INTR, val);
 586                 break;
 587
 588         case U3P_EFUSE_TX_IMP:
 589                 mtk_phy_update_field(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL, val);
 590                 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL);
 591                 break;
 592
 593         case U3P_EFUSE_RX_IMP:
 594                 mtk_phy_update_field(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL, val);
 595                 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL);
 596                 break;
 597
 598         default:
 599                 break;
 600         }
 601
 602         return count;
 603 }
 604
 605 static const struct file_operations u3_phy_fops = {
 606         .open = u3_phy_params_open,
 607         .write = u3_phy_params_write,
 608         .read = seq_read,
 609         .llseek = seq_lseek,
 610         .release = single_release,
 611 };
 612
 613 static void u3_phy_dbgfs_files_create(struct mtk_phy_instance *inst)
 614 {
 615         u32 count = ARRAY_SIZE(u3_phy_files);
 616         int i;
 617
 618         for (i = 0; i < count; i++)
 619                 debugfs_create_file_aux_num(u3_phy_files[i], 0644, inst->phy->debugfs,
 620                                     inst, i, &u3_phy_fops);
 621 }
 622
 623 static int phy_type_show(struct seq_file *sf, void *unused)
 624 {
 625         struct mtk_phy_instance *inst = sf->private;
 626         const char *type;
 627
 628         switch (inst->type) {
 629         case PHY_TYPE_USB2:
 630                 type = "USB2";
 631                 break;
 632         case PHY_TYPE_USB3:
 633                 type = "USB3";
 634                 break;
 635         case PHY_TYPE_PCIE:
 636                 type = "PCIe";
 637                 break;
 638         case PHY_TYPE_SGMII:
 639                 type = "SGMII";
 640                 break;
 641         case PHY_TYPE_SATA:
 642                 type = "SATA";
 643                 break;
 644         default:
 645                 type = "";
 646         }
 647
 648         seq_printf(sf, "%s\n", type);
 649
 650         return 0;
 651 }
 652 DEFINE_SHOW_ATTRIBUTE(phy_type);
 653
 654 /* these files will be removed when phy is released by phy core */
 655 static void phy_debugfs_init(struct mtk_phy_instance *inst)
 656 {
 657         debugfs_create_file("type", 0444, inst->phy->debugfs, inst, &phy_type_fops);
 658
 659         switch (inst->type) {
 660         case PHY_TYPE_USB2:
 661                 u2_phy_dbgfs_files_create(inst);
 662                 break;
 663         case PHY_TYPE_USB3:
 664         case PHY_TYPE_PCIE:
 665                 u3_phy_dbgfs_files_create(inst);
 666                 break;
 667         default:
 668                 break;
 669         }
 670 }
 671
 672 #else
 673
 674 static void phy_debugfs_init(struct mtk_phy_instance *inst)
 675 {}
 676
 677 #endif
 678
 679 static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
 680         struct mtk_phy_instance *instance)
 681 {
 682         struct u2phy_banks *u2_banks = &instance->u2_banks;
 683         void __iomem *fmreg = u2_banks->fmreg;
 684         void __iomem *com = u2_banks->com;
 685         int calibration_val;
 686         int fm_out;
 687         u32 tmp;
 688
 689         /* HW V3 doesn't support slew rate cal anymore */
 690         if (tphy->pdata->version == MTK_PHY_V3)
 691                 return;
 692
 693         /* use force value */
 694         if (instance->eye_src)
 695                 return;
 696
 697         /* enable USB ring oscillator */
 698         mtk_phy_set_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN);
 699         udelay(1);
 700
 701         /*enable free run clock */
 702         mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
 703
 704         /* set cycle count as 1024, and select u2 channel */
 705         tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
 706         tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
 707         tmp |= FIELD_PREP(P2F_RG_CYCLECNT, U3P_FM_DET_CYCLE_CNT);
 708         if (tphy->pdata->version == MTK_PHY_V1)
 709                 tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1);
 710
 711         writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
 712
 713         /* enable frequency meter */
 714         mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
 715
 716         /* ignore return value */
 717         readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp,
 718                            (tmp & P2F_USB_FM_VALID), 10, 200);
 719
 720         fm_out = readl(fmreg + U3P_U2FREQ_VALUE);
 721
 722         /* disable frequency meter */
 723         mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
 724
 725         /*disable free run clock */
 726         mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
 727
 728         if (fm_out) {
 729                 /* ( 1024 / FM_OUT ) x reference clock frequency x coef */
 730                 tmp = tphy->src_ref_clk * tphy->src_coef;
 731                 tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out;
 732                 calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
 733         } else {
 734                 /* if FM detection fail, set default value */
 735                 calibration_val = 4;
 736         }
 737         dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
 738                 instance->index, fm_out, calibration_val,
 739                 tphy->src_ref_clk, tphy->src_coef);
 740
 741         /* set HS slew rate */
 742         mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
 743                              calibration_val);
 744
 745         /* disable USB ring oscillator */
 746         mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN);
 747 }
 748
 749 static void u3_phy_instance_init(struct mtk_tphy *tphy,
 750         struct mtk_phy_instance *instance)
 751 {
 752         struct u3phy_banks *u3_banks = &instance->u3_banks;
 753         void __iomem *phya = u3_banks->phya;
 754         void __iomem *phyd = u3_banks->phyd;
 755
 756         if (instance->type_force_mode) {
 757                 /* force phy as usb mode, default is pcie rc mode */
 758                 mtk_phy_update_field(phyd + U3P_U3_PHYD_TOP1, P3D_RG_PHY_MODE, 1);
 759                 mtk_phy_set_bits(phyd + U3P_U3_PHYD_TOP1, P3D_RG_FORCE_PHY_MODE);
 760                 /* power down phy by ip and pipe reset */
 761                 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD,
 762                                  P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN);
 763                 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE,
 764                                  P3C_RG_SWRST_U3_PHYD | P3C_RG_SWRST_U3_PHYD_FORCE_EN);
 765                 udelay(10);
 766                 /* power on phy again */
 767                 mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD,
 768                                    P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN);
 769                 mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE,
 770                                    P3C_RG_SWRST_U3_PHYD | P3C_RG_SWRST_U3_PHYD_FORCE_EN);
 771         }
 772
 773         /* gating PCIe Analog XTAL clock */
 774         mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
 775                          XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
 776
 777         /* gating XSQ */
 778         mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3, 2);
 779
 780         mtk_phy_update_field(phya + U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX, 4);
 781
 782         mtk_phy_update_field(phya + U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM, 0xe);
 783
 784         mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1,
 785                             P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
 786                             FIELD_PREP(P3D_RG_CDR_BIR_LTD0, 0xc) |
 787                             FIELD_PREP(P3D_RG_CDR_BIR_LTD1, 0x3));
 788
 789         mtk_phy_update_field(phyd + U3P_U3_PHYD_LFPS1, P3D_RG_FWAKE_TH, 0x34);
 790
 791         mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET1, P3D_RG_RXDET_STB2_SET, 0x10);
 792
 793         mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET2, P3D_RG_RXDET_STB2_SET_P3, 0x10);
 794
 795         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 796 }
 797
 798 static void u2_phy_pll_26m_set(struct mtk_tphy *tphy,
 799         struct mtk_phy_instance *instance)
 800 {
 801         struct u2phy_banks *u2_banks = &instance->u2_banks;
 802         void __iomem *com = u2_banks->com;
 803
 804         if (!tphy->pdata->sw_pll_48m_to_26m)
 805                 return;
 806
 807         mtk_phy_update_field(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, 0);
 808
 809         mtk_phy_update_field(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, 3);
 810
 811         writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV);
 812
 813         mtk_phy_set_bits(com + U3P_U2PHYA_RESV1,
 814                          P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL);
 815 }
 816
 817 static void u2_phy_instance_init(struct mtk_tphy *tphy,
 818         struct mtk_phy_instance *instance)
 819 {
 820         struct u2phy_banks *u2_banks = &instance->u2_banks;
 821         void __iomem *com = u2_banks->com;
 822         u32 index = instance->index;
 823
 824         /* switch to USB function, and enable usb pll */
 825         mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
 826
 827         mtk_phy_clear_bits(com + U3P_U2PHYDTM0,
 828                            P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
 829
 830         mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
 831
 832         mtk_phy_set_bits(com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
 833
 834         /* disable switch 100uA current to SSUSB */
 835         mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
 836
 837         mtk_phy_clear_bits(com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
 838
 839         if (tphy->pdata->avoid_rx_sen_degradation) {
 840                 if (!index) {
 841                         mtk_phy_set_bits(com + U3P_USBPHYACR2, PA2_RG_SIF_U2PLL_FORCE_EN);
 842
 843                         mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
 844                 } else {
 845                         mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
 846
 847                         mtk_phy_set_bits(com + U3P_U2PHYDTM0,
 848                                          P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
 849                 }
 850         }
 851
 852         /* DP/DM BC1.1 path Disable */
 853         mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN);
 854
 855         mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, 2);
 856
 857         /* Workaround only for mt8195, HW fix it for others (V3) */
 858         u2_phy_pll_26m_set(tphy, instance);
 859
 860         dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
 861 }
 862
 863 static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
 864         struct mtk_phy_instance *instance)
 865 {
 866         struct u2phy_banks *u2_banks = &instance->u2_banks;
 867         void __iomem *com = u2_banks->com;
 868         u32 index = instance->index;
 869
 870         /* OTG Enable */
 871         mtk_phy_set_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
 872
 873         mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
 874
 875         mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND);
 876
 877         if (tphy->pdata->avoid_rx_sen_degradation && index) {
 878                 mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
 879
 880                 mtk_phy_set_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
 881         }
 882         dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
 883 }
 884
 885 static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
 886         struct mtk_phy_instance *instance)
 887 {
 888         struct u2phy_banks *u2_banks = &instance->u2_banks;
 889         void __iomem *com = u2_banks->com;
 890         u32 index = instance->index;
 891
 892         /* OTG Disable */
 893         mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN);
 894
 895         mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID);
 896
 897         mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND);
 898
 899         if (tphy->pdata->avoid_rx_sen_degradation && index) {
 900                 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
 901
 902                 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
 903         }
 904
 905         dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
 906 }
 907
 908 static void u2_phy_instance_exit(struct mtk_tphy *tphy,
 909         struct mtk_phy_instance *instance)
 910 {
 911         struct u2phy_banks *u2_banks = &instance->u2_banks;
 912         void __iomem *com = u2_banks->com;
 913         u32 index = instance->index;
 914
 915         if (tphy->pdata->avoid_rx_sen_degradation && index) {
 916                 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON);
 917
 918                 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM);
 919         }
 920 }
 921
 922 static void u2_phy_instance_set_mode(struct mtk_tphy *tphy,
 923                                      struct mtk_phy_instance *instance,
 924                                      enum phy_mode mode)
 925 {
 926         struct u2phy_banks *u2_banks = &instance->u2_banks;
 927         u32 tmp;
 928
 929         tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
 930         switch (mode) {
 931         case PHY_MODE_USB_DEVICE:
 932                 tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
 933                 break;
 934         case PHY_MODE_USB_HOST:
 935                 tmp |= P2C_FORCE_IDDIG;
 936                 tmp &= ~P2C_RG_IDDIG;
 937                 break;
 938         case PHY_MODE_USB_OTG:
 939                 tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
 940                 break;
 941         default:
 942                 return;
 943         }
 944         writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
 945 }
 946
 947 static void pcie_phy_instance_init(struct mtk_tphy *tphy,
 948         struct mtk_phy_instance *instance)
 949 {
 950         struct u3phy_banks *u3_banks = &instance->u3_banks;
 951         void __iomem *phya = u3_banks->phya;
 952
 953         if (tphy->pdata->version != MTK_PHY_V1)
 954                 return;
 955
 956         mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0,
 957                             P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
 958                             FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) |
 959                             FIELD_PREP(P3A_RG_XTAL_EXT_PE2H, 0x2));
 960
 961         /* ref clk drive */
 962         mtk_phy_update_field(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, 0x4);
 963
 964         mtk_phy_update_field(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, 0x1);
 965
 966         /* SSC delta -5000ppm */
 967         mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H, 0x3c);
 968
 969         mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H, 0x36);
 970
 971         /* change pll BW 0.6M */
 972         mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG5,
 973                             P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
 974                             FIELD_PREP(P3A_RG_PLL_BR_PE2H, 0x1) |
 975                             FIELD_PREP(P3A_RG_PLL_IC_PE2H, 0x1));
 976
 977         mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG4,
 978                             P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
 979                             FIELD_PREP(P3A_RG_PLL_BC_PE2H, 0x3));
 980
 981         mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H, 0x2);
 982
 983         mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H, 0xa);
 984
 985         /* Tx Detect Rx Timing: 10us -> 5us */
 986         mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
 987                              P3D_RG_RXDET_STB2_SET, 0x10);
 988
 989         mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
 990                              P3D_RG_RXDET_STB2_SET_P3, 0x10);
 991
 992         /* wait for PCIe subsys register to active */
 993         usleep_range(2500, 3000);
 994         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 995 }
 996
 997 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
 998         struct mtk_phy_instance *instance)
 999 {
1000         struct u3phy_banks *bank = &instance->u3_banks;
1001
1002         mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
1003                            P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
1004
1005         mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
1006                            P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
1007 }
1008
1009 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
1010         struct mtk_phy_instance *instance)
1011
1012 {
1013         struct u3phy_banks *bank = &instance->u3_banks;
1014
1015         mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
1016                          P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
1017
1018         mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
1019                          P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
1020 }
1021
1022 static void sata_phy_instance_init(struct mtk_tphy *tphy,
1023         struct mtk_phy_instance *instance)
1024 {
1025         struct u3phy_banks *u3_banks = &instance->u3_banks;
1026         void __iomem *phyd = u3_banks->phyd;
1027
1028         /* charge current adjustment */
1029         mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL6,
1030                             RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK,
1031                             FIELD_PREP(RG_CDR_BIRLTR_GEN1_MSK, 0x6) |
1032                             FIELD_PREP(RG_CDR_BC_GEN1_MSK, 0x1a));
1033
1034         mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK, 0x18);
1035
1036         mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK, 0x06);
1037
1038         mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL4,
1039                             RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK,
1040                             FIELD_PREP(RG_CDR_BICLTR_GEN1_MSK, 0x0c) |
1041                             FIELD_PREP(RG_CDR_BR_GEN2_MSK, 0x07));
1042
1043         mtk_phy_update_bits(phyd + PHYD_CTRL_SIGNAL_MODE4,
1044                             RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK,
1045                             FIELD_PREP(RG_CDR_BICLTD0_GEN1_MSK, 0x08) |
1046                             FIELD_PREP(RG_CDR_BICLTD1_GEN1_MSK, 0x02));
1047
1048         mtk_phy_update_field(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK, 0x02);
1049
1050         mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9,
1051                             RG_T2_MIN_MSK | RG_TG_MIN_MSK,
1052                             FIELD_PREP(RG_T2_MIN_MSK, 0x12) |
1053                             FIELD_PREP(RG_TG_MIN_MSK, 0x04));
1054
1055         mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9,
1056                             RG_T2_MAX_MSK | RG_TG_MAX_MSK,
1057                             FIELD_PREP(RG_T2_MAX_MSK, 0x31) |
1058                             FIELD_PREP(RG_TG_MAX_MSK, 0x0e));
1059
1060         mtk_phy_update_field(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK, 0x20);
1061
1062         mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK, 0x03);
1063
1064         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
1065 }
1066
1067 static void phy_v1_banks_init(struct mtk_tphy *tphy,
1068                               struct mtk_phy_instance *instance)
1069 {
1070         struct u2phy_banks *u2_banks = &instance->u2_banks;
1071         struct u3phy_banks *u3_banks = &instance->u3_banks;
1072
1073         switch (instance->type) {
1074         case PHY_TYPE_USB2:
1075                 u2_banks->misc = NULL;
1076                 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
1077                 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
1078                 break;
1079         case PHY_TYPE_USB3:
1080         case PHY_TYPE_PCIE:
1081                 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
1082                 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
1083                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
1084                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
1085                 break;
1086         case PHY_TYPE_SATA:
1087                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
1088                 break;
1089         default:
1090                 dev_err(tphy->dev, "incompatible PHY type\n");
1091                 return;
1092         }
1093 }
1094
1095 static void phy_v2_banks_init(struct mtk_tphy *tphy,
1096                               struct mtk_phy_instance *instance)
1097 {
1098         struct u2phy_banks *u2_banks = &instance->u2_banks;
1099         struct u3phy_banks *u3_banks = &instance->u3_banks;
1100
1101         switch (instance->type) {
1102         case PHY_TYPE_USB2:
1103                 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
1104                 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
1105                 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
1106                 break;
1107         case PHY_TYPE_USB3:
1108         case PHY_TYPE_PCIE:
1109                 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
1110                 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
1111                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
1112                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
1113                 break;
1114         default:
1115                 dev_err(tphy->dev, "incompatible PHY type\n");
1116                 return;
1117         }
1118 }
1119
1120 static void phy_parse_property(struct mtk_tphy *tphy,
1121                                 struct mtk_phy_instance *instance)
1122 {
1123         struct device *dev = &instance->phy->dev;
1124
1125         if (instance->type == PHY_TYPE_USB3)
1126                 instance->type_force_mode = device_property_read_bool(dev, "mediatek,force-mode");
1127
1128         if (instance->type != PHY_TYPE_USB2)
1129                 return;
1130
1131         instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");
1132         device_property_read_u32(dev, "mediatek,eye-src",
1133                                  &instance->eye_src);
1134         device_property_read_u32(dev, "mediatek,eye-vrt",
1135                                  &instance->eye_vrt);
1136         device_property_read_u32(dev, "mediatek,eye-term",
1137                                  &instance->eye_term);
1138         device_property_read_u32(dev, "mediatek,intr",
1139                                  &instance->intr);
1140         device_property_read_u32(dev, "mediatek,discth",
1141                                  &instance->discth);
1142         device_property_read_u32(dev, "mediatek,pre-emphasis",
1143                                  &instance->pre_emphasis);
1144         dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n",
1145                 instance->bc12_en, instance->eye_src,
1146                 instance->eye_vrt, instance->eye_term,
1147                 instance->intr, instance->discth);
1148         dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis);
1149 }
1150
1151 static void u2_phy_props_set(struct mtk_tphy *tphy,
1152                              struct mtk_phy_instance *instance)
1153 {
1154         struct u2phy_banks *u2_banks = &instance->u2_banks;
1155         void __iomem *com = u2_banks->com;
1156
1157         if (instance->bc12_en) /* BC1.2 path Enable */
1158                 mtk_phy_set_bits(com + U3P_U2PHYBC12C, P2C_RG_CHGDT_EN);
1159
1160         if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src)
1161                 mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
1162                                      instance->eye_src);
1163
1164         if (instance->eye_vrt)
1165                 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL,
1166                                      instance->eye_vrt);
1167
1168         if (instance->eye_term)
1169                 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL,
1170                                      instance->eye_term);
1171
1172         if (instance->intr) {
1173                 if (u2_banks->misc)
1174                         mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1,
1175                                          MR1_EFUSE_AUTO_LOAD_DIS);
1176
1177                 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
1178                                      instance->intr);
1179         }
1180
1181         if (instance->discth)
1182                 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH,
1183                                      instance->discth);
1184
1185         if (instance->pre_emphasis)
1186                 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP,
1187                                      instance->pre_emphasis);
1188 }
1189
1190 /* type switch for usb3/pcie/sgmii/sata */
1191 static int phy_type_syscon_get(struct mtk_phy_instance *instance,
1192                                struct device_node *dn)
1193 {
1194         struct of_phandle_args args;
1195         int ret;
1196
1197         /* type switch function is optional */
1198         if (!of_property_read_bool(dn, "mediatek,syscon-type"))
1199                 return 0;
1200
1201         ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",
1202                                                2, 0, &args);
1203         if (ret)
1204                 return ret;
1205
1206         instance->type_sw_reg = args.args[0];
1207         instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
1208         instance->type_sw = syscon_node_to_regmap(args.np);
1209         of_node_put(args.np);
1210         dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
1211                  instance->type_sw_reg, instance->type_sw_index);
1212
1213         return PTR_ERR_OR_ZERO(instance->type_sw);
1214 }
1215
1216 static int phy_type_set(struct mtk_phy_instance *instance)
1217 {
1218         int type;
1219         u32 offset;
1220
1221         if (!instance->type_sw)
1222                 return 0;
1223
1224         switch (instance->type) {
1225         case PHY_TYPE_USB3:
1226                 type = RG_PHY_SW_USB3;
1227                 break;
1228         case PHY_TYPE_PCIE:
1229                 type = RG_PHY_SW_PCIE;
1230                 break;
1231         case PHY_TYPE_SGMII:
1232                 type = RG_PHY_SW_SGMII;
1233                 break;
1234         case PHY_TYPE_SATA:
1235                 type = RG_PHY_SW_SATA;
1236                 break;
1237         case PHY_TYPE_USB2:
1238         default:
1239                 return 0;
1240         }
1241
1242         offset = instance->type_sw_index * BITS_PER_BYTE;
1243         regmap_update_bits(instance->type_sw, instance->type_sw_reg,
1244                            RG_PHY_SW_TYPE << offset, type << offset);
1245
1246         return 0;
1247 }
1248
1249 static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instance)
1250 {
1251         struct device *dev = &instance->phy->dev;
1252         int ret = 0;
1253
1254         /* tphy v1 doesn't support sw efuse, skip it */
1255         if (!tphy->pdata->sw_efuse_supported) {
1256                 instance->efuse_sw_en = 0;
1257                 return 0;
1258         }
1259
1260         /* software efuse is optional */
1261         instance->efuse_sw_en = device_property_read_bool(dev, "nvmem-cells");
1262         if (!instance->efuse_sw_en)
1263                 return 0;
1264
1265         switch (instance->type) {
1266         case PHY_TYPE_USB2:
1267                 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
1268                 if (ret) {
1269                         dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
1270                         break;
1271                 }
1272
1273                 /* no efuse, ignore it */
1274                 if (!instance->efuse_intr) {
1275                         dev_warn(dev, "no u2 intr efuse, but dts enable it\n");
1276                         instance->efuse_sw_en = 0;
1277                         break;
1278                 }
1279
1280                 dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr);
1281                 break;
1282
1283         case PHY_TYPE_USB3:
1284         case PHY_TYPE_PCIE:
1285                 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
1286                 if (ret) {
1287                         dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
1288                         break;
1289                 }
1290
1291                 ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp);
1292                 if (ret) {
1293                         dev_err(dev, "fail to get u3 rx_imp efuse, %d\n", ret);
1294                         break;
1295                 }
1296
1297                 ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp);
1298                 if (ret) {
1299                         dev_err(dev, "fail to get u3 tx_imp efuse, %d\n", ret);
1300                         break;
1301                 }
1302
1303                 /* no efuse, ignore it */
1304                 if (!instance->efuse_intr &&
1305                     !instance->efuse_rx_imp &&
1306                     !instance->efuse_tx_imp) {
1307                         dev_warn(dev, "no u3 intr efuse, but dts enable it\n");
1308                         instance->efuse_sw_en = 0;
1309                         break;
1310                 }
1311
1312                 dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n",
1313                         instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp);
1314                 break;
1315         default:
1316                 dev_err(dev, "no sw efuse for type %d\n", instance->type);
1317                 ret = -EINVAL;
1318         }
1319
1320         return ret;
1321 }
1322
1323 static void phy_efuse_set(struct mtk_phy_instance *instance)
1324 {
1325         struct device *dev = &instance->phy->dev;
1326         struct u2phy_banks *u2_banks = &instance->u2_banks;
1327         struct u3phy_banks *u3_banks = &instance->u3_banks;
1328
1329         if (!instance->efuse_sw_en)
1330                 return;
1331
1332         switch (instance->type) {
1333         case PHY_TYPE_USB2:
1334                 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS);
1335
1336                 mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
1337                                      instance->efuse_intr);
1338                 break;
1339         case PHY_TYPE_USB3:
1340         case PHY_TYPE_PCIE:
1341                 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS);
1342
1343                 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL,
1344                                     instance->efuse_tx_imp);
1345                 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL);
1346
1347                 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL,
1348                                     instance->efuse_rx_imp);
1349                 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL);
1350
1351                 mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR,
1352                                     instance->efuse_intr);
1353                 break;
1354         default:
1355                 dev_warn(dev, "no sw efuse for type %d\n", instance->type);
1356                 break;
1357         }
1358 }
1359
1360 static int mtk_phy_init(struct phy *phy)
1361 {
1362         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1363         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1364         int ret;
1365
1366         ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks);
1367         if (ret)
1368                 return ret;
1369
1370         phy_efuse_set(instance);
1371
1372         switch (instance->type) {
1373         case PHY_TYPE_USB2:
1374                 u2_phy_instance_init(tphy, instance);
1375                 u2_phy_props_set(tphy, instance);
1376                 break;
1377         case PHY_TYPE_USB3:
1378                 u3_phy_instance_init(tphy, instance);
1379                 break;
1380         case PHY_TYPE_PCIE:
1381                 pcie_phy_instance_init(tphy, instance);
1382                 break;
1383         case PHY_TYPE_SATA:
1384                 sata_phy_instance_init(tphy, instance);
1385                 break;
1386         case PHY_TYPE_SGMII:
1387                 /* nothing to do, only used to set type */
1388                 break;
1389         default:
1390                 dev_err(tphy->dev, "incompatible PHY type\n");
1391                 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);
1392                 return -EINVAL;
1393         }
1394
1395         return 0;
1396 }
1397
1398 static int mtk_phy_power_on(struct phy *phy)
1399 {
1400         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1401         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1402
1403         if (instance->type == PHY_TYPE_USB2) {
1404                 u2_phy_instance_power_on(tphy, instance);
1405                 hs_slew_rate_calibrate(tphy, instance);
1406         } else if (instance->type == PHY_TYPE_PCIE) {
1407                 pcie_phy_instance_power_on(tphy, instance);
1408         }
1409
1410         return 0;
1411 }
1412
1413 static int mtk_phy_power_off(struct phy *phy)
1414 {
1415         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1416         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1417
1418         if (instance->type == PHY_TYPE_USB2)
1419                 u2_phy_instance_power_off(tphy, instance);
1420         else if (instance->type == PHY_TYPE_PCIE)
1421                 pcie_phy_instance_power_off(tphy, instance);
1422
1423         return 0;
1424 }
1425
1426 static int mtk_phy_exit(struct phy *phy)
1427 {
1428         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1429         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1430
1431         if (instance->type == PHY_TYPE_USB2)
1432                 u2_phy_instance_exit(tphy, instance);
1433
1434         clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);
1435         return 0;
1436 }
1437
1438 static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1439 {
1440         struct mtk_phy_instance *instance = phy_get_drvdata(phy);
1441         struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
1442
1443         if (instance->type == PHY_TYPE_USB2)
1444                 u2_phy_instance_set_mode(tphy, instance, mode);
1445
1446         return 0;
1447 }
1448
1449 static struct phy *mtk_phy_xlate(struct device *dev,
1450                                         const struct of_phandle_args *args)
1451 {
1452         struct mtk_tphy *tphy = dev_get_drvdata(dev);
1453         struct mtk_phy_instance *instance = NULL;
1454         struct device_node *phy_np = args->np;
1455         int index;
1456         int ret;
1457
1458         if (args->args_count != 1) {
1459                 dev_err(dev, "invalid number of cells in 'phy' property\n");
1460                 return ERR_PTR(-EINVAL);
1461         }
1462
1463         for (index = 0; index < tphy->nphys; index++)
1464                 if (phy_np == tphy->phys[index]->phy->dev.of_node) {
1465                         instance = tphy->phys[index];
1466                         break;
1467                 }
1468
1469         if (!instance) {
1470                 dev_err(dev, "failed to find appropriate phy\n");
1471                 return ERR_PTR(-EINVAL);
1472         }
1473
1474         instance->type = args->args[0];
1475         if (!(instance->type == PHY_TYPE_USB2 ||
1476               instance->type == PHY_TYPE_USB3 ||
1477               instance->type == PHY_TYPE_PCIE ||
1478               instance->type == PHY_TYPE_SATA ||
1479               instance->type == PHY_TYPE_SGMII)) {
1480                 dev_err(dev, "unsupported device type: %d\n", instance->type);
1481                 return ERR_PTR(-EINVAL);
1482         }
1483
1484         switch (tphy->pdata->version) {
1485         case MTK_PHY_V1:
1486                 phy_v1_banks_init(tphy, instance);
1487                 break;
1488         case MTK_PHY_V2:
1489         case MTK_PHY_V3:
1490                 phy_v2_banks_init(tphy, instance);
1491                 break;
1492         default:
1493                 dev_err(dev, "phy version is not supported\n");
1494                 return ERR_PTR(-EINVAL);
1495         }
1496
1497         ret = phy_efuse_get(tphy, instance);
1498         if (ret)
1499                 return ERR_PTR(ret);
1500
1501         phy_parse_property(tphy, instance);
1502         phy_type_set(instance);
1503         phy_debugfs_init(instance);
1504
1505         return instance->phy;
1506 }
1507
1508 static const struct phy_ops mtk_tphy_ops = {
1509         .init           = mtk_phy_init,
1510         .exit           = mtk_phy_exit,
1511         .power_on       = mtk_phy_power_on,
1512         .power_off      = mtk_phy_power_off,
1513         .set_mode       = mtk_phy_set_mode,
1514         .owner          = THIS_MODULE,
1515 };
1516
1517 static const struct mtk_phy_pdata tphy_v1_pdata = {
1518         .avoid_rx_sen_degradation = false,
1519         .version = MTK_PHY_V1,
1520 };
1521
1522 static const struct mtk_phy_pdata tphy_v2_pdata = {
1523         .avoid_rx_sen_degradation = false,
1524         .sw_efuse_supported = true,
1525         .version = MTK_PHY_V2,
1526 };
1527
1528 static const struct mtk_phy_pdata tphy_v3_pdata = {
1529         .sw_efuse_supported = true,
1530         .version = MTK_PHY_V3,
1531 };
1532
1533 static const struct mtk_phy_pdata mt8173_pdata = {
1534         .avoid_rx_sen_degradation = true,
1535         .version = MTK_PHY_V1,
1536 };
1537
1538 static const struct mtk_phy_pdata mt8195_pdata = {
1539         .sw_pll_48m_to_26m = true,
1540         .sw_efuse_supported = true,
1541         .version = MTK_PHY_V3,
1542 };
1543
1544 static const struct of_device_id mtk_tphy_id_table[] = {
1545         { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
1546         { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
1547         { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
1548         { .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata },
1549         { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
1550         { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
1551         { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
1552         { },
1553 };
1554 MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
1555
1556 static int mtk_tphy_probe(struct platform_device *pdev)
1557 {
1558         struct device *dev = &pdev->dev;
1559         struct device_node *np = dev->of_node;
1560         struct phy_provider *provider;
1561         struct resource *sif_res;
1562         struct mtk_tphy *tphy;
1563         struct resource res;
1564         int port;
1565
1566         tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL);
1567         if (!tphy)
1568                 return -ENOMEM;
1569
1570         tphy->pdata = of_device_get_match_data(dev);
1571         if (!tphy->pdata)
1572                 return -EINVAL;
1573
1574         tphy->nphys = of_get_child_count(np);
1575         tphy->phys = devm_kcalloc(dev, tphy->nphys,
1576                                        sizeof(*tphy->phys), GFP_KERNEL);
1577         if (!tphy->phys)
1578                 return -ENOMEM;
1579
1580         tphy->dev = dev;
1581         platform_set_drvdata(pdev, tphy);
1582
1583         sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1584         /* SATA phy of V1 needn't it if not shared with PCIe or USB */
1585         if (sif_res && tphy->pdata->version == MTK_PHY_V1) {
1586                 /* get banks shared by multiple phys */
1587                 tphy->sif_base = devm_ioremap_resource(dev, sif_res);
1588                 if (IS_ERR(tphy->sif_base)) {
1589                         dev_err(dev, "failed to remap sif regs\n");
1590                         return PTR_ERR(tphy->sif_base);
1591                 }
1592         }
1593
1594         if (tphy->pdata->version < MTK_PHY_V3) {
1595                 tphy->src_ref_clk = U3P_REF_CLK;
1596                 tphy->src_coef = U3P_SLEW_RATE_COEF;
1597                 /* update parameters of slew rate calibrate if exist */
1598                 device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
1599                                          &tphy->src_ref_clk);
1600                 device_property_read_u32(dev, "mediatek,src-coef",
1601                                          &tphy->src_coef);
1602         }
1603
1604         port = 0;
1605         for_each_child_of_node_scoped(np, child_np) {
1606                 struct mtk_phy_instance *instance;
1607                 struct clk_bulk_data *clks;
1608                 struct device *subdev;
1609                 struct phy *phy;
1610                 int retval;
1611
1612                 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
1613                 if (!instance)
1614                         return -ENOMEM;
1615
1616                 tphy->phys[port] = instance;
1617
1618                 phy = devm_phy_create(dev, child_np, &mtk_tphy_ops);
1619                 if (IS_ERR(phy)) {
1620                         dev_err(dev, "failed to create phy\n");
1621                         return PTR_ERR(phy);
1622                 }
1623
1624                 subdev = &phy->dev;
1625                 retval = of_address_to_resource(child_np, 0, &res);
1626                 if (retval) {
1627                         dev_err(subdev, "failed to get address resource(id-%d)\n",
1628                                 port);
1629                         return retval;
1630                 }
1631
1632                 instance->port_base = devm_ioremap_resource(subdev, &res);
1633                 if (IS_ERR(instance->port_base))
1634                         return PTR_ERR(instance->port_base);
1635
1636                 instance->phy = phy;
1637                 instance->index = port;
1638                 phy_set_drvdata(phy, instance);
1639                 port++;
1640
1641                 clks = instance->clks;
1642                 clks[0].id = "ref";     /* digital (& analog) clock */
1643                 clks[1].id = "da_ref";  /* analog clock */
1644                 retval = devm_clk_bulk_get_optional(subdev, TPHY_CLKS_CNT, clks);
1645                 if (retval)
1646                         return retval;
1647
1648                 retval = phy_type_syscon_get(instance, child_np);
1649                 if (retval)
1650                         return retval;
1651         }
1652
1653         provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
1654
1655         return PTR_ERR_OR_ZERO(provider);
1656 }
1657
1658 static struct platform_driver mtk_tphy_driver = {
1659         .probe          = mtk_tphy_probe,
1660         .driver         = {
1661                 .name   = "mtk-tphy",
1662                 .of_match_table = mtk_tphy_id_table,
1663         },
1664 };
1665
1666 module_platform_driver(mtk_tphy_driver);
1667
1668 MODULE_AUTHOR("Chunfeng Yun <[email protected]>");
1669 MODULE_DESCRIPTION("MediaTek T-PHY driver");
1670 MODULE_LICENSE("GPL v2");