drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33
  34 #include <linux/vga_switcheroo.h>
  35 #include <linux/slab.h>
  36 #include <linux/pm_runtime.h>
  37 #include "amdgpu_amdkfd.h"
  38
  39 #if defined(CONFIG_VGA_SWITCHEROO)
  40 bool amdgpu_has_atpx(void);
  41 #else
  42 static inline bool amdgpu_has_atpx(void) { return false; }
  43 #endif
  44
  45 /**
  46  * amdgpu_driver_unload_kms - Main unload function for KMS.
  47  *
  48  * @dev: drm dev pointer
  49  *
  50  * This is the main unload function for KMS (all asics).
  51  * Returns 0 on success.
  52  */
  53 void amdgpu_driver_unload_kms(struct drm_device *dev)
  54 {
  55         struct amdgpu_device *adev = dev->dev_private;
  56
  57         if (adev == NULL)
  58                 return;
  59
  60         if (adev->rmmio == NULL)
  61                 goto done_free;
  62
  63         if (amdgpu_sriov_vf(adev))
  64                 amdgpu_virt_request_full_gpu(adev, false);
  65
  66         if (amdgpu_device_is_px(dev)) {
  67                 pm_runtime_get_sync(dev->dev);
  68                 pm_runtime_forbid(dev->dev);
  69         }
  70
  71         amdgpu_amdkfd_device_fini(adev);
  72
  73         amdgpu_acpi_fini(adev);
  74
  75         amdgpu_device_fini(adev);
  76
  77 done_free:
  78         kfree(adev);
  79         dev->dev_private = NULL;
  80 }
  81
  82 /**
  83  * amdgpu_driver_load_kms - Main load function for KMS.
  84  *
  85  * @dev: drm dev pointer
  86  * @flags: device flags
  87  *
  88  * This is the main load function for KMS (all asics).
  89  * Returns 0 on success, error on failure.
  90  */
  91 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
  92 {
  93         struct amdgpu_device *adev;
  94         int r, acpi_status;
  95
  96         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
  97         if (adev == NULL) {
  98                 return -ENOMEM;
  99         }
 100         dev->dev_private = (void *)adev;
 101
 102         if ((amdgpu_runtime_pm != 0) &&
 103             amdgpu_has_atpx() &&
 104             (amdgpu_is_atpx_hybrid() ||
 105              amdgpu_has_atpx_dgpu_power_cntl()) &&
 106             ((flags & AMD_IS_APU) == 0))
 107                 flags |= AMD_IS_PX;
 108
 109         /* amdgpu_device_init should report only fatal error
 110          * like memory allocation failure or iomapping failure,
 111          * or memory manager initialization failure, it must
 112          * properly initialize the GPU MC controller and permit
 113          * VRAM allocation
 114          */
 115         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 116         if (r) {
 117                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 118                 goto out;
 119         }
 120
 121         /* Call ACPI methods: require modeset init
 122          * but failure is not fatal
 123          */
 124         if (!r) {
 125                 acpi_status = amdgpu_acpi_init(adev);
 126                 if (acpi_status)
 127                 dev_dbg(&dev->pdev->dev,
 128                                 "Error during ACPI methods call\n");
 129         }
 130
 131         amdgpu_amdkfd_load_interface(adev);
 132         amdgpu_amdkfd_device_probe(adev);
 133         amdgpu_amdkfd_device_init(adev);
 134
 135         if (amdgpu_device_is_px(dev)) {
 136                 pm_runtime_use_autosuspend(dev->dev);
 137                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 138                 pm_runtime_set_active(dev->dev);
 139                 pm_runtime_allow(dev->dev);
 140                 pm_runtime_mark_last_busy(dev->dev);
 141                 pm_runtime_put_autosuspend(dev->dev);
 142         }
 143
 144         if (amdgpu_sriov_vf(adev))
 145                 amdgpu_virt_release_full_gpu(adev, true);
 146
 147 out:
 148         if (r) {
 149                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 150                 if (adev->rmmio && amdgpu_device_is_px(dev))
 151                         pm_runtime_put_noidle(dev->dev);
 152                 amdgpu_driver_unload_kms(dev);
 153         }
 154
 155         return r;
 156 }
 157
 158 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 159                                 struct drm_amdgpu_query_fw *query_fw,
 160                                 struct amdgpu_device *adev)
 161 {
 162         switch (query_fw->fw_type) {
 163         case AMDGPU_INFO_FW_VCE:
 164                 fw_info->ver = adev->vce.fw_version;
 165                 fw_info->feature = adev->vce.fb_version;
 166                 break;
 167         case AMDGPU_INFO_FW_UVD:
 168                 fw_info->ver = adev->uvd.fw_version;
 169                 fw_info->feature = 0;
 170                 break;
 171         case AMDGPU_INFO_FW_GMC:
 172                 fw_info->ver = adev->mc.fw_version;
 173                 fw_info->feature = 0;
 174                 break;
 175         case AMDGPU_INFO_FW_GFX_ME:
 176                 fw_info->ver = adev->gfx.me_fw_version;
 177                 fw_info->feature = adev->gfx.me_feature_version;
 178                 break;
 179         case AMDGPU_INFO_FW_GFX_PFP:
 180                 fw_info->ver = adev->gfx.pfp_fw_version;
 181                 fw_info->feature = adev->gfx.pfp_feature_version;
 182                 break;
 183         case AMDGPU_INFO_FW_GFX_CE:
 184                 fw_info->ver = adev->gfx.ce_fw_version;
 185                 fw_info->feature = adev->gfx.ce_feature_version;
 186                 break;
 187         case AMDGPU_INFO_FW_GFX_RLC:
 188                 fw_info->ver = adev->gfx.rlc_fw_version;
 189                 fw_info->feature = adev->gfx.rlc_feature_version;
 190                 break;
 191         case AMDGPU_INFO_FW_GFX_MEC:
 192                 if (query_fw->index == 0) {
 193                         fw_info->ver = adev->gfx.mec_fw_version;
 194                         fw_info->feature = adev->gfx.mec_feature_version;
 195                 } else if (query_fw->index == 1) {
 196                         fw_info->ver = adev->gfx.mec2_fw_version;
 197                         fw_info->feature = adev->gfx.mec2_feature_version;
 198                 } else
 199                         return -EINVAL;
 200                 break;
 201         case AMDGPU_INFO_FW_SMC:
 202                 fw_info->ver = adev->pm.fw_version;
 203                 fw_info->feature = 0;
 204                 break;
 205         case AMDGPU_INFO_FW_SDMA:
 206                 if (query_fw->index >= adev->sdma.num_instances)
 207                         return -EINVAL;
 208                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 209                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 210                 break;
 211         default:
 212                 return -EINVAL;
 213         }
 214         return 0;
 215 }
 216
 217 /*
 218  * Userspace get information ioctl
 219  */
 220 /**
 221  * amdgpu_info_ioctl - answer a device specific request.
 222  *
 223  * @adev: amdgpu device pointer
 224  * @data: request object
 225  * @filp: drm filp
 226  *
 227  * This function is used to pass device specific parameters to the userspace
 228  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 229  * etc. (all asics).
 230  * Returns 0 on success, -EINVAL on failure.
 231  */
 232 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 233 {
 234         struct amdgpu_device *adev = dev->dev_private;
 235         struct drm_amdgpu_info *info = data;
 236         struct amdgpu_mode_info *minfo = &adev->mode_info;
 237         void __user *out = (void __user *)(long)info->return_pointer;
 238         uint32_t size = info->return_size;
 239         struct drm_crtc *crtc;
 240         uint32_t ui32 = 0;
 241         uint64_t ui64 = 0;
 242         int i, found;
 243
 244         if (!info->return_size || !info->return_pointer)
 245                 return -EINVAL;
 246
 247         switch (info->query) {
 248         case AMDGPU_INFO_ACCEL_WORKING:
 249                 ui32 = adev->accel_working;
 250                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 251         case AMDGPU_INFO_CRTC_FROM_ID:
 252                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 253                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 254                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 255                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 256                                 ui32 = amdgpu_crtc->crtc_id;
 257                                 found = 1;
 258                                 break;
 259                         }
 260                 }
 261                 if (!found) {
 262                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 263                         return -EINVAL;
 264                 }
 265                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 266         case AMDGPU_INFO_HW_IP_INFO: {
 267                 struct drm_amdgpu_info_hw_ip ip = {};
 268                 enum amd_ip_block_type type;
 269                 uint32_t ring_mask = 0;
 270                 uint32_t ib_start_alignment = 0;
 271                 uint32_t ib_size_alignment = 0;
 272
 273                 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 274                         return -EINVAL;
 275
 276                 switch (info->query_hw_ip.type) {
 277                 case AMDGPU_HW_IP_GFX:
 278                         type = AMD_IP_BLOCK_TYPE_GFX;
 279                         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 280                                 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
 281                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 282                         ib_size_alignment = 8;
 283                         break;
 284                 case AMDGPU_HW_IP_COMPUTE:
 285                         type = AMD_IP_BLOCK_TYPE_GFX;
 286                         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 287                                 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
 288                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 289                         ib_size_alignment = 8;
 290                         break;
 291                 case AMDGPU_HW_IP_DMA:
 292                         type = AMD_IP_BLOCK_TYPE_SDMA;
 293                         for (i = 0; i < adev->sdma.num_instances; i++)
 294                                 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
 295                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 296                         ib_size_alignment = 1;
 297                         break;
 298                 case AMDGPU_HW_IP_UVD:
 299                         type = AMD_IP_BLOCK_TYPE_UVD;
 300                         ring_mask = adev->uvd.ring.ready ? 1 : 0;
 301                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 302                         ib_size_alignment = 16;
 303                         break;
 304                 case AMDGPU_HW_IP_VCE:
 305                         type = AMD_IP_BLOCK_TYPE_VCE;
 306                         for (i = 0; i < adev->vce.num_rings; i++)
 307                                 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
 308                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 309                         ib_size_alignment = 1;
 310                         break;
 311                 default:
 312                         return -EINVAL;
 313                 }
 314
 315                 for (i = 0; i < adev->num_ip_blocks; i++) {
 316                         if (adev->ip_blocks[i].version->type == type &&
 317                             adev->ip_blocks[i].status.valid) {
 318                                 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
 319                                 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 320                                 ip.capabilities_flags = 0;
 321                                 ip.available_rings = ring_mask;
 322                                 ip.ib_start_alignment = ib_start_alignment;
 323                                 ip.ib_size_alignment = ib_size_alignment;
 324                                 break;
 325                         }
 326                 }
 327                 return copy_to_user(out, &ip,
 328                                     min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
 329         }
 330         case AMDGPU_INFO_HW_IP_COUNT: {
 331                 enum amd_ip_block_type type;
 332                 uint32_t count = 0;
 333
 334                 switch (info->query_hw_ip.type) {
 335                 case AMDGPU_HW_IP_GFX:
 336                         type = AMD_IP_BLOCK_TYPE_GFX;
 337                         break;
 338                 case AMDGPU_HW_IP_COMPUTE:
 339                         type = AMD_IP_BLOCK_TYPE_GFX;
 340                         break;
 341                 case AMDGPU_HW_IP_DMA:
 342                         type = AMD_IP_BLOCK_TYPE_SDMA;
 343                         break;
 344                 case AMDGPU_HW_IP_UVD:
 345                         type = AMD_IP_BLOCK_TYPE_UVD;
 346                         break;
 347                 case AMDGPU_HW_IP_VCE:
 348                         type = AMD_IP_BLOCK_TYPE_VCE;
 349                         break;
 350                 default:
 351                         return -EINVAL;
 352                 }
 353
 354                 for (i = 0; i < adev->num_ip_blocks; i++)
 355                         if (adev->ip_blocks[i].version->type == type &&
 356                             adev->ip_blocks[i].status.valid &&
 357                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 358                                 count++;
 359
 360                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 361         }
 362         case AMDGPU_INFO_TIMESTAMP:
 363                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 364                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 365         case AMDGPU_INFO_FW_VERSION: {
 366                 struct drm_amdgpu_info_firmware fw_info;
 367                 int ret;
 368
 369                 /* We only support one instance of each IP block right now. */
 370                 if (info->query_fw.ip_instance != 0)
 371                         return -EINVAL;
 372
 373                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 374                 if (ret)
 375                         return ret;
 376
 377                 return copy_to_user(out, &fw_info,
 378                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 379         }
 380         case AMDGPU_INFO_NUM_BYTES_MOVED:
 381                 ui64 = atomic64_read(&adev->num_bytes_moved);
 382                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 383         case AMDGPU_INFO_NUM_EVICTIONS:
 384                 ui64 = atomic64_read(&adev->num_evictions);
 385                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 386         case AMDGPU_INFO_VRAM_USAGE:
 387                 ui64 = atomic64_read(&adev->vram_usage);
 388                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 389         case AMDGPU_INFO_VIS_VRAM_USAGE:
 390                 ui64 = atomic64_read(&adev->vram_vis_usage);
 391                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 392         case AMDGPU_INFO_GTT_USAGE:
 393                 ui64 = atomic64_read(&adev->gtt_usage);
 394                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 395         case AMDGPU_INFO_GDS_CONFIG: {
 396                 struct drm_amdgpu_info_gds gds_info;
 397
 398                 memset(&gds_info, 0, sizeof(gds_info));
 399                 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
 400                 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
 401                 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
 402                 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
 403                 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
 404                 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
 405                 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
 406                 return copy_to_user(out, &gds_info,
 407                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 408         }
 409         case AMDGPU_INFO_VRAM_GTT: {
 410                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 411
 412                 vram_gtt.vram_size = adev->mc.real_vram_size;
 413                 vram_gtt.vram_size -= adev->vram_pin_size;
 414                 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
 415                 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
 416                 vram_gtt.gtt_size  = adev->mc.gtt_size;
 417                 vram_gtt.gtt_size -= adev->gart_pin_size;
 418                 return copy_to_user(out, &vram_gtt,
 419                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 420         }
 421         case AMDGPU_INFO_MEMORY: {
 422                 struct drm_amdgpu_memory_info mem;
 423
 424                 memset(&mem, 0, sizeof(mem));
 425                 mem.vram.total_heap_size = adev->mc.real_vram_size;
 426                 mem.vram.usable_heap_size =
 427                         adev->mc.real_vram_size - adev->vram_pin_size;
 428                 mem.vram.heap_usage = atomic64_read(&adev->vram_usage);
 429                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 430
 431                 mem.cpu_accessible_vram.total_heap_size =
 432                         adev->mc.visible_vram_size;
 433                 mem.cpu_accessible_vram.usable_heap_size =
 434                         adev->mc.visible_vram_size -
 435                         (adev->vram_pin_size - adev->invisible_pin_size);
 436                 mem.cpu_accessible_vram.heap_usage =
 437                         atomic64_read(&adev->vram_vis_usage);
 438                 mem.cpu_accessible_vram.max_allocation =
 439                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 440
 441                 mem.gtt.total_heap_size = adev->mc.gtt_size;
 442                 mem.gtt.usable_heap_size =
 443                         adev->mc.gtt_size - adev->gart_pin_size;
 444                 mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage);
 445                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 446
 447                 return copy_to_user(out, &mem,
 448                                     min((size_t)size, sizeof(mem)))
 449                                     ? -EFAULT : 0;
 450         }
 451         case AMDGPU_INFO_READ_MMR_REG: {
 452                 unsigned n, alloc_size;
 453                 uint32_t *regs;
 454                 unsigned se_num = (info->read_mmr_reg.instance >>
 455                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 456                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 457                 unsigned sh_num = (info->read_mmr_reg.instance >>
 458                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 459                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 460
 461                 /* set full masks if the userspace set all bits
 462                  * in the bitfields */
 463                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 464                         se_num = 0xffffffff;
 465                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 466                         sh_num = 0xffffffff;
 467
 468                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 469                 if (!regs)
 470                         return -ENOMEM;
 471                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 472
 473                 for (i = 0; i < info->read_mmr_reg.count; i++)
 474                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 475                                                       info->read_mmr_reg.dword_offset + i,
 476                                                       &regs[i])) {
 477                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 478                                               info->read_mmr_reg.dword_offset + i);
 479                                 kfree(regs);
 480                                 return -EFAULT;
 481                         }
 482                 n = copy_to_user(out, regs, min(size, alloc_size));
 483                 kfree(regs);
 484                 return n ? -EFAULT : 0;
 485         }
 486         case AMDGPU_INFO_DEV_INFO: {
 487                 struct drm_amdgpu_info_device dev_info = {};
 488
 489                 dev_info.device_id = dev->pdev->device;
 490                 dev_info.chip_rev = adev->rev_id;
 491                 dev_info.external_rev = adev->external_rev_id;
 492                 dev_info.pci_rev = dev->pdev->revision;
 493                 dev_info.family = adev->family;
 494                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 495                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 496                 /* return all clocks in KHz */
 497                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 498                 if (adev->pm.dpm_enabled) {
 499                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 500                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 501                 } else {
 502                         dev_info.max_engine_clock = adev->pm.default_sclk * 10;
 503                         dev_info.max_memory_clock = adev->pm.default_mclk * 10;
 504                 }
 505                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 506                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 507                         adev->gfx.config.max_shader_engines;
 508                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 509                 dev_info._pad = 0;
 510                 dev_info.ids_flags = 0;
 511                 if (adev->flags & AMD_IS_APU)
 512                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 513                 if (amdgpu_sriov_vf(adev))
 514                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 515                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 516                 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 517                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 518                 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
 519                                              AMDGPU_GPU_PAGE_SIZE;
 520                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 521
 522                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 523                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 524                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 525                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 526                        sizeof(adev->gfx.cu_info.bitmap));
 527                 dev_info.vram_type = adev->mc.vram_type;
 528                 dev_info.vram_bit_width = adev->mc.vram_width;
 529                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 530
 531                 return copy_to_user(out, &dev_info,
 532                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 533         }
 534         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 535                 unsigned i;
 536                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 537                 struct amd_vce_state *vce_state;
 538
 539                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 540                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 541                         if (vce_state) {
 542                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 543                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 544                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 545                                 vce_clk_table.num_valid_entries++;
 546                         }
 547                 }
 548
 549                 return copy_to_user(out, &vce_clk_table,
 550                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 551         }
 552         case AMDGPU_INFO_VBIOS: {
 553                 uint32_t bios_size = adev->bios_size;
 554
 555                 switch (info->vbios_info.type) {
 556                 case AMDGPU_INFO_VBIOS_SIZE:
 557                         return copy_to_user(out, &bios_size,
 558                                         min((size_t)size, sizeof(bios_size)))
 559                                         ? -EFAULT : 0;
 560                 case AMDGPU_INFO_VBIOS_IMAGE: {
 561                         uint8_t *bios;
 562                         uint32_t bios_offset = info->vbios_info.offset;
 563
 564                         if (bios_offset >= bios_size)
 565                                 return -EINVAL;
 566
 567                         bios = adev->bios + bios_offset;
 568                         return copy_to_user(out, bios,
 569                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 570                                         ? -EFAULT : 0;
 571                 }
 572                 default:
 573                         DRM_DEBUG_KMS("Invalid request %d\n",
 574                                         info->vbios_info.type);
 575                         return -EINVAL;
 576                 }
 577         }
 578         case AMDGPU_INFO_NUM_HANDLES: {
 579                 struct drm_amdgpu_info_num_handles handle;
 580
 581                 switch (info->query_hw_ip.type) {
 582                 case AMDGPU_HW_IP_UVD:
 583                         /* Starting Polaris, we support unlimited UVD handles */
 584                         if (adev->asic_type < CHIP_POLARIS10) {
 585                                 handle.uvd_max_handles = adev->uvd.max_handles;
 586                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 587
 588                                 return copy_to_user(out, &handle,
 589                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 590                         } else {
 591                                 return -ENODATA;
 592                         }
 593
 594                         break;
 595                 default:
 596                         return -EINVAL;
 597                 }
 598         }
 599         default:
 600                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 601                 return -EINVAL;
 602         }
 603         return 0;
 604 }
 605
 606
 607 /*
 608  * Outdated mess for old drm with Xorg being in charge (void function now).
 609  */
 610 /**
 611  * amdgpu_driver_lastclose_kms - drm callback for last close
 612  *
 613  * @dev: drm dev pointer
 614  *
 615  * Switch vga_switcheroo state after last close (all asics).
 616  */
 617 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 618 {
 619         struct amdgpu_device *adev = dev->dev_private;
 620
 621         amdgpu_fbdev_restore_mode(adev);
 622         vga_switcheroo_process_delayed_switch();
 623 }
 624
 625 /**
 626  * amdgpu_driver_open_kms - drm callback for open
 627  *
 628  * @dev: drm dev pointer
 629  * @file_priv: drm file
 630  *
 631  * On device open, init vm on cayman+ (all asics).
 632  * Returns 0 on success, error on failure.
 633  */
 634 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 635 {
 636         struct amdgpu_device *adev = dev->dev_private;
 637         struct amdgpu_fpriv *fpriv;
 638         int r;
 639
 640         file_priv->driver_priv = NULL;
 641
 642         r = pm_runtime_get_sync(dev->dev);
 643         if (r < 0)
 644                 return r;
 645
 646         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 647         if (unlikely(!fpriv)) {
 648                 r = -ENOMEM;
 649                 goto out_suspend;
 650         }
 651
 652         r = amdgpu_vm_init(adev, &fpriv->vm);
 653         if (r) {
 654                 kfree(fpriv);
 655                 goto out_suspend;
 656         }
 657
 658         if (amdgpu_sriov_vf(adev)) {
 659                 r = amdgpu_map_static_csa(adev, &fpriv->vm);
 660                 if (r)
 661                         goto out_suspend;
 662         }
 663
 664         mutex_init(&fpriv->bo_list_lock);
 665         idr_init(&fpriv->bo_list_handles);
 666
 667         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
 668
 669         file_priv->driver_priv = fpriv;
 670
 671 out_suspend:
 672         pm_runtime_mark_last_busy(dev->dev);
 673         pm_runtime_put_autosuspend(dev->dev);
 674
 675         return r;
 676 }
 677
 678 /**
 679  * amdgpu_driver_postclose_kms - drm callback for post close
 680  *
 681  * @dev: drm dev pointer
 682  * @file_priv: drm file
 683  *
 684  * On device post close, tear down vm on cayman+ (all asics).
 685  */
 686 void amdgpu_driver_postclose_kms(struct drm_device *dev,
 687                                  struct drm_file *file_priv)
 688 {
 689         struct amdgpu_device *adev = dev->dev_private;
 690         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 691         struct amdgpu_bo_list *list;
 692         int handle;
 693
 694         if (!fpriv)
 695                 return;
 696
 697         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
 698
 699         amdgpu_uvd_free_handles(adev, file_priv);
 700         amdgpu_vce_free_handles(adev, file_priv);
 701
 702         if (amdgpu_sriov_vf(adev)) {
 703                 /* TODO: how to handle reserve failure */
 704                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, false));
 705                 amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va);
 706                 fpriv->vm.csa_bo_va = NULL;
 707                 amdgpu_bo_unreserve(adev->virt.csa_obj);
 708         }
 709
 710         amdgpu_vm_fini(adev, &fpriv->vm);
 711
 712         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
 713                 amdgpu_bo_list_free(list);
 714
 715         idr_destroy(&fpriv->bo_list_handles);
 716         mutex_destroy(&fpriv->bo_list_lock);
 717
 718         kfree(fpriv);
 719         file_priv->driver_priv = NULL;
 720
 721         pm_runtime_mark_last_busy(dev->dev);
 722         pm_runtime_put_autosuspend(dev->dev);
 723 }
 724
 725 /**
 726  * amdgpu_driver_preclose_kms - drm callback for pre close
 727  *
 728  * @dev: drm dev pointer
 729  * @file_priv: drm file
 730  *
 731  * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
 732  * (all asics).
 733  */
 734 void amdgpu_driver_preclose_kms(struct drm_device *dev,
 735                                 struct drm_file *file_priv)
 736 {
 737         pm_runtime_get_sync(dev->dev);
 738 }
 739
 740 /*
 741  * VBlank related functions.
 742  */
 743 /**
 744  * amdgpu_get_vblank_counter_kms - get frame count
 745  *
 746  * @dev: drm dev pointer
 747  * @pipe: crtc to get the frame count from
 748  *
 749  * Gets the frame count on the requested crtc (all asics).
 750  * Returns frame count on success, -EINVAL on failure.
 751  */
 752 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
 753 {
 754         struct amdgpu_device *adev = dev->dev_private;
 755         int vpos, hpos, stat;
 756         u32 count;
 757
 758         if (pipe >= adev->mode_info.num_crtc) {
 759                 DRM_ERROR("Invalid crtc %u\n", pipe);
 760                 return -EINVAL;
 761         }
 762
 763         /* The hw increments its frame counter at start of vsync, not at start
 764          * of vblank, as is required by DRM core vblank counter handling.
 765          * Cook the hw count here to make it appear to the caller as if it
 766          * incremented at start of vblank. We measure distance to start of
 767          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
 768          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
 769          * result by 1 to give the proper appearance to caller.
 770          */
 771         if (adev->mode_info.crtcs[pipe]) {
 772                 /* Repeat readout if needed to provide stable result if
 773                  * we cross start of vsync during the queries.
 774                  */
 775                 do {
 776                         count = amdgpu_display_vblank_get_counter(adev, pipe);
 777                         /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
 778                          * distance to start of vblank, instead of regular
 779                          * vertical scanout pos.
 780                          */
 781                         stat = amdgpu_get_crtc_scanoutpos(
 782                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
 783                                 &vpos, &hpos, NULL, NULL,
 784                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
 785                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
 786
 787                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
 788                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
 789                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
 790                 } else {
 791                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
 792                                       pipe, vpos);
 793
 794                         /* Bump counter if we are at >= leading edge of vblank,
 795                          * but before vsync where vpos would turn negative and
 796                          * the hw counter really increments.
 797                          */
 798                         if (vpos >= 0)
 799                                 count++;
 800                 }
 801         } else {
 802                 /* Fallback to use value as is. */
 803                 count = amdgpu_display_vblank_get_counter(adev, pipe);
 804                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
 805         }
 806
 807         return count;
 808 }
 809
 810 /**
 811  * amdgpu_enable_vblank_kms - enable vblank interrupt
 812  *
 813  * @dev: drm dev pointer
 814  * @pipe: crtc to enable vblank interrupt for
 815  *
 816  * Enable the interrupt on the requested crtc (all asics).
 817  * Returns 0 on success, -EINVAL on failure.
 818  */
 819 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
 820 {
 821         struct amdgpu_device *adev = dev->dev_private;
 822         int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
 823
 824         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
 825 }
 826
 827 /**
 828  * amdgpu_disable_vblank_kms - disable vblank interrupt
 829  *
 830  * @dev: drm dev pointer
 831  * @pipe: crtc to disable vblank interrupt for
 832  *
 833  * Disable the interrupt on the requested crtc (all asics).
 834  */
 835 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
 836 {
 837         struct amdgpu_device *adev = dev->dev_private;
 838         int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
 839
 840         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
 841 }
 842
 843 /**
 844  * amdgpu_get_vblank_timestamp_kms - get vblank timestamp
 845  *
 846  * @dev: drm dev pointer
 847  * @crtc: crtc to get the timestamp for
 848  * @max_error: max error
 849  * @vblank_time: time value
 850  * @flags: flags passed to the driver
 851  *
 852  * Gets the timestamp on the requested crtc based on the
 853  * scanout position.  (all asics).
 854  * Returns postive status flags on success, negative error on failure.
 855  */
 856 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
 857                                     int *max_error,
 858                                     struct timeval *vblank_time,
 859                                     unsigned flags)
 860 {
 861         struct drm_crtc *crtc;
 862         struct amdgpu_device *adev = dev->dev_private;
 863
 864         if (pipe >= dev->num_crtcs) {
 865                 DRM_ERROR("Invalid crtc %u\n", pipe);
 866                 return -EINVAL;
 867         }
 868
 869         /* Get associated drm_crtc: */
 870         crtc = &adev->mode_info.crtcs[pipe]->base;
 871         if (!crtc) {
 872                 /* This can occur on driver load if some component fails to
 873                  * initialize completely and driver is unloaded */
 874                 DRM_ERROR("Uninitialized crtc %d\n", pipe);
 875                 return -EINVAL;
 876         }
 877
 878         /* Helper routine in DRM core does all the work: */
 879         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 880                                                      vblank_time, flags,
 881                                                      &crtc->hwmode);
 882 }
 883
 884 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
 885         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 886         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 887         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 888         /* KMS */
 889         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 890         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 891         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 892         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 893         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 894         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 895         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 896         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 897         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 898         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 899 };
 900 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
 901
 902 /*
 903  * Debugfs info
 904  */
 905 #if defined(CONFIG_DEBUG_FS)
 906
 907 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
 908 {
 909         struct drm_info_node *node = (struct drm_info_node *) m->private;
 910         struct drm_device *dev = node->minor->dev;
 911         struct amdgpu_device *adev = dev->dev_private;
 912         struct drm_amdgpu_info_firmware fw_info;
 913         struct drm_amdgpu_query_fw query_fw;
 914         int ret, i;
 915
 916         /* VCE */
 917         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
 918         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
 919         if (ret)
 920                 return ret;
 921         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
 922                    fw_info.feature, fw_info.ver);
 923
 924         /* UVD */
 925         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
 926         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
 927         if (ret)
 928                 return ret;
 929         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
 930                    fw_info.feature, fw_info.ver);
 931
 932         /* GMC */
 933         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
 934         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
 935         if (ret)
 936                 return ret;
 937         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
 938                    fw_info.feature, fw_info.ver);
 939
 940         /* ME */
 941         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
 942         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
 943         if (ret)
 944                 return ret;
 945         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
 946                    fw_info.feature, fw_info.ver);
 947
 948         /* PFP */
 949         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
 950         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
 951         if (ret)
 952                 return ret;
 953         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
 954                    fw_info.feature, fw_info.ver);
 955
 956         /* CE */
 957         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
 958         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
 959         if (ret)
 960                 return ret;
 961         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
 962                    fw_info.feature, fw_info.ver);
 963
 964         /* RLC */
 965         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
 966         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
 967         if (ret)
 968                 return ret;
 969         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
 970                    fw_info.feature, fw_info.ver);
 971
 972         /* MEC */
 973         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
 974         query_fw.index = 0;
 975         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
 976         if (ret)
 977                 return ret;
 978         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
 979                    fw_info.feature, fw_info.ver);
 980
 981         /* MEC2 */
 982         if (adev->asic_type == CHIP_KAVERI ||
 983             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
 984                 query_fw.index = 1;
 985                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
 986                 if (ret)
 987                         return ret;
 988                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
 989                            fw_info.feature, fw_info.ver);
 990         }
 991
 992         /* SMC */
 993         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
 994         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
 995         if (ret)
 996                 return ret;
 997         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
 998                    fw_info.feature, fw_info.ver);
 999
1000         /* SDMA */
1001         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1002         for (i = 0; i < adev->sdma.num_instances; i++) {
1003                 query_fw.index = i;
1004                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1005                 if (ret)
1006                         return ret;
1007                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1008                            i, fw_info.feature, fw_info.ver);
1009         }
1010
1011         return 0;
1012 }
1013
1014 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1015         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1016 };
1017 #endif
1018
1019 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1020 {
1021 #if defined(CONFIG_DEBUG_FS)
1022         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1023                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1024 #else
1025         return 0;
1026 #endif
1027 }