sound/soc/sof/intel/byt.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2 //
   3 // This file is provided under a dual BSD/GPLv2 license.  When using or
   4 // redistributing this file, you may do so under either license.
   5 //
   6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
   7 //
   8 // Author: Liam Girdwood <[email protected]>
   9 //
  10
  11 /*
  12  * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <sound/sof.h>
  17 #include <sound/sof/xtensa.h>
  18 #include <sound/soc-acpi.h>
  19 #include <sound/soc-acpi-intel-match.h>
  20 #include <sound/intel-dsp-config.h>
  21 #include "../ops.h"
  22 #include "atom.h"
  23 #include "shim.h"
  24 #include "../sof-acpi-dev.h"
  25 #include "../sof-audio.h"
  26 #include "../../intel/common/soc-intel-quirks.h"
  27
  28 static const struct snd_sof_debugfs_map byt_debugfs[] = {
  29         {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
  30          SOF_DEBUGFS_ACCESS_ALWAYS},
  31         {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
  32          SOF_DEBUGFS_ACCESS_ALWAYS},
  33         {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
  34          SOF_DEBUGFS_ACCESS_ALWAYS},
  35         {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
  36          SOF_DEBUGFS_ACCESS_ALWAYS},
  37         {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
  38          SOF_DEBUGFS_ACCESS_ALWAYS},
  39         {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
  40          SOF_DEBUGFS_ACCESS_D0_ONLY},
  41         {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
  42          SOF_DEBUGFS_ACCESS_D0_ONLY},
  43         {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
  44          SOF_DEBUGFS_ACCESS_ALWAYS},
  45 };
  46
  47 static const struct snd_sof_debugfs_map cht_debugfs[] = {
  48         {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
  49          SOF_DEBUGFS_ACCESS_ALWAYS},
  50         {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
  51          SOF_DEBUGFS_ACCESS_ALWAYS},
  52         {"dmac2", DSP_BAR, DMAC2_OFFSET, DMAC_SIZE,
  53          SOF_DEBUGFS_ACCESS_ALWAYS},
  54         {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
  55          SOF_DEBUGFS_ACCESS_ALWAYS},
  56         {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
  57          SOF_DEBUGFS_ACCESS_ALWAYS},
  58         {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
  59          SOF_DEBUGFS_ACCESS_ALWAYS},
  60         {"ssp3", DSP_BAR, SSP3_OFFSET, SSP_SIZE,
  61          SOF_DEBUGFS_ACCESS_ALWAYS},
  62         {"ssp4", DSP_BAR, SSP4_OFFSET, SSP_SIZE,
  63          SOF_DEBUGFS_ACCESS_ALWAYS},
  64         {"ssp5", DSP_BAR, SSP5_OFFSET, SSP_SIZE,
  65          SOF_DEBUGFS_ACCESS_ALWAYS},
  66         {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
  67          SOF_DEBUGFS_ACCESS_D0_ONLY},
  68         {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
  69          SOF_DEBUGFS_ACCESS_D0_ONLY},
  70         {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT,
  71          SOF_DEBUGFS_ACCESS_ALWAYS},
  72 };
  73
  74 static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev)
  75 {
  76         /* Disable Interrupt from both sides */
  77         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 0x3, 0x3);
  78         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRD, 0x3, 0x3);
  79
  80         /* Put DSP into reset, set reset vector */
  81         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
  82                                   SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL,
  83                                   SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL);
  84 }
  85
  86 static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state)
  87 {
  88         byt_reset_dsp_disable_int(sdev);
  89
  90         return 0;
  91 }
  92
  93 static int byt_resume(struct snd_sof_dev *sdev)
  94 {
  95         /* enable BUSY and disable DONE Interrupt by default */
  96         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
  97                                   SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
  98                                   SHIM_IMRX_DONE);
  99
 100         return 0;
 101 }
 102
 103 static int byt_remove(struct snd_sof_dev *sdev)
 104 {
 105         byt_reset_dsp_disable_int(sdev);
 106
 107         return 0;
 108 }
 109
 110 static int byt_acpi_probe(struct snd_sof_dev *sdev)
 111 {
 112         struct snd_sof_pdata *pdata = sdev->pdata;
 113         const struct sof_dev_desc *desc = pdata->desc;
 114         struct platform_device *pdev =
 115                 container_of(sdev->dev, struct platform_device, dev);
 116         const struct sof_intel_dsp_desc *chip;
 117         struct resource *mmio;
 118         u32 base, size;
 119         int ret;
 120
 121         chip = get_chip_info(sdev->pdata);
 122         if (!chip) {
 123                 dev_err(sdev->dev, "error: no such device supported\n");
 124                 return -EIO;
 125         }
 126
 127         sdev->num_cores = chip->cores_num;
 128
 129         /* DSP DMA can only access low 31 bits of host memory */
 130         ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
 131         if (ret < 0) {
 132                 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
 133                 return ret;
 134         }
 135
 136         /* LPE base */
 137         mmio = platform_get_resource(pdev, IORESOURCE_MEM,
 138                                      desc->resindex_lpe_base);
 139         if (mmio) {
 140                 base = mmio->start;
 141                 size = resource_size(mmio);
 142         } else {
 143                 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
 144                         desc->resindex_lpe_base);
 145                 return -EINVAL;
 146         }
 147
 148         dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
 149         sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size);
 150         if (!sdev->bar[DSP_BAR]) {
 151                 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
 152                         base, size);
 153                 return -ENODEV;
 154         }
 155         dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]);
 156
 157         /* TODO: add offsets */
 158         sdev->mmio_bar = DSP_BAR;
 159         sdev->mailbox_bar = DSP_BAR;
 160
 161         /* IMR base - optional */
 162         if (desc->resindex_imr_base == -1)
 163                 goto irq;
 164
 165         mmio = platform_get_resource(pdev, IORESOURCE_MEM,
 166                                      desc->resindex_imr_base);
 167         if (mmio) {
 168                 base = mmio->start;
 169                 size = resource_size(mmio);
 170         } else {
 171                 dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n",
 172                         desc->resindex_imr_base);
 173                 return -ENODEV;
 174         }
 175
 176         /* some BIOSes don't map IMR */
 177         if (base == 0x55aa55aa || base == 0x0) {
 178                 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
 179                 goto irq;
 180         }
 181
 182         dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
 183         sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size);
 184         if (!sdev->bar[IMR_BAR]) {
 185                 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
 186                         base, size);
 187                 return -ENODEV;
 188         }
 189         dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]);
 190
 191 irq:
 192         /* register our IRQ */
 193         sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
 194         if (sdev->ipc_irq < 0)
 195                 return sdev->ipc_irq;
 196
 197         dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
 198         ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
 199                                         atom_irq_handler, atom_irq_thread,
 200                                         IRQF_SHARED, "AudioDSP", sdev);
 201         if (ret < 0) {
 202                 dev_err(sdev->dev, "error: failed to register IRQ %d\n",
 203                         sdev->ipc_irq);
 204                 return ret;
 205         }
 206
 207         /* enable BUSY and disable DONE Interrupt by default */
 208         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
 209                                   SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
 210                                   SHIM_IMRX_DONE);
 211
 212         /* set default mailbox offset for FW ready message */
 213         sdev->dsp_box.offset = MBOX_OFFSET;
 214
 215         return ret;
 216 }
 217
 218 /* baytrail ops */
 219 static struct snd_sof_dsp_ops sof_byt_ops = {
 220         /* device init */
 221         .probe          = byt_acpi_probe,
 222         .remove         = byt_remove,
 223
 224         /* DSP core boot / reset */
 225         .run            = atom_run,
 226         .reset          = atom_reset,
 227
 228         /* Register IO uses direct mmio */
 229
 230         /* Block IO */
 231         .block_read     = sof_block_read,
 232         .block_write    = sof_block_write,
 233
 234         /* Mailbox IO */
 235         .mailbox_read   = sof_mailbox_read,
 236         .mailbox_write  = sof_mailbox_write,
 237
 238         /* doorbell */
 239         .irq_handler    = atom_irq_handler,
 240         .irq_thread     = atom_irq_thread,
 241
 242         /* ipc */
 243         .send_msg       = atom_send_msg,
 244         .get_mailbox_offset = atom_get_mailbox_offset,
 245         .get_window_offset = atom_get_window_offset,
 246
 247         .ipc_msg_data   = sof_ipc_msg_data,
 248         .set_stream_data_offset = sof_set_stream_data_offset,
 249
 250         /* machine driver */
 251         .machine_select = atom_machine_select,
 252         .machine_register = sof_machine_register,
 253         .machine_unregister = sof_machine_unregister,
 254         .set_mach_params = atom_set_mach_params,
 255
 256         /* debug */
 257         .debug_map      = byt_debugfs,
 258         .debug_map_count        = ARRAY_SIZE(byt_debugfs),
 259         .dbg_dump       = atom_dump,
 260         .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
 261
 262         /* stream callbacks */
 263         .pcm_open       = sof_stream_pcm_open,
 264         .pcm_close      = sof_stream_pcm_close,
 265
 266         /*Firmware loading */
 267         .load_firmware  = snd_sof_load_firmware_memcpy,
 268
 269         /* PM */
 270         .suspend = byt_suspend,
 271         .resume = byt_resume,
 272
 273         /* DAI drivers */
 274         .drv = atom_dai,
 275         .num_drv = 3, /* we have only 3 SSPs on byt*/
 276
 277         /* ALSA HW info flags */
 278         .hw_info =      SNDRV_PCM_INFO_MMAP |
 279                         SNDRV_PCM_INFO_MMAP_VALID |
 280                         SNDRV_PCM_INFO_INTERLEAVED |
 281                         SNDRV_PCM_INFO_PAUSE |
 282                         SNDRV_PCM_INFO_BATCH,
 283
 284         .dsp_arch_ops = &sof_xtensa_arch_ops,
 285 };
 286
 287 static const struct sof_intel_dsp_desc byt_chip_info = {
 288         .cores_num = 1,
 289         .host_managed_cores_mask = 1,
 290         .hw_ip_version = SOF_INTEL_BAYTRAIL,
 291 };
 292
 293 /* cherrytrail and braswell ops */
 294 static struct snd_sof_dsp_ops sof_cht_ops = {
 295         /* device init */
 296         .probe          = byt_acpi_probe,
 297         .remove         = byt_remove,
 298
 299         /* DSP core boot / reset */
 300         .run            = atom_run,
 301         .reset          = atom_reset,
 302
 303         /* Register IO uses direct mmio */
 304
 305         /* Block IO */
 306         .block_read     = sof_block_read,
 307         .block_write    = sof_block_write,
 308
 309         /* Mailbox IO */
 310         .mailbox_read   = sof_mailbox_read,
 311         .mailbox_write  = sof_mailbox_write,
 312
 313         /* doorbell */
 314         .irq_handler    = atom_irq_handler,
 315         .irq_thread     = atom_irq_thread,
 316
 317         /* ipc */
 318         .send_msg       = atom_send_msg,
 319         .get_mailbox_offset = atom_get_mailbox_offset,
 320         .get_window_offset = atom_get_window_offset,
 321
 322         .ipc_msg_data   = sof_ipc_msg_data,
 323         .set_stream_data_offset = sof_set_stream_data_offset,
 324
 325         /* machine driver */
 326         .machine_select = atom_machine_select,
 327         .machine_register = sof_machine_register,
 328         .machine_unregister = sof_machine_unregister,
 329         .set_mach_params = atom_set_mach_params,
 330
 331         /* debug */
 332         .debug_map      = cht_debugfs,
 333         .debug_map_count        = ARRAY_SIZE(cht_debugfs),
 334         .dbg_dump       = atom_dump,
 335         .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
 336
 337         /* stream callbacks */
 338         .pcm_open       = sof_stream_pcm_open,
 339         .pcm_close      = sof_stream_pcm_close,
 340
 341         /*Firmware loading */
 342         .load_firmware  = snd_sof_load_firmware_memcpy,
 343
 344         /* PM */
 345         .suspend = byt_suspend,
 346         .resume = byt_resume,
 347
 348         /* DAI drivers */
 349         .drv = atom_dai,
 350         /* all 6 SSPs may be available for cherrytrail */
 351         .num_drv = 6,
 352
 353         /* ALSA HW info flags */
 354         .hw_info =      SNDRV_PCM_INFO_MMAP |
 355                         SNDRV_PCM_INFO_MMAP_VALID |
 356                         SNDRV_PCM_INFO_INTERLEAVED |
 357                         SNDRV_PCM_INFO_PAUSE |
 358                         SNDRV_PCM_INFO_BATCH,
 359
 360         .dsp_arch_ops = &sof_xtensa_arch_ops,
 361 };
 362
 363 static const struct sof_intel_dsp_desc cht_chip_info = {
 364         .cores_num = 1,
 365         .host_managed_cores_mask = 1,
 366         .hw_ip_version = SOF_INTEL_BAYTRAIL,
 367 };
 368
 369 /* BYTCR uses different IRQ index */
 370 static const struct sof_dev_desc sof_acpi_baytrailcr_desc = {
 371         .machines = snd_soc_acpi_intel_baytrail_machines,
 372         .resindex_lpe_base = 0,
 373         .resindex_pcicfg_base = 1,
 374         .resindex_imr_base = 2,
 375         .irqindex_host_ipc = 0,
 376         .chip_info = &byt_chip_info,
 377         .ipc_supported_mask = BIT(SOF_IPC),
 378         .ipc_default = SOF_IPC,
 379         .default_fw_path = {
 380                 [SOF_IPC] = "intel/sof",
 381         },
 382         .default_tplg_path = {
 383                 [SOF_IPC] = "intel/sof-tplg",
 384         },
 385         .default_fw_filename = {
 386                 [SOF_IPC] = "sof-byt.ri",
 387         },
 388         .nocodec_tplg_filename = "sof-byt-nocodec.tplg",
 389         .ops = &sof_byt_ops,
 390 };
 391
 392 static const struct sof_dev_desc sof_acpi_baytrail_desc = {
 393         .machines = snd_soc_acpi_intel_baytrail_machines,
 394         .resindex_lpe_base = 0,
 395         .resindex_pcicfg_base = 1,
 396         .resindex_imr_base = 2,
 397         .irqindex_host_ipc = 5,
 398         .chip_info = &byt_chip_info,
 399         .ipc_supported_mask = BIT(SOF_IPC),
 400         .ipc_default = SOF_IPC,
 401         .default_fw_path = {
 402                 [SOF_IPC] = "intel/sof",
 403         },
 404         .default_tplg_path = {
 405                 [SOF_IPC] = "intel/sof-tplg",
 406         },
 407         .default_fw_filename = {
 408                 [SOF_IPC] = "sof-byt.ri",
 409         },
 410         .nocodec_tplg_filename = "sof-byt-nocodec.tplg",
 411         .ops = &sof_byt_ops,
 412 };
 413
 414 static const struct sof_dev_desc sof_acpi_cherrytrail_desc = {
 415         .machines = snd_soc_acpi_intel_cherrytrail_machines,
 416         .resindex_lpe_base = 0,
 417         .resindex_pcicfg_base = 1,
 418         .resindex_imr_base = 2,
 419         .irqindex_host_ipc = 5,
 420         .chip_info = &cht_chip_info,
 421         .ipc_supported_mask = BIT(SOF_IPC),
 422         .ipc_default = SOF_IPC,
 423         .default_fw_path = {
 424                 [SOF_IPC] = "intel/sof",
 425         },
 426         .default_tplg_path = {
 427                 [SOF_IPC] = "intel/sof-tplg",
 428         },
 429         .default_fw_filename = {
 430                 [SOF_IPC] = "sof-cht.ri",
 431         },
 432         .nocodec_tplg_filename = "sof-cht-nocodec.tplg",
 433         .ops = &sof_cht_ops,
 434 };
 435
 436 static const struct acpi_device_id sof_baytrail_match[] = {
 437         { "80860F28", (unsigned long)&sof_acpi_baytrail_desc },
 438         { "808622A8", (unsigned long)&sof_acpi_cherrytrail_desc },
 439         { }
 440 };
 441 MODULE_DEVICE_TABLE(acpi, sof_baytrail_match);
 442
 443 static int sof_baytrail_probe(struct platform_device *pdev)
 444 {
 445         struct device *dev = &pdev->dev;
 446         const struct sof_dev_desc *desc;
 447         const struct acpi_device_id *id;
 448         int ret;
 449
 450         id = acpi_match_device(dev->driver->acpi_match_table, dev);
 451         if (!id)
 452                 return -ENODEV;
 453
 454         ret = snd_intel_acpi_dsp_driver_probe(dev, id->id);
 455         if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) {
 456                 dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n");
 457                 return -ENODEV;
 458         }
 459
 460         desc = (const struct sof_dev_desc *)id->driver_data;
 461         if (desc == &sof_acpi_baytrail_desc && soc_intel_is_byt_cr(pdev))
 462                 desc = &sof_acpi_baytrailcr_desc;
 463
 464         return sof_acpi_probe(pdev, desc);
 465 }
 466
 467 /* acpi_driver definition */
 468 static struct platform_driver snd_sof_acpi_intel_byt_driver = {
 469         .probe = sof_baytrail_probe,
 470         .remove = sof_acpi_remove,
 471         .driver = {
 472                 .name = "sof-audio-acpi-intel-byt",
 473                 .pm = &sof_acpi_pm,
 474                 .acpi_match_table = sof_baytrail_match,
 475         },
 476 };
 477 module_platform_driver(snd_sof_acpi_intel_byt_driver);
 478
 479 MODULE_LICENSE("Dual BSD/GPL");
 480 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_HIFI_EP_IPC);
 481 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
 482 MODULE_IMPORT_NS(SND_SOC_SOF_ACPI_DEV);
 483 MODULE_IMPORT_NS(SND_SOC_SOF_INTEL_ATOM_HIFI_EP);