sound/soc/sof/intel/byt.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2 //
   3 // This file is provided under a dual BSD/GPLv2 license.  When using or
   4 // redistributing this file, you may do so under either license.
   5 //
   6 // Copyright(c) 2018 Intel Corporation
   7 //
   8 // Author: Liam Girdwood <[email protected]>
   9 //
  10
  11 /*
  12  * Hardware interface for audio DSP on Baytrail, Braswell and Cherrytrail.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <sound/sof.h>
  17 #include <sound/sof/xtensa.h>
  18 #include <sound/soc-acpi.h>
  19 #include <sound/soc-acpi-intel-match.h>
  20 #include <sound/intel-dsp-config.h>
  21 #include "../ops.h"
  22 #include "atom.h"
  23 #include "shim.h"
  24 #include "../sof-acpi-dev.h"
  25 #include "../sof-audio.h"
  26 #include "../../intel/common/soc-intel-quirks.h"
  27
  28 static const struct snd_sof_debugfs_map byt_debugfs[] = {
  29         {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
  30          SOF_DEBUGFS_ACCESS_ALWAYS},
  31         {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
  32          SOF_DEBUGFS_ACCESS_ALWAYS},
  33         {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
  34          SOF_DEBUGFS_ACCESS_ALWAYS},
  35         {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
  36          SOF_DEBUGFS_ACCESS_ALWAYS},
  37         {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
  38          SOF_DEBUGFS_ACCESS_ALWAYS},
  39         {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
  40          SOF_DEBUGFS_ACCESS_D0_ONLY},
  41         {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
  42          SOF_DEBUGFS_ACCESS_D0_ONLY},
  43         {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_BYT,
  44          SOF_DEBUGFS_ACCESS_ALWAYS},
  45 };
  46
  47 static const struct snd_sof_debugfs_map cht_debugfs[] = {
  48         {"dmac0", DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
  49          SOF_DEBUGFS_ACCESS_ALWAYS},
  50         {"dmac1", DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
  51          SOF_DEBUGFS_ACCESS_ALWAYS},
  52         {"dmac2", DSP_BAR, DMAC2_OFFSET, DMAC_SIZE,
  53          SOF_DEBUGFS_ACCESS_ALWAYS},
  54         {"ssp0", DSP_BAR, SSP0_OFFSET, SSP_SIZE,
  55          SOF_DEBUGFS_ACCESS_ALWAYS},
  56         {"ssp1", DSP_BAR, SSP1_OFFSET, SSP_SIZE,
  57          SOF_DEBUGFS_ACCESS_ALWAYS},
  58         {"ssp2", DSP_BAR, SSP2_OFFSET, SSP_SIZE,
  59          SOF_DEBUGFS_ACCESS_ALWAYS},
  60         {"ssp3", DSP_BAR, SSP3_OFFSET, SSP_SIZE,
  61          SOF_DEBUGFS_ACCESS_ALWAYS},
  62         {"ssp4", DSP_BAR, SSP4_OFFSET, SSP_SIZE,
  63          SOF_DEBUGFS_ACCESS_ALWAYS},
  64         {"ssp5", DSP_BAR, SSP5_OFFSET, SSP_SIZE,
  65          SOF_DEBUGFS_ACCESS_ALWAYS},
  66         {"iram", DSP_BAR, IRAM_OFFSET, IRAM_SIZE,
  67          SOF_DEBUGFS_ACCESS_D0_ONLY},
  68         {"dram", DSP_BAR, DRAM_OFFSET, DRAM_SIZE,
  69          SOF_DEBUGFS_ACCESS_D0_ONLY},
  70         {"shim", DSP_BAR, SHIM_OFFSET, SHIM_SIZE_CHT,
  71          SOF_DEBUGFS_ACCESS_ALWAYS},
  72 };
  73
  74 static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev)
  75 {
  76         /* Disable Interrupt from both sides */
  77         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX, 0x3, 0x3);
  78         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRD, 0x3, 0x3);
  79
  80         /* Put DSP into reset, set reset vector */
  81         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_CSR,
  82                                   SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL,
  83                                   SHIM_BYT_CSR_RST | SHIM_BYT_CSR_VECTOR_SEL);
  84 }
  85
  86 static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state)
  87 {
  88         byt_reset_dsp_disable_int(sdev);
  89
  90         return 0;
  91 }
  92
  93 static int byt_resume(struct snd_sof_dev *sdev)
  94 {
  95         /* enable BUSY and disable DONE Interrupt by default */
  96         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
  97                                   SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
  98                                   SHIM_IMRX_DONE);
  99
 100         return 0;
 101 }
 102
 103 static void byt_remove(struct snd_sof_dev *sdev)
 104 {
 105         byt_reset_dsp_disable_int(sdev);
 106 }
 107
 108 static int byt_acpi_probe(struct snd_sof_dev *sdev)
 109 {
 110         struct snd_sof_pdata *pdata = sdev->pdata;
 111         const struct sof_dev_desc *desc = pdata->desc;
 112         struct platform_device *pdev = to_platform_device(sdev->dev);
 113         const struct sof_intel_dsp_desc *chip;
 114         struct resource *mmio;
 115         u32 base, size;
 116         int ret;
 117
 118         chip = get_chip_info(sdev->pdata);
 119         if (!chip) {
 120                 dev_err(sdev->dev, "error: no such device supported\n");
 121                 return -EIO;
 122         }
 123
 124         sdev->num_cores = chip->cores_num;
 125
 126         /* DSP DMA can only access low 31 bits of host memory */
 127         ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
 128         if (ret < 0) {
 129                 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
 130                 return ret;
 131         }
 132
 133         /* LPE base */
 134         mmio = platform_get_resource(pdev, IORESOURCE_MEM,
 135                                      desc->resindex_lpe_base);
 136         if (mmio) {
 137                 base = mmio->start;
 138                 size = resource_size(mmio);
 139         } else {
 140                 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
 141                         desc->resindex_lpe_base);
 142                 return -EINVAL;
 143         }
 144
 145         dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
 146         sdev->bar[DSP_BAR] = devm_ioremap(sdev->dev, base, size);
 147         if (!sdev->bar[DSP_BAR]) {
 148                 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
 149                         base, size);
 150                 return -ENODEV;
 151         }
 152         dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[DSP_BAR]);
 153
 154         /* TODO: add offsets */
 155         sdev->mmio_bar = DSP_BAR;
 156         sdev->mailbox_bar = DSP_BAR;
 157
 158         /* IMR base - optional */
 159         if (desc->resindex_imr_base == -1)
 160                 goto irq;
 161
 162         mmio = platform_get_resource(pdev, IORESOURCE_MEM,
 163                                      desc->resindex_imr_base);
 164         if (mmio) {
 165                 base = mmio->start;
 166                 size = resource_size(mmio);
 167         } else {
 168                 dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n",
 169                         desc->resindex_imr_base);
 170                 return -ENODEV;
 171         }
 172
 173         /* some BIOSes don't map IMR */
 174         if (base == 0x55aa55aa || base == 0x0) {
 175                 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
 176                 goto irq;
 177         }
 178
 179         dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
 180         sdev->bar[IMR_BAR] = devm_ioremap(sdev->dev, base, size);
 181         if (!sdev->bar[IMR_BAR]) {
 182                 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
 183                         base, size);
 184                 return -ENODEV;
 185         }
 186         dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[IMR_BAR]);
 187
 188 irq:
 189         /* register our IRQ */
 190         sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
 191         if (sdev->ipc_irq < 0)
 192                 return sdev->ipc_irq;
 193
 194         dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
 195         ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
 196                                         atom_irq_handler, atom_irq_thread,
 197                                         IRQF_SHARED, "AudioDSP", sdev);
 198         if (ret < 0) {
 199                 dev_err(sdev->dev, "error: failed to register IRQ %d\n",
 200                         sdev->ipc_irq);
 201                 return ret;
 202         }
 203
 204         /* enable BUSY and disable DONE Interrupt by default */
 205         snd_sof_dsp_update_bits64(sdev, DSP_BAR, SHIM_IMRX,
 206                                   SHIM_IMRX_BUSY | SHIM_IMRX_DONE,
 207                                   SHIM_IMRX_DONE);
 208
 209         /* set default mailbox offset for FW ready message */
 210         sdev->dsp_box.offset = MBOX_OFFSET;
 211
 212         return ret;
 213 }
 214
 215 /* baytrail ops */
 216 static const struct snd_sof_dsp_ops sof_byt_ops = {
 217         /* device init */
 218         .probe          = byt_acpi_probe,
 219         .remove         = byt_remove,
 220
 221         /* DSP core boot / reset */
 222         .run            = atom_run,
 223         .reset          = atom_reset,
 224
 225         /* Register IO uses direct mmio */
 226
 227         /* Block IO */
 228         .block_read     = sof_block_read,
 229         .block_write    = sof_block_write,
 230
 231         /* Mailbox IO */
 232         .mailbox_read   = sof_mailbox_read,
 233         .mailbox_write  = sof_mailbox_write,
 234
 235         /* doorbell */
 236         .irq_handler    = atom_irq_handler,
 237         .irq_thread     = atom_irq_thread,
 238
 239         /* ipc */
 240         .send_msg       = atom_send_msg,
 241         .get_mailbox_offset = atom_get_mailbox_offset,
 242         .get_window_offset = atom_get_window_offset,
 243
 244         .ipc_msg_data   = sof_ipc_msg_data,
 245         .set_stream_data_offset = sof_set_stream_data_offset,
 246
 247         /* machine driver */
 248         .machine_select = atom_machine_select,
 249         .machine_register = sof_machine_register,
 250         .machine_unregister = sof_machine_unregister,
 251         .set_mach_params = atom_set_mach_params,
 252
 253         /* debug */
 254         .debug_map      = byt_debugfs,
 255         .debug_map_count        = ARRAY_SIZE(byt_debugfs),
 256         .dbg_dump       = atom_dump,
 257         .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
 258
 259         /* stream callbacks */
 260         .pcm_open       = sof_stream_pcm_open,
 261         .pcm_close      = sof_stream_pcm_close,
 262
 263         /*Firmware loading */
 264         .load_firmware  = snd_sof_load_firmware_memcpy,
 265
 266         /* PM */
 267         .suspend = byt_suspend,
 268         .resume = byt_resume,
 269
 270         /* DAI drivers */
 271         .drv = atom_dai,
 272         .num_drv = 3, /* we have only 3 SSPs on byt*/
 273
 274         /* ALSA HW info flags */
 275         .hw_info =      SNDRV_PCM_INFO_MMAP |
 276                         SNDRV_PCM_INFO_MMAP_VALID |
 277                         SNDRV_PCM_INFO_INTERLEAVED |
 278                         SNDRV_PCM_INFO_PAUSE |
 279                         SNDRV_PCM_INFO_BATCH,
 280
 281         .dsp_arch_ops = &sof_xtensa_arch_ops,
 282 };
 283
 284 static const struct sof_intel_dsp_desc byt_chip_info = {
 285         .cores_num = 1,
 286         .host_managed_cores_mask = 1,
 287         .hw_ip_version = SOF_INTEL_BAYTRAIL,
 288 };
 289
 290 /* cherrytrail and braswell ops */
 291 static const struct snd_sof_dsp_ops sof_cht_ops = {
 292         /* device init */
 293         .probe          = byt_acpi_probe,
 294         .remove         = byt_remove,
 295
 296         /* DSP core boot / reset */
 297         .run            = atom_run,
 298         .reset          = atom_reset,
 299
 300         /* Register IO uses direct mmio */
 301
 302         /* Block IO */
 303         .block_read     = sof_block_read,
 304         .block_write    = sof_block_write,
 305
 306         /* Mailbox IO */
 307         .mailbox_read   = sof_mailbox_read,
 308         .mailbox_write  = sof_mailbox_write,
 309
 310         /* doorbell */
 311         .irq_handler    = atom_irq_handler,
 312         .irq_thread     = atom_irq_thread,
 313
 314         /* ipc */
 315         .send_msg       = atom_send_msg,
 316         .get_mailbox_offset = atom_get_mailbox_offset,
 317         .get_window_offset = atom_get_window_offset,
 318
 319         .ipc_msg_data   = sof_ipc_msg_data,
 320         .set_stream_data_offset = sof_set_stream_data_offset,
 321
 322         /* machine driver */
 323         .machine_select = atom_machine_select,
 324         .machine_register = sof_machine_register,
 325         .machine_unregister = sof_machine_unregister,
 326         .set_mach_params = atom_set_mach_params,
 327
 328         /* debug */
 329         .debug_map      = cht_debugfs,
 330         .debug_map_count        = ARRAY_SIZE(cht_debugfs),
 331         .dbg_dump       = atom_dump,
 332         .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
 333
 334         /* stream callbacks */
 335         .pcm_open       = sof_stream_pcm_open,
 336         .pcm_close      = sof_stream_pcm_close,
 337
 338         /*Firmware loading */
 339         .load_firmware  = snd_sof_load_firmware_memcpy,
 340
 341         /* PM */
 342         .suspend = byt_suspend,
 343         .resume = byt_resume,
 344
 345         /* DAI drivers */
 346         .drv = atom_dai,
 347         /* all 6 SSPs may be available for cherrytrail */
 348         .num_drv = 6,
 349
 350         /* ALSA HW info flags */
 351         .hw_info =      SNDRV_PCM_INFO_MMAP |
 352                         SNDRV_PCM_INFO_MMAP_VALID |
 353                         SNDRV_PCM_INFO_INTERLEAVED |
 354                         SNDRV_PCM_INFO_PAUSE |
 355                         SNDRV_PCM_INFO_BATCH,
 356
 357         .dsp_arch_ops = &sof_xtensa_arch_ops,
 358 };
 359
 360 static const struct sof_intel_dsp_desc cht_chip_info = {
 361         .cores_num = 1,
 362         .host_managed_cores_mask = 1,
 363         .hw_ip_version = SOF_INTEL_BAYTRAIL,
 364 };
 365
 366 /* BYTCR uses different IRQ index */
 367 static const struct sof_dev_desc sof_acpi_baytrailcr_desc = {
 368         .machines = snd_soc_acpi_intel_baytrail_machines,
 369         .resindex_lpe_base = 0,
 370         .resindex_pcicfg_base = 1,
 371         .resindex_imr_base = 2,
 372         .irqindex_host_ipc = 0,
 373         .chip_info = &byt_chip_info,
 374         .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
 375         .ipc_default = SOF_IPC_TYPE_3,
 376         .default_fw_path = {
 377                 [SOF_IPC_TYPE_3] = "intel/sof",
 378         },
 379         .default_tplg_path = {
 380                 [SOF_IPC_TYPE_3] = "intel/sof-tplg",
 381         },
 382         .default_fw_filename = {
 383                 [SOF_IPC_TYPE_3] = "sof-byt.ri",
 384         },
 385         .nocodec_tplg_filename = "sof-byt-nocodec.tplg",
 386         .ops = &sof_byt_ops,
 387 };
 388
 389 static const struct sof_dev_desc sof_acpi_baytrail_desc = {
 390         .machines = snd_soc_acpi_intel_baytrail_machines,
 391         .resindex_lpe_base = 0,
 392         .resindex_pcicfg_base = 1,
 393         .resindex_imr_base = 2,
 394         .irqindex_host_ipc = 5,
 395         .chip_info = &byt_chip_info,
 396         .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
 397         .ipc_default = SOF_IPC_TYPE_3,
 398         .default_fw_path = {
 399                 [SOF_IPC_TYPE_3] = "intel/sof",
 400         },
 401         .default_tplg_path = {
 402                 [SOF_IPC_TYPE_3] = "intel/sof-tplg",
 403         },
 404         .default_fw_filename = {
 405                 [SOF_IPC_TYPE_3] = "sof-byt.ri",
 406         },
 407         .nocodec_tplg_filename = "sof-byt-nocodec.tplg",
 408         .ops = &sof_byt_ops,
 409 };
 410
 411 static const struct sof_dev_desc sof_acpi_cherrytrail_desc = {
 412         .machines = snd_soc_acpi_intel_cherrytrail_machines,
 413         .resindex_lpe_base = 0,
 414         .resindex_pcicfg_base = 1,
 415         .resindex_imr_base = 2,
 416         .irqindex_host_ipc = 5,
 417         .chip_info = &cht_chip_info,
 418         .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
 419         .ipc_default = SOF_IPC_TYPE_3,
 420         .default_fw_path = {
 421                 [SOF_IPC_TYPE_3] = "intel/sof",
 422         },
 423         .default_tplg_path = {
 424                 [SOF_IPC_TYPE_3] = "intel/sof-tplg",
 425         },
 426         .default_fw_filename = {
 427                 [SOF_IPC_TYPE_3] = "sof-cht.ri",
 428         },
 429         .nocodec_tplg_filename = "sof-cht-nocodec.tplg",
 430         .ops = &sof_cht_ops,
 431 };
 432
 433 static const struct acpi_device_id sof_baytrail_match[] = {
 434         { "80860F28", (unsigned long)&sof_acpi_baytrail_desc },
 435         { "808622A8", (unsigned long)&sof_acpi_cherrytrail_desc },
 436         { }
 437 };
 438 MODULE_DEVICE_TABLE(acpi, sof_baytrail_match);
 439
 440 static int sof_baytrail_probe(struct platform_device *pdev)
 441 {
 442         struct device *dev = &pdev->dev;
 443         const struct sof_dev_desc *desc;
 444         const struct acpi_device_id *id;
 445         int ret;
 446
 447         id = acpi_match_device(dev->driver->acpi_match_table, dev);
 448         if (!id)
 449                 return -ENODEV;
 450
 451         ret = snd_intel_acpi_dsp_driver_probe(dev, id->id);
 452         if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) {
 453                 dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n");
 454                 return -ENODEV;
 455         }
 456
 457         desc = (const struct sof_dev_desc *)id->driver_data;
 458         if (desc == &sof_acpi_baytrail_desc && soc_intel_is_byt_cr(pdev))
 459                 desc = &sof_acpi_baytrailcr_desc;
 460
 461         return sof_acpi_probe(pdev, desc);
 462 }
 463
 464 /* acpi_driver definition */
 465 static struct platform_driver snd_sof_acpi_intel_byt_driver = {
 466         .probe = sof_baytrail_probe,
 467         .remove = sof_acpi_remove,
 468         .driver = {
 469                 .name = "sof-audio-acpi-intel-byt",
 470                 .pm = &sof_acpi_pm,
 471                 .acpi_match_table = sof_baytrail_match,
 472         },
 473 };
 474 module_platform_driver(snd_sof_acpi_intel_byt_driver);
 475
 476 MODULE_LICENSE("Dual BSD/GPL");
 477 MODULE_DESCRIPTION("SOF support for Baytrail/Cherrytrail");
 478 MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_HIFI_EP_IPC");
 479 MODULE_IMPORT_NS("SND_SOC_SOF_XTENSA");
 480 MODULE_IMPORT_NS("SND_SOC_SOF_ACPI_DEV");
 481 MODULE_IMPORT_NS("SND_SOC_SOF_INTEL_ATOM_HIFI_EP");