1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
6 #include <linux/bitfield.h>
8 #include <linux/component.h>
9 #include <linux/delay.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/media-bus-format.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/of_graph.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21 #include <linux/swab.h>
24 #include <drm/drm_atomic.h>
25 #include <drm/drm_atomic_uapi.h>
26 #include <drm/drm_blend.h>
27 #include <drm/drm_crtc.h>
28 #include <drm/drm_debugfs.h>
29 #include <drm/drm_flip_work.h>
30 #include <drm/drm_framebuffer.h>
31 #include <drm/drm_probe_helper.h>
32 #include <drm/drm_vblank.h>
34 #include <uapi/linux/videodev2.h>
35 #include <dt-bindings/soc/rockchip,vop2.h>
37 #include "rockchip_drm_drv.h"
38 #include "rockchip_drm_gem.h"
39 #include "rockchip_drm_fb.h"
40 #include "rockchip_drm_vop2.h"
41 #include "rockchip_rgb.h"
46 +----------+ +-------------+ +-----------+
47 | Cluster | | Sel 1 from 6| | 1 from 3 |
48 | window0 | | Layer0 | | RGB |
49 +----------+ +-------------+ +---------------+ +-------------+ +-----------+
50 +----------+ +-------------+ |N from 6 layers| | |
51 | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+
52 | window1 | | Layer1 | | | | | | 1 from 3 |
53 +----------+ +-------------+ +---------------+ +-------------+ | LVDS |
54 +----------+ +-------------+ +-----------+
55 | Esmart | | Sel 1 from 6|
56 | window0 | | Layer2 | +---------------+ +-------------+ +-----------+
57 +----------+ +-------------+ |N from 6 Layers| | | +--> | 1 from 3 |
58 +----------+ +-------------+ --------> | Overlay1 +--->| Video Port1 | | MIPI |
59 | Esmart | | Sel 1 from 6| --------> | | | | +-----------+
60 | Window1 | | Layer3 | +---------------+ +-------------+
61 +----------+ +-------------+ +-----------+
62 +----------+ +-------------+ | 1 from 3 |
63 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | HDMI |
64 | Window0 | | Layer4 | |N from 6 Layers| | | +-----------+
65 +----------+ +-------------+ | Overlay2 +--->| Video Port2 |
66 +----------+ +-------------+ | | | | +-----------+
67 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | 1 from 3 |
68 | Window1 | | Layer5 | | eDP |
69 +----------+ +-------------+ +-----------+
73 enum vop2_data_format {
74 VOP2_FMT_ARGB8888 = 0,
85 VOP2_FMT_YUV420SP_TILE_8x4 = 0x10,
86 VOP2_FMT_YUV420SP_TILE_16x2,
87 VOP2_FMT_YUV422SP_TILE_8x4,
88 VOP2_FMT_YUV422SP_TILE_16x2,
94 enum vop2_afbc_format {
96 VOP2_AFBC_FMT_ARGB2101010 = 2,
97 VOP2_AFBC_FMT_YUV420_10BIT,
99 VOP2_AFBC_FMT_ARGB8888,
100 VOP2_AFBC_FMT_YUV420 = 9,
101 VOP2_AFBC_FMT_YUV422 = 0xb,
102 VOP2_AFBC_FMT_YUV422_10BIT = 0xe,
103 VOP2_AFBC_FMT_INVALID = -1,
106 union vop2_alpha_ctrl {
114 u32 alpha_cal_mode:1;
127 union vop2_alpha_ctrl src_color_ctrl;
128 union vop2_alpha_ctrl dst_color_ctrl;
129 union vop2_alpha_ctrl src_alpha_ctrl;
130 union vop2_alpha_ctrl dst_alpha_ctrl;
133 struct vop2_alpha_config {
134 bool src_premulti_en;
135 bool dst_premulti_en;
136 bool src_pixel_alpha_en;
137 bool dst_pixel_alpha_en;
138 u16 src_glb_alpha_value;
139 u16 dst_glb_alpha_value;
144 struct drm_plane base;
145 const struct vop2_win_data *data;
146 struct regmap_field *reg[VOP2_WIN_MAX_REG];
149 * @win_id: graphic window id, a cluster may be split into two
156 enum drm_plane_type type;
159 struct vop2_video_port {
160 struct drm_crtc crtc;
164 const struct vop2_video_port_regs *regs;
165 const struct vop2_video_port_data *data;
167 struct completion dsp_hold_completion;
170 * @win_mask: Bitmask of windows attached to the video port;
174 struct vop2_win *primary_plane;
175 struct drm_pending_vblank_event *event;
177 unsigned int nlayers;
182 struct drm_device *drm;
183 struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
185 const struct vop2_data *data;
187 * Number of windows that are registered as plane, may be less than the
188 * total number of hardware windows.
190 u32 registered_num_wins;
197 /* physical map length of vop2 register */
200 void __iomem *lut_regs;
202 /* protects crtc enable/disable */
203 struct mutex vop2_lock;
208 * Some global resources are shared between all video ports(crtcs), so
209 * we need a ref counter here.
211 unsigned int enable_count;
215 /* optional internal rgb encoder */
216 struct rockchip_rgb *rgb;
218 /* must be put at the end of the struct */
219 struct vop2_win win[];
222 static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc)
224 return container_of(crtc, struct vop2_video_port, crtc);
227 static struct vop2_win *to_vop2_win(struct drm_plane *p)
229 return container_of(p, struct vop2_win, base);
232 static void vop2_lock(struct vop2 *vop2)
234 mutex_lock(&vop2->vop2_lock);
237 static void vop2_unlock(struct vop2 *vop2)
239 mutex_unlock(&vop2->vop2_lock);
242 static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)
244 regmap_write(vop2->map, offset, v);
247 static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v)
249 regmap_write(vp->vop2->map, vp->data->offset + offset, v);
252 static u32 vop2_readl(struct vop2 *vop2, u32 offset)
256 regmap_read(vop2->map, offset, &val);
261 static void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v)
263 regmap_field_write(win->reg[reg], v);
266 static bool vop2_cluster_window(const struct vop2_win *win)
268 return win->data->feature & WIN_FEATURE_CLUSTER;
271 static void vop2_cfg_done(struct vop2_video_port *vp)
273 struct vop2 *vop2 = vp->vop2;
275 regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE,
276 BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
279 static void vop2_win_disable(struct vop2_win *win)
281 vop2_win_write(win, VOP2_WIN_ENABLE, 0);
283 if (vop2_cluster_window(win))
284 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0);
287 static enum vop2_data_format vop2_convert_format(u32 format)
290 case DRM_FORMAT_XRGB8888:
291 case DRM_FORMAT_ARGB8888:
292 case DRM_FORMAT_XBGR8888:
293 case DRM_FORMAT_ABGR8888:
294 return VOP2_FMT_ARGB8888;
295 case DRM_FORMAT_RGB888:
296 case DRM_FORMAT_BGR888:
297 return VOP2_FMT_RGB888;
298 case DRM_FORMAT_RGB565:
299 case DRM_FORMAT_BGR565:
300 return VOP2_FMT_RGB565;
301 case DRM_FORMAT_NV12:
302 return VOP2_FMT_YUV420SP;
303 case DRM_FORMAT_NV16:
304 return VOP2_FMT_YUV422SP;
305 case DRM_FORMAT_NV24:
306 return VOP2_FMT_YUV444SP;
307 case DRM_FORMAT_YUYV:
308 case DRM_FORMAT_YVYU:
309 return VOP2_FMT_VYUY422;
310 case DRM_FORMAT_VYUY:
311 case DRM_FORMAT_UYVY:
312 return VOP2_FMT_YUYV422;
314 DRM_ERROR("unsupported format[%08x]\n", format);
319 static enum vop2_afbc_format vop2_convert_afbc_format(u32 format)
322 case DRM_FORMAT_XRGB8888:
323 case DRM_FORMAT_ARGB8888:
324 case DRM_FORMAT_XBGR8888:
325 case DRM_FORMAT_ABGR8888:
326 return VOP2_AFBC_FMT_ARGB8888;
327 case DRM_FORMAT_RGB888:
328 case DRM_FORMAT_BGR888:
329 return VOP2_AFBC_FMT_RGB888;
330 case DRM_FORMAT_RGB565:
331 case DRM_FORMAT_BGR565:
332 return VOP2_AFBC_FMT_RGB565;
333 case DRM_FORMAT_NV12:
334 return VOP2_AFBC_FMT_YUV420;
335 case DRM_FORMAT_NV16:
336 return VOP2_AFBC_FMT_YUV422;
338 return VOP2_AFBC_FMT_INVALID;
341 return VOP2_AFBC_FMT_INVALID;
344 static bool vop2_win_rb_swap(u32 format)
347 case DRM_FORMAT_XBGR8888:
348 case DRM_FORMAT_ABGR8888:
349 case DRM_FORMAT_BGR888:
350 case DRM_FORMAT_BGR565:
357 static bool vop2_afbc_rb_swap(u32 format)
360 case DRM_FORMAT_NV24:
367 static bool vop2_afbc_uv_swap(u32 format)
370 case DRM_FORMAT_NV12:
371 case DRM_FORMAT_NV16:
378 static bool vop2_win_uv_swap(u32 format)
381 case DRM_FORMAT_NV12:
382 case DRM_FORMAT_NV16:
383 case DRM_FORMAT_NV24:
390 static bool vop2_win_dither_up(u32 format)
393 case DRM_FORMAT_BGR565:
394 case DRM_FORMAT_RGB565:
401 static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode)
406 * There is no media type for YUV444 output,
407 * so when out_mode is AAAA or P888, assume output is YUV444 on
410 * From H/W testing, YUV444 mode need a rb swap.
412 if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 ||
413 bus_format == MEDIA_BUS_FMT_VYUY8_1X16 ||
414 bus_format == MEDIA_BUS_FMT_YVYU8_2X8 ||
415 bus_format == MEDIA_BUS_FMT_VYUY8_2X8 ||
416 ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
417 bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
418 (output_mode == ROCKCHIP_OUT_MODE_AAAA ||
419 output_mode == ROCKCHIP_OUT_MODE_P888)))
425 static bool is_yuv_output(u32 bus_format)
427 switch (bus_format) {
428 case MEDIA_BUS_FMT_YUV8_1X24:
429 case MEDIA_BUS_FMT_YUV10_1X30:
430 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
431 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
432 case MEDIA_BUS_FMT_YUYV8_2X8:
433 case MEDIA_BUS_FMT_YVYU8_2X8:
434 case MEDIA_BUS_FMT_UYVY8_2X8:
435 case MEDIA_BUS_FMT_VYUY8_2X8:
436 case MEDIA_BUS_FMT_YUYV8_1X16:
437 case MEDIA_BUS_FMT_YVYU8_1X16:
438 case MEDIA_BUS_FMT_UYVY8_1X16:
439 case MEDIA_BUS_FMT_VYUY8_1X16:
446 static bool rockchip_afbc(struct drm_plane *plane, u64 modifier)
450 if (modifier == DRM_FORMAT_MOD_LINEAR)
453 for (i = 0 ; i < plane->modifier_count; i++)
454 if (plane->modifiers[i] == modifier)
460 static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format,
463 struct vop2_win *win = to_vop2_win(plane);
464 struct vop2 *vop2 = win->vop2;
466 if (modifier == DRM_FORMAT_MOD_INVALID)
469 if (modifier == DRM_FORMAT_MOD_LINEAR)
472 if (!rockchip_afbc(plane, modifier)) {
473 drm_err(vop2->drm, "Unsupported format modifier 0x%llx\n",
479 return vop2_convert_afbc_format(format) >= 0;
482 static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate,
483 bool afbc_half_block_en)
485 struct drm_rect *src = &pstate->src;
486 struct drm_framebuffer *fb = pstate->fb;
487 u32 bpp = fb->format->cpp[0] * 8;
488 u32 vir_width = (fb->pitches[0] << 3) / bpp;
489 u32 width = drm_rect_width(src) >> 16;
490 u32 height = drm_rect_height(src) >> 16;
491 u32 act_xoffset = src->x1 >> 16;
492 u32 act_yoffset = src->y1 >> 16;
493 u32 align16_crop = 0;
494 u32 align64_crop = 0;
497 u8 bottom_crop_line_num = 0;
501 align16_crop = 16 - (height & 0xf);
503 height_tmp = height + align16_crop;
506 if (height_tmp & 0x3f)
507 align64_crop = 64 - (height_tmp & 0x3f);
509 bottom_crop_line_num = align16_crop + align64_crop;
511 switch (pstate->rotation &
512 (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y |
513 DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) {
514 case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y:
515 tx = 16 - ((act_xoffset + width) & 0xf);
516 ty = bottom_crop_line_num - act_yoffset;
518 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90:
519 tx = bottom_crop_line_num - act_yoffset;
520 ty = vir_width - width - act_xoffset;
522 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270:
526 case DRM_MODE_REFLECT_X:
527 tx = 16 - ((act_xoffset + width) & 0xf);
530 case DRM_MODE_REFLECT_Y:
532 ty = bottom_crop_line_num - act_yoffset;
534 case DRM_MODE_ROTATE_90:
535 tx = bottom_crop_line_num - act_yoffset;
538 case DRM_MODE_ROTATE_270:
540 ty = vir_width - width - act_xoffset;
548 if (afbc_half_block_en)
551 #define TRANSFORM_XOFFSET GENMASK(7, 0)
552 #define TRANSFORM_YOFFSET GENMASK(23, 16)
553 return FIELD_PREP(TRANSFORM_XOFFSET, tx) |
554 FIELD_PREP(TRANSFORM_YOFFSET, ty);
558 * A Cluster window has 2048 x 16 line buffer, which can
559 * works at 2048 x 16(Full) or 4096 x 8 (Half) mode.
560 * for Cluster_lb_mode register:
561 * 0: half mode, for plane input width range 2048 ~ 4096
562 * 1: half mode, for cluster work at 2 * 2048 plane mode
563 * 2: half mode, for rotate_90/270 mode
566 static int vop2_get_cluster_lb_mode(struct vop2_win *win,
567 struct drm_plane_state *pstate)
569 if ((pstate->rotation & DRM_MODE_ROTATE_270) ||
570 (pstate->rotation & DRM_MODE_ROTATE_90))
576 static u16 vop2_scale_factor(u32 src, u32 dst)
598 fac = DIV_ROUND_UP(src << shift, dst) - 1;
606 static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
607 u32 src_w, u32 src_h, u32 dst_w,
608 u32 dst_h, u32 pixel_format)
610 const struct drm_format_info *info;
611 u16 hor_scl_mode, ver_scl_mode;
612 u16 hscl_filter_mode, vscl_filter_mode;
617 info = drm_format_info(pixel_format);
619 if (src_h >= (4 * dst_h)) {
622 } else if (src_h >= (2 * dst_h)) {
627 hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
628 ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
630 if (hor_scl_mode == SCALE_UP)
631 hscl_filter_mode = VOP2_SCALE_UP_BIC;
633 hscl_filter_mode = VOP2_SCALE_DOWN_BIL;
635 if (ver_scl_mode == SCALE_UP)
636 vscl_filter_mode = VOP2_SCALE_UP_BIL;
638 vscl_filter_mode = VOP2_SCALE_DOWN_BIL;
641 * RK3568 VOP Esmart/Smart dsp_w should be even pixel
644 if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
645 if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) {
646 drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n",
647 win->data->name, dst_w);
652 val = vop2_scale_factor(src_w, dst_w);
653 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val);
654 val = vop2_scale_factor(src_h, dst_h);
655 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val);
657 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4);
658 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2);
660 vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode);
661 vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode);
663 if (vop2_cluster_window(win))
666 vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode);
667 vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode);
676 if (src_h >= (4 * dst_h)) {
679 } else if (src_h >= (2 * dst_h)) {
684 hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
685 ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
687 val = vop2_scale_factor(src_w, dst_w);
688 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val);
690 val = vop2_scale_factor(src_h, dst_h);
691 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val);
693 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4);
694 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2);
695 vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode);
696 vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode);
697 vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode);
698 vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode);
702 static int vop2_convert_csc_mode(int csc_mode)
705 case V4L2_COLORSPACE_SMPTE170M:
706 case V4L2_COLORSPACE_470_SYSTEM_M:
707 case V4L2_COLORSPACE_470_SYSTEM_BG:
709 case V4L2_COLORSPACE_REC709:
710 case V4L2_COLORSPACE_SMPTE240M:
711 case V4L2_COLORSPACE_DEFAULT:
713 case V4L2_COLORSPACE_JPEG:
715 case V4L2_COLORSPACE_BT2020:
724 * Input Win csc Output
725 * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
728 * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020)
729 * RGB --> 709To2020->R2Y __/
731 * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709)
734 * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
735 * RGB --> 709To2020->R2Y __/
737 * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709)
740 * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601)
741 * RGB --> R2Y(601) __/
743 * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709)
746 * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020)
748 * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709)
750 * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601)
752 * 11. RGB --> bypass --> RGB_OUTPUT(709)
755 static void vop2_setup_csc_mode(struct vop2_video_port *vp,
756 struct vop2_win *win,
757 struct drm_plane_state *pstate)
759 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
760 int is_input_yuv = pstate->fb->format->is_yuv;
761 int is_output_yuv = is_yuv_output(vcstate->bus_format);
762 int input_csc = V4L2_COLORSPACE_DEFAULT;
763 int output_csc = vcstate->color_space;
767 if (is_input_yuv && !is_output_yuv) {
770 csc_mode = vop2_convert_csc_mode(input_csc);
771 } else if (!is_input_yuv && is_output_yuv) {
774 csc_mode = vop2_convert_csc_mode(output_csc);
781 vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en);
782 vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en);
783 vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode);
786 static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq)
788 struct vop2 *vop2 = vp->vop2;
790 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq);
791 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq);
794 static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq)
796 struct vop2 *vop2 = vp->vop2;
798 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16);
801 static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
805 ret = clk_prepare_enable(vop2->hclk);
807 drm_err(vop2->drm, "failed to enable hclk - %d\n", ret);
811 ret = clk_prepare_enable(vop2->aclk);
813 drm_err(vop2->drm, "failed to enable aclk - %d\n", ret);
819 clk_disable_unprepare(vop2->hclk);
824 static void vop2_enable(struct vop2 *vop2)
828 ret = pm_runtime_resume_and_get(vop2->dev);
830 drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret);
834 ret = vop2_core_clks_prepare_enable(vop2);
836 pm_runtime_put_sync(vop2->dev);
840 ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev);
842 drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret);
846 regcache_sync(vop2->map);
848 if (vop2->data->soc_id == 3566)
849 vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);
851 vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
854 * Disable auto gating, this is a workaround to
855 * avoid display image shift when a window enabled.
857 regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL,
858 RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN);
860 vop2_writel(vop2, RK3568_SYS0_INT_CLR,
861 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
862 vop2_writel(vop2, RK3568_SYS0_INT_EN,
863 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
864 vop2_writel(vop2, RK3568_SYS1_INT_CLR,
865 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
866 vop2_writel(vop2, RK3568_SYS1_INT_EN,
867 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
870 static void vop2_disable(struct vop2 *vop2)
872 rockchip_drm_dma_detach_device(vop2->drm, vop2->dev);
874 pm_runtime_put_sync(vop2->dev);
876 regcache_mark_dirty(vop2->map);
878 clk_disable_unprepare(vop2->aclk);
879 clk_disable_unprepare(vop2->hclk);
882 static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
883 struct drm_atomic_state *state)
885 struct vop2_video_port *vp = to_vop2_video_port(crtc);
886 struct vop2 *vop2 = vp->vop2;
887 struct drm_crtc_state *old_crtc_state;
892 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
893 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
895 drm_crtc_vblank_off(crtc);
898 * Vop standby will take effect at end of current frame,
899 * if dsp hold valid irq happen, it means standby complete.
901 * we must wait standby complete when we want to disable aclk,
902 * if not, memory bus maybe dead.
904 reinit_completion(&vp->dsp_hold_completion);
906 vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID);
908 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY);
910 ret = wait_for_completion_timeout(&vp->dsp_hold_completion,
911 msecs_to_jiffies(50));
913 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id);
915 vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID);
917 clk_disable_unprepare(vp->dclk);
919 vop2->enable_count--;
921 if (!vop2->enable_count)
926 if (crtc->state->event && !crtc->state->active) {
927 spin_lock_irq(&crtc->dev->event_lock);
928 drm_crtc_send_vblank_event(crtc, crtc->state->event);
929 spin_unlock_irq(&crtc->dev->event_lock);
931 crtc->state->event = NULL;
935 static int vop2_plane_atomic_check(struct drm_plane *plane,
936 struct drm_atomic_state *astate)
938 struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane);
939 struct drm_framebuffer *fb = pstate->fb;
940 struct drm_crtc *crtc = pstate->crtc;
941 struct drm_crtc_state *cstate;
942 struct vop2_video_port *vp;
944 const struct vop2_data *vop2_data;
945 struct drm_rect *dest = &pstate->dst;
946 struct drm_rect *src = &pstate->src;
947 int min_scale = FRAC_16_16(1, 8);
948 int max_scale = FRAC_16_16(8, 1);
955 vp = to_vop2_video_port(crtc);
957 vop2_data = vop2->data;
959 cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc);
960 if (WARN_ON(!cstate))
963 ret = drm_atomic_helper_check_plane_state(pstate, cstate,
964 min_scale, max_scale,
969 if (!pstate->visible)
972 format = vop2_convert_format(fb->format->format);
976 if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 ||
977 drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) {
978 drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n",
979 drm_rect_width(src) >> 16, drm_rect_height(src) >> 16,
980 drm_rect_width(dest), drm_rect_height(dest));
981 pstate->visible = false;
985 if (drm_rect_width(src) >> 16 > vop2_data->max_input.width ||
986 drm_rect_height(src) >> 16 > vop2_data->max_input.height) {
987 drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n",
988 drm_rect_width(src) >> 16,
989 drm_rect_height(src) >> 16,
990 vop2_data->max_input.width,
991 vop2_data->max_input.height);
996 * Src.x1 can be odd when do clip, but yuv plane start point
997 * need align with 2 pixel.
999 if (fb->format->is_yuv && ((pstate->src.x1 >> 16) % 2)) {
1000 drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n");
1007 static void vop2_plane_atomic_disable(struct drm_plane *plane,
1008 struct drm_atomic_state *state)
1010 struct drm_plane_state *old_pstate = NULL;
1011 struct vop2_win *win = to_vop2_win(plane);
1012 struct vop2 *vop2 = win->vop2;
1014 drm_dbg(vop2->drm, "%s disable\n", win->data->name);
1017 old_pstate = drm_atomic_get_old_plane_state(state, plane);
1018 if (old_pstate && !old_pstate->crtc)
1021 vop2_win_disable(win);
1022 vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0);
1026 * The color key is 10 bit, so all format should
1027 * convert to 10 bit here.
1029 static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key)
1031 struct drm_plane_state *pstate = plane->state;
1032 struct drm_framebuffer *fb = pstate->fb;
1033 struct vop2_win *win = to_vop2_win(plane);
1034 u32 color_key_en = 0;
1039 if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) {
1040 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0);
1044 switch (fb->format->format) {
1045 case DRM_FORMAT_RGB565:
1046 case DRM_FORMAT_BGR565:
1047 r = (color_key & 0xf800) >> 11;
1048 g = (color_key & 0x7e0) >> 5;
1049 b = (color_key & 0x1f);
1055 case DRM_FORMAT_XRGB8888:
1056 case DRM_FORMAT_ARGB8888:
1057 case DRM_FORMAT_XBGR8888:
1058 case DRM_FORMAT_ABGR8888:
1059 case DRM_FORMAT_RGB888:
1060 case DRM_FORMAT_BGR888:
1061 r = (color_key & 0xff0000) >> 16;
1062 g = (color_key & 0xff00) >> 8;
1063 b = (color_key & 0xff);
1071 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, color_key_en);
1072 vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b);
1075 static void vop2_plane_atomic_update(struct drm_plane *plane,
1076 struct drm_atomic_state *state)
1078 struct drm_plane_state *pstate = plane->state;
1079 struct drm_crtc *crtc = pstate->crtc;
1080 struct vop2_win *win = to_vop2_win(plane);
1081 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1082 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1083 struct vop2 *vop2 = win->vop2;
1084 struct drm_framebuffer *fb = pstate->fb;
1085 u32 bpp = fb->format->cpp[0] * 8;
1086 u32 actual_w, actual_h, dsp_w, dsp_h;
1087 u32 act_info, dsp_info;
1092 struct drm_rect *src = &pstate->src;
1093 struct drm_rect *dest = &pstate->dst;
1095 u32 transform_offset;
1097 bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false;
1098 bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false;
1099 bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270;
1100 bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90;
1101 struct rockchip_gem_object *rk_obj;
1102 unsigned long offset;
1104 dma_addr_t yrgb_mst;
1108 * can't update plane when vop2 is disabled.
1113 if (!pstate->visible) {
1114 vop2_plane_atomic_disable(plane, state);
1118 afbc_en = rockchip_afbc(plane, fb->modifier);
1120 offset = (src->x1 >> 16) * fb->format->cpp[0];
1123 * AFBC HDR_PTR must set to the zero offset of the framebuffer.
1127 else if (pstate->rotation & DRM_MODE_REFLECT_Y)
1128 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1130 offset += (src->y1 >> 16) * fb->pitches[0];
1132 rk_obj = to_rockchip_obj(fb->obj[0]);
1134 yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
1135 if (fb->format->is_yuv) {
1136 int hsub = fb->format->hsub;
1137 int vsub = fb->format->vsub;
1139 offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub;
1140 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1142 if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en)
1143 offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub;
1145 rk_obj = to_rockchip_obj(fb->obj[0]);
1146 uv_mst = rk_obj->dma_addr + offset + fb->offsets[1];
1149 actual_w = drm_rect_width(src) >> 16;
1150 actual_h = drm_rect_height(src) >> 16;
1151 dsp_w = drm_rect_width(dest);
1153 if (dest->x1 + dsp_w > adjusted_mode->hdisplay) {
1154 drm_err(vop2->drm, "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
1155 vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay);
1156 dsp_w = adjusted_mode->hdisplay - dest->x1;
1159 actual_w = dsp_w * actual_w / drm_rect_width(dest);
1162 dsp_h = drm_rect_height(dest);
1164 if (dest->y1 + dsp_h > adjusted_mode->vdisplay) {
1165 drm_err(vop2->drm, "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
1166 vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay);
1167 dsp_h = adjusted_mode->vdisplay - dest->y1;
1170 actual_h = dsp_h * actual_h / drm_rect_height(dest);
1174 * This is workaround solution for IC design:
1175 * esmart can't support scale down when actual_w % 16 == 1.
1177 if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
1178 if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
1179 drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n",
1180 vp->id, win->data->name, actual_w);
1185 if (afbc_en && actual_w % 4) {
1186 drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n",
1187 vp->id, win->data->name, actual_w);
1188 actual_w = ALIGN_DOWN(actual_w, 4);
1191 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1192 dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff);
1194 format = vop2_convert_format(fb->format->format);
1196 drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n",
1197 vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h,
1199 &fb->format->format,
1200 afbc_en ? "AFBC" : "", &yrgb_mst);
1205 /* the afbc superblock is 16 x 16 */
1206 afbc_format = vop2_convert_afbc_format(fb->format->format);
1208 /* Enable color transform for YTR */
1209 if (fb->modifier & AFBC_FORMAT_MOD_YTR)
1210 afbc_format |= (1 << 4);
1212 afbc_tile_num = ALIGN(actual_w, 16) >> 4;
1215 * AFBC pic_vir_width is count by pixel, this is different
1216 * with WIN_VIR_STRIDE.
1218 stride = (fb->pitches[0] << 3) / bpp;
1219 if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270))
1220 drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n",
1221 vp->id, win->data->name, stride);
1223 rb_swap = vop2_afbc_rb_swap(fb->format->format);
1224 uv_swap = vop2_afbc_uv_swap(fb->format->format);
1226 * This is a workaround for crazy IC design, Cluster
1227 * and Esmart/Smart use different format configuration map:
1228 * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart.
1230 * This is one thing we can make the convert simple:
1231 * AFBCD decode all the YUV data to YUV444. So we just
1232 * set all the yuv 10 bit to YUV444_10.
1234 if (fb->format->is_yuv && bpp == 10)
1235 format = VOP2_CLUSTER_YUV444_10;
1237 if (vop2_cluster_window(win))
1238 vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1);
1239 vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format);
1240 vop2_win_write(win, VOP2_WIN_AFBC_RB_SWAP, rb_swap);
1241 vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap);
1242 vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0);
1243 vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0);
1244 if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) {
1245 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 0);
1246 transform_offset = vop2_afbc_transform_offset(pstate, false);
1248 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 1);
1249 transform_offset = vop2_afbc_transform_offset(pstate, true);
1251 vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst);
1252 vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info);
1253 vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset);
1254 vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1));
1255 vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16)));
1256 vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride);
1257 vop2_win_write(win, VOP2_WIN_AFBC_TILE_NUM, afbc_tile_num);
1258 vop2_win_write(win, VOP2_WIN_XMIRROR, xmirror);
1259 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270);
1260 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90);
1262 vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4));
1265 vop2_win_write(win, VOP2_WIN_YMIRROR, ymirror);
1267 if (rotate_90 || rotate_270) {
1268 act_info = swahw32(act_info);
1269 actual_w = drm_rect_height(src) >> 16;
1270 actual_h = drm_rect_width(src) >> 16;
1273 vop2_win_write(win, VOP2_WIN_FORMAT, format);
1274 vop2_win_write(win, VOP2_WIN_YRGB_MST, yrgb_mst);
1276 rb_swap = vop2_win_rb_swap(fb->format->format);
1277 vop2_win_write(win, VOP2_WIN_RB_SWAP, rb_swap);
1278 if (!vop2_cluster_window(win)) {
1279 uv_swap = vop2_win_uv_swap(fb->format->format);
1280 vop2_win_write(win, VOP2_WIN_UV_SWAP, uv_swap);
1283 if (fb->format->is_yuv) {
1284 vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4));
1285 vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst);
1288 vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format);
1289 if (!vop2_cluster_window(win))
1290 vop2_plane_setup_color_key(plane, 0);
1291 vop2_win_write(win, VOP2_WIN_ACT_INFO, act_info);
1292 vop2_win_write(win, VOP2_WIN_DSP_INFO, dsp_info);
1293 vop2_win_write(win, VOP2_WIN_DSP_ST, dest->y1 << 16 | (dest->x1 & 0xffff));
1295 vop2_setup_csc_mode(vp, win, pstate);
1297 dither_up = vop2_win_dither_up(fb->format->format);
1298 vop2_win_write(win, VOP2_WIN_DITHER_UP, dither_up);
1300 vop2_win_write(win, VOP2_WIN_ENABLE, 1);
1302 if (vop2_cluster_window(win)) {
1303 int lb_mode = vop2_get_cluster_lb_mode(win, pstate);
1305 vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode);
1306 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1);
1310 static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = {
1311 .atomic_check = vop2_plane_atomic_check,
1312 .atomic_update = vop2_plane_atomic_update,
1313 .atomic_disable = vop2_plane_atomic_disable,
1316 static const struct drm_plane_funcs vop2_plane_funcs = {
1317 .update_plane = drm_atomic_helper_update_plane,
1318 .disable_plane = drm_atomic_helper_disable_plane,
1319 .destroy = drm_plane_cleanup,
1320 .reset = drm_atomic_helper_plane_reset,
1321 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1322 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1323 .format_mod_supported = rockchip_vop2_mod_supported,
1326 static int vop2_crtc_enable_vblank(struct drm_crtc *crtc)
1328 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1330 vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD);
1335 static void vop2_crtc_disable_vblank(struct drm_crtc *crtc)
1337 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1339 vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD);
1342 static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
1343 const struct drm_display_mode *mode,
1344 struct drm_display_mode *adj_mode)
1346 drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V |
1347 CRTC_STEREO_DOUBLE);
1352 static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl)
1354 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1356 switch (vcstate->bus_format) {
1357 case MEDIA_BUS_FMT_RGB565_1X16:
1358 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN;
1360 case MEDIA_BUS_FMT_RGB666_1X18:
1361 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1362 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
1363 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN;
1364 *dsp_ctrl |= RGB888_TO_RGB666;
1366 case MEDIA_BUS_FMT_YUV8_1X24:
1367 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1368 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN;
1374 if (vcstate->output_mode != ROCKCHIP_OUT_MODE_AAAA)
1375 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN;
1377 *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL,
1378 DITHER_DOWN_ALLEGRO);
1381 static void vop2_post_config(struct drm_crtc *crtc)
1383 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1384 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1385 u16 vtotal = mode->crtc_vtotal;
1386 u16 hdisplay = mode->crtc_hdisplay;
1387 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1388 u16 vdisplay = mode->crtc_vdisplay;
1389 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1390 u32 left_margin = 100, right_margin = 100;
1391 u32 top_margin = 100, bottom_margin = 100;
1392 u16 hsize = hdisplay * (left_margin + right_margin) / 200;
1393 u16 vsize = vdisplay * (top_margin + bottom_margin) / 200;
1394 u16 hact_end, vact_end;
1397 vsize = rounddown(vsize, 2);
1398 hsize = rounddown(hsize, 2);
1399 hact_st += hdisplay * (100 - left_margin) / 200;
1400 hact_end = hact_st + hsize;
1401 val = hact_st << 16;
1403 vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val);
1404 vact_st += vdisplay * (100 - top_margin) / 200;
1405 vact_end = vact_st + vsize;
1406 val = vact_st << 16;
1408 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val);
1409 val = scl_cal_scale2(vdisplay, vsize) << 16;
1410 val |= scl_cal_scale2(hdisplay, hsize);
1411 vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val);
1414 if (hdisplay != hsize)
1415 val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN;
1416 if (vdisplay != vsize)
1417 val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN;
1418 vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val);
1420 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1421 u16 vact_st_f1 = vtotal + vact_st + 1;
1422 u16 vact_end_f1 = vact_st_f1 + vsize;
1424 val = vact_st_f1 << 16 | vact_end_f1;
1425 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val);
1428 vop2_vp_write(vp, RK3568_VP_DSP_BG, 0);
1431 static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id,
1434 struct vop2 *vop2 = vp->vop2;
1437 die = vop2_readl(vop2, RK3568_DSP_IF_EN);
1438 dip = vop2_readl(vop2, RK3568_DSP_IF_POL);
1441 case ROCKCHIP_VOP2_EP_RGB0:
1442 die &= ~RK3568_SYS_DSP_INFACE_EN_RGB_MUX;
1443 die |= RK3568_SYS_DSP_INFACE_EN_RGB |
1444 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id);
1445 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1446 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1447 if (polflags & POLFLAG_DCLK_INV)
1448 regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3));
1450 regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16));
1452 case ROCKCHIP_VOP2_EP_HDMI0:
1453 die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX;
1454 die |= RK3568_SYS_DSP_INFACE_EN_HDMI |
1455 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id);
1456 dip &= ~RK3568_DSP_IF_POL__HDMI_PIN_POL;
1457 dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags);
1459 case ROCKCHIP_VOP2_EP_EDP0:
1460 die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX;
1461 die |= RK3568_SYS_DSP_INFACE_EN_EDP |
1462 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id);
1463 dip &= ~RK3568_DSP_IF_POL__EDP_PIN_POL;
1464 dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags);
1466 case ROCKCHIP_VOP2_EP_MIPI0:
1467 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX;
1468 die |= RK3568_SYS_DSP_INFACE_EN_MIPI0 |
1469 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id);
1470 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL;
1471 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags);
1473 case ROCKCHIP_VOP2_EP_MIPI1:
1474 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX;
1475 die |= RK3568_SYS_DSP_INFACE_EN_MIPI1 |
1476 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id);
1477 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL;
1478 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags);
1480 case ROCKCHIP_VOP2_EP_LVDS0:
1481 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX;
1482 die |= RK3568_SYS_DSP_INFACE_EN_LVDS0 |
1483 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id);
1484 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1485 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1487 case ROCKCHIP_VOP2_EP_LVDS1:
1488 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX;
1489 die |= RK3568_SYS_DSP_INFACE_EN_LVDS1 |
1490 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id);
1491 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1492 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1495 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
1499 dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD;
1501 vop2_writel(vop2, RK3568_DSP_IF_EN, die);
1502 vop2_writel(vop2, RK3568_DSP_IF_POL, dip);
1505 static int us_to_vertical_line(struct drm_display_mode *mode, int us)
1507 return us * mode->clock / mode->htotal / 1000;
1510 static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
1511 struct drm_atomic_state *state)
1513 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1514 struct vop2 *vop2 = vp->vop2;
1515 const struct vop2_data *vop2_data = vop2->data;
1516 const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
1517 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1518 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1519 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1520 unsigned long clock = mode->crtc_clock * 1000;
1521 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
1522 u16 hdisplay = mode->crtc_hdisplay;
1523 u16 htotal = mode->crtc_htotal;
1524 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1525 u16 hact_end = hact_st + hdisplay;
1526 u16 vdisplay = mode->crtc_vdisplay;
1527 u16 vtotal = mode->crtc_vtotal;
1528 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
1529 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1530 u16 vact_end = vact_st + vdisplay;
1536 struct drm_encoder *encoder;
1538 drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
1539 hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
1540 drm_mode_vrefresh(mode), vcstate->output_type, vp->id);
1544 ret = clk_prepare_enable(vp->dclk);
1546 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n",
1552 if (!vop2->enable_count)
1555 vop2->enable_count++;
1557 vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY);
1560 if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
1561 polflags |= POLFLAG_DCLK_INV;
1562 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1563 polflags |= BIT(HSYNC_POSITIVE);
1564 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1565 polflags |= BIT(VSYNC_POSITIVE);
1567 drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
1568 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
1570 rk3568_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags);
1573 if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1574 !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1575 out_mode = ROCKCHIP_OUT_MODE_P888;
1577 out_mode = vcstate->output_mode;
1579 dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode);
1581 if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode))
1582 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP;
1584 if (is_yuv_output(vcstate->bus_format))
1585 dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y;
1587 vop2_dither_setup(crtc, &dsp_ctrl);
1589 vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len);
1590 val = hact_st << 16;
1592 vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val);
1594 val = vact_st << 16;
1596 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val);
1598 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1599 u16 vact_st_f1 = vtotal + vact_st + 1;
1600 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1602 val = vact_st_f1 << 16 | vact_end_f1;
1603 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val);
1605 val = vtotal << 16 | (vtotal + vsync_len);
1606 vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val);
1607 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE;
1608 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL;
1609 dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN;
1610 vtotal += vtotal + 1;
1611 act_end = vact_end_f1;
1616 vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id),
1617 (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end);
1619 vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len);
1621 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1622 dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV;
1626 vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0);
1628 clk_set_rate(vp->dclk, clock);
1630 vop2_post_config(crtc);
1634 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
1636 drm_crtc_vblank_on(crtc);
1641 static int vop2_crtc_atomic_check(struct drm_crtc *crtc,
1642 struct drm_atomic_state *state)
1644 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1645 struct drm_plane *plane;
1647 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1649 drm_atomic_crtc_state_for_each_plane(plane, crtc_state)
1652 if (nplanes > vp->nlayers)
1658 static bool is_opaque(u16 alpha)
1660 return (alpha >> 8) == 0xff;
1663 static void vop2_parse_alpha(struct vop2_alpha_config *alpha_config,
1664 struct vop2_alpha *alpha)
1666 int src_glb_alpha_en = is_opaque(alpha_config->src_glb_alpha_value) ? 0 : 1;
1667 int dst_glb_alpha_en = is_opaque(alpha_config->dst_glb_alpha_value) ? 0 : 1;
1668 int src_color_mode = alpha_config->src_premulti_en ?
1669 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL;
1670 int dst_color_mode = alpha_config->dst_premulti_en ?
1671 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL;
1673 alpha->src_color_ctrl.val = 0;
1674 alpha->dst_color_ctrl.val = 0;
1675 alpha->src_alpha_ctrl.val = 0;
1676 alpha->dst_alpha_ctrl.val = 0;
1678 if (!alpha_config->src_pixel_alpha_en)
1679 alpha->src_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
1680 else if (alpha_config->src_pixel_alpha_en && !src_glb_alpha_en)
1681 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX;
1683 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
1685 alpha->src_color_ctrl.bits.alpha_en = 1;
1687 if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_GLOBAL) {
1688 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
1689 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
1690 } else if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_PER_PIX) {
1691 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
1692 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_ONE;
1694 alpha->src_color_ctrl.bits.color_mode = ALPHA_SRC_PRE_MUL;
1695 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
1697 alpha->src_color_ctrl.bits.glb_alpha = alpha_config->src_glb_alpha_value >> 8;
1698 alpha->src_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1699 alpha->src_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1701 alpha->dst_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1702 alpha->dst_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1703 alpha->dst_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
1704 alpha->dst_color_ctrl.bits.glb_alpha = alpha_config->dst_glb_alpha_value >> 8;
1705 alpha->dst_color_ctrl.bits.color_mode = dst_color_mode;
1706 alpha->dst_color_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
1708 alpha->src_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1709 alpha->src_alpha_ctrl.bits.blend_mode = alpha->src_color_ctrl.bits.blend_mode;
1710 alpha->src_alpha_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1711 alpha->src_alpha_ctrl.bits.factor_mode = ALPHA_ONE;
1713 alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1714 if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en)
1715 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX;
1717 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
1718 alpha->dst_alpha_ctrl.bits.alpha_cal_mode = ALPHA_NO_SATURATION;
1719 alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
1722 static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id)
1724 struct vop2_video_port *vp;
1728 for (i = 0; i < port_id; i++) {
1730 used_layer += hweight32(vp->win_mask);
1736 static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win)
1738 u32 offset = (main_win->data->phys_id * 0x10);
1739 struct vop2_alpha_config alpha_config;
1740 struct vop2_alpha alpha;
1741 struct drm_plane_state *bottom_win_pstate;
1742 bool src_pixel_alpha_en = false;
1743 u16 src_glb_alpha_val, dst_glb_alpha_val;
1744 bool premulti_en = false;
1747 /* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */
1748 bottom_win_pstate = main_win->base.state;
1749 src_glb_alpha_val = 0;
1750 dst_glb_alpha_val = main_win->base.state->alpha;
1752 if (!bottom_win_pstate->fb)
1755 alpha_config.src_premulti_en = premulti_en;
1756 alpha_config.dst_premulti_en = false;
1757 alpha_config.src_pixel_alpha_en = src_pixel_alpha_en;
1758 alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
1759 alpha_config.src_glb_alpha_value = src_glb_alpha_val;
1760 alpha_config.dst_glb_alpha_value = dst_glb_alpha_val;
1761 vop2_parse_alpha(&alpha_config, &alpha);
1763 alpha.src_color_ctrl.bits.src_dst_swap = swap;
1764 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset,
1765 alpha.src_color_ctrl.val);
1766 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset,
1767 alpha.dst_color_ctrl.val);
1768 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset,
1769 alpha.src_alpha_ctrl.val);
1770 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset,
1771 alpha.dst_alpha_ctrl.val);
1774 static void vop2_setup_alpha(struct vop2_video_port *vp)
1776 struct vop2 *vop2 = vp->vop2;
1777 struct drm_framebuffer *fb;
1778 struct vop2_alpha_config alpha_config;
1779 struct vop2_alpha alpha;
1780 struct drm_plane *plane;
1782 int premulti_en, gpremulti_en = 0;
1785 bool bottom_layer_alpha_en = false;
1786 u32 dst_global_alpha = DRM_BLEND_ALPHA_OPAQUE;
1788 mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id);
1789 alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
1791 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1792 struct vop2_win *win = to_vop2_win(plane);
1794 if (plane->state->normalized_zpos == 0 &&
1795 !is_opaque(plane->state->alpha) &&
1796 !vop2_cluster_window(win)) {
1798 * If bottom layer have global alpha effect [except cluster layer,
1799 * because cluster have deal with bottom layer global alpha value
1800 * at cluster mix], bottom layer mix need deal with global alpha.
1802 bottom_layer_alpha_en = true;
1803 dst_global_alpha = plane->state->alpha;
1807 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1808 struct vop2_win *win = to_vop2_win(plane);
1809 int zpos = plane->state->normalized_zpos;
1811 if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
1817 fb = plane->state->fb;
1819 pixel_alpha_en = fb->format->has_alpha;
1821 alpha_config.src_premulti_en = premulti_en;
1823 if (bottom_layer_alpha_en && zpos == 1) {
1824 gpremulti_en = premulti_en;
1825 /* Cd = Cs + (1 - As) * Cd * Agd */
1826 alpha_config.dst_premulti_en = false;
1827 alpha_config.src_pixel_alpha_en = pixel_alpha_en;
1828 alpha_config.src_glb_alpha_value = plane->state->alpha;
1829 alpha_config.dst_glb_alpha_value = dst_global_alpha;
1830 } else if (vop2_cluster_window(win)) {
1831 /* Mix output data only have pixel alpha */
1832 alpha_config.dst_premulti_en = true;
1833 alpha_config.src_pixel_alpha_en = true;
1834 alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1835 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1837 /* Cd = Cs + (1 - As) * Cd */
1838 alpha_config.dst_premulti_en = true;
1839 alpha_config.src_pixel_alpha_en = pixel_alpha_en;
1840 alpha_config.src_glb_alpha_value = plane->state->alpha;
1841 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1844 vop2_parse_alpha(&alpha_config, &alpha);
1846 offset = (mixer_id + zpos - 1) * 0x10;
1847 vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset,
1848 alpha.src_color_ctrl.val);
1849 vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset,
1850 alpha.dst_color_ctrl.val);
1851 vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset,
1852 alpha.src_alpha_ctrl.val);
1853 vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset,
1854 alpha.dst_alpha_ctrl.val);
1858 if (bottom_layer_alpha_en) {
1859 /* Transfer pixel alpha to hdr mix */
1860 alpha_config.src_premulti_en = gpremulti_en;
1861 alpha_config.dst_premulti_en = true;
1862 alpha_config.src_pixel_alpha_en = true;
1863 alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1864 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1865 vop2_parse_alpha(&alpha_config, &alpha);
1867 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL,
1868 alpha.src_color_ctrl.val);
1869 vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL,
1870 alpha.dst_color_ctrl.val);
1871 vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL,
1872 alpha.src_alpha_ctrl.val);
1873 vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL,
1874 alpha.dst_alpha_ctrl.val);
1876 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0);
1881 static void vop2_setup_layer_mixer(struct vop2_video_port *vp)
1883 struct vop2 *vop2 = vp->vop2;
1884 struct drm_plane *plane;
1887 unsigned int nlayer, ofs;
1888 struct drm_display_mode *adjusted_mode;
1894 struct vop2_video_port *vp0 = &vop2->vps[0];
1895 struct vop2_video_port *vp1 = &vop2->vps[1];
1896 struct vop2_video_port *vp2 = &vop2->vps[2];
1898 adjusted_mode = &vp->crtc.state->adjusted_mode;
1899 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1900 hdisplay = adjusted_mode->crtc_hdisplay;
1902 bg_dly = vp->data->pre_scan_max_dly[3];
1903 vop2_writel(vop2, RK3568_VP_BG_MIX_CTRL(vp->id),
1904 FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly));
1906 pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;
1907 vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly);
1909 vop2_writel(vop2, RK3568_OVL_CTRL, 0);
1910 port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL);
1911 port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT;
1914 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX,
1917 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 8);
1920 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX,
1921 (vp0->nlayers + vp1->nlayers - 1));
1923 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8);
1926 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX,
1927 (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1));
1929 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8);
1931 layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);
1934 for (i = 0; i < vp->id; i++)
1935 ofs += vop2->vps[i].nlayers;
1938 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1939 struct vop2_win *win = to_vop2_win(plane);
1941 switch (win->data->phys_id) {
1942 case ROCKCHIP_VOP2_CLUSTER0:
1943 port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER0;
1944 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id);
1946 case ROCKCHIP_VOP2_CLUSTER1:
1947 port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1;
1948 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id);
1950 case ROCKCHIP_VOP2_ESMART0:
1951 port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0;
1952 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id);
1954 case ROCKCHIP_VOP2_ESMART1:
1955 port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1;
1956 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id);
1958 case ROCKCHIP_VOP2_SMART0:
1959 port_sel &= ~RK3568_OVL_PORT_SEL__SMART0;
1960 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id);
1962 case ROCKCHIP_VOP2_SMART1:
1963 port_sel &= ~RK3568_OVL_PORT_SEL__SMART1;
1964 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id);
1968 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs,
1970 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos + ofs,
1971 win->data->layer_sel_id);
1975 /* configure unused layers to 0x5 (reserved) */
1976 for (; nlayer < vp->nlayers; nlayer++) {
1977 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 0x7);
1978 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 5);
1981 vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel);
1982 vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel);
1983 vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD);
1986 static void vop2_setup_dly_for_windows(struct vop2 *vop2)
1988 struct vop2_win *win;
1990 u32 cdly = 0, sdly = 0;
1992 for (i = 0; i < vop2->data->win_size; i++) {
1995 win = &vop2->win[i];
1998 switch (win->data->phys_id) {
1999 case ROCKCHIP_VOP2_CLUSTER0:
2000 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_0, dly);
2001 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_1, dly);
2003 case ROCKCHIP_VOP2_CLUSTER1:
2004 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_0, dly);
2005 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_1, dly);
2007 case ROCKCHIP_VOP2_ESMART0:
2008 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART0, dly);
2010 case ROCKCHIP_VOP2_ESMART1:
2011 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly);
2013 case ROCKCHIP_VOP2_SMART0:
2014 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly);
2016 case ROCKCHIP_VOP2_SMART1:
2017 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly);
2022 vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly);
2023 vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly);
2026 static void vop2_crtc_atomic_begin(struct drm_crtc *crtc,
2027 struct drm_atomic_state *state)
2029 struct vop2_video_port *vp = to_vop2_video_port(crtc);
2030 struct vop2 *vop2 = vp->vop2;
2031 struct drm_plane *plane;
2035 drm_atomic_crtc_for_each_plane(plane, crtc) {
2036 struct vop2_win *win = to_vop2_win(plane);
2038 win->delay = win->data->dly[VOP2_DLY_MODE_DEFAULT];
2040 vp->win_mask |= BIT(win->data->phys_id);
2042 if (vop2_cluster_window(win))
2043 vop2_setup_cluster_alpha(vop2, win);
2049 vop2_setup_layer_mixer(vp);
2050 vop2_setup_alpha(vp);
2051 vop2_setup_dly_for_windows(vop2);
2054 static void vop2_crtc_atomic_flush(struct drm_crtc *crtc,
2055 struct drm_atomic_state *state)
2057 struct vop2_video_port *vp = to_vop2_video_port(crtc);
2059 vop2_post_config(crtc);
2063 spin_lock_irq(&crtc->dev->event_lock);
2065 if (crtc->state->event) {
2066 WARN_ON(drm_crtc_vblank_get(crtc));
2067 vp->event = crtc->state->event;
2068 crtc->state->event = NULL;
2071 spin_unlock_irq(&crtc->dev->event_lock);
2074 static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = {
2075 .mode_fixup = vop2_crtc_mode_fixup,
2076 .atomic_check = vop2_crtc_atomic_check,
2077 .atomic_begin = vop2_crtc_atomic_begin,
2078 .atomic_flush = vop2_crtc_atomic_flush,
2079 .atomic_enable = vop2_crtc_atomic_enable,
2080 .atomic_disable = vop2_crtc_atomic_disable,
2083 static void vop2_crtc_reset(struct drm_crtc *crtc)
2085 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
2088 __drm_atomic_helper_crtc_destroy_state(crtc->state);
2092 vcstate = kzalloc(sizeof(*vcstate), GFP_KERNEL);
2096 crtc->state = &vcstate->base;
2097 crtc->state->crtc = crtc;
2100 static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc)
2102 struct rockchip_crtc_state *vcstate, *old_vcstate;
2104 old_vcstate = to_rockchip_crtc_state(crtc->state);
2106 vcstate = kmemdup(old_vcstate, sizeof(*old_vcstate), GFP_KERNEL);
2110 __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base);
2112 return &vcstate->base;
2115 static void vop2_crtc_destroy_state(struct drm_crtc *crtc,
2116 struct drm_crtc_state *state)
2118 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
2120 __drm_atomic_helper_crtc_destroy_state(&vcstate->base);
2124 static const struct drm_crtc_funcs vop2_crtc_funcs = {
2125 .set_config = drm_atomic_helper_set_config,
2126 .page_flip = drm_atomic_helper_page_flip,
2127 .destroy = drm_crtc_cleanup,
2128 .reset = vop2_crtc_reset,
2129 .atomic_duplicate_state = vop2_crtc_duplicate_state,
2130 .atomic_destroy_state = vop2_crtc_destroy_state,
2131 .enable_vblank = vop2_crtc_enable_vblank,
2132 .disable_vblank = vop2_crtc_disable_vblank,
2135 static irqreturn_t vop2_isr(int irq, void *data)
2137 struct vop2 *vop2 = data;
2138 const struct vop2_data *vop2_data = vop2->data;
2139 u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM];
2144 * The irq is shared with the iommu. If the runtime-pm state of the
2145 * vop2-device is disabled the irq has to be targeted at the iommu.
2147 if (!pm_runtime_get_if_in_use(vop2->dev))
2150 for (i = 0; i < vop2_data->nr_vps; i++) {
2151 struct vop2_video_port *vp = &vop2->vps[i];
2152 struct drm_crtc *crtc = &vp->crtc;
2155 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id));
2156 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs);
2158 if (irqs & VP_INT_DSP_HOLD_VALID) {
2159 complete(&vp->dsp_hold_completion);
2163 if (irqs & VP_INT_FS_FIELD) {
2164 drm_crtc_handle_vblank(crtc);
2165 spin_lock(&crtc->dev->event_lock);
2167 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE);
2169 if (!(val & BIT(vp->id))) {
2170 drm_crtc_send_vblank_event(crtc, vp->event);
2172 drm_crtc_vblank_put(crtc);
2175 spin_unlock(&crtc->dev->event_lock);
2180 if (irqs & VP_INT_POST_BUF_EMPTY) {
2181 drm_err_ratelimited(vop2->drm,
2182 "POST_BUF_EMPTY irq err at vp%d\n",
2188 axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS);
2189 vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]);
2190 axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS);
2191 vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]);
2193 for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) {
2194 if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) {
2195 drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n");
2200 pm_runtime_put(vop2->dev);
2205 static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win,
2206 unsigned long possible_crtcs)
2208 const struct vop2_win_data *win_data = win->data;
2209 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
2210 BIT(DRM_MODE_BLEND_PREMULTI) |
2211 BIT(DRM_MODE_BLEND_COVERAGE);
2214 ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs,
2215 &vop2_plane_funcs, win_data->formats,
2217 win_data->format_modifiers,
2218 win->type, win_data->name);
2220 drm_err(vop2->drm, "failed to initialize plane %d\n", ret);
2224 drm_plane_helper_add(&win->base, &vop2_plane_helper_funcs);
2226 if (win->data->supported_rotations)
2227 drm_plane_create_rotation_property(&win->base, DRM_MODE_ROTATE_0,
2229 win->data->supported_rotations);
2230 drm_plane_create_alpha_property(&win->base);
2231 drm_plane_create_blend_mode_property(&win->base, blend_caps);
2232 drm_plane_create_zpos_property(&win->base, win->win_id, 0,
2233 vop2->registered_num_wins - 1);
2238 static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2)
2242 for (i = 0; i < vop2->data->nr_vps; i++) {
2243 struct vop2_video_port *vp = &vop2->vps[i];
2247 if (vp->primary_plane)
2258 static int vop2_create_crtcs(struct vop2 *vop2)
2260 const struct vop2_data *vop2_data = vop2->data;
2261 struct drm_device *drm = vop2->drm;
2262 struct device *dev = vop2->dev;
2263 struct drm_plane *plane;
2264 struct device_node *port;
2265 struct vop2_video_port *vp;
2266 int i, nvp, nvps = 0;
2269 for (i = 0; i < vop2_data->nr_vps; i++) {
2270 const struct vop2_video_port_data *vp_data;
2271 struct device_node *np;
2274 vp_data = &vop2_data->vp[i];
2277 vp->id = vp_data->id;
2278 vp->regs = vp_data->regs;
2281 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id);
2282 vp->dclk = devm_clk_get(vop2->dev, dclk_name);
2283 if (IS_ERR(vp->dclk)) {
2284 drm_err(vop2->drm, "failed to get %s\n", dclk_name);
2285 return PTR_ERR(vp->dclk);
2288 np = of_graph_get_remote_node(dev->of_node, i, -1);
2290 drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i);
2295 port = of_graph_get_port_by_id(dev->of_node, i);
2297 drm_err(vop2->drm, "no port node found for video_port%d\n", i);
2301 vp->crtc.port = port;
2306 for (i = 0; i < vop2->registered_num_wins; i++) {
2307 struct vop2_win *win = &vop2->win[i];
2308 u32 possible_crtcs = 0;
2310 if (vop2->data->soc_id == 3566) {
2312 * On RK3566 these windows don't have an independent
2313 * framebuffer. They share the framebuffer with smart0,
2314 * esmart0 and cluster0 respectively.
2316 switch (win->data->phys_id) {
2317 case ROCKCHIP_VOP2_SMART1:
2318 case ROCKCHIP_VOP2_ESMART1:
2319 case ROCKCHIP_VOP2_CLUSTER1:
2324 if (win->type == DRM_PLANE_TYPE_PRIMARY) {
2325 vp = find_vp_without_primary(vop2);
2327 possible_crtcs = BIT(nvp);
2328 vp->primary_plane = win;
2331 /* change the unused primary window to overlay window */
2332 win->type = DRM_PLANE_TYPE_OVERLAY;
2336 if (win->type == DRM_PLANE_TYPE_OVERLAY)
2337 possible_crtcs = (1 << nvps) - 1;
2339 ret = vop2_plane_init(vop2, win, possible_crtcs);
2341 drm_err(vop2->drm, "failed to init plane %s: %d\n",
2342 win->data->name, ret);
2347 for (i = 0; i < vop2_data->nr_vps; i++) {
2353 plane = &vp->primary_plane->base;
2355 ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL,
2357 "video_port%d", vp->id);
2359 drm_err(vop2->drm, "crtc init for video_port%d failed\n", i);
2363 drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs);
2365 init_completion(&vp->dsp_hold_completion);
2369 * On the VOP2 it's very hard to change the number of layers on a VP
2370 * during runtime, so we distribute the layers equally over the used
2373 for (i = 0; i < vop2->data->nr_vps; i++) {
2374 struct vop2_video_port *vp = &vop2->vps[i];
2377 vp->nlayers = NR_LAYERS / nvps;
2383 static void vop2_destroy_crtcs(struct vop2 *vop2)
2385 struct drm_device *drm = vop2->drm;
2386 struct list_head *crtc_list = &drm->mode_config.crtc_list;
2387 struct list_head *plane_list = &drm->mode_config.plane_list;
2388 struct drm_crtc *crtc, *tmpc;
2389 struct drm_plane *plane, *tmpp;
2391 list_for_each_entry_safe(plane, tmpp, plane_list, head)
2392 drm_plane_cleanup(plane);
2395 * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane()
2396 * references the CRTC.
2398 list_for_each_entry_safe(crtc, tmpc, crtc_list, head) {
2399 of_node_put(crtc->port);
2400 drm_crtc_cleanup(crtc);
2404 static int vop2_find_rgb_encoder(struct vop2 *vop2)
2406 struct device_node *node = vop2->dev->of_node;
2407 struct device_node *endpoint;
2410 for (i = 0; i < vop2->data->nr_vps; i++) {
2411 endpoint = of_graph_get_endpoint_by_regs(node, i,
2412 ROCKCHIP_VOP2_EP_RGB0);
2416 of_node_put(endpoint);
2423 static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = {
2424 [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0),
2425 [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5),
2426 [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14),
2427 [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18),
2428 [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31),
2429 [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31),
2430 [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31),
2431 [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31),
2432 [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31),
2433 [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19),
2434 [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15),
2435 [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31),
2436 [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8),
2437 [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9),
2438 [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11),
2441 [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15),
2442 [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31),
2443 [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15),
2444 [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13),
2445 [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3),
2446 [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28),
2447 [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29),
2450 [VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1),
2451 [VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0),
2452 [VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7),
2455 [VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6),
2456 [VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9),
2457 [VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10),
2458 [VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4),
2459 [VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7),
2460 [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8),
2461 [VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31),
2462 [VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31),
2463 [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15),
2464 [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31),
2465 [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31),
2466 [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31),
2467 [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31),
2468 [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0),
2469 [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1),
2470 [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2),
2471 [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3),
2472 [VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff },
2473 [VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff },
2474 [VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff },
2475 [VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff },
2476 [VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff },
2477 [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
2478 [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
2479 [VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff },
2480 [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
2481 [VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff },
2482 [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
2483 [VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff },
2484 [VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff },
2487 static int vop2_cluster_init(struct vop2_win *win)
2489 struct vop2 *vop2 = win->vop2;
2490 struct reg_field *cluster_regs;
2493 cluster_regs = kmemdup(vop2_cluster_regs, sizeof(vop2_cluster_regs),
2498 for (i = 0; i < ARRAY_SIZE(vop2_cluster_regs); i++)
2499 if (cluster_regs[i].reg != 0xffffffff)
2500 cluster_regs[i].reg += win->offset;
2502 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
2504 ARRAY_SIZE(vop2_cluster_regs));
2506 kfree(cluster_regs);
2511 static struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = {
2512 [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0),
2513 [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5),
2514 [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12),
2515 [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14),
2516 [VOP2_WIN_UV_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16),
2517 [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31),
2518 [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31),
2519 [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28),
2520 [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31),
2521 [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31),
2522 [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17),
2523 [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15),
2524 [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31),
2525 [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_SMART_CTRL0, 0, 0),
2526 [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_SMART_CTRL0, 1, 1),
2527 [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_SMART_CTRL0, 2, 3),
2528 [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31),
2529 [VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29),
2530 [VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31),
2533 [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15),
2534 [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 16, 31),
2535 [VOP2_WIN_SCALE_CBCR_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 0, 15),
2536 [VOP2_WIN_SCALE_CBCR_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 16, 31),
2537 [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 0, 1),
2538 [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 2, 3),
2539 [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 4, 5),
2540 [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 6, 7),
2541 [VOP2_WIN_CBCR_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 8, 9),
2542 [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 10, 11),
2543 [VOP2_WIN_CBCR_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 12, 13),
2544 [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 14, 15),
2545 [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 17),
2546 [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8),
2547 [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9),
2548 [VOP2_WIN_VSD_CBCR_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10),
2549 [VOP2_WIN_VSD_CBCR_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11),
2550 [VOP2_WIN_XMIRROR] = { .reg = 0xffffffff },
2551 [VOP2_WIN_CLUSTER_ENABLE] = { .reg = 0xffffffff },
2552 [VOP2_WIN_AFBC_ENABLE] = { .reg = 0xffffffff },
2553 [VOP2_WIN_CLUSTER_LB_MODE] = { .reg = 0xffffffff },
2554 [VOP2_WIN_AFBC_FORMAT] = { .reg = 0xffffffff },
2555 [VOP2_WIN_AFBC_RB_SWAP] = { .reg = 0xffffffff },
2556 [VOP2_WIN_AFBC_UV_SWAP] = { .reg = 0xffffffff },
2557 [VOP2_WIN_AFBC_AUTO_GATING_EN] = { .reg = 0xffffffff },
2558 [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = { .reg = 0xffffffff },
2559 [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = { .reg = 0xffffffff },
2560 [VOP2_WIN_AFBC_TILE_NUM] = { .reg = 0xffffffff },
2561 [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff },
2562 [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff },
2563 [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff },
2564 [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff },
2565 [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff },
2566 [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff },
2567 [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff },
2568 [VOP2_WIN_AFBC_ROTATE_90] = { .reg = 0xffffffff },
2571 static int vop2_esmart_init(struct vop2_win *win)
2573 struct vop2 *vop2 = win->vop2;
2574 struct reg_field *esmart_regs;
2577 esmart_regs = kmemdup(vop2_esmart_regs, sizeof(vop2_esmart_regs),
2582 for (i = 0; i < ARRAY_SIZE(vop2_esmart_regs); i++)
2583 if (esmart_regs[i].reg != 0xffffffff)
2584 esmart_regs[i].reg += win->offset;
2586 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
2588 ARRAY_SIZE(vop2_esmart_regs));
2595 static int vop2_win_init(struct vop2 *vop2)
2597 const struct vop2_data *vop2_data = vop2->data;
2598 struct vop2_win *win;
2601 for (i = 0; i < vop2_data->win_size; i++) {
2602 const struct vop2_win_data *win_data = &vop2_data->win[i];
2604 win = &vop2->win[i];
2605 win->data = win_data;
2606 win->type = win_data->type;
2607 win->offset = win_data->base;
2610 if (vop2_cluster_window(win))
2611 ret = vop2_cluster_init(win);
2613 ret = vop2_esmart_init(win);
2618 vop2->registered_num_wins = vop2_data->win_size;
2624 * The window registers are only updated when config done is written.
2625 * Until that they read back the old value. As we read-modify-write
2626 * these registers mark them as non-volatile. This makes sure we read
2627 * the new values from the regmap register cache.
2629 static const struct regmap_range vop2_nonvolatile_range[] = {
2630 regmap_reg_range(0x1000, 0x23ff),
2633 static const struct regmap_access_table vop2_volatile_table = {
2634 .no_ranges = vop2_nonvolatile_range,
2635 .n_no_ranges = ARRAY_SIZE(vop2_nonvolatile_range),
2638 static const struct regmap_config vop2_regmap_config = {
2642 .max_register = 0x3000,
2644 .volatile_table = &vop2_volatile_table,
2645 .cache_type = REGCACHE_RBTREE,
2648 static int vop2_bind(struct device *dev, struct device *master, void *data)
2650 struct platform_device *pdev = to_platform_device(dev);
2651 const struct vop2_data *vop2_data;
2652 struct drm_device *drm = data;
2654 struct resource *res;
2658 vop2_data = of_device_get_match_data(dev);
2662 /* Allocate vop2 struct and its vop2_win array */
2663 alloc_size = struct_size(vop2, win, vop2_data->win_size);
2664 vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2669 vop2->data = vop2_data;
2672 dev_set_drvdata(dev, vop2);
2674 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vop");
2676 drm_err(vop2->drm, "failed to get vop2 register byname\n");
2680 vop2->regs = devm_ioremap_resource(dev, res);
2681 if (IS_ERR(vop2->regs))
2682 return PTR_ERR(vop2->regs);
2683 vop2->len = resource_size(res);
2685 vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config);
2686 if (IS_ERR(vop2->map))
2687 return PTR_ERR(vop2->map);
2689 ret = vop2_win_init(vop2);
2693 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma-lut");
2695 vop2->lut_regs = devm_ioremap_resource(dev, res);
2696 if (IS_ERR(vop2->lut_regs))
2697 return PTR_ERR(vop2->lut_regs);
2700 vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
2702 vop2->hclk = devm_clk_get(vop2->dev, "hclk");
2703 if (IS_ERR(vop2->hclk)) {
2704 drm_err(vop2->drm, "failed to get hclk source\n");
2705 return PTR_ERR(vop2->hclk);
2708 vop2->aclk = devm_clk_get(vop2->dev, "aclk");
2709 if (IS_ERR(vop2->aclk)) {
2710 drm_err(vop2->drm, "failed to get aclk source\n");
2711 return PTR_ERR(vop2->aclk);
2714 vop2->irq = platform_get_irq(pdev, 0);
2715 if (vop2->irq < 0) {
2716 drm_err(vop2->drm, "cannot find irq for vop2\n");
2720 mutex_init(&vop2->vop2_lock);
2722 ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2);
2726 ret = vop2_create_crtcs(vop2);
2730 ret = vop2_find_rgb_encoder(vop2);
2732 vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc,
2734 if (IS_ERR(vop2->rgb)) {
2735 if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) {
2736 ret = PTR_ERR(vop2->rgb);
2743 rockchip_drm_dma_init_device(vop2->drm, vop2->dev);
2745 pm_runtime_enable(&pdev->dev);
2750 vop2_destroy_crtcs(vop2);
2755 static void vop2_unbind(struct device *dev, struct device *master, void *data)
2757 struct vop2 *vop2 = dev_get_drvdata(dev);
2759 pm_runtime_disable(dev);
2762 rockchip_rgb_fini(vop2->rgb);
2764 vop2_destroy_crtcs(vop2);
2767 const struct component_ops vop2_component_ops = {
2769 .unbind = vop2_unbind,
2771 EXPORT_SYMBOL_GPL(vop2_component_ops);