drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
   4  * Author: Andy Yan <[email protected]>
   5  */
   6 #include <linux/bitfield.h>
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/delay.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/kernel.h>
  12 #include <linux/media-bus-format.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_graph.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/regmap.h>
  20 #include <linux/swab.h>
  21
  22 #include <drm/drm.h>
  23 #include <drm/drm_atomic.h>
  24 #include <drm/drm_atomic_uapi.h>
  25 #include <drm/drm_blend.h>
  26 #include <drm/drm_crtc.h>
  27 #include <linux/debugfs.h>
  28 #include <drm/drm_debugfs.h>
  29 #include <drm/drm_flip_work.h>
  30 #include <drm/drm_framebuffer.h>
  31 #include <drm/drm_gem_framebuffer_helper.h>
  32 #include <drm/drm_probe_helper.h>
  33 #include <drm/drm_vblank.h>
  34
  35 #include <uapi/linux/videodev2.h>
  36 #include <dt-bindings/soc/rockchip,vop2.h>
  37
  38 #include "rockchip_drm_gem.h"
  39 #include "rockchip_drm_vop2.h"
  40 #include "rockchip_rgb.h"
  41
  42 /*
  43  * VOP2 architecture
  44  *
  45  +----------+   +-------------+                                                        +-----------+
  46  |  Cluster |   | Sel 1 from 6|                                                        | 1 from 3  |
  47  |  window0 |   |    Layer0   |                                                        |    RGB    |
  48  +----------+   +-------------+              +---------------+    +-------------+      +-----------+
  49  +----------+   +-------------+              |N from 6 layers|    |             |
  50  |  Cluster |   | Sel 1 from 6|              |   Overlay0    +--->| Video Port0 |      +-----------+
  51  |  window1 |   |    Layer1   |              |               |    |             |      | 1 from 3  |
  52  +----------+   +-------------+              +---------------+    +-------------+      |   LVDS    |
  53  +----------+   +-------------+                                                        +-----------+
  54  |  Esmart  |   | Sel 1 from 6|
  55  |  window0 |   |   Layer2    |              +---------------+    +-------------+      +-----------+
  56  +----------+   +-------------+              |N from 6 Layers|    |             | +--> | 1 from 3  |
  57  +----------+   +-------------+   -------->  |   Overlay1    +--->| Video Port1 |      |   MIPI    |
  58  |  Esmart  |   | Sel 1 from 6|   -------->  |               |    |             |      +-----------+
  59  |  Window1 |   |   Layer3    |              +---------------+    +-------------+
  60  +----------+   +-------------+                                                        +-----------+
  61  +----------+   +-------------+                                                        | 1 from 3  |
  62  |  Smart   |   | Sel 1 from 6|              +---------------+    +-------------+      |   HDMI    |
  63  |  Window0 |   |    Layer4   |              |N from 6 Layers|    |             |      +-----------+
  64  +----------+   +-------------+              |   Overlay2    +--->| Video Port2 |
  65  +----------+   +-------------+              |               |    |             |      +-----------+
  66  |  Smart   |   | Sel 1 from 6|              +---------------+    +-------------+      |  1 from 3 |
  67  |  Window1 |   |    Layer5   |                                                        |    eDP    |
  68  +----------+   +-------------+                                                        +-----------+
  69  *
  70  */
  71
  72 enum vop2_data_format {
  73         VOP2_FMT_ARGB8888 = 0,
  74         VOP2_FMT_RGB888,
  75         VOP2_FMT_RGB565,
  76         VOP2_FMT_XRGB101010,
  77         VOP2_FMT_YUV420SP,
  78         VOP2_FMT_YUV422SP,
  79         VOP2_FMT_YUV444SP,
  80         VOP2_FMT_YUYV422 = 8,
  81         VOP2_FMT_YUYV420,
  82         VOP2_FMT_VYUY422,
  83         VOP2_FMT_VYUY420,
  84         VOP2_FMT_YUV420SP_TILE_8x4 = 0x10,
  85         VOP2_FMT_YUV420SP_TILE_16x2,
  86         VOP2_FMT_YUV422SP_TILE_8x4,
  87         VOP2_FMT_YUV422SP_TILE_16x2,
  88         VOP2_FMT_YUV420SP_10,
  89         VOP2_FMT_YUV422SP_10,
  90         VOP2_FMT_YUV444SP_10,
  91 };
  92
  93 enum vop2_afbc_format {
  94         VOP2_AFBC_FMT_RGB565,
  95         VOP2_AFBC_FMT_ARGB2101010 = 2,
  96         VOP2_AFBC_FMT_YUV420_10BIT,
  97         VOP2_AFBC_FMT_RGB888,
  98         VOP2_AFBC_FMT_ARGB8888,
  99         VOP2_AFBC_FMT_YUV420 = 9,
 100         VOP2_AFBC_FMT_YUV422 = 0xb,
 101         VOP2_AFBC_FMT_YUV422_10BIT = 0xe,
 102         VOP2_AFBC_FMT_INVALID = -1,
 103 };
 104
 105 union vop2_alpha_ctrl {
 106         u32 val;
 107         struct {
 108                 /* [0:1] */
 109                 u32 color_mode:1;
 110                 u32 alpha_mode:1;
 111                 /* [2:3] */
 112                 u32 blend_mode:2;
 113                 u32 alpha_cal_mode:1;
 114                 /* [5:7] */
 115                 u32 factor_mode:3;
 116                 /* [8:9] */
 117                 u32 alpha_en:1;
 118                 u32 src_dst_swap:1;
 119                 u32 reserved:6;
 120                 /* [16:23] */
 121                 u32 glb_alpha:8;
 122         } bits;
 123 };
 124
 125 struct vop2_alpha {
 126         union vop2_alpha_ctrl src_color_ctrl;
 127         union vop2_alpha_ctrl dst_color_ctrl;
 128         union vop2_alpha_ctrl src_alpha_ctrl;
 129         union vop2_alpha_ctrl dst_alpha_ctrl;
 130 };
 131
 132 struct vop2_alpha_config {
 133         bool src_premulti_en;
 134         bool dst_premulti_en;
 135         bool src_pixel_alpha_en;
 136         bool dst_pixel_alpha_en;
 137         u16 src_glb_alpha_value;
 138         u16 dst_glb_alpha_value;
 139 };
 140
 141 struct vop2_win {
 142         struct vop2 *vop2;
 143         struct drm_plane base;
 144         const struct vop2_win_data *data;
 145         struct regmap_field *reg[VOP2_WIN_MAX_REG];
 146
 147         /**
 148          * @win_id: graphic window id, a cluster may be split into two
 149          * graphics windows.
 150          */
 151         u8 win_id;
 152         u8 delay;
 153         u32 offset;
 154
 155         enum drm_plane_type type;
 156 };
 157
 158 struct vop2_video_port {
 159         struct drm_crtc crtc;
 160         struct vop2 *vop2;
 161         struct clk *dclk;
 162         unsigned int id;
 163         const struct vop2_video_port_data *data;
 164
 165         struct completion dsp_hold_completion;
 166
 167         /**
 168          * @win_mask: Bitmask of windows attached to the video port;
 169          */
 170         u32 win_mask;
 171
 172         struct vop2_win *primary_plane;
 173         struct drm_pending_vblank_event *event;
 174
 175         unsigned int nlayers;
 176 };
 177
 178 struct vop2 {
 179         struct device *dev;
 180         struct drm_device *drm;
 181         struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
 182
 183         const struct vop2_data *data;
 184         /*
 185          * Number of windows that are registered as plane, may be less than the
 186          * total number of hardware windows.
 187          */
 188         u32 registered_num_wins;
 189
 190         struct resource *res;
 191         void __iomem *regs;
 192         struct regmap *map;
 193
 194         struct regmap *sys_grf;
 195         struct regmap *vop_grf;
 196         struct regmap *vo1_grf;
 197         struct regmap *sys_pmu;
 198
 199         /* physical map length of vop2 register */
 200         u32 len;
 201
 202         void __iomem *lut_regs;
 203
 204         /* protects crtc enable/disable */
 205         struct mutex vop2_lock;
 206
 207         int irq;
 208
 209         /*
 210          * Some global resources are shared between all video ports(crtcs), so
 211          * we need a ref counter here.
 212          */
 213         unsigned int enable_count;
 214         struct clk *hclk;
 215         struct clk *aclk;
 216         struct clk *pclk;
 217
 218         /* optional internal rgb encoder */
 219         struct rockchip_rgb *rgb;
 220
 221         /* must be put at the end of the struct */
 222         struct vop2_win win[];
 223 };
 224
 225 #define vop2_output_if_is_hdmi(x)       ((x) == ROCKCHIP_VOP2_EP_HDMI0 || \
 226                                          (x) == ROCKCHIP_VOP2_EP_HDMI1)
 227
 228 #define vop2_output_if_is_dp(x)         ((x) == ROCKCHIP_VOP2_EP_DP0 || \
 229                                          (x) == ROCKCHIP_VOP2_EP_DP1)
 230
 231 #define vop2_output_if_is_edp(x)        ((x) == ROCKCHIP_VOP2_EP_EDP0 || \
 232                                          (x) == ROCKCHIP_VOP2_EP_EDP1)
 233
 234 #define vop2_output_if_is_mipi(x)       ((x) == ROCKCHIP_VOP2_EP_MIPI0 || \
 235                                          (x) == ROCKCHIP_VOP2_EP_MIPI1)
 236
 237 #define vop2_output_if_is_lvds(x)       ((x) == ROCKCHIP_VOP2_EP_LVDS0 || \
 238                                          (x) == ROCKCHIP_VOP2_EP_LVDS1)
 239
 240 #define vop2_output_if_is_dpi(x)        ((x) == ROCKCHIP_VOP2_EP_RGB0)
 241
 242 /*
 243  * bus-format types.
 244  */
 245 struct drm_bus_format_enum_list {
 246         int type;
 247         const char *name;
 248 };
 249
 250 static const struct drm_bus_format_enum_list drm_bus_format_enum_list[] = {
 251         { DRM_MODE_CONNECTOR_Unknown, "Unknown" },
 252         { MEDIA_BUS_FMT_RGB565_1X16, "RGB565_1X16" },
 253         { MEDIA_BUS_FMT_RGB666_1X18, "RGB666_1X18" },
 254         { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, "RGB666_1X24_CPADHI" },
 255         { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, "RGB666_1X7X3_SPWG" },
 256         { MEDIA_BUS_FMT_YUV8_1X24, "YUV8_1X24" },
 257         { MEDIA_BUS_FMT_UYYVYY8_0_5X24, "UYYVYY8_0_5X24" },
 258         { MEDIA_BUS_FMT_YUV10_1X30, "YUV10_1X30" },
 259         { MEDIA_BUS_FMT_UYYVYY10_0_5X30, "UYYVYY10_0_5X30" },
 260         { MEDIA_BUS_FMT_RGB888_3X8, "RGB888_3X8" },
 261         { MEDIA_BUS_FMT_RGB888_1X24, "RGB888_1X24" },
 262         { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, "RGB888_1X7X4_SPWG" },
 263         { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, "RGB888_1X7X4_JEIDA" },
 264         { MEDIA_BUS_FMT_UYVY8_2X8, "UYVY8_2X8" },
 265         { MEDIA_BUS_FMT_YUYV8_1X16, "YUYV8_1X16" },
 266         { MEDIA_BUS_FMT_UYVY8_1X16, "UYVY8_1X16" },
 267         { MEDIA_BUS_FMT_RGB101010_1X30, "RGB101010_1X30" },
 268         { MEDIA_BUS_FMT_YUYV10_1X20, "YUYV10_1X20" },
 269 };
 270
 271 static DRM_ENUM_NAME_FN(drm_get_bus_format_name, drm_bus_format_enum_list)
 272
 273 static const struct regmap_config vop2_regmap_config;
 274
 275 static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc)
 276 {
 277         return container_of(crtc, struct vop2_video_port, crtc);
 278 }
 279
 280 static struct vop2_win *to_vop2_win(struct drm_plane *p)
 281 {
 282         return container_of(p, struct vop2_win, base);
 283 }
 284
 285 static void vop2_lock(struct vop2 *vop2)
 286 {
 287         mutex_lock(&vop2->vop2_lock);
 288 }
 289
 290 static void vop2_unlock(struct vop2 *vop2)
 291 {
 292         mutex_unlock(&vop2->vop2_lock);
 293 }
 294
 295 static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)
 296 {
 297         regmap_write(vop2->map, offset, v);
 298 }
 299
 300 static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v)
 301 {
 302         regmap_write(vp->vop2->map, vp->data->offset + offset, v);
 303 }
 304
 305 static u32 vop2_readl(struct vop2 *vop2, u32 offset)
 306 {
 307         u32 val;
 308
 309         regmap_read(vop2->map, offset, &val);
 310
 311         return val;
 312 }
 313
 314 static u32 vop2_vp_read(struct vop2_video_port *vp, u32 offset)
 315 {
 316         u32 val;
 317
 318         regmap_read(vp->vop2->map, vp->data->offset + offset, &val);
 319
 320         return val;
 321 }
 322
 323 static void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v)
 324 {
 325         regmap_field_write(win->reg[reg], v);
 326 }
 327
 328 static bool vop2_cluster_window(const struct vop2_win *win)
 329 {
 330         return win->data->feature & WIN_FEATURE_CLUSTER;
 331 }
 332
 333 /*
 334  * Note:
 335  * The write mask function is documented but missing on rk3566/8, writes
 336  * to these bits have no effect. For newer soc(rk3588 and following) the
 337  * write mask is needed for register writes.
 338  *
 339  * GLB_CFG_DONE_EN has no write mask bit.
 340  *
 341  */
 342 static void vop2_cfg_done(struct vop2_video_port *vp)
 343 {
 344         struct vop2 *vop2 = vp->vop2;
 345         u32 val = RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN;
 346
 347         val |= BIT(vp->id) | (BIT(vp->id) << 16);
 348
 349         regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, val);
 350 }
 351
 352 static void vop2_win_disable(struct vop2_win *win)
 353 {
 354         vop2_win_write(win, VOP2_WIN_ENABLE, 0);
 355
 356         if (vop2_cluster_window(win))
 357                 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0);
 358 }
 359
 360 static u32 vop2_get_bpp(const struct drm_format_info *format)
 361 {
 362         switch (format->format) {
 363         case DRM_FORMAT_YUV420_8BIT:
 364                 return 12;
 365         case DRM_FORMAT_YUV420_10BIT:
 366                 return 15;
 367         case DRM_FORMAT_VUY101010:
 368                 return 30;
 369         default:
 370                 return drm_format_info_bpp(format, 0);
 371         }
 372 }
 373
 374 static enum vop2_data_format vop2_convert_format(u32 format)
 375 {
 376         switch (format) {
 377         case DRM_FORMAT_XRGB2101010:
 378         case DRM_FORMAT_ARGB2101010:
 379         case DRM_FORMAT_XBGR2101010:
 380         case DRM_FORMAT_ABGR2101010:
 381                 return VOP2_FMT_XRGB101010;
 382         case DRM_FORMAT_XRGB8888:
 383         case DRM_FORMAT_ARGB8888:
 384         case DRM_FORMAT_XBGR8888:
 385         case DRM_FORMAT_ABGR8888:
 386                 return VOP2_FMT_ARGB8888;
 387         case DRM_FORMAT_RGB888:
 388         case DRM_FORMAT_BGR888:
 389                 return VOP2_FMT_RGB888;
 390         case DRM_FORMAT_RGB565:
 391         case DRM_FORMAT_BGR565:
 392                 return VOP2_FMT_RGB565;
 393         case DRM_FORMAT_NV12:
 394         case DRM_FORMAT_NV21:
 395         case DRM_FORMAT_YUV420_8BIT:
 396                 return VOP2_FMT_YUV420SP;
 397         case DRM_FORMAT_NV15:
 398         case DRM_FORMAT_YUV420_10BIT:
 399                 return VOP2_FMT_YUV420SP_10;
 400         case DRM_FORMAT_NV16:
 401         case DRM_FORMAT_NV61:
 402                 return VOP2_FMT_YUV422SP;
 403         case DRM_FORMAT_NV20:
 404         case DRM_FORMAT_Y210:
 405                 return VOP2_FMT_YUV422SP_10;
 406         case DRM_FORMAT_NV24:
 407         case DRM_FORMAT_NV42:
 408                 return VOP2_FMT_YUV444SP;
 409         case DRM_FORMAT_NV30:
 410                 return VOP2_FMT_YUV444SP_10;
 411         case DRM_FORMAT_YUYV:
 412         case DRM_FORMAT_YVYU:
 413                 return VOP2_FMT_VYUY422;
 414         case DRM_FORMAT_VYUY:
 415         case DRM_FORMAT_UYVY:
 416                 return VOP2_FMT_YUYV422;
 417         default:
 418                 DRM_ERROR("unsupported format[%08x]\n", format);
 419                 return -EINVAL;
 420         }
 421 }
 422
 423 static enum vop2_afbc_format vop2_convert_afbc_format(u32 format)
 424 {
 425         switch (format) {
 426         case DRM_FORMAT_XRGB2101010:
 427         case DRM_FORMAT_ARGB2101010:
 428         case DRM_FORMAT_XBGR2101010:
 429         case DRM_FORMAT_ABGR2101010:
 430                 return VOP2_AFBC_FMT_ARGB2101010;
 431         case DRM_FORMAT_XRGB8888:
 432         case DRM_FORMAT_ARGB8888:
 433         case DRM_FORMAT_XBGR8888:
 434         case DRM_FORMAT_ABGR8888:
 435                 return VOP2_AFBC_FMT_ARGB8888;
 436         case DRM_FORMAT_RGB888:
 437         case DRM_FORMAT_BGR888:
 438                 return VOP2_AFBC_FMT_RGB888;
 439         case DRM_FORMAT_RGB565:
 440         case DRM_FORMAT_BGR565:
 441                 return VOP2_AFBC_FMT_RGB565;
 442         case DRM_FORMAT_YUV420_8BIT:
 443                 return VOP2_AFBC_FMT_YUV420;
 444         case DRM_FORMAT_YUV420_10BIT:
 445                 return VOP2_AFBC_FMT_YUV420_10BIT;
 446         case DRM_FORMAT_YVYU:
 447         case DRM_FORMAT_YUYV:
 448         case DRM_FORMAT_VYUY:
 449         case DRM_FORMAT_UYVY:
 450                 return VOP2_AFBC_FMT_YUV422;
 451         case DRM_FORMAT_Y210:
 452                 return VOP2_AFBC_FMT_YUV422_10BIT;
 453         default:
 454                 return VOP2_AFBC_FMT_INVALID;
 455         }
 456
 457         return VOP2_AFBC_FMT_INVALID;
 458 }
 459
 460 static bool vop2_win_rb_swap(u32 format)
 461 {
 462         switch (format) {
 463         case DRM_FORMAT_XBGR2101010:
 464         case DRM_FORMAT_ABGR2101010:
 465         case DRM_FORMAT_XBGR8888:
 466         case DRM_FORMAT_ABGR8888:
 467         case DRM_FORMAT_BGR888:
 468         case DRM_FORMAT_BGR565:
 469                 return true;
 470         default:
 471                 return false;
 472         }
 473 }
 474
 475 static bool vop2_afbc_uv_swap(u32 format)
 476 {
 477         switch (format) {
 478         case DRM_FORMAT_YUYV:
 479         case DRM_FORMAT_Y210:
 480         case DRM_FORMAT_YUV420_8BIT:
 481         case DRM_FORMAT_YUV420_10BIT:
 482                 return true;
 483         default:
 484                 return false;
 485         }
 486 }
 487
 488 static bool vop2_win_uv_swap(u32 format)
 489 {
 490         switch (format) {
 491         case DRM_FORMAT_NV12:
 492         case DRM_FORMAT_NV16:
 493         case DRM_FORMAT_NV24:
 494         case DRM_FORMAT_NV15:
 495         case DRM_FORMAT_NV20:
 496         case DRM_FORMAT_NV30:
 497         case DRM_FORMAT_YUYV:
 498         case DRM_FORMAT_UYVY:
 499                 return true;
 500         default:
 501                 return false;
 502         }
 503 }
 504
 505 static bool vop2_win_dither_up(u32 format)
 506 {
 507         switch (format) {
 508         case DRM_FORMAT_BGR565:
 509         case DRM_FORMAT_RGB565:
 510                 return true;
 511         default:
 512                 return false;
 513         }
 514 }
 515
 516 static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode)
 517 {
 518         /*
 519          * FIXME:
 520          *
 521          * There is no media type for YUV444 output,
 522          * so when out_mode is AAAA or P888, assume output is YUV444 on
 523          * yuv format.
 524          *
 525          * From H/W testing, YUV444 mode need a rb swap.
 526          */
 527         if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 ||
 528             bus_format == MEDIA_BUS_FMT_VYUY8_1X16 ||
 529             bus_format == MEDIA_BUS_FMT_YVYU8_2X8 ||
 530             bus_format == MEDIA_BUS_FMT_VYUY8_2X8 ||
 531             ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
 532               bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
 533              (output_mode == ROCKCHIP_OUT_MODE_AAAA ||
 534               output_mode == ROCKCHIP_OUT_MODE_P888)))
 535                 return true;
 536         else
 537                 return false;
 538 }
 539
 540 static bool vop2_output_rg_swap(struct vop2 *vop2, u32 bus_format)
 541 {
 542         if (vop2->data->soc_id == 3588) {
 543                 if (bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
 544                     bus_format == MEDIA_BUS_FMT_YUV10_1X30)
 545                         return true;
 546         }
 547
 548         return false;
 549 }
 550
 551 static bool is_yuv_output(u32 bus_format)
 552 {
 553         switch (bus_format) {
 554         case MEDIA_BUS_FMT_YUV8_1X24:
 555         case MEDIA_BUS_FMT_YUV10_1X30:
 556         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 557         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 558         case MEDIA_BUS_FMT_YUYV8_2X8:
 559         case MEDIA_BUS_FMT_YVYU8_2X8:
 560         case MEDIA_BUS_FMT_UYVY8_2X8:
 561         case MEDIA_BUS_FMT_VYUY8_2X8:
 562         case MEDIA_BUS_FMT_YUYV8_1X16:
 563         case MEDIA_BUS_FMT_YVYU8_1X16:
 564         case MEDIA_BUS_FMT_UYVY8_1X16:
 565         case MEDIA_BUS_FMT_VYUY8_1X16:
 566                 return true;
 567         default:
 568                 return false;
 569         }
 570 }
 571
 572 static bool rockchip_afbc(struct drm_plane *plane, u64 modifier)
 573 {
 574         int i;
 575
 576         if (modifier == DRM_FORMAT_MOD_LINEAR)
 577                 return false;
 578
 579         for (i = 0 ; i < plane->modifier_count; i++)
 580                 if (plane->modifiers[i] == modifier)
 581                         return true;
 582
 583         return false;
 584 }
 585
 586 static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format,
 587                                         u64 modifier)
 588 {
 589         struct vop2_win *win = to_vop2_win(plane);
 590         struct vop2 *vop2 = win->vop2;
 591
 592         if (modifier == DRM_FORMAT_MOD_INVALID)
 593                 return false;
 594
 595         if (vop2->data->soc_id == 3568 || vop2->data->soc_id == 3566) {
 596                 if (vop2_cluster_window(win)) {
 597                         if (modifier == DRM_FORMAT_MOD_LINEAR) {
 598                                 drm_dbg_kms(vop2->drm,
 599                                             "Cluster window only supports format with afbc\n");
 600                                 return false;
 601                         }
 602                 }
 603         }
 604
 605         if (format == DRM_FORMAT_XRGB2101010 || format == DRM_FORMAT_XBGR2101010) {
 606                 if (vop2->data->soc_id == 3588) {
 607                         if (!rockchip_afbc(plane, modifier)) {
 608                                 drm_dbg_kms(vop2->drm, "Only support 32 bpp format with afbc\n");
 609                                 return false;
 610                         }
 611                 }
 612         }
 613
 614         if (modifier == DRM_FORMAT_MOD_LINEAR)
 615                 return true;
 616
 617         if (!rockchip_afbc(plane, modifier)) {
 618                 drm_dbg_kms(vop2->drm, "Unsupported format modifier 0x%llx\n",
 619                             modifier);
 620
 621                 return false;
 622         }
 623
 624         return vop2_convert_afbc_format(format) >= 0;
 625 }
 626
 627 /*
 628  * 0: Full mode, 16 lines for one tail
 629  * 1: half block mode, 8 lines one tail
 630  */
 631 static bool vop2_half_block_enable(struct drm_plane_state *pstate)
 632 {
 633         if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90))
 634                 return false;
 635         else
 636                 return true;
 637 }
 638
 639 static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate,
 640                                       bool afbc_half_block_en)
 641 {
 642         struct drm_rect *src = &pstate->src;
 643         struct drm_framebuffer *fb = pstate->fb;
 644         u32 bpp = vop2_get_bpp(fb->format);
 645         u32 vir_width = (fb->pitches[0] << 3) / bpp;
 646         u32 width = drm_rect_width(src) >> 16;
 647         u32 height = drm_rect_height(src) >> 16;
 648         u32 act_xoffset = src->x1 >> 16;
 649         u32 act_yoffset = src->y1 >> 16;
 650         u32 align16_crop = 0;
 651         u32 align64_crop = 0;
 652         u32 height_tmp;
 653         u8 tx, ty;
 654         u8 bottom_crop_line_num = 0;
 655
 656         /* 16 pixel align */
 657         if (height & 0xf)
 658                 align16_crop = 16 - (height & 0xf);
 659
 660         height_tmp = height + align16_crop;
 661
 662         /* 64 pixel align */
 663         if (height_tmp & 0x3f)
 664                 align64_crop = 64 - (height_tmp & 0x3f);
 665
 666         bottom_crop_line_num = align16_crop + align64_crop;
 667
 668         switch (pstate->rotation &
 669                 (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y |
 670                  DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) {
 671         case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y:
 672                 tx = 16 - ((act_xoffset + width) & 0xf);
 673                 ty = bottom_crop_line_num - act_yoffset;
 674                 break;
 675         case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90:
 676                 tx = bottom_crop_line_num - act_yoffset;
 677                 ty = vir_width - width - act_xoffset;
 678                 break;
 679         case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270:
 680                 tx = act_yoffset;
 681                 ty = act_xoffset;
 682                 break;
 683         case DRM_MODE_REFLECT_X:
 684                 tx = 16 - ((act_xoffset + width) & 0xf);
 685                 ty = act_yoffset;
 686                 break;
 687         case DRM_MODE_REFLECT_Y:
 688                 tx = act_xoffset;
 689                 ty = bottom_crop_line_num - act_yoffset;
 690                 break;
 691         case DRM_MODE_ROTATE_90:
 692                 tx = bottom_crop_line_num - act_yoffset;
 693                 ty = act_xoffset;
 694                 break;
 695         case DRM_MODE_ROTATE_270:
 696                 tx = act_yoffset;
 697                 ty = vir_width - width - act_xoffset;
 698                 break;
 699         case 0:
 700                 tx = act_xoffset;
 701                 ty = act_yoffset;
 702                 break;
 703         }
 704
 705         if (afbc_half_block_en)
 706                 ty &= 0x7f;
 707
 708 #define TRANSFORM_XOFFSET GENMASK(7, 0)
 709 #define TRANSFORM_YOFFSET GENMASK(23, 16)
 710         return FIELD_PREP(TRANSFORM_XOFFSET, tx) |
 711                 FIELD_PREP(TRANSFORM_YOFFSET, ty);
 712 }
 713
 714 /*
 715  * A Cluster window has 2048 x 16 line buffer, which can
 716  * works at 2048 x 16(Full) or 4096 x 8 (Half) mode.
 717  * for Cluster_lb_mode register:
 718  * 0: half mode, for plane input width range 2048 ~ 4096
 719  * 1: half mode, for cluster work at 2 * 2048 plane mode
 720  * 2: half mode, for rotate_90/270 mode
 721  *
 722  */
 723 static int vop2_get_cluster_lb_mode(struct vop2_win *win,
 724                                     struct drm_plane_state *pstate)
 725 {
 726         if ((pstate->rotation & DRM_MODE_ROTATE_270) ||
 727             (pstate->rotation & DRM_MODE_ROTATE_90))
 728                 return 2;
 729         else
 730                 return 0;
 731 }
 732
 733 static u16 vop2_scale_factor(u32 src, u32 dst)
 734 {
 735         u32 fac;
 736         int shift;
 737
 738         if (src == dst)
 739                 return 0;
 740
 741         if (dst < 2)
 742                 return U16_MAX;
 743
 744         if (src < 2)
 745                 return 0;
 746
 747         if (src > dst)
 748                 shift = 12;
 749         else
 750                 shift = 16;
 751
 752         src--;
 753         dst--;
 754
 755         fac = DIV_ROUND_UP(src << shift, dst) - 1;
 756
 757         if (fac > U16_MAX)
 758                 return U16_MAX;
 759
 760         return fac;
 761 }
 762
 763 static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
 764                              u32 src_w, u32 src_h, u32 dst_w,
 765                              u32 dst_h, u32 pixel_format)
 766 {
 767         const struct drm_format_info *info;
 768         u16 hor_scl_mode, ver_scl_mode;
 769         u16 hscl_filter_mode, vscl_filter_mode;
 770         uint16_t cbcr_src_w = src_w;
 771         uint16_t cbcr_src_h = src_h;
 772         u8 gt2 = 0;
 773         u8 gt4 = 0;
 774         u32 val;
 775
 776         info = drm_format_info(pixel_format);
 777
 778         if (src_h >= (4 * dst_h)) {
 779                 gt4 = 1;
 780                 src_h >>= 2;
 781         } else if (src_h >= (2 * dst_h)) {
 782                 gt2 = 1;
 783                 src_h >>= 1;
 784         }
 785
 786         hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 787         ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 788
 789         if (hor_scl_mode == SCALE_UP)
 790                 hscl_filter_mode = VOP2_SCALE_UP_BIC;
 791         else
 792                 hscl_filter_mode = VOP2_SCALE_DOWN_BIL;
 793
 794         if (ver_scl_mode == SCALE_UP)
 795                 vscl_filter_mode = VOP2_SCALE_UP_BIL;
 796         else
 797                 vscl_filter_mode = VOP2_SCALE_DOWN_BIL;
 798
 799         /*
 800          * RK3568 VOP Esmart/Smart dsp_w should be even pixel
 801          * at scale down mode
 802          */
 803         if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
 804                 if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) {
 805                         drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n",
 806                                 win->data->name, dst_w);
 807                         dst_w++;
 808                 }
 809         }
 810
 811         val = vop2_scale_factor(src_w, dst_w);
 812         vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val);
 813         val = vop2_scale_factor(src_h, dst_h);
 814         vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val);
 815
 816         vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4);
 817         vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2);
 818
 819         vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode);
 820         vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode);
 821
 822         if (vop2_cluster_window(win))
 823                 return;
 824
 825         vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode);
 826         vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode);
 827
 828         if (info->is_yuv) {
 829                 cbcr_src_w /= info->hsub;
 830                 cbcr_src_h /= info->vsub;
 831
 832                 gt4 = 0;
 833                 gt2 = 0;
 834
 835                 if (cbcr_src_h >= (4 * dst_h)) {
 836                         gt4 = 1;
 837                         cbcr_src_h >>= 2;
 838                 } else if (cbcr_src_h >= (2 * dst_h)) {
 839                         gt2 = 1;
 840                         cbcr_src_h >>= 1;
 841                 }
 842
 843                 hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 844                 ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 845
 846                 val = vop2_scale_factor(cbcr_src_w, dst_w);
 847                 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val);
 848
 849                 val = vop2_scale_factor(cbcr_src_h, dst_h);
 850                 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val);
 851
 852                 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4);
 853                 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2);
 854                 vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode);
 855                 vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode);
 856                 vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode);
 857                 vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode);
 858         }
 859 }
 860
 861 static int vop2_convert_csc_mode(int csc_mode)
 862 {
 863         switch (csc_mode) {
 864         case V4L2_COLORSPACE_SMPTE170M:
 865         case V4L2_COLORSPACE_470_SYSTEM_M:
 866         case V4L2_COLORSPACE_470_SYSTEM_BG:
 867                 return CSC_BT601L;
 868         case V4L2_COLORSPACE_REC709:
 869         case V4L2_COLORSPACE_SMPTE240M:
 870         case V4L2_COLORSPACE_DEFAULT:
 871                 return CSC_BT709L;
 872         case V4L2_COLORSPACE_JPEG:
 873                 return CSC_BT601F;
 874         case V4L2_COLORSPACE_BT2020:
 875                 return CSC_BT2020;
 876         default:
 877                 return CSC_BT709L;
 878         }
 879 }
 880
 881 /*
 882  * colorspace path:
 883  *      Input        Win csc                     Output
 884  * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
 885  *    RGB        --> R2Y                  __/
 886  *
 887  * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
 888  *    RGB        --> 709To2020->R2Y       __/
 889  *
 890  * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
 891  *    RGB        --> R2Y                  __/
 892  *
 893  * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
 894  *    RGB        --> 709To2020->R2Y       __/
 895  *
 896  * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
 897  *    RGB        --> R2Y                  __/
 898  *
 899  * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
 900  *    RGB        --> R2Y(601)             __/
 901  *
 902  * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
 903  *    RGB        --> bypass               __/
 904  *
 905  * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
 906  *
 907  * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
 908  *
 909  * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
 910  *
 911  * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
 912  */
 913
 914 static void vop2_setup_csc_mode(struct vop2_video_port *vp,
 915                                 struct vop2_win *win,
 916                                 struct drm_plane_state *pstate)
 917 {
 918         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
 919         int is_input_yuv = pstate->fb->format->is_yuv;
 920         int is_output_yuv = is_yuv_output(vcstate->bus_format);
 921         int input_csc = V4L2_COLORSPACE_DEFAULT;
 922         int output_csc = vcstate->color_space;
 923         bool r2y_en, y2r_en;
 924         int csc_mode;
 925
 926         if (is_input_yuv && !is_output_yuv) {
 927                 y2r_en = true;
 928                 r2y_en = false;
 929                 csc_mode = vop2_convert_csc_mode(input_csc);
 930         } else if (!is_input_yuv && is_output_yuv) {
 931                 y2r_en = false;
 932                 r2y_en = true;
 933                 csc_mode = vop2_convert_csc_mode(output_csc);
 934         } else {
 935                 y2r_en = false;
 936                 r2y_en = false;
 937                 csc_mode = false;
 938         }
 939
 940         vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en);
 941         vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en);
 942         vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode);
 943 }
 944
 945 static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq)
 946 {
 947         struct vop2 *vop2 = vp->vop2;
 948
 949         vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq);
 950         vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq);
 951 }
 952
 953 static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq)
 954 {
 955         struct vop2 *vop2 = vp->vop2;
 956
 957         vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16);
 958 }
 959
 960 static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
 961 {
 962         int ret;
 963
 964         ret = clk_prepare_enable(vop2->hclk);
 965         if (ret < 0) {
 966                 drm_err(vop2->drm, "failed to enable hclk - %d\n", ret);
 967                 return ret;
 968         }
 969
 970         ret = clk_prepare_enable(vop2->aclk);
 971         if (ret < 0) {
 972                 drm_err(vop2->drm, "failed to enable aclk - %d\n", ret);
 973                 goto err;
 974         }
 975
 976         ret = clk_prepare_enable(vop2->pclk);
 977         if (ret < 0) {
 978                 drm_err(vop2->drm, "failed to enable pclk - %d\n", ret);
 979                 goto err1;
 980         }
 981
 982         return 0;
 983 err1:
 984         clk_disable_unprepare(vop2->aclk);
 985 err:
 986         clk_disable_unprepare(vop2->hclk);
 987
 988         return ret;
 989 }
 990
 991 static void rk3588_vop2_power_domain_enable_all(struct vop2 *vop2)
 992 {
 993         u32 pd;
 994
 995         pd = vop2_readl(vop2, RK3588_SYS_PD_CTRL);
 996         pd &= ~(VOP2_PD_CLUSTER0 | VOP2_PD_CLUSTER1 | VOP2_PD_CLUSTER2 |
 997                 VOP2_PD_CLUSTER3 | VOP2_PD_ESMART);
 998
 999         vop2_writel(vop2, RK3588_SYS_PD_CTRL, pd);
1000 }
1001
1002 static void vop2_enable(struct vop2 *vop2)
1003 {
1004         int ret;
1005
1006         ret = pm_runtime_resume_and_get(vop2->dev);
1007         if (ret < 0) {
1008                 drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret);
1009                 return;
1010         }
1011
1012         ret = vop2_core_clks_prepare_enable(vop2);
1013         if (ret) {
1014                 pm_runtime_put_sync(vop2->dev);
1015                 return;
1016         }
1017
1018         ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev);
1019         if (ret) {
1020                 drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret);
1021                 return;
1022         }
1023
1024         if (vop2->data->soc_id == 3566)
1025                 vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);
1026
1027         if (vop2->data->soc_id == 3588)
1028                 rk3588_vop2_power_domain_enable_all(vop2);
1029
1030         vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
1031
1032         /*
1033          * Disable auto gating, this is a workaround to
1034          * avoid display image shift when a window enabled.
1035          */
1036         regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL,
1037                           RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN);
1038
1039         vop2_writel(vop2, RK3568_SYS0_INT_CLR,
1040                     VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
1041         vop2_writel(vop2, RK3568_SYS0_INT_EN,
1042                     VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
1043         vop2_writel(vop2, RK3568_SYS1_INT_CLR,
1044                     VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
1045         vop2_writel(vop2, RK3568_SYS1_INT_EN,
1046                     VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
1047 }
1048
1049 static void vop2_disable(struct vop2 *vop2)
1050 {
1051         rockchip_drm_dma_detach_device(vop2->drm, vop2->dev);
1052
1053         pm_runtime_put_sync(vop2->dev);
1054
1055         regcache_drop_region(vop2->map, 0, vop2_regmap_config.max_register);
1056
1057         clk_disable_unprepare(vop2->pclk);
1058         clk_disable_unprepare(vop2->aclk);
1059         clk_disable_unprepare(vop2->hclk);
1060 }
1061
1062 static bool vop2_vp_dsp_lut_is_enabled(struct vop2_video_port *vp)
1063 {
1064         u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL);
1065
1066         return dsp_ctrl & RK3568_VP_DSP_CTRL__DSP_LUT_EN;
1067 }
1068
1069 static void vop2_vp_dsp_lut_disable(struct vop2_video_port *vp)
1070 {
1071         u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL);
1072
1073         dsp_ctrl &= ~RK3568_VP_DSP_CTRL__DSP_LUT_EN;
1074         vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
1075 }
1076
1077 static bool vop2_vp_dsp_lut_poll_disabled(struct vop2_video_port *vp)
1078 {
1079         u32 dsp_ctrl;
1080         int ret = readx_poll_timeout(vop2_vp_dsp_lut_is_enabled, vp, dsp_ctrl,
1081                                 !dsp_ctrl, 5, 30 * 1000);
1082         if (ret) {
1083                 drm_err(vp->vop2->drm, "display LUT RAM enable timeout!\n");
1084                 return false;
1085         }
1086
1087         return true;
1088 }
1089
1090 static void vop2_vp_dsp_lut_enable(struct vop2_video_port *vp)
1091 {
1092         u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL);
1093
1094         dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_LUT_EN;
1095         vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
1096 }
1097
1098 static void vop2_vp_dsp_lut_update_enable(struct vop2_video_port *vp)
1099 {
1100         u32 dsp_ctrl = vop2_vp_read(vp, RK3568_VP_DSP_CTRL);
1101
1102         dsp_ctrl |= RK3588_VP_DSP_CTRL__GAMMA_UPDATE_EN;
1103         vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
1104 }
1105
1106 static inline bool vop2_supports_seamless_gamma_lut_update(struct vop2 *vop2)
1107 {
1108         return (vop2->data->soc_id != 3566 && vop2->data->soc_id != 3568);
1109 }
1110
1111 static bool vop2_gamma_lut_in_use(struct vop2 *vop2, struct vop2_video_port *vp)
1112 {
1113         const int nr_vps = vop2->data->nr_vps;
1114         int gamma_en_vp_id;
1115
1116         for (gamma_en_vp_id = 0; gamma_en_vp_id < nr_vps; gamma_en_vp_id++)
1117                 if (vop2_vp_dsp_lut_is_enabled(&vop2->vps[gamma_en_vp_id]))
1118                         break;
1119
1120         return gamma_en_vp_id != nr_vps && gamma_en_vp_id != vp->id;
1121 }
1122
1123 static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
1124                                      struct drm_atomic_state *state)
1125 {
1126         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1127         struct vop2 *vop2 = vp->vop2;
1128         struct drm_crtc_state *old_crtc_state;
1129         int ret;
1130
1131         vop2_lock(vop2);
1132
1133         old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
1134         drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
1135
1136         drm_crtc_vblank_off(crtc);
1137
1138         /*
1139          * Vop standby will take effect at end of current frame,
1140          * if dsp hold valid irq happen, it means standby complete.
1141          *
1142          * we must wait standby complete when we want to disable aclk,
1143          * if not, memory bus maybe dead.
1144          */
1145         reinit_completion(&vp->dsp_hold_completion);
1146
1147         vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID);
1148
1149         vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY);
1150
1151         ret = wait_for_completion_timeout(&vp->dsp_hold_completion,
1152                                           msecs_to_jiffies(50));
1153         if (!ret)
1154                 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id);
1155
1156         vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID);
1157
1158         clk_disable_unprepare(vp->dclk);
1159
1160         vop2->enable_count--;
1161
1162         if (!vop2->enable_count)
1163                 vop2_disable(vop2);
1164
1165         vop2_unlock(vop2);
1166
1167         if (crtc->state->event && !crtc->state->active) {
1168                 spin_lock_irq(&crtc->dev->event_lock);
1169                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1170                 spin_unlock_irq(&crtc->dev->event_lock);
1171
1172                 crtc->state->event = NULL;
1173         }
1174 }
1175
1176 static int vop2_plane_atomic_check(struct drm_plane *plane,
1177                                    struct drm_atomic_state *astate)
1178 {
1179         struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane);
1180         struct drm_framebuffer *fb = pstate->fb;
1181         struct drm_crtc *crtc = pstate->crtc;
1182         struct drm_crtc_state *cstate;
1183         struct vop2_video_port *vp;
1184         struct vop2 *vop2;
1185         const struct vop2_data *vop2_data;
1186         struct drm_rect *dest = &pstate->dst;
1187         struct drm_rect *src = &pstate->src;
1188         int min_scale = FRAC_16_16(1, 8);
1189         int max_scale = FRAC_16_16(8, 1);
1190         int format;
1191         int ret;
1192
1193         if (!crtc)
1194                 return 0;
1195
1196         vp = to_vop2_video_port(crtc);
1197         vop2 = vp->vop2;
1198         vop2_data = vop2->data;
1199
1200         cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc);
1201         if (WARN_ON(!cstate))
1202                 return -EINVAL;
1203
1204         ret = drm_atomic_helper_check_plane_state(pstate, cstate,
1205                                                   min_scale, max_scale,
1206                                                   true, true);
1207         if (ret)
1208                 return ret;
1209
1210         if (!pstate->visible)
1211                 return 0;
1212
1213         format = vop2_convert_format(fb->format->format);
1214         if (format < 0)
1215                 return format;
1216
1217         if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 ||
1218             drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) {
1219                 drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n",
1220                         drm_rect_width(src) >> 16, drm_rect_height(src) >> 16,
1221                         drm_rect_width(dest), drm_rect_height(dest));
1222                 pstate->visible = false;
1223                 return 0;
1224         }
1225
1226         if (drm_rect_width(src) >> 16 > vop2_data->max_input.width ||
1227             drm_rect_height(src) >> 16 > vop2_data->max_input.height) {
1228                 drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n",
1229                         drm_rect_width(src) >> 16,
1230                         drm_rect_height(src) >> 16,
1231                         vop2_data->max_input.width,
1232                         vop2_data->max_input.height);
1233                 return -EINVAL;
1234         }
1235
1236         /*
1237          * Src.x1 can be odd when do clip, but yuv plane start point
1238          * need align with 2 pixel.
1239          */
1240         if (fb->format->is_yuv && ((pstate->src.x1 >> 16) % 2)) {
1241                 drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n");
1242                 return -EINVAL;
1243         }
1244
1245         return 0;
1246 }
1247
1248 static void vop2_plane_atomic_disable(struct drm_plane *plane,
1249                                       struct drm_atomic_state *state)
1250 {
1251         struct drm_plane_state *old_pstate = NULL;
1252         struct vop2_win *win = to_vop2_win(plane);
1253         struct vop2 *vop2 = win->vop2;
1254
1255         drm_dbg(vop2->drm, "%s disable\n", win->data->name);
1256
1257         if (state)
1258                 old_pstate = drm_atomic_get_old_plane_state(state, plane);
1259         if (old_pstate && !old_pstate->crtc)
1260                 return;
1261
1262         vop2_win_disable(win);
1263         vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0);
1264 }
1265
1266 /*
1267  * The color key is 10 bit, so all format should
1268  * convert to 10 bit here.
1269  */
1270 static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key)
1271 {
1272         struct drm_plane_state *pstate = plane->state;
1273         struct drm_framebuffer *fb = pstate->fb;
1274         struct vop2_win *win = to_vop2_win(plane);
1275         u32 color_key_en = 0;
1276         u32 r = 0;
1277         u32 g = 0;
1278         u32 b = 0;
1279
1280         if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) {
1281                 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0);
1282                 return;
1283         }
1284
1285         switch (fb->format->format) {
1286         case DRM_FORMAT_RGB565:
1287         case DRM_FORMAT_BGR565:
1288                 r = (color_key & 0xf800) >> 11;
1289                 g = (color_key & 0x7e0) >> 5;
1290                 b = (color_key & 0x1f);
1291                 r <<= 5;
1292                 g <<= 4;
1293                 b <<= 5;
1294                 color_key_en = 1;
1295                 break;
1296         case DRM_FORMAT_XRGB8888:
1297         case DRM_FORMAT_ARGB8888:
1298         case DRM_FORMAT_XBGR8888:
1299         case DRM_FORMAT_ABGR8888:
1300         case DRM_FORMAT_RGB888:
1301         case DRM_FORMAT_BGR888:
1302                 r = (color_key & 0xff0000) >> 16;
1303                 g = (color_key & 0xff00) >> 8;
1304                 b = (color_key & 0xff);
1305                 r <<= 2;
1306                 g <<= 2;
1307                 b <<= 2;
1308                 color_key_en = 1;
1309                 break;
1310         }
1311
1312         vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, color_key_en);
1313         vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b);
1314 }
1315
1316 static void vop2_plane_atomic_update(struct drm_plane *plane,
1317                                      struct drm_atomic_state *state)
1318 {
1319         struct drm_plane_state *pstate = plane->state;
1320         struct drm_crtc *crtc = pstate->crtc;
1321         struct vop2_win *win = to_vop2_win(plane);
1322         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1323         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1324         struct vop2 *vop2 = win->vop2;
1325         struct drm_framebuffer *fb = pstate->fb;
1326         u32 bpp = vop2_get_bpp(fb->format);
1327         u32 actual_w, actual_h, dsp_w, dsp_h;
1328         u32 act_info, dsp_info;
1329         u32 format;
1330         u32 afbc_format;
1331         u32 rb_swap;
1332         u32 uv_swap;
1333         struct drm_rect *src = &pstate->src;
1334         struct drm_rect *dest = &pstate->dst;
1335         u32 afbc_tile_num;
1336         u32 transform_offset;
1337         bool dither_up;
1338         bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false;
1339         bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false;
1340         bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270;
1341         bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90;
1342         struct rockchip_gem_object *rk_obj;
1343         unsigned long offset;
1344         bool half_block_en;
1345         bool afbc_en;
1346         dma_addr_t yrgb_mst;
1347         dma_addr_t uv_mst;
1348
1349         /*
1350          * can't update plane when vop2 is disabled.
1351          */
1352         if (WARN_ON(!crtc))
1353                 return;
1354
1355         if (!pstate->visible) {
1356                 vop2_plane_atomic_disable(plane, state);
1357                 return;
1358         }
1359
1360         afbc_en = rockchip_afbc(plane, fb->modifier);
1361
1362         offset = (src->x1 >> 16) * fb->format->cpp[0];
1363
1364         /*
1365          * AFBC HDR_PTR must set to the zero offset of the framebuffer.
1366          */
1367         if (afbc_en)
1368                 offset = 0;
1369         else if (pstate->rotation & DRM_MODE_REFLECT_Y)
1370                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1371         else
1372                 offset += (src->y1 >> 16) * fb->pitches[0];
1373
1374         rk_obj = to_rockchip_obj(fb->obj[0]);
1375
1376         yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
1377         if (fb->format->is_yuv) {
1378                 int hsub = fb->format->hsub;
1379                 int vsub = fb->format->vsub;
1380
1381                 offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub;
1382                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1383
1384                 if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en)
1385                         offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub;
1386
1387                 rk_obj = to_rockchip_obj(fb->obj[0]);
1388                 uv_mst = rk_obj->dma_addr + offset + fb->offsets[1];
1389         }
1390
1391         actual_w = drm_rect_width(src) >> 16;
1392         actual_h = drm_rect_height(src) >> 16;
1393         dsp_w = drm_rect_width(dest);
1394
1395         if (dest->x1 + dsp_w > adjusted_mode->hdisplay) {
1396                 drm_dbg_kms(vop2->drm,
1397                             "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
1398                             vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay);
1399                 dsp_w = adjusted_mode->hdisplay - dest->x1;
1400                 if (dsp_w < 4)
1401                         dsp_w = 4;
1402                 actual_w = dsp_w * actual_w / drm_rect_width(dest);
1403         }
1404
1405         dsp_h = drm_rect_height(dest);
1406
1407         if (dest->y1 + dsp_h > adjusted_mode->vdisplay) {
1408                 drm_dbg_kms(vop2->drm,
1409                             "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
1410                             vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay);
1411                 dsp_h = adjusted_mode->vdisplay - dest->y1;
1412                 if (dsp_h < 4)
1413                         dsp_h = 4;
1414                 actual_h = dsp_h * actual_h / drm_rect_height(dest);
1415         }
1416
1417         /*
1418          * This is workaround solution for IC design:
1419          * esmart can't support scale down when actual_w % 16 == 1.
1420          */
1421         if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
1422                 if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
1423                         drm_dbg_kms(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n",
1424                                     vp->id, win->data->name, actual_w);
1425                         actual_w -= 1;
1426                 }
1427         }
1428
1429         if (afbc_en && actual_w % 4) {
1430                 drm_dbg_kms(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n",
1431                             vp->id, win->data->name, actual_w);
1432                 actual_w = ALIGN_DOWN(actual_w, 4);
1433         }
1434
1435         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1436         dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff);
1437
1438         format = vop2_convert_format(fb->format->format);
1439         half_block_en = vop2_half_block_enable(pstate);
1440
1441         drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n",
1442                 vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h,
1443                 dest->x1, dest->y1,
1444                 &fb->format->format,
1445                 afbc_en ? "AFBC" : "", &yrgb_mst);
1446
1447         if (vop2->data->soc_id > 3568) {
1448                 vop2_win_write(win, VOP2_WIN_AXI_BUS_ID, win->data->axi_bus_id);
1449                 vop2_win_write(win, VOP2_WIN_AXI_YRGB_R_ID, win->data->axi_yrgb_r_id);
1450                 vop2_win_write(win, VOP2_WIN_AXI_UV_R_ID, win->data->axi_uv_r_id);
1451         }
1452
1453         if (vop2_cluster_window(win))
1454                 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, half_block_en);
1455
1456         if (afbc_en) {
1457                 u32 stride, block_w;
1458
1459                 /* the afbc superblock is 16 x 16 or 32 x 8 */
1460                 block_w = fb->modifier & AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 ? 32 : 16;
1461
1462                 afbc_format = vop2_convert_afbc_format(fb->format->format);
1463
1464                 /* Enable color transform for YTR */
1465                 if (fb->modifier & AFBC_FORMAT_MOD_YTR)
1466                         afbc_format |= (1 << 4);
1467
1468                 afbc_tile_num = ALIGN(actual_w, block_w) / block_w;
1469
1470                 /*
1471                  * AFBC pic_vir_width is count by pixel, this is different
1472                  * with WIN_VIR_STRIDE.
1473                  */
1474                 stride = (fb->pitches[0] << 3) / bpp;
1475                 if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270))
1476                         drm_dbg_kms(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n",
1477                                     vp->id, win->data->name, stride);
1478
1479                  /* It's for head stride, each head size is 16 byte */
1480                 stride = ALIGN(stride, block_w) / block_w * 16;
1481
1482                 uv_swap = vop2_afbc_uv_swap(fb->format->format);
1483                 /*
1484                  * This is a workaround for crazy IC design, Cluster
1485                  * and Esmart/Smart use different format configuration map:
1486                  * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart.
1487                  *
1488                  * This is one thing we can make the convert simple:
1489                  * AFBCD decode all the YUV data to YUV444. So we just
1490                  * set all the yuv 10 bit to YUV444_10.
1491                  */
1492                 if (fb->format->is_yuv && bpp == 10)
1493                         format = VOP2_CLUSTER_YUV444_10;
1494
1495                 if (vop2_cluster_window(win))
1496                         vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1);
1497                 vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format);
1498                 vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap);
1499                 /*
1500                  * On rk3566/8, this bit is auto gating enable,
1501                  * but this function is not work well so we need
1502                  * to disable it for these two platform.
1503                  * On rk3588, and the following new soc(rk3528/rk3576),
1504                  * this bit is gating disable, we should write 1 to
1505                  * disable gating when enable afbc.
1506                  */
1507                 if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568)
1508                         vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0);
1509                 else
1510                         vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 1);
1511
1512                 if (fb->modifier & AFBC_FORMAT_MOD_SPLIT)
1513                         vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 1);
1514                 else
1515                         vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0);
1516
1517                 transform_offset = vop2_afbc_transform_offset(pstate, half_block_en);
1518                 vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst);
1519                 vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info);
1520                 vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset);
1521                 vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1));
1522                 vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16)));
1523                 vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride);
1524                 vop2_win_write(win, VOP2_WIN_AFBC_TILE_NUM, afbc_tile_num);
1525                 vop2_win_write(win, VOP2_WIN_XMIRROR, xmirror);
1526                 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270);
1527                 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90);
1528         } else {
1529                 if (vop2_cluster_window(win)) {
1530                         vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 0);
1531                         vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, 0);
1532                 }
1533
1534                 vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4));
1535         }
1536
1537         vop2_win_write(win, VOP2_WIN_YMIRROR, ymirror);
1538
1539         if (rotate_90 || rotate_270) {
1540                 act_info = swahw32(act_info);
1541                 actual_w = drm_rect_height(src) >> 16;
1542                 actual_h = drm_rect_width(src) >> 16;
1543         }
1544
1545         vop2_win_write(win, VOP2_WIN_FORMAT, format);
1546         vop2_win_write(win, VOP2_WIN_YRGB_MST, yrgb_mst);
1547
1548         rb_swap = vop2_win_rb_swap(fb->format->format);
1549         vop2_win_write(win, VOP2_WIN_RB_SWAP, rb_swap);
1550         if (!vop2_cluster_window(win)) {
1551                 uv_swap = vop2_win_uv_swap(fb->format->format);
1552                 vop2_win_write(win, VOP2_WIN_UV_SWAP, uv_swap);
1553         }
1554
1555         if (fb->format->is_yuv) {
1556                 vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4));
1557                 vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst);
1558         }
1559
1560         vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format);
1561         if (!vop2_cluster_window(win))
1562                 vop2_plane_setup_color_key(plane, 0);
1563         vop2_win_write(win, VOP2_WIN_ACT_INFO, act_info);
1564         vop2_win_write(win, VOP2_WIN_DSP_INFO, dsp_info);
1565         vop2_win_write(win, VOP2_WIN_DSP_ST, dest->y1 << 16 | (dest->x1 & 0xffff));
1566
1567         vop2_setup_csc_mode(vp, win, pstate);
1568
1569         dither_up = vop2_win_dither_up(fb->format->format);
1570         vop2_win_write(win, VOP2_WIN_DITHER_UP, dither_up);
1571
1572         vop2_win_write(win, VOP2_WIN_ENABLE, 1);
1573
1574         if (vop2_cluster_window(win)) {
1575                 int lb_mode = vop2_get_cluster_lb_mode(win, pstate);
1576
1577                 vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode);
1578                 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1);
1579         }
1580 }
1581
1582 static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = {
1583         .atomic_check = vop2_plane_atomic_check,
1584         .atomic_update = vop2_plane_atomic_update,
1585         .atomic_disable = vop2_plane_atomic_disable,
1586 };
1587
1588 static const struct drm_plane_funcs vop2_plane_funcs = {
1589         .update_plane   = drm_atomic_helper_update_plane,
1590         .disable_plane  = drm_atomic_helper_disable_plane,
1591         .destroy = drm_plane_cleanup,
1592         .reset = drm_atomic_helper_plane_reset,
1593         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1594         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1595         .format_mod_supported = rockchip_vop2_mod_supported,
1596 };
1597
1598 static int vop2_crtc_enable_vblank(struct drm_crtc *crtc)
1599 {
1600         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1601
1602         vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD);
1603
1604         return 0;
1605 }
1606
1607 static void vop2_crtc_disable_vblank(struct drm_crtc *crtc)
1608 {
1609         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1610
1611         vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD);
1612 }
1613
1614 static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
1615                                  const struct drm_display_mode *mode,
1616                                  struct drm_display_mode *adj_mode)
1617 {
1618         drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V |
1619                                         CRTC_STEREO_DOUBLE);
1620
1621         return true;
1622 }
1623
1624 static void vop2_crtc_write_gamma_lut(struct vop2 *vop2, struct drm_crtc *crtc)
1625 {
1626         const struct vop2_video_port *vp = to_vop2_video_port(crtc);
1627         const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
1628         struct drm_color_lut *lut = crtc->state->gamma_lut->data;
1629         unsigned int i, bpc = ilog2(vp_data->gamma_lut_len);
1630         u32 word;
1631
1632         for (i = 0; i < crtc->gamma_size; i++) {
1633                 word = (drm_color_lut_extract(lut[i].blue, bpc) << (2 * bpc)) |
1634                     (drm_color_lut_extract(lut[i].green, bpc) << bpc) |
1635                     drm_color_lut_extract(lut[i].red, bpc);
1636
1637                 writel(word, vop2->lut_regs + i * 4);
1638         }
1639 }
1640
1641 static void vop2_crtc_atomic_set_gamma_seamless(struct vop2 *vop2,
1642                                                 struct vop2_video_port *vp,
1643                                                 struct drm_crtc *crtc)
1644 {
1645         vop2_writel(vop2, RK3568_LUT_PORT_SEL,
1646                     FIELD_PREP(RK3588_LUT_PORT_SEL__GAMMA_AHB_WRITE_SEL, vp->id));
1647         vop2_vp_dsp_lut_enable(vp);
1648         vop2_crtc_write_gamma_lut(vop2, crtc);
1649         vop2_vp_dsp_lut_update_enable(vp);
1650 }
1651
1652 static void vop2_crtc_atomic_set_gamma_rk356x(struct vop2 *vop2,
1653                                               struct vop2_video_port *vp,
1654                                               struct drm_crtc *crtc)
1655 {
1656         vop2_vp_dsp_lut_disable(vp);
1657         vop2_cfg_done(vp);
1658         if (!vop2_vp_dsp_lut_poll_disabled(vp))
1659                 return;
1660
1661         vop2_writel(vop2, RK3568_LUT_PORT_SEL, vp->id);
1662         vop2_crtc_write_gamma_lut(vop2, crtc);
1663         vop2_vp_dsp_lut_enable(vp);
1664 }
1665
1666 static void vop2_crtc_atomic_try_set_gamma(struct vop2 *vop2,
1667                                            struct vop2_video_port *vp,
1668                                            struct drm_crtc *crtc,
1669                                            struct drm_crtc_state *crtc_state)
1670 {
1671         if (!vop2->lut_regs)
1672                 return;
1673
1674         if (!crtc_state->gamma_lut) {
1675                 vop2_vp_dsp_lut_disable(vp);
1676                 return;
1677         }
1678
1679         if (vop2_supports_seamless_gamma_lut_update(vop2))
1680                 vop2_crtc_atomic_set_gamma_seamless(vop2, vp, crtc);
1681         else
1682                 vop2_crtc_atomic_set_gamma_rk356x(vop2, vp, crtc);
1683 }
1684
1685 static inline void vop2_crtc_atomic_try_set_gamma_locked(struct vop2 *vop2,
1686                                                          struct vop2_video_port *vp,
1687                                                          struct drm_crtc *crtc,
1688                                                          struct drm_crtc_state *crtc_state)
1689 {
1690         vop2_lock(vop2);
1691         vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state);
1692         vop2_unlock(vop2);
1693 }
1694
1695 static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl)
1696 {
1697         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1698
1699         switch (vcstate->bus_format) {
1700         case MEDIA_BUS_FMT_RGB565_1X16:
1701                 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN;
1702                 break;
1703         case MEDIA_BUS_FMT_RGB666_1X18:
1704         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1705         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
1706                 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN;
1707                 *dsp_ctrl |= RGB888_TO_RGB666;
1708                 break;
1709         case MEDIA_BUS_FMT_YUV8_1X24:
1710         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1711                 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN;
1712                 break;
1713         default:
1714                 break;
1715         }
1716
1717         if (vcstate->output_mode != ROCKCHIP_OUT_MODE_AAAA)
1718                 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN;
1719
1720         *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL,
1721                                 DITHER_DOWN_ALLEGRO);
1722 }
1723
1724 static void vop2_post_config(struct drm_crtc *crtc)
1725 {
1726         struct vop2_video_port *vp = to_vop2_video_port(crtc);
1727         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1728         u16 vtotal = mode->crtc_vtotal;
1729         u16 hdisplay = mode->crtc_hdisplay;
1730         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1731         u16 vdisplay = mode->crtc_vdisplay;
1732         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1733         u32 left_margin = 100, right_margin = 100;
1734         u32 top_margin = 100, bottom_margin = 100;
1735         u16 hsize = hdisplay * (left_margin + right_margin) / 200;
1736         u16 vsize = vdisplay * (top_margin + bottom_margin) / 200;
1737         u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
1738         u16 hact_end, vact_end;
1739         u32 val;
1740         u32 bg_dly;
1741         u32 pre_scan_dly;
1742
1743         bg_dly = vp->data->pre_scan_max_dly[3];
1744         vop2_writel(vp->vop2, RK3568_VP_BG_MIX_CTRL(vp->id),
1745                     FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly));
1746
1747         pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;
1748         vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly);
1749
1750         vsize = rounddown(vsize, 2);
1751         hsize = rounddown(hsize, 2);
1752         hact_st += hdisplay * (100 - left_margin) / 200;
1753         hact_end = hact_st + hsize;
1754         val = hact_st << 16;
1755         val |= hact_end;
1756         vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val);
1757         vact_st += vdisplay * (100 - top_margin) / 200;
1758         vact_end = vact_st + vsize;
1759         val = vact_st << 16;
1760         val |= vact_end;
1761         vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val);
1762         val = scl_cal_scale2(vdisplay, vsize) << 16;
1763         val |= scl_cal_scale2(hdisplay, hsize);
1764         vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val);
1765
1766         val = 0;
1767         if (hdisplay != hsize)
1768                 val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN;
1769         if (vdisplay != vsize)
1770                 val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN;
1771         vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val);
1772
1773         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1774                 u16 vact_st_f1 = vtotal + vact_st + 1;
1775                 u16 vact_end_f1 = vact_st_f1 + vsize;
1776
1777                 val = vact_st_f1 << 16 | vact_end_f1;
1778                 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val);
1779         }
1780
1781         vop2_vp_write(vp, RK3568_VP_DSP_BG, 0);
1782 }
1783
1784 static unsigned long rk3568_set_intf_mux(struct vop2_video_port *vp, int id, u32 polflags)
1785 {
1786         struct vop2 *vop2 = vp->vop2;
1787         struct drm_crtc *crtc = &vp->crtc;
1788         u32 die, dip;
1789
1790         die = vop2_readl(vop2, RK3568_DSP_IF_EN);
1791         dip = vop2_readl(vop2, RK3568_DSP_IF_POL);
1792
1793         switch (id) {
1794         case ROCKCHIP_VOP2_EP_RGB0:
1795                 die &= ~RK3568_SYS_DSP_INFACE_EN_RGB_MUX;
1796                 die |= RK3568_SYS_DSP_INFACE_EN_RGB |
1797                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id);
1798                 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1799                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1800                 if (polflags & POLFLAG_DCLK_INV)
1801                         regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3));
1802                 else
1803                         regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16));
1804                 break;
1805         case ROCKCHIP_VOP2_EP_HDMI0:
1806                 die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX;
1807                 die |= RK3568_SYS_DSP_INFACE_EN_HDMI |
1808                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id);
1809                 dip &= ~RK3568_DSP_IF_POL__HDMI_PIN_POL;
1810                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags);
1811                 break;
1812         case ROCKCHIP_VOP2_EP_EDP0:
1813                 die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX;
1814                 die |= RK3568_SYS_DSP_INFACE_EN_EDP |
1815                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id);
1816                 dip &= ~RK3568_DSP_IF_POL__EDP_PIN_POL;
1817                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags);
1818                 break;
1819         case ROCKCHIP_VOP2_EP_MIPI0:
1820                 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX;
1821                 die |= RK3568_SYS_DSP_INFACE_EN_MIPI0 |
1822                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id);
1823                 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL;
1824                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags);
1825                 break;
1826         case ROCKCHIP_VOP2_EP_MIPI1:
1827                 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX;
1828                 die |= RK3568_SYS_DSP_INFACE_EN_MIPI1 |
1829                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id);
1830                 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL;
1831                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags);
1832                 break;
1833         case ROCKCHIP_VOP2_EP_LVDS0:
1834                 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX;
1835                 die |= RK3568_SYS_DSP_INFACE_EN_LVDS0 |
1836                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id);
1837                 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1838                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1839                 break;
1840         case ROCKCHIP_VOP2_EP_LVDS1:
1841                 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX;
1842                 die |= RK3568_SYS_DSP_INFACE_EN_LVDS1 |
1843                            FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id);
1844                 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1845                 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1846                 break;
1847         default:
1848                 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
1849                 return 0;
1850         }
1851
1852         dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD;
1853
1854         vop2_writel(vop2, RK3568_DSP_IF_EN, die);
1855         vop2_writel(vop2, RK3568_DSP_IF_POL, dip);
1856
1857         return crtc->state->adjusted_mode.crtc_clock  * 1000LL;
1858 }
1859
1860 /*
1861  * calc the dclk on rk3588
1862  * the available div of dclk is 1, 2, 4
1863  */
1864 static unsigned long rk3588_calc_dclk(unsigned long child_clk, unsigned long max_dclk)
1865 {
1866         if (child_clk * 4 <= max_dclk)
1867                 return child_clk * 4;
1868         else if (child_clk * 2 <= max_dclk)
1869                 return child_clk * 2;
1870         else if (child_clk <= max_dclk)
1871                 return child_clk;
1872         else
1873                 return 0;
1874 }
1875
1876 /*
1877  * 4 pixclk/cycle on rk3588
1878  * RGB/eDP/HDMI: if_pixclk >= dclk_core
1879  * DP: dp_pixclk = dclk_out <= dclk_core
1880  * DSI: mipi_pixclk <= dclk_out <= dclk_core
1881  */
1882 static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
1883                                          int *dclk_core_div, int *dclk_out_div,
1884                                          int *if_pixclk_div, int *if_dclk_div)
1885 {
1886         struct vop2 *vop2 = vp->vop2;
1887         struct drm_crtc *crtc = &vp->crtc;
1888         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1889         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1890         int output_mode = vcstate->output_mode;
1891         unsigned long v_pixclk = adjusted_mode->crtc_clock * 1000LL; /* video timing pixclk */
1892         unsigned long dclk_core_rate = v_pixclk >> 2;
1893         unsigned long dclk_rate = v_pixclk;
1894         unsigned long dclk_out_rate;
1895         unsigned long if_pixclk_rate;
1896         int K = 1;
1897
1898         if (vop2_output_if_is_hdmi(id)) {
1899                 /*
1900                  * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate
1901                  * K = 1: dclk_core = hdmie_edp_dclk > if_pixclk_rate
1902                  */
1903                 if (output_mode == ROCKCHIP_OUT_MODE_YUV420) {
1904                         dclk_rate = dclk_rate >> 1;
1905                         K = 2;
1906                 }
1907
1908                 if_pixclk_rate = (dclk_core_rate << 1) / K;
1909                 /*
1910                  * if_dclk_rate = dclk_core_rate / K;
1911                  * *if_pixclk_div = dclk_rate / if_pixclk_rate;
1912                  * *if_dclk_div = dclk_rate / if_dclk_rate;
1913                  */
1914                 *if_pixclk_div = 2;
1915                 *if_dclk_div = 4;
1916         } else if (vop2_output_if_is_edp(id)) {
1917                 /*
1918                  * edp_pixclk = edp_dclk > dclk_core
1919                  */
1920                 if_pixclk_rate = v_pixclk / K;
1921                 dclk_rate = if_pixclk_rate * K;
1922                 /*
1923                  * *if_pixclk_div = dclk_rate / if_pixclk_rate;
1924                  * *if_dclk_div = *if_pixclk_div;
1925                  */
1926                 *if_pixclk_div = K;
1927                 *if_dclk_div = K;
1928         } else if (vop2_output_if_is_dp(id)) {
1929                 if (output_mode == ROCKCHIP_OUT_MODE_YUV420)
1930                         dclk_out_rate = v_pixclk >> 3;
1931                 else
1932                         dclk_out_rate = v_pixclk >> 2;
1933
1934                 dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000000);
1935                 if (!dclk_rate) {
1936                         drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld Hz\n",
1937                                 dclk_out_rate);
1938                         return 0;
1939                 }
1940                 *dclk_out_div = dclk_rate / dclk_out_rate;
1941         } else if (vop2_output_if_is_mipi(id)) {
1942                 if_pixclk_rate = dclk_core_rate / K;
1943                 /*
1944                  * dclk_core = dclk_out * K = if_pixclk * K = v_pixclk / 4
1945                  */
1946                 dclk_out_rate = if_pixclk_rate;
1947                 /*
1948                  * dclk_rate = N * dclk_core_rate N = (1,2,4 ),
1949                  * we get a little factor here
1950                  */
1951                 dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000000);
1952                 if (!dclk_rate) {
1953                         drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld Hz\n",
1954                                 dclk_out_rate);
1955                         return 0;
1956                 }
1957                 *dclk_out_div = dclk_rate / dclk_out_rate;
1958                 /*
1959                  * mipi pixclk == dclk_out
1960                  */
1961                 *if_pixclk_div = 1;
1962         } else if (vop2_output_if_is_dpi(id)) {
1963                 dclk_rate = v_pixclk;
1964         }
1965
1966         *dclk_core_div = dclk_rate / dclk_core_rate;
1967         *if_pixclk_div = ilog2(*if_pixclk_div);
1968         *if_dclk_div = ilog2(*if_dclk_div);
1969         *dclk_core_div = ilog2(*dclk_core_div);
1970         *dclk_out_div = ilog2(*dclk_out_div);
1971
1972         drm_dbg(vop2->drm, "dclk: %ld, pixclk_div: %d, dclk_div: %d\n",
1973                 dclk_rate, *if_pixclk_div, *if_dclk_div);
1974
1975         return dclk_rate;
1976 }
1977
1978 /*
1979  * MIPI port mux on rk3588:
1980  * 0: Video Port2
1981  * 1: Video Port3
1982  * 3: Video Port 1(MIPI1 only)
1983  */
1984 static u32 rk3588_get_mipi_port_mux(int vp_id)
1985 {
1986         if (vp_id == 1)
1987                 return 3;
1988         else if (vp_id == 3)
1989                 return 1;
1990         else
1991                 return 0;
1992 }
1993
1994 static u32 rk3588_get_hdmi_pol(u32 flags)
1995 {
1996         u32 val;
1997
1998         val = (flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0;
1999         val |= (flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0;
2000
2001         return val;
2002 }
2003
2004 static unsigned long rk3588_set_intf_mux(struct vop2_video_port *vp, int id, u32 polflags)
2005 {
2006         struct vop2 *vop2 = vp->vop2;
2007         int dclk_core_div, dclk_out_div, if_pixclk_div, if_dclk_div;
2008         unsigned long clock;
2009         u32 die, dip, div, vp_clk_div, val;
2010
2011         clock = rk3588_calc_cru_cfg(vp, id, &dclk_core_div, &dclk_out_div,
2012                                     &if_pixclk_div, &if_dclk_div);
2013         if (!clock)
2014                 return 0;
2015
2016         vp_clk_div = FIELD_PREP(RK3588_VP_CLK_CTRL__DCLK_CORE_DIV, dclk_core_div);
2017         vp_clk_div |= FIELD_PREP(RK3588_VP_CLK_CTRL__DCLK_OUT_DIV, dclk_out_div);
2018
2019         die = vop2_readl(vop2, RK3568_DSP_IF_EN);
2020         dip = vop2_readl(vop2, RK3568_DSP_IF_POL);
2021         div = vop2_readl(vop2, RK3568_DSP_IF_CTRL);
2022
2023         switch (id) {
2024         case ROCKCHIP_VOP2_EP_HDMI0:
2025                 div &= ~RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV;
2026                 div &= ~RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV;
2027                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV, if_dclk_div);
2028                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV, if_pixclk_div);
2029                 die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX;
2030                 die |= RK3588_SYS_DSP_INFACE_EN_HDMI0 |
2031                             FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id);
2032                 val = rk3588_get_hdmi_pol(polflags);
2033                 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 1, 1));
2034                 regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 6, 5));
2035                 break;
2036         case ROCKCHIP_VOP2_EP_HDMI1:
2037                 div &= ~RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV;
2038                 div &= ~RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV;
2039                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV, if_dclk_div);
2040                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV, if_pixclk_div);
2041                 die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX;
2042                 die |= RK3588_SYS_DSP_INFACE_EN_HDMI1 |
2043                             FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id);
2044                 val = rk3588_get_hdmi_pol(polflags);
2045                 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 4, 4));
2046                 regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 8, 7));
2047                 break;
2048         case ROCKCHIP_VOP2_EP_EDP0:
2049                 div &= ~RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV;
2050                 div &= ~RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV;
2051                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV, if_dclk_div);
2052                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV, if_pixclk_div);
2053                 die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX;
2054                 die |= RK3588_SYS_DSP_INFACE_EN_EDP0 |
2055                            FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id);
2056                 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 0, 0));
2057                 break;
2058         case ROCKCHIP_VOP2_EP_EDP1:
2059                 div &= ~RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV;
2060                 div &= ~RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV;
2061                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV, if_dclk_div);
2062                 div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV, if_pixclk_div);
2063                 die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX;
2064                 die |= RK3588_SYS_DSP_INFACE_EN_EDP1 |
2065                            FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id);
2066                 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 3, 3));
2067                 break;
2068         case ROCKCHIP_VOP2_EP_MIPI0:
2069                 div &= ~RK3588_DSP_IF_MIPI0_PCLK_DIV;
2070                 div |= FIELD_PREP(RK3588_DSP_IF_MIPI0_PCLK_DIV, if_pixclk_div);
2071                 die &= ~RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX;
2072                 val = rk3588_get_mipi_port_mux(vp->id);
2073                 die |= RK3588_SYS_DSP_INFACE_EN_MIPI0 |
2074                            FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX, !!val);
2075                 break;
2076         case ROCKCHIP_VOP2_EP_MIPI1:
2077                 div &= ~RK3588_DSP_IF_MIPI1_PCLK_DIV;
2078                 div |= FIELD_PREP(RK3588_DSP_IF_MIPI1_PCLK_DIV, if_pixclk_div);
2079                 die &= ~RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX;
2080                 val = rk3588_get_mipi_port_mux(vp->id);
2081                 die |= RK3588_SYS_DSP_INFACE_EN_MIPI1 |
2082                            FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX, val);
2083                 break;
2084         case ROCKCHIP_VOP2_EP_DP0:
2085                 die &= ~RK3588_SYS_DSP_INFACE_EN_DP0_MUX;
2086                 die |= RK3588_SYS_DSP_INFACE_EN_DP0 |
2087                            FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_DP0_MUX, vp->id);
2088                 dip &= ~RK3588_DSP_IF_POL__DP0_PIN_POL;
2089                 dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP0_PIN_POL, polflags);
2090                 break;
2091         case ROCKCHIP_VOP2_EP_DP1:
2092                 die &= ~RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX;
2093                 die |= RK3588_SYS_DSP_INFACE_EN_MIPI1 |
2094                            FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id);
2095                 dip &= ~RK3588_DSP_IF_POL__DP1_PIN_POL;
2096                 dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP1_PIN_POL, polflags);
2097                 break;
2098         default:
2099                 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
2100                 return 0;
2101         }
2102
2103         dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD;
2104
2105         vop2_vp_write(vp, RK3588_VP_CLK_CTRL, vp_clk_div);
2106         vop2_writel(vop2, RK3568_DSP_IF_EN, die);
2107         vop2_writel(vop2, RK3568_DSP_IF_CTRL, div);
2108         vop2_writel(vop2, RK3568_DSP_IF_POL, dip);
2109
2110         return clock;
2111 }
2112
2113 static unsigned long vop2_set_intf_mux(struct vop2_video_port *vp, int ep_id, u32 polflags)
2114 {
2115         struct vop2 *vop2 = vp->vop2;
2116
2117         if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568)
2118                 return rk3568_set_intf_mux(vp, ep_id, polflags);
2119         else if (vop2->data->soc_id == 3588)
2120                 return rk3588_set_intf_mux(vp, ep_id, polflags);
2121         else
2122                 return 0;
2123 }
2124
2125 static int us_to_vertical_line(struct drm_display_mode *mode, int us)
2126 {
2127         return us * mode->clock / mode->htotal / 1000;
2128 }
2129
2130 static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
2131                                     struct drm_atomic_state *state)
2132 {
2133         struct vop2_video_port *vp = to_vop2_video_port(crtc);
2134         struct vop2 *vop2 = vp->vop2;
2135         const struct vop2_data *vop2_data = vop2->data;
2136         const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
2137         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
2138         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
2139         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2140         unsigned long clock = mode->crtc_clock * 1000;
2141         u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
2142         u16 hdisplay = mode->crtc_hdisplay;
2143         u16 htotal = mode->crtc_htotal;
2144         u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
2145         u16 hact_end = hact_st + hdisplay;
2146         u16 vdisplay = mode->crtc_vdisplay;
2147         u16 vtotal = mode->crtc_vtotal;
2148         u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
2149         u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
2150         u16 vact_end = vact_st + vdisplay;
2151         u8 out_mode;
2152         u32 dsp_ctrl = 0;
2153         int act_end;
2154         u32 val, polflags;
2155         int ret;
2156         struct drm_encoder *encoder;
2157
2158         drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
2159                 hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
2160                 drm_mode_vrefresh(mode), vcstate->output_type, vp->id);
2161
2162         vop2_lock(vop2);
2163
2164         ret = clk_prepare_enable(vp->dclk);
2165         if (ret < 0) {
2166                 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n",
2167                         vp->id, ret);
2168                 vop2_unlock(vop2);
2169                 return;
2170         }
2171
2172         if (!vop2->enable_count)
2173                 vop2_enable(vop2);
2174
2175         vop2->enable_count++;
2176
2177         vcstate->yuv_overlay = is_yuv_output(vcstate->bus_format);
2178
2179         vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY);
2180
2181         polflags = 0;
2182         if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
2183                 polflags |= POLFLAG_DCLK_INV;
2184         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
2185                 polflags |= BIT(HSYNC_POSITIVE);
2186         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
2187                 polflags |= BIT(VSYNC_POSITIVE);
2188
2189         drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
2190                 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
2191
2192                 /*
2193                  * for drive a high resolution(4KP120, 8K), vop on rk3588/rk3576 need
2194                  * process multi(1/2/4/8) pixels per cycle, so the dclk feed by the
2195                  * system cru may be the 1/2 or 1/4 of mode->clock.
2196                  */
2197                 clock = vop2_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags);
2198         }
2199
2200         if (!clock) {
2201                 vop2_unlock(vop2);
2202                 return;
2203         }
2204
2205         if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
2206             !(vp_data->feature & VOP2_VP_FEATURE_OUTPUT_10BIT))
2207                 out_mode = ROCKCHIP_OUT_MODE_P888;
2208         else
2209                 out_mode = vcstate->output_mode;
2210
2211         dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode);
2212
2213         if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode))
2214                 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP;
2215         if (vop2_output_rg_swap(vop2, vcstate->bus_format))
2216                 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RG_SWAP;
2217
2218         if (vcstate->yuv_overlay)
2219                 dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y;
2220
2221         vop2_dither_setup(crtc, &dsp_ctrl);
2222
2223         vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len);
2224         val = hact_st << 16;
2225         val |= hact_end;
2226         vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val);
2227
2228         val = vact_st << 16;
2229         val |= vact_end;
2230         vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val);
2231
2232         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2233                 u16 vact_st_f1 = vtotal + vact_st + 1;
2234                 u16 vact_end_f1 = vact_st_f1 + vdisplay;
2235
2236                 val = vact_st_f1 << 16 | vact_end_f1;
2237                 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val);
2238
2239                 val = vtotal << 16 | (vtotal + vsync_len);
2240                 vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val);
2241                 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE;
2242                 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL;
2243                 dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN;
2244                 vtotal += vtotal + 1;
2245                 act_end = vact_end_f1;
2246         } else {
2247                 act_end = vact_end;
2248         }
2249
2250         vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id),
2251                     (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end);
2252
2253         vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len);
2254
2255         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2256                 dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV;
2257                 clock *= 2;
2258         }
2259
2260         vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0);
2261
2262         clk_set_rate(vp->dclk, clock);
2263
2264         vop2_post_config(crtc);
2265
2266         vop2_cfg_done(vp);
2267
2268         vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
2269
2270         vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state);
2271
2272         drm_crtc_vblank_on(crtc);
2273
2274         vop2_unlock(vop2);
2275 }
2276
2277 static int vop2_crtc_atomic_check_gamma(struct vop2_video_port *vp,
2278                                         struct drm_crtc *crtc,
2279                                         struct drm_atomic_state *state,
2280                                         struct drm_crtc_state *crtc_state)
2281 {
2282         struct vop2 *vop2 = vp->vop2;
2283         unsigned int len;
2284
2285         if (!vp->vop2->lut_regs || !crtc_state->color_mgmt_changed ||
2286             !crtc_state->gamma_lut)
2287                 return 0;
2288
2289         len = drm_color_lut_size(crtc_state->gamma_lut);
2290         if (len != crtc->gamma_size) {
2291                 drm_dbg(vop2->drm, "Invalid LUT size; got %d, expected %d\n",
2292                         len, crtc->gamma_size);
2293                 return -EINVAL;
2294         }
2295
2296         if (!vop2_supports_seamless_gamma_lut_update(vop2) && vop2_gamma_lut_in_use(vop2, vp)) {
2297                 drm_info(vop2->drm, "Gamma LUT can be enabled for only one CRTC at a time\n");
2298                 return -EINVAL;
2299         }
2300
2301         return 0;
2302 }
2303
2304 static int vop2_crtc_atomic_check(struct drm_crtc *crtc,
2305                                   struct drm_atomic_state *state)
2306 {
2307         struct vop2_video_port *vp = to_vop2_video_port(crtc);
2308         struct drm_plane *plane;
2309         int nplanes = 0;
2310         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
2311         int ret;
2312
2313         ret = vop2_crtc_atomic_check_gamma(vp, crtc, state, crtc_state);
2314         if (ret)
2315                 return ret;
2316
2317         drm_atomic_crtc_state_for_each_plane(plane, crtc_state)
2318                 nplanes++;
2319
2320         if (nplanes > vp->nlayers)
2321                 return -EINVAL;
2322
2323         return 0;
2324 }
2325
2326 static bool is_opaque(u16 alpha)
2327 {
2328         return (alpha >> 8) == 0xff;
2329 }
2330
2331 static void vop2_parse_alpha(struct vop2_alpha_config *alpha_config,
2332                              struct vop2_alpha *alpha)
2333 {
2334         int src_glb_alpha_en = is_opaque(alpha_config->src_glb_alpha_value) ? 0 : 1;
2335         int dst_glb_alpha_en = is_opaque(alpha_config->dst_glb_alpha_value) ? 0 : 1;
2336         int src_color_mode = alpha_config->src_premulti_en ?
2337                                 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL;
2338         int dst_color_mode = alpha_config->dst_premulti_en ?
2339                                 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL;
2340
2341         alpha->src_color_ctrl.val = 0;
2342         alpha->dst_color_ctrl.val = 0;
2343         alpha->src_alpha_ctrl.val = 0;
2344         alpha->dst_alpha_ctrl.val = 0;
2345
2346         if (!alpha_config->src_pixel_alpha_en)
2347                 alpha->src_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
2348         else if (alpha_config->src_pixel_alpha_en && !src_glb_alpha_en)
2349                 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX;
2350         else
2351                 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
2352
2353         alpha->src_color_ctrl.bits.alpha_en = 1;
2354
2355         if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_GLOBAL) {
2356                 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
2357                 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
2358         } else if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_PER_PIX) {
2359                 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
2360                 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_ONE;
2361         } else {
2362                 alpha->src_color_ctrl.bits.color_mode = ALPHA_SRC_PRE_MUL;
2363                 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
2364         }
2365         alpha->src_color_ctrl.bits.glb_alpha = alpha_config->src_glb_alpha_value >> 8;
2366         alpha->src_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
2367         alpha->src_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
2368
2369         alpha->dst_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
2370         alpha->dst_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
2371         alpha->dst_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
2372         alpha->dst_color_ctrl.bits.glb_alpha = alpha_config->dst_glb_alpha_value >> 8;
2373         alpha->dst_color_ctrl.bits.color_mode = dst_color_mode;
2374         alpha->dst_color_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
2375
2376         alpha->src_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
2377         alpha->src_alpha_ctrl.bits.blend_mode = alpha->src_color_ctrl.bits.blend_mode;
2378         alpha->src_alpha_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
2379         alpha->src_alpha_ctrl.bits.factor_mode = ALPHA_ONE;
2380
2381         alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
2382         if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en)
2383                 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX;
2384         else
2385                 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
2386         alpha->dst_alpha_ctrl.bits.alpha_cal_mode = ALPHA_NO_SATURATION;
2387         alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
2388 }
2389
2390 static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id)
2391 {
2392         struct vop2_video_port *vp;
2393         int used_layer = 0;
2394         int i;
2395
2396         for (i = 0; i < port_id; i++) {
2397                 vp = &vop2->vps[i];
2398                 used_layer += hweight32(vp->win_mask);
2399         }
2400
2401         return used_layer;
2402 }
2403
2404 static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win)
2405 {
2406         struct vop2_alpha_config alpha_config;
2407         struct vop2_alpha alpha;
2408         struct drm_plane_state *bottom_win_pstate;
2409         bool src_pixel_alpha_en = false;
2410         u16 src_glb_alpha_val, dst_glb_alpha_val;
2411         bool premulti_en = false;
2412         bool swap = false;
2413         u32 offset = 0;
2414
2415         /* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */
2416         bottom_win_pstate = main_win->base.state;
2417         src_glb_alpha_val = 0;
2418         dst_glb_alpha_val = main_win->base.state->alpha;
2419
2420         if (!bottom_win_pstate->fb)
2421                 return;
2422
2423         alpha_config.src_premulti_en = premulti_en;
2424         alpha_config.dst_premulti_en = false;
2425         alpha_config.src_pixel_alpha_en = src_pixel_alpha_en;
2426         alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
2427         alpha_config.src_glb_alpha_value = src_glb_alpha_val;
2428         alpha_config.dst_glb_alpha_value = dst_glb_alpha_val;
2429         vop2_parse_alpha(&alpha_config, &alpha);
2430
2431         alpha.src_color_ctrl.bits.src_dst_swap = swap;
2432
2433         switch (main_win->data->phys_id) {
2434         case ROCKCHIP_VOP2_CLUSTER0:
2435                 offset = 0x0;
2436                 break;
2437         case ROCKCHIP_VOP2_CLUSTER1:
2438                 offset = 0x10;
2439                 break;
2440         case ROCKCHIP_VOP2_CLUSTER2:
2441                 offset = 0x20;
2442                 break;
2443         case ROCKCHIP_VOP2_CLUSTER3:
2444                 offset = 0x30;
2445                 break;
2446         }
2447
2448         vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset,
2449                     alpha.src_color_ctrl.val);
2450         vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset,
2451                     alpha.dst_color_ctrl.val);
2452         vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset,
2453                     alpha.src_alpha_ctrl.val);
2454         vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset,
2455                     alpha.dst_alpha_ctrl.val);
2456 }
2457
2458 static void vop2_setup_alpha(struct vop2_video_port *vp)
2459 {
2460         struct vop2 *vop2 = vp->vop2;
2461         struct drm_framebuffer *fb;
2462         struct vop2_alpha_config alpha_config;
2463         struct vop2_alpha alpha;
2464         struct drm_plane *plane;
2465         int pixel_alpha_en;
2466         int premulti_en, gpremulti_en = 0;
2467         int mixer_id;
2468         u32 offset;
2469         bool bottom_layer_alpha_en = false;
2470         u32 dst_global_alpha = DRM_BLEND_ALPHA_OPAQUE;
2471
2472         mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id);
2473         alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
2474
2475         drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
2476                 struct vop2_win *win = to_vop2_win(plane);
2477
2478                 if (plane->state->normalized_zpos == 0 &&
2479                     !is_opaque(plane->state->alpha) &&
2480                     !vop2_cluster_window(win)) {
2481                         /*
2482                          * If bottom layer have global alpha effect [except cluster layer,
2483                          * because cluster have deal with bottom layer global alpha value
2484                          * at cluster mix], bottom layer mix need deal with global alpha.
2485                          */
2486                         bottom_layer_alpha_en = true;
2487                         dst_global_alpha = plane->state->alpha;
2488                 }
2489         }
2490
2491         drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
2492                 struct vop2_win *win = to_vop2_win(plane);
2493                 int zpos = plane->state->normalized_zpos;
2494
2495                 /*
2496                  * Need to configure alpha from second layer.
2497                  */
2498                 if (zpos == 0)
2499                         continue;
2500
2501                 if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
2502                         premulti_en = 1;
2503                 else
2504                         premulti_en = 0;
2505
2506                 plane = &win->base;
2507                 fb = plane->state->fb;
2508
2509                 pixel_alpha_en = fb->format->has_alpha;
2510
2511                 alpha_config.src_premulti_en = premulti_en;
2512
2513                 if (bottom_layer_alpha_en && zpos == 1) {
2514                         gpremulti_en = premulti_en;
2515                         /* Cd = Cs + (1 - As) * Cd * Agd */
2516                         alpha_config.dst_premulti_en = false;
2517                         alpha_config.src_pixel_alpha_en = pixel_alpha_en;
2518                         alpha_config.src_glb_alpha_value = plane->state->alpha;
2519                         alpha_config.dst_glb_alpha_value = dst_global_alpha;
2520                 } else if (vop2_cluster_window(win)) {
2521                         /* Mix output data only have pixel alpha */
2522                         alpha_config.dst_premulti_en = true;
2523                         alpha_config.src_pixel_alpha_en = true;
2524                         alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
2525                         alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
2526                 } else {
2527                         /* Cd = Cs + (1 - As) * Cd */
2528                         alpha_config.dst_premulti_en = true;
2529                         alpha_config.src_pixel_alpha_en = pixel_alpha_en;
2530                         alpha_config.src_glb_alpha_value = plane->state->alpha;
2531                         alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
2532                 }
2533
2534                 vop2_parse_alpha(&alpha_config, &alpha);
2535
2536                 offset = (mixer_id + zpos - 1) * 0x10;
2537                 vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset,
2538                             alpha.src_color_ctrl.val);
2539                 vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset,
2540                             alpha.dst_color_ctrl.val);
2541                 vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset,
2542                             alpha.src_alpha_ctrl.val);
2543                 vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset,
2544                             alpha.dst_alpha_ctrl.val);
2545         }
2546
2547         if (vp->id == 0) {
2548                 if (bottom_layer_alpha_en) {
2549                         /* Transfer pixel alpha to hdr mix */
2550                         alpha_config.src_premulti_en = gpremulti_en;
2551                         alpha_config.dst_premulti_en = true;
2552                         alpha_config.src_pixel_alpha_en = true;
2553                         alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
2554                         alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
2555                         vop2_parse_alpha(&alpha_config, &alpha);
2556
2557                         vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL,
2558                                     alpha.src_color_ctrl.val);
2559                         vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL,
2560                                     alpha.dst_color_ctrl.val);
2561                         vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL,
2562                                     alpha.src_alpha_ctrl.val);
2563                         vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL,
2564                                     alpha.dst_alpha_ctrl.val);
2565                 } else {
2566                         vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0);
2567                 }
2568         }
2569 }
2570
2571 static void vop2_setup_layer_mixer(struct vop2_video_port *vp)
2572 {
2573         struct vop2 *vop2 = vp->vop2;
2574         struct drm_plane *plane;
2575         u32 layer_sel = 0;
2576         u32 port_sel;
2577         u8 layer_id;
2578         u8 old_layer_id;
2579         u8 layer_sel_id;
2580         unsigned int ofs;
2581         u32 ovl_ctrl;
2582         int i;
2583         struct vop2_video_port *vp0 = &vop2->vps[0];
2584         struct vop2_video_port *vp1 = &vop2->vps[1];
2585         struct vop2_video_port *vp2 = &vop2->vps[2];
2586         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
2587
2588         ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL);
2589         ovl_ctrl |= RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD;
2590         if (vcstate->yuv_overlay)
2591                 ovl_ctrl |= RK3568_OVL_CTRL__YUV_MODE(vp->id);
2592         else
2593                 ovl_ctrl &= ~RK3568_OVL_CTRL__YUV_MODE(vp->id);
2594
2595         vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl);
2596
2597         port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL);
2598         port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT;
2599
2600         if (vp0->nlayers)
2601                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX,
2602                                      vp0->nlayers - 1);
2603         else
2604                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 8);
2605
2606         if (vp1->nlayers)
2607                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX,
2608                                      (vp0->nlayers + vp1->nlayers - 1));
2609         else
2610                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8);
2611
2612         if (vp2->nlayers)
2613                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX,
2614                         (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1));
2615         else
2616                 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX, 8);
2617
2618         layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);
2619
2620         ofs = 0;
2621         for (i = 0; i < vp->id; i++)
2622                 ofs += vop2->vps[i].nlayers;
2623
2624         drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
2625                 struct vop2_win *win = to_vop2_win(plane);
2626                 struct vop2_win *old_win;
2627
2628                 layer_id = (u8)(plane->state->normalized_zpos + ofs);
2629
2630                 /*
2631                  * Find the layer this win bind in old state.
2632                  */
2633                 for (old_layer_id = 0; old_layer_id < vop2->data->win_size; old_layer_id++) {
2634                         layer_sel_id = (layer_sel >> (4 * old_layer_id)) & 0xf;
2635                         if (layer_sel_id == win->data->layer_sel_id)
2636                                 break;
2637                 }
2638
2639                 /*
2640                  * Find the win bind to this layer in old state
2641                  */
2642                 for (i = 0; i < vop2->data->win_size; i++) {
2643                         old_win = &vop2->win[i];
2644                         layer_sel_id = (layer_sel >> (4 * layer_id)) & 0xf;
2645                         if (layer_sel_id == old_win->data->layer_sel_id)
2646                                 break;
2647                 }
2648
2649                 switch (win->data->phys_id) {
2650                 case ROCKCHIP_VOP2_CLUSTER0:
2651                         port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER0;
2652                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id);
2653                         break;
2654                 case ROCKCHIP_VOP2_CLUSTER1:
2655                         port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1;
2656                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id);
2657                         break;
2658                 case ROCKCHIP_VOP2_CLUSTER2:
2659                         port_sel &= ~RK3588_OVL_PORT_SEL__CLUSTER2;
2660                         port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__CLUSTER2, vp->id);
2661                         break;
2662                 case ROCKCHIP_VOP2_CLUSTER3:
2663                         port_sel &= ~RK3588_OVL_PORT_SEL__CLUSTER3;
2664                         port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__CLUSTER3, vp->id);
2665                         break;
2666                 case ROCKCHIP_VOP2_ESMART0:
2667                         port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0;
2668                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id);
2669                         break;
2670                 case ROCKCHIP_VOP2_ESMART1:
2671                         port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1;
2672                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id);
2673                         break;
2674                 case ROCKCHIP_VOP2_ESMART2:
2675                         port_sel &= ~RK3588_OVL_PORT_SEL__ESMART2;
2676                         port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__ESMART2, vp->id);
2677                         break;
2678                 case ROCKCHIP_VOP2_ESMART3:
2679                         port_sel &= ~RK3588_OVL_PORT_SEL__ESMART3;
2680                         port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__ESMART3, vp->id);
2681                         break;
2682                 case ROCKCHIP_VOP2_SMART0:
2683                         port_sel &= ~RK3568_OVL_PORT_SEL__SMART0;
2684                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id);
2685                         break;
2686                 case ROCKCHIP_VOP2_SMART1:
2687                         port_sel &= ~RK3568_OVL_PORT_SEL__SMART1;
2688                         port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id);
2689                         break;
2690                 }
2691
2692                 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(layer_id, 0x7);
2693                 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(layer_id, win->data->layer_sel_id);
2694                 /*
2695                  * When we bind a window from layerM to layerN, we also need to move the old
2696                  * window on layerN to layerM to avoid one window selected by two or more layers.
2697                  */
2698                 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(old_layer_id, 0x7);
2699                 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(old_layer_id, old_win->data->layer_sel_id);
2700         }
2701
2702         vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel);
2703         vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel);
2704 }
2705
2706 static void vop2_setup_dly_for_windows(struct vop2 *vop2)
2707 {
2708         struct vop2_win *win;
2709         int i = 0;
2710         u32 cdly = 0, sdly = 0;
2711
2712         for (i = 0; i < vop2->data->win_size; i++) {
2713                 u32 dly;
2714
2715                 win = &vop2->win[i];
2716                 dly = win->delay;
2717
2718                 switch (win->data->phys_id) {
2719                 case ROCKCHIP_VOP2_CLUSTER0:
2720                         cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_0, dly);
2721                         cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_1, dly);
2722                         break;
2723                 case ROCKCHIP_VOP2_CLUSTER1:
2724                         cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_0, dly);
2725                         cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_1, dly);
2726                         break;
2727                 case ROCKCHIP_VOP2_ESMART0:
2728                         sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART0, dly);
2729                         break;
2730                 case ROCKCHIP_VOP2_ESMART1:
2731                         sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly);
2732                         break;
2733                 case ROCKCHIP_VOP2_SMART0:
2734                 case ROCKCHIP_VOP2_ESMART2:
2735                         sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly);
2736                         break;
2737                 case ROCKCHIP_VOP2_SMART1:
2738                 case ROCKCHIP_VOP2_ESMART3:
2739                         sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly);
2740                         break;
2741                 }
2742         }
2743
2744         vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly);
2745         vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly);
2746 }
2747
2748 static void vop2_crtc_atomic_begin(struct drm_crtc *crtc,
2749                                    struct drm_atomic_state *state)
2750 {
2751         struct vop2_video_port *vp = to_vop2_video_port(crtc);
2752         struct vop2 *vop2 = vp->vop2;
2753         struct drm_plane *plane;
2754
2755         vp->win_mask = 0;
2756
2757         drm_atomic_crtc_for_each_plane(plane, crtc) {
2758                 struct vop2_win *win = to_vop2_win(plane);
2759
2760                 win->delay = win->data->dly[VOP2_DLY_MODE_DEFAULT];
2761
2762                 vp->win_mask |= BIT(win->data->phys_id);
2763
2764                 if (vop2_cluster_window(win))
2765                         vop2_setup_cluster_alpha(vop2, win);
2766         }
2767
2768         if (!vp->win_mask)
2769                 return;
2770
2771         vop2_setup_layer_mixer(vp);
2772         vop2_setup_alpha(vp);
2773         vop2_setup_dly_for_windows(vop2);
2774 }
2775
2776 static void vop2_crtc_atomic_flush(struct drm_crtc *crtc,
2777                                    struct drm_atomic_state *state)
2778 {
2779         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
2780         struct vop2_video_port *vp = to_vop2_video_port(crtc);
2781         struct vop2 *vop2 = vp->vop2;
2782
2783         /* In case of modeset, gamma lut update already happened in atomic enable */
2784         if (!drm_atomic_crtc_needs_modeset(crtc_state) && crtc_state->color_mgmt_changed)
2785                 vop2_crtc_atomic_try_set_gamma_locked(vop2, vp, crtc, crtc_state);
2786
2787         vop2_post_config(crtc);
2788
2789         vop2_cfg_done(vp);
2790
2791         spin_lock_irq(&crtc->dev->event_lock);
2792
2793         if (crtc->state->event) {
2794                 WARN_ON(drm_crtc_vblank_get(crtc));
2795                 vp->event = crtc->state->event;
2796                 crtc->state->event = NULL;
2797         }
2798
2799         spin_unlock_irq(&crtc->dev->event_lock);
2800 }
2801
2802 static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = {
2803         .mode_fixup = vop2_crtc_mode_fixup,
2804         .atomic_check = vop2_crtc_atomic_check,
2805         .atomic_begin = vop2_crtc_atomic_begin,
2806         .atomic_flush = vop2_crtc_atomic_flush,
2807         .atomic_enable = vop2_crtc_atomic_enable,
2808         .atomic_disable = vop2_crtc_atomic_disable,
2809 };
2810
2811 static void vop2_dump_connector_on_crtc(struct drm_crtc *crtc, struct seq_file *s)
2812 {
2813         struct drm_connector_list_iter conn_iter;
2814         struct drm_connector *connector;
2815
2816         drm_connector_list_iter_begin(crtc->dev, &conn_iter);
2817         drm_for_each_connector_iter(connector, &conn_iter) {
2818                 if (crtc->state->connector_mask & drm_connector_mask(connector))
2819                         seq_printf(s, "    Connector: %s\n", connector->name);
2820         }
2821         drm_connector_list_iter_end(&conn_iter);
2822 }
2823
2824 static int vop2_plane_state_dump(struct seq_file *s, struct drm_plane *plane)
2825 {
2826         struct vop2_win *win = to_vop2_win(plane);
2827         struct drm_plane_state *pstate = plane->state;
2828         struct drm_rect *src, *dst;
2829         struct drm_framebuffer *fb;
2830         struct drm_gem_object *obj;
2831         struct rockchip_gem_object *rk_obj;
2832         bool xmirror;
2833         bool ymirror;
2834         bool rotate_270;
2835         bool rotate_90;
2836         dma_addr_t fb_addr;
2837         int i;
2838
2839         seq_printf(s, "    %s: %s\n", win->data->name, !pstate ?
2840                    "DISABLED" : pstate->crtc ? "ACTIVE" : "DISABLED");
2841
2842         if (!pstate || !pstate->fb)
2843                 return 0;
2844
2845         fb = pstate->fb;
2846         src = &pstate->src;
2847         dst = &pstate->dst;
2848         xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false;
2849         ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false;
2850         rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270;
2851         rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90;
2852
2853         seq_printf(s, "\twin_id: %d\n", win->win_id);
2854
2855         seq_printf(s, "\tformat: %p4cc%s glb_alpha[0x%x]\n",
2856                    &fb->format->format,
2857                    drm_is_afbc(fb->modifier) ? "[AFBC]" : "",
2858                    pstate->alpha >> 8);
2859         seq_printf(s, "\trotate: xmirror: %d ymirror: %d rotate_90: %d rotate_270: %d\n",
2860                    xmirror, ymirror, rotate_90, rotate_270);
2861         seq_printf(s, "\tzpos: %d\n", pstate->normalized_zpos);
2862         seq_printf(s, "\tsrc: pos[%d, %d] rect[%d x %d]\n", src->x1 >> 16,
2863                    src->y1 >> 16, drm_rect_width(src) >> 16,
2864                    drm_rect_height(src) >> 16);
2865         seq_printf(s, "\tdst: pos[%d, %d] rect[%d x %d]\n", dst->x1, dst->y1,
2866                    drm_rect_width(dst), drm_rect_height(dst));
2867
2868         for (i = 0; i < fb->format->num_planes; i++) {
2869                 obj = fb->obj[i];
2870                 rk_obj = to_rockchip_obj(obj);
2871                 fb_addr = rk_obj->dma_addr + fb->offsets[i];
2872
2873                 seq_printf(s, "\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
2874                            i, &fb_addr, fb->pitches[i], fb->offsets[i]);
2875         }
2876
2877         return 0;
2878 }
2879
2880 static int vop2_crtc_state_dump(struct drm_crtc *crtc, struct seq_file *s)
2881 {
2882         struct vop2_video_port *vp = to_vop2_video_port(crtc);
2883         struct drm_crtc_state *cstate = crtc->state;
2884         struct rockchip_crtc_state *vcstate;
2885         struct drm_display_mode *mode;
2886         struct drm_plane *plane;
2887         bool interlaced;
2888
2889         seq_printf(s, "Video Port%d: %s\n", vp->id, !cstate ?
2890                    "DISABLED" : cstate->active ? "ACTIVE" : "DISABLED");
2891
2892         if (!cstate || !cstate->active)
2893                 return 0;
2894
2895         mode = &crtc->state->adjusted_mode;
2896         vcstate = to_rockchip_crtc_state(cstate);
2897         interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
2898
2899         vop2_dump_connector_on_crtc(crtc, s);
2900         seq_printf(s, "\tbus_format[%x]: %s\n", vcstate->bus_format,
2901                    drm_get_bus_format_name(vcstate->bus_format));
2902         seq_printf(s, "\toutput_mode[%x]", vcstate->output_mode);
2903         seq_printf(s, " color_space[%d]\n", vcstate->color_space);
2904         seq_printf(s, "    Display mode: %dx%d%s%d\n",
2905                    mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
2906                    drm_mode_vrefresh(mode));
2907         seq_printf(s, "\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
2908                    mode->clock, mode->crtc_clock, mode->type, mode->flags);
2909         seq_printf(s, "\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
2910                    mode->hsync_end, mode->htotal);
2911         seq_printf(s, "\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
2912                    mode->vsync_end, mode->vtotal);
2913
2914         drm_atomic_crtc_for_each_plane(plane, crtc) {
2915                 vop2_plane_state_dump(s, plane);
2916         }
2917
2918         return 0;
2919 }
2920
2921 static int vop2_summary_show(struct seq_file *s, void *data)
2922 {
2923         struct drm_info_node *node = s->private;
2924         struct drm_minor *minor = node->minor;
2925         struct drm_device *drm_dev = minor->dev;
2926         struct drm_crtc *crtc;
2927
2928         drm_modeset_lock_all(drm_dev);
2929         drm_for_each_crtc(crtc, drm_dev) {
2930                 vop2_crtc_state_dump(crtc, s);
2931         }
2932         drm_modeset_unlock_all(drm_dev);
2933
2934         return 0;
2935 }
2936
2937 static void vop2_regs_print(struct vop2 *vop2, struct seq_file *s,
2938                             const struct vop2_regs_dump *dump, bool active_only)
2939 {
2940         resource_size_t start;
2941         u32 val;
2942         int i;
2943
2944         if (dump->en_mask && active_only) {
2945                 val = vop2_readl(vop2, dump->base + dump->en_reg);
2946                 if ((val & dump->en_mask) != dump->en_val)
2947                         return;
2948         }
2949
2950         seq_printf(s, "\n%s:\n", dump->name);
2951
2952         start = vop2->res->start + dump->base;
2953         for (i = 0; i < dump->size >> 2; i += 4) {
2954                 seq_printf(s, "%08x:  %08x %08x %08x %08x\n", (u32)start + i * 4,
2955                            vop2_readl(vop2, dump->base + (4 * i)),
2956                            vop2_readl(vop2, dump->base + (4 * (i + 1))),
2957                            vop2_readl(vop2, dump->base + (4 * (i + 2))),
2958                            vop2_readl(vop2, dump->base + (4 * (i + 3))));
2959         }
2960 }
2961
2962 static void __vop2_regs_dump(struct seq_file *s, bool active_only)
2963 {
2964         struct drm_info_node *node = s->private;
2965         struct vop2 *vop2 = node->info_ent->data;
2966         struct drm_minor *minor = node->minor;
2967         struct drm_device *drm_dev = minor->dev;
2968         const struct vop2_regs_dump *dump;
2969         unsigned int i;
2970
2971         drm_modeset_lock_all(drm_dev);
2972
2973         regcache_drop_region(vop2->map, 0, vop2_regmap_config.max_register);
2974
2975         if (vop2->enable_count) {
2976                 for (i = 0; i < vop2->data->regs_dump_size; i++) {
2977                         dump = &vop2->data->regs_dump[i];
2978                         vop2_regs_print(vop2, s, dump, active_only);
2979                 }
2980         } else {
2981                 seq_puts(s, "VOP disabled\n");
2982         }
2983         drm_modeset_unlock_all(drm_dev);
2984 }
2985
2986 static int vop2_regs_show(struct seq_file *s, void *arg)
2987 {
2988         __vop2_regs_dump(s, false);
2989
2990         return 0;
2991 }
2992
2993 static int vop2_active_regs_show(struct seq_file *s, void *data)
2994 {
2995         __vop2_regs_dump(s, true);
2996
2997         return 0;
2998 }
2999
3000 static struct drm_info_list vop2_debugfs_list[] = {
3001         { "summary", vop2_summary_show, 0, NULL },
3002         { "active_regs", vop2_active_regs_show,   0, NULL },
3003         { "regs", vop2_regs_show,   0, NULL },
3004 };
3005
3006 static void vop2_debugfs_init(struct vop2 *vop2, struct drm_minor *minor)
3007 {
3008         struct dentry *root;
3009         unsigned int i;
3010
3011         root = debugfs_create_dir("vop2", minor->debugfs_root);
3012         if (!IS_ERR(root)) {
3013                 for (i = 0; i < ARRAY_SIZE(vop2_debugfs_list); i++)
3014                         vop2_debugfs_list[i].data = vop2;
3015
3016                 drm_debugfs_create_files(vop2_debugfs_list,
3017                                          ARRAY_SIZE(vop2_debugfs_list),
3018                                          root, minor);
3019         }
3020 }
3021
3022 static int vop2_crtc_late_register(struct drm_crtc *crtc)
3023 {
3024         struct vop2_video_port *vp = to_vop2_video_port(crtc);
3025         struct vop2 *vop2 = vp->vop2;
3026
3027         if (drm_crtc_index(crtc) == 0)
3028                 vop2_debugfs_init(vop2, crtc->dev->primary);
3029
3030         return 0;
3031 }
3032
3033 static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc)
3034 {
3035         struct rockchip_crtc_state *vcstate;
3036
3037         if (WARN_ON(!crtc->state))
3038                 return NULL;
3039
3040         vcstate = kmemdup(to_rockchip_crtc_state(crtc->state),
3041                           sizeof(*vcstate), GFP_KERNEL);
3042         if (!vcstate)
3043                 return NULL;
3044
3045         __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base);
3046
3047         return &vcstate->base;
3048 }
3049
3050 static void vop2_crtc_destroy_state(struct drm_crtc *crtc,
3051                                     struct drm_crtc_state *state)
3052 {
3053         struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
3054
3055         __drm_atomic_helper_crtc_destroy_state(&vcstate->base);
3056         kfree(vcstate);
3057 }
3058
3059 static void vop2_crtc_reset(struct drm_crtc *crtc)
3060 {
3061         struct rockchip_crtc_state *vcstate =
3062                 kzalloc(sizeof(*vcstate), GFP_KERNEL);
3063
3064         if (crtc->state)
3065                 vop2_crtc_destroy_state(crtc, crtc->state);
3066
3067         if (vcstate)
3068                 __drm_atomic_helper_crtc_reset(crtc, &vcstate->base);
3069         else
3070                 __drm_atomic_helper_crtc_reset(crtc, NULL);
3071 }
3072
3073 static const struct drm_crtc_funcs vop2_crtc_funcs = {
3074         .set_config = drm_atomic_helper_set_config,
3075         .page_flip = drm_atomic_helper_page_flip,
3076         .destroy = drm_crtc_cleanup,
3077         .reset = vop2_crtc_reset,
3078         .atomic_duplicate_state = vop2_crtc_duplicate_state,
3079         .atomic_destroy_state = vop2_crtc_destroy_state,
3080         .enable_vblank = vop2_crtc_enable_vblank,
3081         .disable_vblank = vop2_crtc_disable_vblank,
3082         .late_register = vop2_crtc_late_register,
3083 };
3084
3085 static irqreturn_t vop2_isr(int irq, void *data)
3086 {
3087         struct vop2 *vop2 = data;
3088         const struct vop2_data *vop2_data = vop2->data;
3089         u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM];
3090         int ret = IRQ_NONE;
3091         int i;
3092
3093         /*
3094          * The irq is shared with the iommu. If the runtime-pm state of the
3095          * vop2-device is disabled the irq has to be targeted at the iommu.
3096          */
3097         if (!pm_runtime_get_if_in_use(vop2->dev))
3098                 return IRQ_NONE;
3099
3100         for (i = 0; i < vop2_data->nr_vps; i++) {
3101                 struct vop2_video_port *vp = &vop2->vps[i];
3102                 struct drm_crtc *crtc = &vp->crtc;
3103                 u32 irqs;
3104
3105                 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id));
3106                 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs);
3107
3108                 if (irqs & VP_INT_DSP_HOLD_VALID) {
3109                         complete(&vp->dsp_hold_completion);
3110                         ret = IRQ_HANDLED;
3111                 }
3112
3113                 if (irqs & VP_INT_FS_FIELD) {
3114                         drm_crtc_handle_vblank(crtc);
3115                         spin_lock(&crtc->dev->event_lock);
3116                         if (vp->event) {
3117                                 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE);
3118
3119                                 if (!(val & BIT(vp->id))) {
3120                                         drm_crtc_send_vblank_event(crtc, vp->event);
3121                                         vp->event = NULL;
3122                                         drm_crtc_vblank_put(crtc);
3123                                 }
3124                         }
3125                         spin_unlock(&crtc->dev->event_lock);
3126
3127                         ret = IRQ_HANDLED;
3128                 }
3129
3130                 if (irqs & VP_INT_POST_BUF_EMPTY) {
3131                         drm_err_ratelimited(vop2->drm,
3132                                             "POST_BUF_EMPTY irq err at vp%d\n",
3133                                             vp->id);
3134                         ret = IRQ_HANDLED;
3135                 }
3136         }
3137
3138         axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS);
3139         vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]);
3140         axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS);
3141         vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]);
3142
3143         for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) {
3144                 if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) {
3145                         drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n");
3146                         ret = IRQ_HANDLED;
3147                 }
3148         }
3149
3150         pm_runtime_put(vop2->dev);
3151
3152         return ret;
3153 }
3154
3155 static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win,
3156                            unsigned long possible_crtcs)
3157 {
3158         const struct vop2_win_data *win_data = win->data;
3159         unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
3160                                   BIT(DRM_MODE_BLEND_PREMULTI) |
3161                                   BIT(DRM_MODE_BLEND_COVERAGE);
3162         int ret;
3163
3164         ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs,
3165                                        &vop2_plane_funcs, win_data->formats,
3166                                        win_data->nformats,
3167                                        win_data->format_modifiers,
3168                                        win->type, win_data->name);
3169         if (ret) {
3170                 drm_err(vop2->drm, "failed to initialize plane %d\n", ret);
3171                 return ret;
3172         }
3173
3174         drm_plane_helper_add(&win->base, &vop2_plane_helper_funcs);
3175
3176         if (win->data->supported_rotations)
3177                 drm_plane_create_rotation_property(&win->base, DRM_MODE_ROTATE_0,
3178                                                    DRM_MODE_ROTATE_0 |
3179                                                    win->data->supported_rotations);
3180         drm_plane_create_alpha_property(&win->base);
3181         drm_plane_create_blend_mode_property(&win->base, blend_caps);
3182         drm_plane_create_zpos_property(&win->base, win->win_id, 0,
3183                                        vop2->registered_num_wins - 1);
3184
3185         return 0;
3186 }
3187
3188 static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2)
3189 {
3190         int i;
3191
3192         for (i = 0; i < vop2->data->nr_vps; i++) {
3193                 struct vop2_video_port *vp = &vop2->vps[i];
3194
3195                 if (!vp->crtc.port)
3196                         continue;
3197                 if (vp->primary_plane)
3198                         continue;
3199
3200                 return vp;
3201         }
3202
3203         return NULL;
3204 }
3205
3206 static int vop2_create_crtcs(struct vop2 *vop2)
3207 {
3208         const struct vop2_data *vop2_data = vop2->data;
3209         struct drm_device *drm = vop2->drm;
3210         struct device *dev = vop2->dev;
3211         struct drm_plane *plane;
3212         struct device_node *port;
3213         struct vop2_video_port *vp;
3214         int i, nvp, nvps = 0;
3215         int ret;
3216
3217         for (i = 0; i < vop2_data->nr_vps; i++) {
3218                 const struct vop2_video_port_data *vp_data;
3219                 struct device_node *np;
3220                 char dclk_name[9];
3221
3222                 vp_data = &vop2_data->vp[i];
3223                 vp = &vop2->vps[i];
3224                 vp->vop2 = vop2;
3225                 vp->id = vp_data->id;
3226                 vp->data = vp_data;
3227
3228                 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id);
3229                 vp->dclk = devm_clk_get(vop2->dev, dclk_name);
3230                 if (IS_ERR(vp->dclk)) {
3231                         drm_err(vop2->drm, "failed to get %s\n", dclk_name);
3232                         return PTR_ERR(vp->dclk);
3233                 }
3234
3235                 np = of_graph_get_remote_node(dev->of_node, i, -1);
3236                 if (!np) {
3237                         drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i);
3238                         continue;
3239                 }
3240                 of_node_put(np);
3241
3242                 port = of_graph_get_port_by_id(dev->of_node, i);
3243                 if (!port) {
3244                         drm_err(vop2->drm, "no port node found for video_port%d\n", i);
3245                         return -ENOENT;
3246                 }
3247
3248                 vp->crtc.port = port;
3249                 nvps++;
3250         }
3251
3252         nvp = 0;
3253         for (i = 0; i < vop2->registered_num_wins; i++) {
3254                 struct vop2_win *win = &vop2->win[i];
3255                 u32 possible_crtcs = 0;
3256
3257                 if (vop2->data->soc_id == 3566) {
3258                         /*
3259                          * On RK3566 these windows don't have an independent
3260                          * framebuffer. They share the framebuffer with smart0,
3261                          * esmart0 and cluster0 respectively.
3262                          */
3263                         switch (win->data->phys_id) {
3264                         case ROCKCHIP_VOP2_SMART1:
3265                         case ROCKCHIP_VOP2_ESMART1:
3266                         case ROCKCHIP_VOP2_CLUSTER1:
3267                                 continue;
3268                         }
3269                 }
3270
3271                 if (win->type == DRM_PLANE_TYPE_PRIMARY) {
3272                         vp = find_vp_without_primary(vop2);
3273                         if (vp) {
3274                                 possible_crtcs = BIT(nvp);
3275                                 vp->primary_plane = win;
3276                                 nvp++;
3277                         } else {
3278                                 /* change the unused primary window to overlay window */
3279                                 win->type = DRM_PLANE_TYPE_OVERLAY;
3280                         }
3281                 }
3282
3283                 if (win->type == DRM_PLANE_TYPE_OVERLAY)
3284                         possible_crtcs = (1 << nvps) - 1;
3285
3286                 ret = vop2_plane_init(vop2, win, possible_crtcs);
3287                 if (ret) {
3288                         drm_err(vop2->drm, "failed to init plane %s: %d\n",
3289                                 win->data->name, ret);
3290                         return ret;
3291                 }
3292         }
3293
3294         for (i = 0; i < vop2_data->nr_vps; i++) {
3295                 vp = &vop2->vps[i];
3296
3297                 if (!vp->crtc.port)
3298                         continue;
3299
3300                 plane = &vp->primary_plane->base;
3301
3302                 ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL,
3303                                                 &vop2_crtc_funcs,
3304                                                 "video_port%d", vp->id);
3305                 if (ret) {
3306                         drm_err(vop2->drm, "crtc init for video_port%d failed\n", i);
3307                         return ret;
3308                 }
3309
3310                 drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs);
3311                 if (vop2->lut_regs) {
3312                         const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
3313
3314                         drm_mode_crtc_set_gamma_size(&vp->crtc, vp_data->gamma_lut_len);
3315                         drm_crtc_enable_color_mgmt(&vp->crtc, 0, false, vp_data->gamma_lut_len);
3316                 }
3317                 init_completion(&vp->dsp_hold_completion);
3318         }
3319
3320         /*
3321          * On the VOP2 it's very hard to change the number of layers on a VP
3322          * during runtime, so we distribute the layers equally over the used
3323          * VPs
3324          */
3325         for (i = 0; i < vop2->data->nr_vps; i++) {
3326                 struct vop2_video_port *vp = &vop2->vps[i];
3327
3328                 if (vp->crtc.port)
3329                         vp->nlayers = vop2_data->win_size / nvps;
3330         }
3331
3332         return 0;
3333 }
3334
3335 static void vop2_destroy_crtcs(struct vop2 *vop2)
3336 {
3337         struct drm_device *drm = vop2->drm;
3338         struct list_head *crtc_list = &drm->mode_config.crtc_list;
3339         struct list_head *plane_list = &drm->mode_config.plane_list;
3340         struct drm_crtc *crtc, *tmpc;
3341         struct drm_plane *plane, *tmpp;
3342
3343         list_for_each_entry_safe(plane, tmpp, plane_list, head)
3344                 drm_plane_cleanup(plane);
3345
3346         /*
3347          * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane()
3348          * references the CRTC.
3349          */
3350         list_for_each_entry_safe(crtc, tmpc, crtc_list, head) {
3351                 of_node_put(crtc->port);
3352                 drm_crtc_cleanup(crtc);
3353         }
3354 }
3355
3356 static int vop2_find_rgb_encoder(struct vop2 *vop2)
3357 {
3358         struct device_node *node = vop2->dev->of_node;
3359         struct device_node *endpoint;
3360         int i;
3361
3362         for (i = 0; i < vop2->data->nr_vps; i++) {
3363                 endpoint = of_graph_get_endpoint_by_regs(node, i,
3364                                                          ROCKCHIP_VOP2_EP_RGB0);
3365                 if (!endpoint)
3366                         continue;
3367
3368                 of_node_put(endpoint);
3369                 return i;
3370         }
3371
3372         return -ENOENT;
3373 }
3374
3375 static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = {
3376         [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0),
3377         [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5),
3378         [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14),
3379         [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18),
3380         [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31),
3381         [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31),
3382         [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31),
3383         [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31),
3384         [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31),
3385         [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19),
3386         [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15),
3387         [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31),
3388         [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8),
3389         [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9),
3390         [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11),
3391         [VOP2_WIN_AXI_YRGB_R_ID] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL2, 0, 3),
3392         [VOP2_WIN_AXI_UV_R_ID] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL2, 5, 8),
3393         /* RK3588 only, reserved bit on rk3568*/
3394         [VOP2_WIN_AXI_BUS_ID] = REG_FIELD(RK3568_CLUSTER_CTRL, 13, 13),
3395
3396         /* Scale */
3397         [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15),
3398         [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31),
3399         [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15),
3400         [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13),
3401         [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3),
3402         [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28),
3403         [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29),
3404
3405         /* cluster regs */
3406         [VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1),
3407         [VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0),
3408         [VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7),
3409
3410         /* afbc regs */
3411         [VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6),
3412         [VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9),
3413         [VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10),
3414         [VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4),
3415         [VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7),
3416         [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8),
3417         [VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31),
3418         [VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31),
3419         [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15),
3420         [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31),
3421         [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31),
3422         [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31),
3423         [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31),
3424         [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0),
3425         [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1),
3426         [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2),
3427         [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3),
3428         [VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff },
3429         [VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff },
3430         [VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff },
3431         [VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff },
3432         [VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff },
3433         [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
3434         [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
3435         [VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff },
3436         [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
3437         [VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff },
3438         [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
3439         [VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff },
3440         [VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff },
3441 };
3442
3443 static int vop2_cluster_init(struct vop2_win *win)
3444 {
3445         struct vop2 *vop2 = win->vop2;
3446         struct reg_field *cluster_regs;
3447         int ret, i;
3448
3449         cluster_regs = kmemdup(vop2_cluster_regs, sizeof(vop2_cluster_regs),
3450                                GFP_KERNEL);
3451         if (!cluster_regs)
3452                 return -ENOMEM;
3453
3454         for (i = 0; i < ARRAY_SIZE(vop2_cluster_regs); i++)
3455                 if (cluster_regs[i].reg != 0xffffffff)
3456                         cluster_regs[i].reg += win->offset;
3457
3458         ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
3459                                            cluster_regs,
3460                                            ARRAY_SIZE(vop2_cluster_regs));
3461
3462         kfree(cluster_regs);
3463
3464         return ret;
3465 };
3466
3467 static struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = {
3468         [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0),
3469         [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5),
3470         [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12),
3471         [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14),
3472         [VOP2_WIN_UV_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16),
3473         [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31),
3474         [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31),
3475         [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28),
3476         [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31),
3477         [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31),
3478         [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17),
3479         [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15),
3480         [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31),
3481         [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_SMART_CTRL0, 0, 0),
3482         [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_SMART_CTRL0, 1, 1),
3483         [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_SMART_CTRL0, 2, 3),
3484         [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31),
3485         [VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29),
3486         [VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31),
3487         [VOP2_WIN_AXI_YRGB_R_ID] = REG_FIELD(RK3568_SMART_CTRL1, 4, 8),
3488         [VOP2_WIN_AXI_UV_R_ID] = REG_FIELD(RK3568_SMART_CTRL1, 12, 16),
3489         /* RK3588 only, reserved register on rk3568 */
3490         [VOP2_WIN_AXI_BUS_ID] = REG_FIELD(RK3588_SMART_AXI_CTRL, 1, 1),
3491
3492         /* Scale */
3493         [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15),
3494         [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 16, 31),
3495         [VOP2_WIN_SCALE_CBCR_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 0, 15),
3496         [VOP2_WIN_SCALE_CBCR_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 16, 31),
3497         [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 0, 1),
3498         [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 2, 3),
3499         [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 4, 5),
3500         [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 6, 7),
3501         [VOP2_WIN_CBCR_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 8, 9),
3502         [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 10, 11),
3503         [VOP2_WIN_CBCR_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 12, 13),
3504         [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 14, 15),
3505         [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 17),
3506         [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8),
3507         [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9),
3508         [VOP2_WIN_VSD_CBCR_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10),
3509         [VOP2_WIN_VSD_CBCR_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11),
3510         [VOP2_WIN_XMIRROR] = { .reg = 0xffffffff },
3511         [VOP2_WIN_CLUSTER_ENABLE] = { .reg = 0xffffffff },
3512         [VOP2_WIN_AFBC_ENABLE] = { .reg = 0xffffffff },
3513         [VOP2_WIN_CLUSTER_LB_MODE] = { .reg = 0xffffffff },
3514         [VOP2_WIN_AFBC_FORMAT] = { .reg = 0xffffffff },
3515         [VOP2_WIN_AFBC_RB_SWAP] = { .reg = 0xffffffff },
3516         [VOP2_WIN_AFBC_UV_SWAP] = { .reg = 0xffffffff },
3517         [VOP2_WIN_AFBC_AUTO_GATING_EN] = { .reg = 0xffffffff },
3518         [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = { .reg = 0xffffffff },
3519         [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = { .reg = 0xffffffff },
3520         [VOP2_WIN_AFBC_TILE_NUM] = { .reg = 0xffffffff },
3521         [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff },
3522         [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff },
3523         [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff },
3524         [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff },
3525         [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff },
3526         [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff },
3527         [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff },
3528         [VOP2_WIN_AFBC_ROTATE_90] = { .reg = 0xffffffff },
3529 };
3530
3531 static int vop2_esmart_init(struct vop2_win *win)
3532 {
3533         struct vop2 *vop2 = win->vop2;
3534         struct reg_field *esmart_regs;
3535         int ret, i;
3536
3537         esmart_regs = kmemdup(vop2_esmart_regs, sizeof(vop2_esmart_regs),
3538                               GFP_KERNEL);
3539         if (!esmart_regs)
3540                 return -ENOMEM;
3541
3542         for (i = 0; i < ARRAY_SIZE(vop2_esmart_regs); i++)
3543                 if (esmart_regs[i].reg != 0xffffffff)
3544                         esmart_regs[i].reg += win->offset;
3545
3546         ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
3547                                            esmart_regs,
3548                                            ARRAY_SIZE(vop2_esmart_regs));
3549
3550         kfree(esmart_regs);
3551
3552         return ret;
3553 };
3554
3555 static int vop2_win_init(struct vop2 *vop2)
3556 {
3557         const struct vop2_data *vop2_data = vop2->data;
3558         struct vop2_win *win;
3559         int i, ret;
3560
3561         for (i = 0; i < vop2_data->win_size; i++) {
3562                 const struct vop2_win_data *win_data = &vop2_data->win[i];
3563
3564                 win = &vop2->win[i];
3565                 win->data = win_data;
3566                 win->type = win_data->type;
3567                 win->offset = win_data->base;
3568                 win->win_id = i;
3569                 win->vop2 = vop2;
3570                 if (vop2_cluster_window(win))
3571                         ret = vop2_cluster_init(win);
3572                 else
3573                         ret = vop2_esmart_init(win);
3574                 if (ret)
3575                         return ret;
3576         }
3577
3578         vop2->registered_num_wins = vop2_data->win_size;
3579
3580         return 0;
3581 }
3582
3583 /*
3584  * The window registers are only updated when config done is written.
3585  * Until that they read back the old value. As we read-modify-write
3586  * these registers mark them as non-volatile. This makes sure we read
3587  * the new values from the regmap register cache.
3588  */
3589 static const struct regmap_range vop2_nonvolatile_range[] = {
3590         regmap_reg_range(0x1000, 0x23ff),
3591 };
3592
3593 static const struct regmap_access_table vop2_volatile_table = {
3594         .no_ranges = vop2_nonvolatile_range,
3595         .n_no_ranges = ARRAY_SIZE(vop2_nonvolatile_range),
3596 };
3597
3598 static const struct regmap_config vop2_regmap_config = {
3599         .reg_bits       = 32,
3600         .val_bits       = 32,
3601         .reg_stride     = 4,
3602         .max_register   = 0x3000,
3603         .name           = "vop2",
3604         .volatile_table = &vop2_volatile_table,
3605         .cache_type     = REGCACHE_MAPLE,
3606 };
3607
3608 static int vop2_bind(struct device *dev, struct device *master, void *data)
3609 {
3610         struct platform_device *pdev = to_platform_device(dev);
3611         const struct vop2_data *vop2_data;
3612         struct drm_device *drm = data;
3613         struct vop2 *vop2;
3614         struct resource *res;
3615         size_t alloc_size;
3616         int ret;
3617
3618         vop2_data = of_device_get_match_data(dev);
3619         if (!vop2_data)
3620                 return -ENODEV;
3621
3622         /* Allocate vop2 struct and its vop2_win array */
3623         alloc_size = struct_size(vop2, win, vop2_data->win_size);
3624         vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
3625         if (!vop2)
3626                 return -ENOMEM;
3627
3628         vop2->dev = dev;
3629         vop2->data = vop2_data;
3630         vop2->drm = drm;
3631
3632         dev_set_drvdata(dev, vop2);
3633
3634         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vop");
3635         if (!res) {
3636                 drm_err(vop2->drm, "failed to get vop2 register byname\n");
3637                 return -EINVAL;
3638         }
3639
3640         vop2->res = res;
3641         vop2->regs = devm_ioremap_resource(dev, res);
3642         if (IS_ERR(vop2->regs))
3643                 return PTR_ERR(vop2->regs);
3644         vop2->len = resource_size(res);
3645
3646         vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config);
3647         if (IS_ERR(vop2->map))
3648                 return PTR_ERR(vop2->map);
3649
3650         ret = vop2_win_init(vop2);
3651         if (ret)
3652                 return ret;
3653
3654         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma-lut");
3655         if (res) {
3656                 vop2->lut_regs = devm_ioremap_resource(dev, res);
3657                 if (IS_ERR(vop2->lut_regs))
3658                         return PTR_ERR(vop2->lut_regs);
3659         }
3660         if (vop2_data->feature & VOP2_FEATURE_HAS_SYS_GRF) {
3661                 vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
3662                 if (IS_ERR(vop2->sys_grf))
3663                         return dev_err_probe(dev, PTR_ERR(vop2->sys_grf), "cannot get sys_grf");
3664         }
3665
3666         if (vop2_data->feature & VOP2_FEATURE_HAS_VOP_GRF) {
3667                 vop2->vop_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf");
3668                 if (IS_ERR(vop2->vop_grf))
3669                         return dev_err_probe(dev, PTR_ERR(vop2->vop_grf), "cannot get vop_grf");
3670         }
3671
3672         if (vop2_data->feature & VOP2_FEATURE_HAS_VO1_GRF) {
3673                 vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf");
3674                 if (IS_ERR(vop2->vo1_grf))
3675                         return dev_err_probe(dev, PTR_ERR(vop2->vo1_grf), "cannot get vo1_grf");
3676         }
3677
3678         if (vop2_data->feature & VOP2_FEATURE_HAS_SYS_PMU) {
3679                 vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");
3680                 if (IS_ERR(vop2->sys_pmu))
3681                         return dev_err_probe(dev, PTR_ERR(vop2->sys_pmu), "cannot get sys_pmu");
3682         }
3683
3684         vop2->hclk = devm_clk_get(vop2->dev, "hclk");
3685         if (IS_ERR(vop2->hclk)) {
3686                 drm_err(vop2->drm, "failed to get hclk source\n");
3687                 return PTR_ERR(vop2->hclk);
3688         }
3689
3690         vop2->aclk = devm_clk_get(vop2->dev, "aclk");
3691         if (IS_ERR(vop2->aclk)) {
3692                 drm_err(vop2->drm, "failed to get aclk source\n");
3693                 return PTR_ERR(vop2->aclk);
3694         }
3695
3696         vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop");
3697         if (IS_ERR(vop2->pclk)) {
3698                 drm_err(vop2->drm, "failed to get pclk source\n");
3699                 return PTR_ERR(vop2->pclk);
3700         }
3701
3702         vop2->irq = platform_get_irq(pdev, 0);
3703         if (vop2->irq < 0) {
3704                 drm_err(vop2->drm, "cannot find irq for vop2\n");
3705                 return vop2->irq;
3706         }
3707
3708         mutex_init(&vop2->vop2_lock);
3709
3710         ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2);
3711         if (ret)
3712                 return ret;
3713
3714         ret = vop2_create_crtcs(vop2);
3715         if (ret)
3716                 return ret;
3717
3718         ret = vop2_find_rgb_encoder(vop2);
3719         if (ret >= 0) {
3720                 vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc,
3721                                               vop2->drm, ret);
3722                 if (IS_ERR(vop2->rgb)) {
3723                         if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) {
3724                                 ret = PTR_ERR(vop2->rgb);
3725                                 goto err_crtcs;
3726                         }
3727                         vop2->rgb = NULL;
3728                 }
3729         }
3730
3731         rockchip_drm_dma_init_device(vop2->drm, vop2->dev);
3732
3733         pm_runtime_enable(&pdev->dev);
3734
3735         return 0;
3736
3737 err_crtcs:
3738         vop2_destroy_crtcs(vop2);
3739
3740         return ret;
3741 }
3742
3743 static void vop2_unbind(struct device *dev, struct device *master, void *data)
3744 {
3745         struct vop2 *vop2 = dev_get_drvdata(dev);
3746
3747         pm_runtime_disable(dev);
3748
3749         if (vop2->rgb)
3750                 rockchip_rgb_fini(vop2->rgb);
3751
3752         vop2_destroy_crtcs(vop2);
3753 }
3754
3755 const struct component_ops vop2_component_ops = {
3756         .bind = vop2_bind,
3757         .unbind = vop2_unbind,
3758 };
3759 EXPORT_SYMBOL_GPL(vop2_component_ops);