drivers/gpu/drm/i915/gt/uc/intel_guc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2014-2019 Intel Corporation
   4  */
   5
   6 #include "gem/i915_gem_lmem.h"
   7 #include "gt/intel_gt.h"
   8 #include "gt/intel_gt_irq.h"
   9 #include "gt/intel_gt_pm_irq.h"
  10 #include "gt/intel_gt_regs.h"
  11 #include "intel_guc.h"
  12 #include "intel_guc_ads.h"
  13 #include "intel_guc_capture.h"
  14 #include "intel_guc_print.h"
  15 #include "intel_guc_slpc.h"
  16 #include "intel_guc_submission.h"
  17 #include "i915_drv.h"
  18 #include "i915_irq.h"
  19 #include "i915_reg.h"
  20
  21 /**
  22  * DOC: GuC
  23  *
  24  * The GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is
  25  * designed to offload some of the functionality usually performed by the host
  26  * driver; currently the main operations it can take care of are:
  27  *
  28  * - Authentication of the HuC, which is required to fully enable HuC usage.
  29  * - Low latency graphics context scheduling (a.k.a. GuC submission).
  30  * - GT Power management.
  31  *
  32  * The enable_guc module parameter can be used to select which of those
  33  * operations to enable within GuC. Note that not all the operations are
  34  * supported on all gen9+ platforms.
  35  *
  36  * Enabling the GuC is not mandatory and therefore the firmware is only loaded
  37  * if at least one of the operations is selected. However, not loading the GuC
  38  * might result in the loss of some features that do require the GuC (currently
  39  * just the HuC, but more are expected to land in the future).
  40  */
  41
  42 void intel_guc_notify(struct intel_guc *guc)
  43 {
  44         struct intel_gt *gt = guc_to_gt(guc);
  45
  46         /*
  47          * On Gen11+, the value written to the register is passes as a payload
  48          * to the FW. However, the FW currently treats all values the same way
  49          * (H2G interrupt), so we can just write the value that the HW expects
  50          * on older gens.
  51          */
  52         intel_uncore_write(gt->uncore, guc->notify_reg, GUC_SEND_TRIGGER);
  53 }
  54
  55 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
  56 {
  57         GEM_BUG_ON(!guc->send_regs.base);
  58         GEM_BUG_ON(!guc->send_regs.count);
  59         GEM_BUG_ON(i >= guc->send_regs.count);
  60
  61         return _MMIO(guc->send_regs.base + 4 * i);
  62 }
  63
  64 void intel_guc_init_send_regs(struct intel_guc *guc)
  65 {
  66         struct intel_gt *gt = guc_to_gt(guc);
  67         enum forcewake_domains fw_domains = 0;
  68         unsigned int i;
  69
  70         GEM_BUG_ON(!guc->send_regs.base);
  71         GEM_BUG_ON(!guc->send_regs.count);
  72
  73         for (i = 0; i < guc->send_regs.count; i++) {
  74                 fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore,
  75                                         guc_send_reg(guc, i),
  76                                         FW_REG_READ | FW_REG_WRITE);
  77         }
  78         guc->send_regs.fw_domains = fw_domains;
  79 }
  80
  81 static void gen9_reset_guc_interrupts(struct intel_guc *guc)
  82 {
  83         struct intel_gt *gt = guc_to_gt(guc);
  84
  85         assert_rpm_wakelock_held(&gt->i915->runtime_pm);
  86
  87         spin_lock_irq(gt->irq_lock);
  88         gen6_gt_pm_reset_iir(gt, gt->pm_guc_events);
  89         spin_unlock_irq(gt->irq_lock);
  90 }
  91
  92 static void gen9_enable_guc_interrupts(struct intel_guc *guc)
  93 {
  94         struct intel_gt *gt = guc_to_gt(guc);
  95
  96         assert_rpm_wakelock_held(&gt->i915->runtime_pm);
  97
  98         spin_lock_irq(gt->irq_lock);
  99         guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
 100                          gt->pm_guc_events);
 101         gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
 102         spin_unlock_irq(gt->irq_lock);
 103
 104         guc->interrupts.enabled = true;
 105 }
 106
 107 static void gen9_disable_guc_interrupts(struct intel_guc *guc)
 108 {
 109         struct intel_gt *gt = guc_to_gt(guc);
 110
 111         assert_rpm_wakelock_held(&gt->i915->runtime_pm);
 112         guc->interrupts.enabled = false;
 113
 114         spin_lock_irq(gt->irq_lock);
 115
 116         gen6_gt_pm_disable_irq(gt, gt->pm_guc_events);
 117
 118         spin_unlock_irq(gt->irq_lock);
 119         intel_synchronize_irq(gt->i915);
 120
 121         gen9_reset_guc_interrupts(guc);
 122 }
 123
 124 static bool __gen11_reset_guc_interrupts(struct intel_gt *gt)
 125 {
 126         u32 irq = gt->type == GT_MEDIA ? MTL_MGUC : GEN11_GUC;
 127
 128         lockdep_assert_held(gt->irq_lock);
 129         return gen11_gt_reset_one_iir(gt, 0, irq);
 130 }
 131
 132 static void gen11_reset_guc_interrupts(struct intel_guc *guc)
 133 {
 134         struct intel_gt *gt = guc_to_gt(guc);
 135
 136         spin_lock_irq(gt->irq_lock);
 137         __gen11_reset_guc_interrupts(gt);
 138         spin_unlock_irq(gt->irq_lock);
 139 }
 140
 141 static void gen11_enable_guc_interrupts(struct intel_guc *guc)
 142 {
 143         struct intel_gt *gt = guc_to_gt(guc);
 144
 145         spin_lock_irq(gt->irq_lock);
 146         __gen11_reset_guc_interrupts(gt);
 147         spin_unlock_irq(gt->irq_lock);
 148
 149         guc->interrupts.enabled = true;
 150 }
 151
 152 static void gen11_disable_guc_interrupts(struct intel_guc *guc)
 153 {
 154         struct intel_gt *gt = guc_to_gt(guc);
 155
 156         guc->interrupts.enabled = false;
 157         intel_synchronize_irq(gt->i915);
 158
 159         gen11_reset_guc_interrupts(guc);
 160 }
 161
 162 void intel_guc_init_early(struct intel_guc *guc)
 163 {
 164         struct intel_gt *gt = guc_to_gt(guc);
 165         struct drm_i915_private *i915 = gt->i915;
 166
 167         intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, true);
 168         intel_guc_ct_init_early(&guc->ct);
 169         intel_guc_log_init_early(&guc->log);
 170         intel_guc_submission_init_early(guc);
 171         intel_guc_slpc_init_early(&guc->slpc);
 172         intel_guc_rc_init_early(guc);
 173
 174         mutex_init(&guc->send_mutex);
 175         spin_lock_init(&guc->irq_lock);
 176         if (GRAPHICS_VER(i915) >= 11) {
 177                 guc->interrupts.reset = gen11_reset_guc_interrupts;
 178                 guc->interrupts.enable = gen11_enable_guc_interrupts;
 179                 guc->interrupts.disable = gen11_disable_guc_interrupts;
 180                 if (gt->type == GT_MEDIA) {
 181                         guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT;
 182                         guc->send_regs.base = i915_mmio_reg_offset(MEDIA_SOFT_SCRATCH(0));
 183                 } else {
 184                         guc->notify_reg = GEN11_GUC_HOST_INTERRUPT;
 185                         guc->send_regs.base = i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
 186                 }
 187
 188                 guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
 189
 190         } else {
 191                 guc->notify_reg = GUC_SEND_INTERRUPT;
 192                 guc->interrupts.reset = gen9_reset_guc_interrupts;
 193                 guc->interrupts.enable = gen9_enable_guc_interrupts;
 194                 guc->interrupts.disable = gen9_disable_guc_interrupts;
 195                 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
 196                 guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
 197                 BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
 198         }
 199
 200         intel_guc_enable_msg(guc, INTEL_GUC_RECV_MSG_EXCEPTION |
 201                                   INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
 202 }
 203
 204 void intel_guc_init_late(struct intel_guc *guc)
 205 {
 206         intel_guc_ads_init_late(guc);
 207 }
 208
 209 static u32 guc_ctl_debug_flags(struct intel_guc *guc)
 210 {
 211         u32 level = intel_guc_log_get_level(&guc->log);
 212         u32 flags = 0;
 213
 214         if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
 215                 flags |= GUC_LOG_DISABLED;
 216         else
 217                 flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
 218                          GUC_LOG_VERBOSITY_SHIFT;
 219
 220         return flags;
 221 }
 222
 223 static u32 guc_ctl_feature_flags(struct intel_guc *guc)
 224 {
 225         u32 flags = 0;
 226
 227         if (!intel_guc_submission_is_used(guc))
 228                 flags |= GUC_CTL_DISABLE_SCHEDULER;
 229
 230         if (intel_guc_slpc_is_used(guc))
 231                 flags |= GUC_CTL_ENABLE_SLPC;
 232
 233         return flags;
 234 }
 235
 236 static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
 237 {
 238         struct intel_guc_log *log = &guc->log;
 239         u32 offset, flags;
 240
 241         GEM_BUG_ON(!log->sizes_initialised);
 242
 243         offset = intel_guc_ggtt_offset(guc, log->vma) >> PAGE_SHIFT;
 244
 245         flags = GUC_LOG_VALID |
 246                 GUC_LOG_NOTIFY_ON_HALF_FULL |
 247                 log->sizes[GUC_LOG_SECTIONS_DEBUG].flag |
 248                 log->sizes[GUC_LOG_SECTIONS_CAPTURE].flag |
 249                 (log->sizes[GUC_LOG_SECTIONS_CRASH].count << GUC_LOG_CRASH_SHIFT) |
 250                 (log->sizes[GUC_LOG_SECTIONS_DEBUG].count << GUC_LOG_DEBUG_SHIFT) |
 251                 (log->sizes[GUC_LOG_SECTIONS_CAPTURE].count << GUC_LOG_CAPTURE_SHIFT) |
 252                 (offset << GUC_LOG_BUF_ADDR_SHIFT);
 253
 254         return flags;
 255 }
 256
 257 static u32 guc_ctl_ads_flags(struct intel_guc *guc)
 258 {
 259         u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
 260         u32 flags = ads << GUC_ADS_ADDR_SHIFT;
 261
 262         return flags;
 263 }
 264
 265 static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 266 {
 267         struct intel_gt *gt = guc_to_gt(guc);
 268         u32 flags = 0;
 269
 270         /* Wa_22012773006:gen11,gen12 < XeHP */
 271         if (GRAPHICS_VER(gt->i915) >= 11 &&
 272             GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50))
 273                 flags |= GUC_WA_POLLCS;
 274
 275         /* Wa_16011759253:dg2_g10:a0 */
 276         if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))
 277                 flags |= GUC_WA_GAM_CREDITS;
 278
 279         /* Wa_14014475959 */
 280         if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
 281             IS_DG2(gt->i915))
 282                 flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
 283
 284         /*
 285          * Wa_14012197797:dg2_g10:a0,dg2_g11:a0
 286          * Wa_22011391025:dg2_g10,dg2_g11,dg2_g12
 287          *
 288          * The same WA bit is used for both and 22011391025 is applicable to
 289          * all DG2.
 290          */
 291         if (IS_DG2(gt->i915))
 292                 flags |= GUC_WA_DUAL_QUEUE;
 293
 294         /* Wa_22011802037: graphics version 11/12 */
 295         if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
 296             (GRAPHICS_VER(gt->i915) >= 11 &&
 297             GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
 298                 flags |= GUC_WA_PRE_PARSER;
 299
 300         /* Wa_16011777198:dg2 */
 301         if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
 302             IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
 303                 flags |= GUC_WA_RCS_RESET_BEFORE_RC6;
 304
 305         /*
 306          * Wa_22012727170:dg2_g10[a0-c0), dg2_g11[a0..)
 307          * Wa_22012727685:dg2_g11[a0..)
 308          */
 309         if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
 310             IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER))
 311                 flags |= GUC_WA_CONTEXT_ISOLATION;
 312
 313         /* Wa_16015675438 */
 314         if (!RCS_MASK(gt))
 315                 flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
 316
 317         return flags;
 318 }
 319
 320 static u32 guc_ctl_devid(struct intel_guc *guc)
 321 {
 322         struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
 323
 324         return (INTEL_DEVID(i915) << 16) | INTEL_REVID(i915);
 325 }
 326
 327 /*
 328  * Initialise the GuC parameter block before starting the firmware
 329  * transfer. These parameters are read by the firmware on startup
 330  * and cannot be changed thereafter.
 331  */
 332 static void guc_init_params(struct intel_guc *guc)
 333 {
 334         u32 *params = guc->params;
 335         int i;
 336
 337         BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32));
 338
 339         params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
 340         params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
 341         params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
 342         params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
 343         params[GUC_CTL_WA] = guc_ctl_wa_flags(guc);
 344         params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
 345
 346         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 347                 guc_dbg(guc, "param[%2d] = %#x\n", i, params[i]);
 348 }
 349
 350 /*
 351  * Initialise the GuC parameter block before starting the firmware
 352  * transfer. These parameters are read by the firmware on startup
 353  * and cannot be changed thereafter.
 354  */
 355 void intel_guc_write_params(struct intel_guc *guc)
 356 {
 357         struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
 358         int i;
 359
 360         /*
 361          * All SOFT_SCRATCH registers are in FORCEWAKE_GT domain and
 362          * they are power context saved so it's ok to release forcewake
 363          * when we are done here and take it again at xfer time.
 364          */
 365         intel_uncore_forcewake_get(uncore, FORCEWAKE_GT);
 366
 367         intel_uncore_write(uncore, SOFT_SCRATCH(0), 0);
 368
 369         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 370                 intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), guc->params[i]);
 371
 372         intel_uncore_forcewake_put(uncore, FORCEWAKE_GT);
 373 }
 374
 375 void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p)
 376 {
 377         struct intel_gt *gt = guc_to_gt(guc);
 378         intel_wakeref_t wakeref;
 379         u32 stamp = 0;
 380         u64 ktime;
 381
 382         with_intel_runtime_pm(&gt->i915->runtime_pm, wakeref)
 383                 stamp = intel_uncore_read(gt->uncore, GUCPMTIMESTAMP);
 384         ktime = ktime_get_boottime_ns();
 385
 386         drm_printf(p, "Kernel timestamp: 0x%08llX [%llu]\n", ktime, ktime);
 387         drm_printf(p, "GuC timestamp: 0x%08X [%u]\n", stamp, stamp);
 388         drm_printf(p, "CS timestamp frequency: %u Hz, %u ns\n",
 389                    gt->clock_frequency, gt->clock_period_ns);
 390 }
 391
 392 int intel_guc_init(struct intel_guc *guc)
 393 {
 394         int ret;
 395
 396         ret = intel_uc_fw_init(&guc->fw);
 397         if (ret)
 398                 goto out;
 399
 400         ret = intel_guc_log_create(&guc->log);
 401         if (ret)
 402                 goto err_fw;
 403
 404         ret = intel_guc_capture_init(guc);
 405         if (ret)
 406                 goto err_log;
 407
 408         ret = intel_guc_ads_create(guc);
 409         if (ret)
 410                 goto err_capture;
 411
 412         GEM_BUG_ON(!guc->ads_vma);
 413
 414         ret = intel_guc_ct_init(&guc->ct);
 415         if (ret)
 416                 goto err_ads;
 417
 418         if (intel_guc_submission_is_used(guc)) {
 419                 /*
 420                  * This is stuff we need to have available at fw load time
 421                  * if we are planning to enable submission later
 422                  */
 423                 ret = intel_guc_submission_init(guc);
 424                 if (ret)
 425                         goto err_ct;
 426         }
 427
 428         if (intel_guc_slpc_is_used(guc)) {
 429                 ret = intel_guc_slpc_init(&guc->slpc);
 430                 if (ret)
 431                         goto err_submission;
 432         }
 433
 434         /* now that everything is perma-pinned, initialize the parameters */
 435         guc_init_params(guc);
 436
 437         intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_LOADABLE);
 438
 439         return 0;
 440
 441 err_submission:
 442         intel_guc_submission_fini(guc);
 443 err_ct:
 444         intel_guc_ct_fini(&guc->ct);
 445 err_ads:
 446         intel_guc_ads_destroy(guc);
 447 err_capture:
 448         intel_guc_capture_destroy(guc);
 449 err_log:
 450         intel_guc_log_destroy(&guc->log);
 451 err_fw:
 452         intel_uc_fw_fini(&guc->fw);
 453 out:
 454         intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
 455         guc_probe_error(guc, "failed with %pe\n", ERR_PTR(ret));
 456         return ret;
 457 }
 458
 459 void intel_guc_fini(struct intel_guc *guc)
 460 {
 461         if (!intel_uc_fw_is_loadable(&guc->fw))
 462                 return;
 463
 464         if (intel_guc_slpc_is_used(guc))
 465                 intel_guc_slpc_fini(&guc->slpc);
 466
 467         if (intel_guc_submission_is_used(guc))
 468                 intel_guc_submission_fini(guc);
 469
 470         intel_guc_ct_fini(&guc->ct);
 471
 472         intel_guc_ads_destroy(guc);
 473         intel_guc_capture_destroy(guc);
 474         intel_guc_log_destroy(&guc->log);
 475         intel_uc_fw_fini(&guc->fw);
 476 }
 477
 478 /*
 479  * This function implements the MMIO based host to GuC interface.
 480  */
 481 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
 482                         u32 *response_buf, u32 response_buf_size)
 483 {
 484         struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
 485         u32 header;
 486         int i;
 487         int ret;
 488
 489         GEM_BUG_ON(!len);
 490         GEM_BUG_ON(len > guc->send_regs.count);
 491
 492         GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) != GUC_HXG_ORIGIN_HOST);
 493         GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) != GUC_HXG_TYPE_REQUEST);
 494
 495         mutex_lock(&guc->send_mutex);
 496         intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains);
 497
 498 retry:
 499         for (i = 0; i < len; i++)
 500                 intel_uncore_write(uncore, guc_send_reg(guc, i), request[i]);
 501
 502         intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1));
 503
 504         intel_guc_notify(guc);
 505
 506         /*
 507          * No GuC command should ever take longer than 10ms.
 508          * Fast commands should still complete in 10us.
 509          */
 510         ret = __intel_wait_for_register_fw(uncore,
 511                                            guc_send_reg(guc, 0),
 512                                            GUC_HXG_MSG_0_ORIGIN,
 513                                            FIELD_PREP(GUC_HXG_MSG_0_ORIGIN,
 514                                                       GUC_HXG_ORIGIN_GUC),
 515                                            10, 10, &header);
 516         if (unlikely(ret)) {
 517 timeout:
 518                 guc_err(guc, "mmio request %#x: no reply %x\n",
 519                         request[0], header);
 520                 goto out;
 521         }
 522
 523         if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_BUSY) {
 524 #define done ({ header = intel_uncore_read(uncore, guc_send_reg(guc, 0)); \
 525                 FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != GUC_HXG_ORIGIN_GUC || \
 526                 FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_NO_RESPONSE_BUSY; })
 527
 528                 ret = wait_for(done, 1000);
 529                 if (unlikely(ret))
 530                         goto timeout;
 531                 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=
 532                                        GUC_HXG_ORIGIN_GUC))
 533                         goto proto;
 534 #undef done
 535         }
 536
 537         if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
 538                 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
 539
 540                 guc_dbg(guc, "mmio request %#x: retrying, reason %u\n",
 541                         request[0], reason);
 542                 goto retry;
 543         }
 544
 545         if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_RESPONSE_FAILURE) {
 546                 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
 547                 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
 548
 549                 guc_err(guc, "mmio request %#x: failure %x/%u\n",
 550                         request[0], error, hint);
 551                 ret = -ENXIO;
 552                 goto out;
 553         }
 554
 555         if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) {
 556 proto:
 557                 guc_err(guc, "mmio request %#x: unexpected reply %#x\n",
 558                         request[0], header);
 559                 ret = -EPROTO;
 560                 goto out;
 561         }
 562
 563         if (response_buf) {
 564                 int count = min(response_buf_size, guc->send_regs.count);
 565
 566                 GEM_BUG_ON(!count);
 567
 568                 response_buf[0] = header;
 569
 570                 for (i = 1; i < count; i++)
 571                         response_buf[i] = intel_uncore_read(uncore,
 572                                                             guc_send_reg(guc, i));
 573
 574                 /* Use number of copied dwords as our return value */
 575                 ret = count;
 576         } else {
 577                 /* Use data from the GuC response as our return value */
 578                 ret = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header);
 579         }
 580
 581 out:
 582         intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains);
 583         mutex_unlock(&guc->send_mutex);
 584
 585         return ret;
 586 }
 587
 588 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
 589                                        const u32 *payload, u32 len)
 590 {
 591         u32 msg;
 592
 593         if (unlikely(!len))
 594                 return -EPROTO;
 595
 596         /* Make sure to handle only enabled messages */
 597         msg = payload[0] & guc->msg_enabled_mask;
 598
 599         if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
 600                 guc_err(guc, "Received early crash dump notification!\n");
 601         if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
 602                 guc_err(guc, "Received early exception notification!\n");
 603
 604         return 0;
 605 }
 606
 607 /**
 608  * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
 609  * @guc: intel_guc structure
 610  * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
 611  *
 612  * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
 613  * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
 614  * intel_huc_auth().
 615  *
 616  * Return:      non-zero code on error
 617  */
 618 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
 619 {
 620         u32 action[] = {
 621                 INTEL_GUC_ACTION_AUTHENTICATE_HUC,
 622                 rsa_offset
 623         };
 624
 625         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 626 }
 627
 628 /**
 629  * intel_guc_suspend() - notify GuC entering suspend state
 630  * @guc:        the guc
 631  */
 632 int intel_guc_suspend(struct intel_guc *guc)
 633 {
 634         int ret;
 635         u32 action[] = {
 636                 INTEL_GUC_ACTION_CLIENT_SOFT_RESET,
 637         };
 638
 639         if (!intel_guc_is_ready(guc))
 640                 return 0;
 641
 642         if (intel_guc_submission_is_used(guc)) {
 643                 /*
 644                  * This H2G MMIO command tears down the GuC in two steps. First it will
 645                  * generate a G2H CTB for every active context indicating a reset. In
 646                  * practice the i915 shouldn't ever get a G2H as suspend should only be
 647                  * called when the GPU is idle. Next, it tears down the CTBs and this
 648                  * H2G MMIO command completes.
 649                  *
 650                  * Don't abort on a failure code from the GuC. Keep going and do the
 651                  * clean up in santize() and re-initialisation on resume and hopefully
 652                  * the error here won't be problematic.
 653                  */
 654                 ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
 655                 if (ret)
 656                         guc_err(guc, "suspend: RESET_CLIENT action failed with %pe\n",
 657                                 ERR_PTR(ret));
 658         }
 659
 660         /* Signal that the GuC isn't running. */
 661         intel_guc_sanitize(guc);
 662
 663         return 0;
 664 }
 665
 666 /**
 667  * intel_guc_resume() - notify GuC resuming from suspend state
 668  * @guc:        the guc
 669  */
 670 int intel_guc_resume(struct intel_guc *guc)
 671 {
 672         /*
 673          * NB: This function can still be called even if GuC submission is
 674          * disabled, e.g. if GuC is enabled for HuC authentication only. Thus,
 675          * if any code is later added here, it must be support doing nothing
 676          * if submission is disabled (as per intel_guc_suspend).
 677          */
 678         return 0;
 679 }
 680
 681 /**
 682  * DOC: GuC Memory Management
 683  *
 684  * GuC can't allocate any memory for its own usage, so all the allocations must
 685  * be handled by the host driver. GuC accesses the memory via the GGTT, with the
 686  * exception of the top and bottom parts of the 4GB address space, which are
 687  * instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM)
 688  * or other parts of the HW. The driver must take care not to place objects that
 689  * the GuC is going to access in these reserved ranges. The layout of the GuC
 690  * address space is shown below:
 691  *
 692  * ::
 693  *
 694  *     +===========> +====================+ <== FFFF_FFFF
 695  *     ^             |      Reserved      |
 696  *     |             +====================+ <== GUC_GGTT_TOP
 697  *     |             |                    |
 698  *     |             |        DRAM        |
 699  *    GuC            |                    |
 700  *  Address    +===> +====================+ <== GuC ggtt_pin_bias
 701  *   Space     ^     |                    |
 702  *     |       |     |                    |
 703  *     |      GuC    |        GuC         |
 704  *     |     WOPCM   |       WOPCM        |
 705  *     |      Size   |                    |
 706  *     |       |     |                    |
 707  *     v       v     |                    |
 708  *     +=======+===> +====================+ <== 0000_0000
 709  *
 710  * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM
 711  * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
 712  * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
 713  */
 714
 715 /**
 716  * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
 717  * @guc:        the guc
 718  * @size:       size of area to allocate (both virtual space and memory)
 719  *
 720  * This is a wrapper to create an object for use with the GuC. In order to
 721  * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
 722  * both some backing storage and a range inside the Global GTT. We must pin
 723  * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that
 724  * range is reserved inside GuC.
 725  *
 726  * Return:      A i915_vma if successful, otherwise an ERR_PTR.
 727  */
 728 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 729 {
 730         struct intel_gt *gt = guc_to_gt(guc);
 731         struct drm_i915_gem_object *obj;
 732         struct i915_vma *vma;
 733         u64 flags;
 734         int ret;
 735
 736         if (HAS_LMEM(gt->i915))
 737                 obj = i915_gem_object_create_lmem(gt->i915, size,
 738                                                   I915_BO_ALLOC_CPU_CLEAR |
 739                                                   I915_BO_ALLOC_CONTIGUOUS |
 740                                                   I915_BO_ALLOC_PM_EARLY);
 741         else
 742                 obj = i915_gem_object_create_shmem(gt->i915, size);
 743
 744         if (IS_ERR(obj))
 745                 return ERR_CAST(obj);
 746
 747         /*
 748          * Wa_22016122933: For MTL the shared memory needs to be mapped
 749          * as WC on CPU side and UC (PAT index 2) on GPU side
 750          */
 751         if (IS_METEORLAKE(gt->i915))
 752                 i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
 753
 754         vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 755         if (IS_ERR(vma))
 756                 goto err;
 757
 758         flags = PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
 759         ret = i915_ggtt_pin(vma, NULL, 0, flags);
 760         if (ret) {
 761                 vma = ERR_PTR(ret);
 762                 goto err;
 763         }
 764
 765         return i915_vma_make_unshrinkable(vma);
 766
 767 err:
 768         i915_gem_object_put(obj);
 769         return vma;
 770 }
 771
 772 /**
 773  * intel_guc_allocate_and_map_vma() - Allocate and map VMA for GuC usage
 774  * @guc:        the guc
 775  * @size:       size of area to allocate (both virtual space and memory)
 776  * @out_vma:    return variable for the allocated vma pointer
 777  * @out_vaddr:  return variable for the obj mapping
 778  *
 779  * This wrapper calls intel_guc_allocate_vma() and then maps the allocated
 780  * object with I915_MAP_WB.
 781  *
 782  * Return:      0 if successful, a negative errno code otherwise.
 783  */
 784 int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size,
 785                                    struct i915_vma **out_vma, void **out_vaddr)
 786 {
 787         struct i915_vma *vma;
 788         void *vaddr;
 789
 790         vma = intel_guc_allocate_vma(guc, size);
 791         if (IS_ERR(vma))
 792                 return PTR_ERR(vma);
 793
 794         vaddr = i915_gem_object_pin_map_unlocked(vma->obj,
 795                                                  i915_coherent_map_type(guc_to_gt(guc)->i915,
 796                                                                         vma->obj, true));
 797         if (IS_ERR(vaddr)) {
 798                 i915_vma_unpin_and_release(&vma, 0);
 799                 return PTR_ERR(vaddr);
 800         }
 801
 802         *out_vma = vma;
 803         *out_vaddr = vaddr;
 804
 805         return 0;
 806 }
 807
 808 static int __guc_action_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
 809 {
 810         u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = {
 811                 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |
 812                 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) |
 813                 FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, GUC_ACTION_HOST2GUC_SELF_CFG),
 814                 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) |
 815                 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len),
 816                 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, lower_32_bits(value)),
 817                 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, upper_32_bits(value)),
 818         };
 819         int ret;
 820
 821         GEM_BUG_ON(len > 2);
 822         GEM_BUG_ON(len == 1 && upper_32_bits(value));
 823
 824         /* Self config must go over MMIO */
 825         ret = intel_guc_send_mmio(guc, request, ARRAY_SIZE(request), NULL, 0);
 826
 827         if (unlikely(ret < 0))
 828                 return ret;
 829         if (unlikely(ret > 1))
 830                 return -EPROTO;
 831         if (unlikely(!ret))
 832                 return -ENOKEY;
 833
 834         return 0;
 835 }
 836
 837 static int __guc_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
 838 {
 839         int err = __guc_action_self_cfg(guc, key, len, value);
 840
 841         if (unlikely(err))
 842                 guc_probe_error(guc, "Unsuccessful self-config (%pe) key %#hx value %#llx\n",
 843                                 ERR_PTR(err), key, value);
 844         return err;
 845 }
 846
 847 int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value)
 848 {
 849         return __guc_self_cfg(guc, key, 1, value);
 850 }
 851
 852 int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value)
 853 {
 854         return __guc_self_cfg(guc, key, 2, value);
 855 }
 856
 857 /**
 858  * intel_guc_load_status - dump information about GuC load status
 859  * @guc: the GuC
 860  * @p: the &drm_printer
 861  *
 862  * Pretty printer for GuC load status.
 863  */
 864 void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p)
 865 {
 866         struct intel_gt *gt = guc_to_gt(guc);
 867         struct intel_uncore *uncore = gt->uncore;
 868         intel_wakeref_t wakeref;
 869
 870         if (!intel_guc_is_supported(guc)) {
 871                 drm_printf(p, "GuC not supported\n");
 872                 return;
 873         }
 874
 875         if (!intel_guc_is_wanted(guc)) {
 876                 drm_printf(p, "GuC disabled\n");
 877                 return;
 878         }
 879
 880         intel_uc_fw_dump(&guc->fw, p);
 881
 882         with_intel_runtime_pm(uncore->rpm, wakeref) {
 883                 u32 status = intel_uncore_read(uncore, GUC_STATUS);
 884                 u32 i;
 885
 886                 drm_printf(p, "GuC status 0x%08x:\n", status);
 887                 drm_printf(p, "\tBootrom status = 0x%x\n",
 888                            (status & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
 889                 drm_printf(p, "\tuKernel status = 0x%x\n",
 890                            (status & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
 891                 drm_printf(p, "\tMIA Core status = 0x%x\n",
 892                            (status & GS_MIA_MASK) >> GS_MIA_SHIFT);
 893                 drm_puts(p, "Scratch registers:\n");
 894                 for (i = 0; i < 16; i++) {
 895                         drm_printf(p, "\t%2d: \t0x%x\n",
 896                                    i, intel_uncore_read(uncore, SOFT_SCRATCH(i)));
 897                 }
 898         }
 899 }
 900
 901 void intel_guc_write_barrier(struct intel_guc *guc)
 902 {
 903         struct intel_gt *gt = guc_to_gt(guc);
 904
 905         if (i915_gem_object_is_lmem(guc->ct.vma->obj)) {
 906                 /*
 907                  * Ensure intel_uncore_write_fw can be used rather than
 908                  * intel_uncore_write.
 909                  */
 910                 GEM_BUG_ON(guc->send_regs.fw_domains);
 911
 912                 /*
 913                  * This register is used by the i915 and GuC for MMIO based
 914                  * communication. Once we are in this code CTBs are the only
 915                  * method the i915 uses to communicate with the GuC so it is
 916                  * safe to write to this register (a value of 0 is NOP for MMIO
 917                  * communication). If we ever start mixing CTBs and MMIOs a new
 918                  * register will have to be chosen. This function is also used
 919                  * to enforce ordering of a work queue item write and an update
 920                  * to the process descriptor. When a work queue is being used,
 921                  * CTBs are also the only mechanism of communication.
 922                  */
 923                 intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0);
 924         } else {
 925                 /* wmb() sufficient for a barrier if in smem */
 926                 wmb();
 927         }
 928 }