1 // SPDX-License-Identifier: MIT
3 * Copyright © 2014-2019 Intel Corporation
6 #include "gem/i915_gem_lmem.h"
7 #include "gt/intel_gt.h"
8 #include "gt/intel_gt_irq.h"
9 #include "gt/intel_gt_pm_irq.h"
10 #include "gt/intel_gt_regs.h"
11 #include "intel_guc.h"
12 #include "intel_guc_ads.h"
13 #include "intel_guc_capture.h"
14 #include "intel_guc_print.h"
15 #include "intel_guc_slpc.h"
16 #include "intel_guc_submission.h"
24 * The GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is
25 * designed to offload some of the functionality usually performed by the host
26 * driver; currently the main operations it can take care of are:
28 * - Authentication of the HuC, which is required to fully enable HuC usage.
29 * - Low latency graphics context scheduling (a.k.a. GuC submission).
30 * - GT Power management.
32 * The enable_guc module parameter can be used to select which of those
33 * operations to enable within GuC. Note that not all the operations are
34 * supported on all gen9+ platforms.
36 * Enabling the GuC is not mandatory and therefore the firmware is only loaded
37 * if at least one of the operations is selected. However, not loading the GuC
38 * might result in the loss of some features that do require the GuC (currently
39 * just the HuC, but more are expected to land in the future).
42 void intel_guc_notify(struct intel_guc *guc)
44 struct intel_gt *gt = guc_to_gt(guc);
47 * On Gen11+, the value written to the register is passes as a payload
48 * to the FW. However, the FW currently treats all values the same way
49 * (H2G interrupt), so we can just write the value that the HW expects
52 intel_uncore_write(gt->uncore, guc->notify_reg, GUC_SEND_TRIGGER);
55 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
57 GEM_BUG_ON(!guc->send_regs.base);
58 GEM_BUG_ON(!guc->send_regs.count);
59 GEM_BUG_ON(i >= guc->send_regs.count);
61 return _MMIO(guc->send_regs.base + 4 * i);
64 void intel_guc_init_send_regs(struct intel_guc *guc)
66 struct intel_gt *gt = guc_to_gt(guc);
67 enum forcewake_domains fw_domains = 0;
70 GEM_BUG_ON(!guc->send_regs.base);
71 GEM_BUG_ON(!guc->send_regs.count);
73 for (i = 0; i < guc->send_regs.count; i++) {
74 fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore,
76 FW_REG_READ | FW_REG_WRITE);
78 guc->send_regs.fw_domains = fw_domains;
81 static void gen9_reset_guc_interrupts(struct intel_guc *guc)
83 struct intel_gt *gt = guc_to_gt(guc);
85 assert_rpm_wakelock_held(>->i915->runtime_pm);
87 spin_lock_irq(gt->irq_lock);
88 gen6_gt_pm_reset_iir(gt, gt->pm_guc_events);
89 spin_unlock_irq(gt->irq_lock);
92 static void gen9_enable_guc_interrupts(struct intel_guc *guc)
94 struct intel_gt *gt = guc_to_gt(guc);
96 assert_rpm_wakelock_held(>->i915->runtime_pm);
98 spin_lock_irq(gt->irq_lock);
99 guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
101 gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
102 spin_unlock_irq(gt->irq_lock);
104 guc->interrupts.enabled = true;
107 static void gen9_disable_guc_interrupts(struct intel_guc *guc)
109 struct intel_gt *gt = guc_to_gt(guc);
111 assert_rpm_wakelock_held(>->i915->runtime_pm);
112 guc->interrupts.enabled = false;
114 spin_lock_irq(gt->irq_lock);
116 gen6_gt_pm_disable_irq(gt, gt->pm_guc_events);
118 spin_unlock_irq(gt->irq_lock);
119 intel_synchronize_irq(gt->i915);
121 gen9_reset_guc_interrupts(guc);
124 static bool __gen11_reset_guc_interrupts(struct intel_gt *gt)
126 u32 irq = gt->type == GT_MEDIA ? MTL_MGUC : GEN11_GUC;
128 lockdep_assert_held(gt->irq_lock);
129 return gen11_gt_reset_one_iir(gt, 0, irq);
132 static void gen11_reset_guc_interrupts(struct intel_guc *guc)
134 struct intel_gt *gt = guc_to_gt(guc);
136 spin_lock_irq(gt->irq_lock);
137 __gen11_reset_guc_interrupts(gt);
138 spin_unlock_irq(gt->irq_lock);
141 static void gen11_enable_guc_interrupts(struct intel_guc *guc)
143 struct intel_gt *gt = guc_to_gt(guc);
145 spin_lock_irq(gt->irq_lock);
146 __gen11_reset_guc_interrupts(gt);
147 spin_unlock_irq(gt->irq_lock);
149 guc->interrupts.enabled = true;
152 static void gen11_disable_guc_interrupts(struct intel_guc *guc)
154 struct intel_gt *gt = guc_to_gt(guc);
156 guc->interrupts.enabled = false;
157 intel_synchronize_irq(gt->i915);
159 gen11_reset_guc_interrupts(guc);
162 static void guc_dead_worker_func(struct work_struct *w)
164 struct intel_guc *guc = container_of(w, struct intel_guc, dead_guc_worker);
165 struct intel_gt *gt = guc_to_gt(guc);
166 unsigned long last = guc->last_dead_guc_jiffies;
167 unsigned long delta = jiffies_to_msecs(jiffies - last);
170 intel_gt_set_wedged(gt);
172 intel_gt_handle_error(gt, ALL_ENGINES, I915_ERROR_CAPTURE, "dead GuC");
173 guc->last_dead_guc_jiffies = jiffies;
177 void intel_guc_init_early(struct intel_guc *guc)
179 struct intel_gt *gt = guc_to_gt(guc);
180 struct drm_i915_private *i915 = gt->i915;
182 intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, true);
183 intel_guc_ct_init_early(&guc->ct);
184 intel_guc_log_init_early(&guc->log);
185 intel_guc_submission_init_early(guc);
186 intel_guc_slpc_init_early(&guc->slpc);
187 intel_guc_rc_init_early(guc);
189 INIT_WORK(&guc->dead_guc_worker, guc_dead_worker_func);
191 mutex_init(&guc->send_mutex);
192 spin_lock_init(&guc->irq_lock);
193 if (GRAPHICS_VER(i915) >= 11) {
194 guc->interrupts.reset = gen11_reset_guc_interrupts;
195 guc->interrupts.enable = gen11_enable_guc_interrupts;
196 guc->interrupts.disable = gen11_disable_guc_interrupts;
197 if (gt->type == GT_MEDIA) {
198 guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT;
199 guc->send_regs.base = i915_mmio_reg_offset(MEDIA_SOFT_SCRATCH(0));
201 guc->notify_reg = GEN11_GUC_HOST_INTERRUPT;
202 guc->send_regs.base = i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
205 guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
208 guc->notify_reg = GUC_SEND_INTERRUPT;
209 guc->interrupts.reset = gen9_reset_guc_interrupts;
210 guc->interrupts.enable = gen9_enable_guc_interrupts;
211 guc->interrupts.disable = gen9_disable_guc_interrupts;
212 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
213 guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
214 BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
217 intel_guc_enable_msg(guc, INTEL_GUC_RECV_MSG_EXCEPTION |
218 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
221 void intel_guc_init_late(struct intel_guc *guc)
223 intel_guc_ads_init_late(guc);
226 static u32 guc_ctl_debug_flags(struct intel_guc *guc)
228 u32 level = intel_guc_log_get_level(&guc->log);
231 if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
232 flags |= GUC_LOG_DISABLED;
234 flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
235 GUC_LOG_VERBOSITY_SHIFT;
240 static u32 guc_ctl_feature_flags(struct intel_guc *guc)
242 struct intel_gt *gt = guc_to_gt(guc);
246 * Enable PXP GuC autoteardown flow.
247 * NB: MTL does things differently.
249 if (HAS_PXP(gt->i915) && !IS_METEORLAKE(gt->i915))
250 flags |= GUC_CTL_ENABLE_GUC_PXP_CTL;
252 if (!intel_guc_submission_is_used(guc))
253 flags |= GUC_CTL_DISABLE_SCHEDULER;
255 if (intel_guc_slpc_is_used(guc))
256 flags |= GUC_CTL_ENABLE_SLPC;
261 static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
263 struct intel_guc_log *log = &guc->log;
266 GEM_BUG_ON(!log->sizes_initialised);
268 offset = intel_guc_ggtt_offset(guc, log->vma) >> PAGE_SHIFT;
270 flags = GUC_LOG_VALID |
271 GUC_LOG_NOTIFY_ON_HALF_FULL |
272 log->sizes[GUC_LOG_SECTIONS_DEBUG].flag |
273 log->sizes[GUC_LOG_SECTIONS_CAPTURE].flag |
274 (log->sizes[GUC_LOG_SECTIONS_CRASH].count << GUC_LOG_CRASH_SHIFT) |
275 (log->sizes[GUC_LOG_SECTIONS_DEBUG].count << GUC_LOG_DEBUG_SHIFT) |
276 (log->sizes[GUC_LOG_SECTIONS_CAPTURE].count << GUC_LOG_CAPTURE_SHIFT) |
277 (offset << GUC_LOG_BUF_ADDR_SHIFT);
282 static u32 guc_ctl_ads_flags(struct intel_guc *guc)
284 u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
285 u32 flags = ads << GUC_ADS_ADDR_SHIFT;
290 static u32 guc_ctl_wa_flags(struct intel_guc *guc)
292 struct intel_gt *gt = guc_to_gt(guc);
295 /* Wa_22012773006:gen11,gen12 < XeHP */
296 if (GRAPHICS_VER(gt->i915) >= 11 &&
297 GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 55))
298 flags |= GUC_WA_POLLCS;
301 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
303 flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
307 if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
308 flags |= GUC_WA_RCS_CCS_SWITCHOUT;
314 * The same WA bit is used for both and 22011391025 is applicable to
317 if (IS_DG2(gt->i915))
318 flags |= GUC_WA_DUAL_QUEUE;
320 /* Wa_22011802037: graphics version 11/12 */
321 if (intel_engine_reset_needs_wa_22011802037(gt))
322 flags |= GUC_WA_PRE_PARSER;
328 if (IS_DG2_G11(gt->i915))
329 flags |= GUC_WA_CONTEXT_ISOLATION;
332 * Wa_14018913170: Applicable to all platforms supported by i915 so
333 * don't bother testing for all X/Y/Z platforms explicitly.
335 if (GUC_FIRMWARE_VER(guc) >= MAKE_GUC_VER(70, 7, 0))
336 flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6;
341 static u32 guc_ctl_devid(struct intel_guc *guc)
343 struct drm_i915_private *i915 = guc_to_i915(guc);
345 return (INTEL_DEVID(i915) << 16) | INTEL_REVID(i915);
349 * Initialise the GuC parameter block before starting the firmware
350 * transfer. These parameters are read by the firmware on startup
351 * and cannot be changed thereafter.
353 static void guc_init_params(struct intel_guc *guc)
355 u32 *params = guc->params;
358 BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32));
360 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
361 params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
362 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
363 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
364 params[GUC_CTL_WA] = guc_ctl_wa_flags(guc);
365 params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
367 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
368 guc_dbg(guc, "param[%2d] = %#x\n", i, params[i]);
372 * Initialise the GuC parameter block before starting the firmware
373 * transfer. These parameters are read by the firmware on startup
374 * and cannot be changed thereafter.
376 void intel_guc_write_params(struct intel_guc *guc)
378 struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
382 * All SOFT_SCRATCH registers are in FORCEWAKE_GT domain and
383 * they are power context saved so it's ok to release forcewake
384 * when we are done here and take it again at xfer time.
386 intel_uncore_forcewake_get(uncore, FORCEWAKE_GT);
388 intel_uncore_write(uncore, SOFT_SCRATCH(0), 0);
390 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
391 intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), guc->params[i]);
393 intel_uncore_forcewake_put(uncore, FORCEWAKE_GT);
396 void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p)
398 struct intel_gt *gt = guc_to_gt(guc);
399 intel_wakeref_t wakeref;
403 with_intel_runtime_pm(>->i915->runtime_pm, wakeref)
404 stamp = intel_uncore_read(gt->uncore, GUCPMTIMESTAMP);
405 ktime = ktime_get_boottime_ns();
407 drm_printf(p, "Kernel timestamp: 0x%08llX [%llu]\n", ktime, ktime);
408 drm_printf(p, "GuC timestamp: 0x%08X [%u]\n", stamp, stamp);
409 drm_printf(p, "CS timestamp frequency: %u Hz, %u ns\n",
410 gt->clock_frequency, gt->clock_period_ns);
413 int intel_guc_init(struct intel_guc *guc)
417 ret = intel_uc_fw_init(&guc->fw);
421 ret = intel_guc_log_create(&guc->log);
425 ret = intel_guc_capture_init(guc);
429 ret = intel_guc_ads_create(guc);
433 GEM_BUG_ON(!guc->ads_vma);
435 ret = intel_guc_ct_init(&guc->ct);
439 if (intel_guc_submission_is_used(guc)) {
441 * This is stuff we need to have available at fw load time
442 * if we are planning to enable submission later
444 ret = intel_guc_submission_init(guc);
449 if (intel_guc_slpc_is_used(guc)) {
450 ret = intel_guc_slpc_init(&guc->slpc);
455 /* now that everything is perma-pinned, initialize the parameters */
456 guc_init_params(guc);
458 intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_LOADABLE);
463 intel_guc_submission_fini(guc);
465 intel_guc_ct_fini(&guc->ct);
467 intel_guc_ads_destroy(guc);
469 intel_guc_capture_destroy(guc);
471 intel_guc_log_destroy(&guc->log);
473 intel_uc_fw_fini(&guc->fw);
475 intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
476 guc_probe_error(guc, "failed with %pe\n", ERR_PTR(ret));
480 void intel_guc_fini(struct intel_guc *guc)
482 if (!intel_uc_fw_is_loadable(&guc->fw))
485 flush_work(&guc->dead_guc_worker);
487 if (intel_guc_slpc_is_used(guc))
488 intel_guc_slpc_fini(&guc->slpc);
490 if (intel_guc_submission_is_used(guc))
491 intel_guc_submission_fini(guc);
493 intel_guc_ct_fini(&guc->ct);
495 intel_guc_ads_destroy(guc);
496 intel_guc_capture_destroy(guc);
497 intel_guc_log_destroy(&guc->log);
498 intel_uc_fw_fini(&guc->fw);
502 * This function implements the MMIO based host to GuC interface.
504 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
505 u32 *response_buf, u32 response_buf_size)
507 struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
513 GEM_BUG_ON(len > guc->send_regs.count);
515 GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) != GUC_HXG_ORIGIN_HOST);
516 GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) != GUC_HXG_TYPE_REQUEST);
518 mutex_lock(&guc->send_mutex);
519 intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains);
522 for (i = 0; i < len; i++)
523 intel_uncore_write(uncore, guc_send_reg(guc, i), request[i]);
525 intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1));
527 intel_guc_notify(guc);
530 * No GuC command should ever take longer than 10ms.
531 * Fast commands should still complete in 10us.
533 ret = __intel_wait_for_register_fw(uncore,
534 guc_send_reg(guc, 0),
535 GUC_HXG_MSG_0_ORIGIN,
536 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN,
541 guc_err(guc, "mmio request %#x: no reply %x\n",
546 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_BUSY) {
547 #define done ({ header = intel_uncore_read(uncore, guc_send_reg(guc, 0)); \
548 FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != GUC_HXG_ORIGIN_GUC || \
549 FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_NO_RESPONSE_BUSY; })
551 ret = wait_for(done, 1000);
554 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=
560 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
561 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
563 guc_dbg(guc, "mmio request %#x: retrying, reason %u\n",
568 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_RESPONSE_FAILURE) {
569 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
570 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
572 guc_err(guc, "mmio request %#x: failure %x/%u\n",
573 request[0], error, hint);
578 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) {
580 guc_err(guc, "mmio request %#x: unexpected reply %#x\n",
587 int count = min(response_buf_size, guc->send_regs.count);
591 response_buf[0] = header;
593 for (i = 1; i < count; i++)
594 response_buf[i] = intel_uncore_read(uncore,
595 guc_send_reg(guc, i));
597 /* Use number of copied dwords as our return value */
600 /* Use data from the GuC response as our return value */
601 ret = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header);
605 intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains);
606 mutex_unlock(&guc->send_mutex);
611 int intel_guc_crash_process_msg(struct intel_guc *guc, u32 action)
613 if (action == INTEL_GUC_ACTION_NOTIFY_CRASH_DUMP_POSTED)
614 guc_err(guc, "Crash dump notification\n");
615 else if (action == INTEL_GUC_ACTION_NOTIFY_EXCEPTION)
616 guc_err(guc, "Exception notification\n");
618 guc_err(guc, "Unknown crash notification: 0x%04X\n", action);
620 queue_work(system_unbound_wq, &guc->dead_guc_worker);
625 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
626 const u32 *payload, u32 len)
633 /* Make sure to handle only enabled messages */
634 msg = payload[0] & guc->msg_enabled_mask;
636 if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
637 guc_err(guc, "Received early crash dump notification!\n");
638 if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
639 guc_err(guc, "Received early exception notification!\n");
641 if (msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED | INTEL_GUC_RECV_MSG_EXCEPTION))
642 queue_work(system_unbound_wq, &guc->dead_guc_worker);
648 * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
649 * @guc: intel_guc structure
650 * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
652 * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
653 * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
656 * Return: non-zero code on error
658 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
661 INTEL_GUC_ACTION_AUTHENTICATE_HUC,
665 return intel_guc_send(guc, action, ARRAY_SIZE(action));
669 * intel_guc_suspend() - notify GuC entering suspend state
672 int intel_guc_suspend(struct intel_guc *guc)
676 INTEL_GUC_ACTION_CLIENT_SOFT_RESET,
679 if (!intel_guc_is_ready(guc))
682 if (intel_guc_submission_is_used(guc)) {
683 flush_work(&guc->dead_guc_worker);
686 * This H2G MMIO command tears down the GuC in two steps. First it will
687 * generate a G2H CTB for every active context indicating a reset. In
688 * practice the i915 shouldn't ever get a G2H as suspend should only be
689 * called when the GPU is idle. Next, it tears down the CTBs and this
690 * H2G MMIO command completes.
692 * Don't abort on a failure code from the GuC. Keep going and do the
693 * clean up in santize() and re-initialisation on resume and hopefully
694 * the error here won't be problematic.
696 ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
698 guc_err(guc, "suspend: RESET_CLIENT action failed with %pe\n",
702 /* Signal that the GuC isn't running. */
703 intel_guc_sanitize(guc);
709 * intel_guc_resume() - notify GuC resuming from suspend state
712 int intel_guc_resume(struct intel_guc *guc)
715 * NB: This function can still be called even if GuC submission is
716 * disabled, e.g. if GuC is enabled for HuC authentication only. Thus,
717 * if any code is later added here, it must be support doing nothing
718 * if submission is disabled (as per intel_guc_suspend).
724 * DOC: GuC Memory Management
726 * GuC can't allocate any memory for its own usage, so all the allocations must
727 * be handled by the host driver. GuC accesses the memory via the GGTT, with the
728 * exception of the top and bottom parts of the 4GB address space, which are
729 * instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM)
730 * or other parts of the HW. The driver must take care not to place objects that
731 * the GuC is going to access in these reserved ranges. The layout of the GuC
732 * address space is shown below:
736 * +===========> +====================+ <== FFFF_FFFF
738 * | +====================+ <== GUC_GGTT_TOP
742 * Address +===> +====================+ <== GuC ggtt_pin_bias
750 * +=======+===> +====================+ <== 0000_0000
752 * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM
753 * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
754 * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
758 * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
760 * @size: size of area to allocate (both virtual space and memory)
762 * This is a wrapper to create an object for use with the GuC. In order to
763 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
764 * both some backing storage and a range inside the Global GTT. We must pin
765 * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that
766 * range is reserved inside GuC.
768 * Return: A i915_vma if successful, otherwise an ERR_PTR.
770 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
772 struct intel_gt *gt = guc_to_gt(guc);
773 struct drm_i915_gem_object *obj;
774 struct i915_vma *vma;
778 if (HAS_LMEM(gt->i915))
779 obj = i915_gem_object_create_lmem(gt->i915, size,
780 I915_BO_ALLOC_CPU_CLEAR |
781 I915_BO_ALLOC_CONTIGUOUS |
782 I915_BO_ALLOC_PM_EARLY);
784 obj = i915_gem_object_create_shmem(gt->i915, size);
787 return ERR_CAST(obj);
790 * Wa_22016122933: For Media version 13.0, all Media GT shared
791 * memory needs to be mapped as WC on CPU side and UC (PAT
792 * index 2) on GPU side.
794 if (intel_gt_needs_wa_22016122933(gt))
795 i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
797 vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
801 flags = PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
802 ret = i915_ggtt_pin(vma, NULL, 0, flags);
808 return i915_vma_make_unshrinkable(vma);
811 i915_gem_object_put(obj);
816 * intel_guc_allocate_and_map_vma() - Allocate and map VMA for GuC usage
818 * @size: size of area to allocate (both virtual space and memory)
819 * @out_vma: return variable for the allocated vma pointer
820 * @out_vaddr: return variable for the obj mapping
822 * This wrapper calls intel_guc_allocate_vma() and then maps the allocated
823 * object with I915_MAP_WB.
825 * Return: 0 if successful, a negative errno code otherwise.
827 int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size,
828 struct i915_vma **out_vma, void **out_vaddr)
830 struct i915_vma *vma;
833 vma = intel_guc_allocate_vma(guc, size);
837 vaddr = i915_gem_object_pin_map_unlocked(vma->obj,
838 intel_gt_coherent_map_type(guc_to_gt(guc),
841 i915_vma_unpin_and_release(&vma, 0);
842 return PTR_ERR(vaddr);
851 static int __guc_action_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
853 u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = {
854 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |
855 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) |
856 FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, GUC_ACTION_HOST2GUC_SELF_CFG),
857 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) |
858 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len),
859 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, lower_32_bits(value)),
860 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, upper_32_bits(value)),
865 GEM_BUG_ON(len == 1 && upper_32_bits(value));
867 /* Self config must go over MMIO */
868 ret = intel_guc_send_mmio(guc, request, ARRAY_SIZE(request), NULL, 0);
870 if (unlikely(ret < 0))
872 if (unlikely(ret > 1))
880 static int __guc_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
882 int err = __guc_action_self_cfg(guc, key, len, value);
885 guc_probe_error(guc, "Unsuccessful self-config (%pe) key %#hx value %#llx\n",
886 ERR_PTR(err), key, value);
890 int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value)
892 return __guc_self_cfg(guc, key, 1, value);
895 int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value)
897 return __guc_self_cfg(guc, key, 2, value);
901 * intel_guc_load_status - dump information about GuC load status
903 * @p: the &drm_printer
905 * Pretty printer for GuC load status.
907 void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p)
909 struct intel_gt *gt = guc_to_gt(guc);
910 struct intel_uncore *uncore = gt->uncore;
911 intel_wakeref_t wakeref;
913 if (!intel_guc_is_supported(guc)) {
914 drm_printf(p, "GuC not supported\n");
918 if (!intel_guc_is_wanted(guc)) {
919 drm_printf(p, "GuC disabled\n");
923 intel_uc_fw_dump(&guc->fw, p);
925 with_intel_runtime_pm(uncore->rpm, wakeref) {
926 u32 status = intel_uncore_read(uncore, GUC_STATUS);
929 drm_printf(p, "GuC status 0x%08x:\n", status);
930 drm_printf(p, "\tBootrom status = 0x%x\n",
931 (status & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
932 drm_printf(p, "\tuKernel status = 0x%x\n",
933 (status & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
934 drm_printf(p, "\tMIA Core status = 0x%x\n",
935 (status & GS_MIA_MASK) >> GS_MIA_SHIFT);
936 drm_puts(p, "Scratch registers:\n");
937 for (i = 0; i < 16; i++) {
938 drm_printf(p, "\t%2d: \t0x%x\n",
939 i, intel_uncore_read(uncore, SOFT_SCRATCH(i)));
944 void intel_guc_write_barrier(struct intel_guc *guc)
946 struct intel_gt *gt = guc_to_gt(guc);
948 if (i915_gem_object_is_lmem(guc->ct.vma->obj)) {
950 * Ensure intel_uncore_write_fw can be used rather than
951 * intel_uncore_write.
953 GEM_BUG_ON(guc->send_regs.fw_domains);
956 * This register is used by the i915 and GuC for MMIO based
957 * communication. Once we are in this code CTBs are the only
958 * method the i915 uses to communicate with the GuC so it is
959 * safe to write to this register (a value of 0 is NOP for MMIO
960 * communication). If we ever start mixing CTBs and MMIOs a new
961 * register will have to be chosen. This function is also used
962 * to enforce ordering of a work queue item write and an update
963 * to the process descriptor. When a work queue is being used,
964 * CTBs are also the only mechanism of communication.
966 intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0);
968 /* wmb() sufficient for a barrier if in smem */