drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_sched.h"
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34
  35 #include <linux/vga_switcheroo.h>
  36 #include <linux/slab.h>
  37 #include <linux/pm_runtime.h>
  38 #include "amdgpu_amdkfd.h"
  39
  40 /**
  41  * amdgpu_driver_unload_kms - Main unload function for KMS.
  42  *
  43  * @dev: drm dev pointer
  44  *
  45  * This is the main unload function for KMS (all asics).
  46  * Returns 0 on success.
  47  */
  48 void amdgpu_driver_unload_kms(struct drm_device *dev)
  49 {
  50         struct amdgpu_device *adev = dev->dev_private;
  51
  52         if (adev == NULL)
  53                 return;
  54
  55         if (adev->rmmio == NULL)
  56                 goto done_free;
  57
  58         if (amdgpu_sriov_vf(adev))
  59                 amdgpu_virt_request_full_gpu(adev, false);
  60
  61         if (amdgpu_device_is_px(dev)) {
  62                 pm_runtime_get_sync(dev->dev);
  63                 pm_runtime_forbid(dev->dev);
  64         }
  65
  66         amdgpu_acpi_fini(adev);
  67
  68         amdgpu_device_fini(adev);
  69
  70 done_free:
  71         kfree(adev);
  72         dev->dev_private = NULL;
  73 }
  74
  75 /**
  76  * amdgpu_driver_load_kms - Main load function for KMS.
  77  *
  78  * @dev: drm dev pointer
  79  * @flags: device flags
  80  *
  81  * This is the main load function for KMS (all asics).
  82  * Returns 0 on success, error on failure.
  83  */
  84 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
  85 {
  86         struct amdgpu_device *adev;
  87         int r, acpi_status;
  88
  89 #ifdef CONFIG_DRM_AMDGPU_SI
  90         if (!amdgpu_si_support) {
  91                 switch (flags & AMD_ASIC_MASK) {
  92                 case CHIP_TAHITI:
  93                 case CHIP_PITCAIRN:
  94                 case CHIP_VERDE:
  95                 case CHIP_OLAND:
  96                 case CHIP_HAINAN:
  97                         dev_info(dev->dev,
  98                                  "SI support provided by radeon.\n");
  99                         dev_info(dev->dev,
 100                                  "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
 101                                 );
 102                         return -ENODEV;
 103                 }
 104         }
 105 #endif
 106 #ifdef CONFIG_DRM_AMDGPU_CIK
 107         if (!amdgpu_cik_support) {
 108                 switch (flags & AMD_ASIC_MASK) {
 109                 case CHIP_KAVERI:
 110                 case CHIP_BONAIRE:
 111                 case CHIP_HAWAII:
 112                 case CHIP_KABINI:
 113                 case CHIP_MULLINS:
 114                         dev_info(dev->dev,
 115                                  "CIK support provided by radeon.\n");
 116                         dev_info(dev->dev,
 117                                  "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
 118                                 );
 119                         return -ENODEV;
 120                 }
 121         }
 122 #endif
 123
 124         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 125         if (adev == NULL) {
 126                 return -ENOMEM;
 127         }
 128         dev->dev_private = (void *)adev;
 129
 130         if ((amdgpu_runtime_pm != 0) &&
 131             amdgpu_has_atpx() &&
 132             (amdgpu_is_atpx_hybrid() ||
 133              amdgpu_has_atpx_dgpu_power_cntl()) &&
 134             ((flags & AMD_IS_APU) == 0) &&
 135             !pci_is_thunderbolt_attached(dev->pdev))
 136                 flags |= AMD_IS_PX;
 137
 138         /* amdgpu_device_init should report only fatal error
 139          * like memory allocation failure or iomapping failure,
 140          * or memory manager initialization failure, it must
 141          * properly initialize the GPU MC controller and permit
 142          * VRAM allocation
 143          */
 144         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 145         if (r) {
 146                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 147                 goto out;
 148         }
 149
 150         /* Call ACPI methods: require modeset init
 151          * but failure is not fatal
 152          */
 153         if (!r) {
 154                 acpi_status = amdgpu_acpi_init(adev);
 155                 if (acpi_status)
 156                 dev_dbg(&dev->pdev->dev,
 157                                 "Error during ACPI methods call\n");
 158         }
 159
 160         if (amdgpu_device_is_px(dev)) {
 161                 pm_runtime_use_autosuspend(dev->dev);
 162                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 163                 pm_runtime_set_active(dev->dev);
 164                 pm_runtime_allow(dev->dev);
 165                 pm_runtime_mark_last_busy(dev->dev);
 166                 pm_runtime_put_autosuspend(dev->dev);
 167         }
 168
 169 out:
 170         if (r) {
 171                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 172                 if (adev->rmmio && amdgpu_device_is_px(dev))
 173                         pm_runtime_put_noidle(dev->dev);
 174                 amdgpu_driver_unload_kms(dev);
 175         }
 176
 177         return r;
 178 }
 179
 180 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 181                                 struct drm_amdgpu_query_fw *query_fw,
 182                                 struct amdgpu_device *adev)
 183 {
 184         switch (query_fw->fw_type) {
 185         case AMDGPU_INFO_FW_VCE:
 186                 fw_info->ver = adev->vce.fw_version;
 187                 fw_info->feature = adev->vce.fb_version;
 188                 break;
 189         case AMDGPU_INFO_FW_UVD:
 190                 fw_info->ver = adev->uvd.fw_version;
 191                 fw_info->feature = 0;
 192                 break;
 193         case AMDGPU_INFO_FW_GMC:
 194                 fw_info->ver = adev->gmc.fw_version;
 195                 fw_info->feature = 0;
 196                 break;
 197         case AMDGPU_INFO_FW_GFX_ME:
 198                 fw_info->ver = adev->gfx.me_fw_version;
 199                 fw_info->feature = adev->gfx.me_feature_version;
 200                 break;
 201         case AMDGPU_INFO_FW_GFX_PFP:
 202                 fw_info->ver = adev->gfx.pfp_fw_version;
 203                 fw_info->feature = adev->gfx.pfp_feature_version;
 204                 break;
 205         case AMDGPU_INFO_FW_GFX_CE:
 206                 fw_info->ver = adev->gfx.ce_fw_version;
 207                 fw_info->feature = adev->gfx.ce_feature_version;
 208                 break;
 209         case AMDGPU_INFO_FW_GFX_RLC:
 210                 fw_info->ver = adev->gfx.rlc_fw_version;
 211                 fw_info->feature = adev->gfx.rlc_feature_version;
 212                 break;
 213         case AMDGPU_INFO_FW_GFX_MEC:
 214                 if (query_fw->index == 0) {
 215                         fw_info->ver = adev->gfx.mec_fw_version;
 216                         fw_info->feature = adev->gfx.mec_feature_version;
 217                 } else if (query_fw->index == 1) {
 218                         fw_info->ver = adev->gfx.mec2_fw_version;
 219                         fw_info->feature = adev->gfx.mec2_feature_version;
 220                 } else
 221                         return -EINVAL;
 222                 break;
 223         case AMDGPU_INFO_FW_SMC:
 224                 fw_info->ver = adev->pm.fw_version;
 225                 fw_info->feature = 0;
 226                 break;
 227         case AMDGPU_INFO_FW_SDMA:
 228                 if (query_fw->index >= adev->sdma.num_instances)
 229                         return -EINVAL;
 230                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 231                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 232                 break;
 233         case AMDGPU_INFO_FW_SOS:
 234                 fw_info->ver = adev->psp.sos_fw_version;
 235                 fw_info->feature = adev->psp.sos_feature_version;
 236                 break;
 237         case AMDGPU_INFO_FW_ASD:
 238                 fw_info->ver = adev->psp.asd_fw_version;
 239                 fw_info->feature = adev->psp.asd_feature_version;
 240                 break;
 241         default:
 242                 return -EINVAL;
 243         }
 244         return 0;
 245 }
 246
 247 /*
 248  * Userspace get information ioctl
 249  */
 250 /**
 251  * amdgpu_info_ioctl - answer a device specific request.
 252  *
 253  * @adev: amdgpu device pointer
 254  * @data: request object
 255  * @filp: drm filp
 256  *
 257  * This function is used to pass device specific parameters to the userspace
 258  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 259  * etc. (all asics).
 260  * Returns 0 on success, -EINVAL on failure.
 261  */
 262 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 263 {
 264         struct amdgpu_device *adev = dev->dev_private;
 265         struct drm_amdgpu_info *info = data;
 266         struct amdgpu_mode_info *minfo = &adev->mode_info;
 267         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 268         uint32_t size = info->return_size;
 269         struct drm_crtc *crtc;
 270         uint32_t ui32 = 0;
 271         uint64_t ui64 = 0;
 272         int i, found;
 273         int ui32_size = sizeof(ui32);
 274
 275         if (!info->return_size || !info->return_pointer)
 276                 return -EINVAL;
 277
 278         switch (info->query) {
 279         case AMDGPU_INFO_ACCEL_WORKING:
 280                 ui32 = adev->accel_working;
 281                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 282         case AMDGPU_INFO_CRTC_FROM_ID:
 283                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 284                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 285                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 286                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 287                                 ui32 = amdgpu_crtc->crtc_id;
 288                                 found = 1;
 289                                 break;
 290                         }
 291                 }
 292                 if (!found) {
 293                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 294                         return -EINVAL;
 295                 }
 296                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 297         case AMDGPU_INFO_HW_IP_INFO: {
 298                 struct drm_amdgpu_info_hw_ip ip = {};
 299                 enum amd_ip_block_type type;
 300                 uint32_t ring_mask = 0;
 301                 uint32_t ib_start_alignment = 0;
 302                 uint32_t ib_size_alignment = 0;
 303
 304                 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 305                         return -EINVAL;
 306
 307                 switch (info->query_hw_ip.type) {
 308                 case AMDGPU_HW_IP_GFX:
 309                         type = AMD_IP_BLOCK_TYPE_GFX;
 310                         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 311                                 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
 312                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 313                         ib_size_alignment = 8;
 314                         break;
 315                 case AMDGPU_HW_IP_COMPUTE:
 316                         type = AMD_IP_BLOCK_TYPE_GFX;
 317                         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 318                                 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
 319                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 320                         ib_size_alignment = 8;
 321                         break;
 322                 case AMDGPU_HW_IP_DMA:
 323                         type = AMD_IP_BLOCK_TYPE_SDMA;
 324                         for (i = 0; i < adev->sdma.num_instances; i++)
 325                                 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
 326                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 327                         ib_size_alignment = 1;
 328                         break;
 329                 case AMDGPU_HW_IP_UVD:
 330                         type = AMD_IP_BLOCK_TYPE_UVD;
 331                         ring_mask = adev->uvd.ring.ready ? 1 : 0;
 332                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 333                         ib_size_alignment = 16;
 334                         break;
 335                 case AMDGPU_HW_IP_VCE:
 336                         type = AMD_IP_BLOCK_TYPE_VCE;
 337                         for (i = 0; i < adev->vce.num_rings; i++)
 338                                 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
 339                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 340                         ib_size_alignment = 1;
 341                         break;
 342                 case AMDGPU_HW_IP_UVD_ENC:
 343                         type = AMD_IP_BLOCK_TYPE_UVD;
 344                         for (i = 0; i < adev->uvd.num_enc_rings; i++)
 345                                 ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i);
 346                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 347                         ib_size_alignment = 1;
 348                         break;
 349                 case AMDGPU_HW_IP_VCN_DEC:
 350                         type = AMD_IP_BLOCK_TYPE_VCN;
 351                         ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
 352                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 353                         ib_size_alignment = 16;
 354                         break;
 355                 case AMDGPU_HW_IP_VCN_ENC:
 356                         type = AMD_IP_BLOCK_TYPE_VCN;
 357                         for (i = 0; i < adev->vcn.num_enc_rings; i++)
 358                                 ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i);
 359                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 360                         ib_size_alignment = 1;
 361                         break;
 362                 default:
 363                         return -EINVAL;
 364                 }
 365
 366                 for (i = 0; i < adev->num_ip_blocks; i++) {
 367                         if (adev->ip_blocks[i].version->type == type &&
 368                             adev->ip_blocks[i].status.valid) {
 369                                 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
 370                                 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 371                                 ip.capabilities_flags = 0;
 372                                 ip.available_rings = ring_mask;
 373                                 ip.ib_start_alignment = ib_start_alignment;
 374                                 ip.ib_size_alignment = ib_size_alignment;
 375                                 break;
 376                         }
 377                 }
 378                 return copy_to_user(out, &ip,
 379                                     min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
 380         }
 381         case AMDGPU_INFO_HW_IP_COUNT: {
 382                 enum amd_ip_block_type type;
 383                 uint32_t count = 0;
 384
 385                 switch (info->query_hw_ip.type) {
 386                 case AMDGPU_HW_IP_GFX:
 387                         type = AMD_IP_BLOCK_TYPE_GFX;
 388                         break;
 389                 case AMDGPU_HW_IP_COMPUTE:
 390                         type = AMD_IP_BLOCK_TYPE_GFX;
 391                         break;
 392                 case AMDGPU_HW_IP_DMA:
 393                         type = AMD_IP_BLOCK_TYPE_SDMA;
 394                         break;
 395                 case AMDGPU_HW_IP_UVD:
 396                         type = AMD_IP_BLOCK_TYPE_UVD;
 397                         break;
 398                 case AMDGPU_HW_IP_VCE:
 399                         type = AMD_IP_BLOCK_TYPE_VCE;
 400                         break;
 401                 case AMDGPU_HW_IP_UVD_ENC:
 402                         type = AMD_IP_BLOCK_TYPE_UVD;
 403                         break;
 404                 case AMDGPU_HW_IP_VCN_DEC:
 405                 case AMDGPU_HW_IP_VCN_ENC:
 406                         type = AMD_IP_BLOCK_TYPE_VCN;
 407                         break;
 408                 default:
 409                         return -EINVAL;
 410                 }
 411
 412                 for (i = 0; i < adev->num_ip_blocks; i++)
 413                         if (adev->ip_blocks[i].version->type == type &&
 414                             adev->ip_blocks[i].status.valid &&
 415                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 416                                 count++;
 417
 418                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 419         }
 420         case AMDGPU_INFO_TIMESTAMP:
 421                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 422                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 423         case AMDGPU_INFO_FW_VERSION: {
 424                 struct drm_amdgpu_info_firmware fw_info;
 425                 int ret;
 426
 427                 /* We only support one instance of each IP block right now. */
 428                 if (info->query_fw.ip_instance != 0)
 429                         return -EINVAL;
 430
 431                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 432                 if (ret)
 433                         return ret;
 434
 435                 return copy_to_user(out, &fw_info,
 436                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 437         }
 438         case AMDGPU_INFO_NUM_BYTES_MOVED:
 439                 ui64 = atomic64_read(&adev->num_bytes_moved);
 440                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 441         case AMDGPU_INFO_NUM_EVICTIONS:
 442                 ui64 = atomic64_read(&adev->num_evictions);
 443                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 444         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 445                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 446                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 447         case AMDGPU_INFO_VRAM_USAGE:
 448                 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 449                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 450         case AMDGPU_INFO_VIS_VRAM_USAGE:
 451                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 452                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 453         case AMDGPU_INFO_GTT_USAGE:
 454                 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 455                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 456         case AMDGPU_INFO_GDS_CONFIG: {
 457                 struct drm_amdgpu_info_gds gds_info;
 458
 459                 memset(&gds_info, 0, sizeof(gds_info));
 460                 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
 461                 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
 462                 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
 463                 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
 464                 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
 465                 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
 466                 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
 467                 return copy_to_user(out, &gds_info,
 468                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 469         }
 470         case AMDGPU_INFO_VRAM_GTT: {
 471                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 472
 473                 vram_gtt.vram_size = adev->gmc.real_vram_size;
 474                 vram_gtt.vram_size -= adev->vram_pin_size;
 475                 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size;
 476                 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
 477                 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
 478                 vram_gtt.gtt_size *= PAGE_SIZE;
 479                 vram_gtt.gtt_size -= adev->gart_pin_size;
 480                 return copy_to_user(out, &vram_gtt,
 481                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 482         }
 483         case AMDGPU_INFO_MEMORY: {
 484                 struct drm_amdgpu_memory_info mem;
 485
 486                 memset(&mem, 0, sizeof(mem));
 487                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 488                 mem.vram.usable_heap_size =
 489                         adev->gmc.real_vram_size - adev->vram_pin_size;
 490                 mem.vram.heap_usage =
 491                         amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 492                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 493
 494                 mem.cpu_accessible_vram.total_heap_size =
 495                         adev->gmc.visible_vram_size;
 496                 mem.cpu_accessible_vram.usable_heap_size =
 497                         adev->gmc.visible_vram_size -
 498                         (adev->vram_pin_size - adev->invisible_pin_size);
 499                 mem.cpu_accessible_vram.heap_usage =
 500                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 501                 mem.cpu_accessible_vram.max_allocation =
 502                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 503
 504                 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
 505                 mem.gtt.total_heap_size *= PAGE_SIZE;
 506                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size
 507                         - adev->gart_pin_size;
 508                 mem.gtt.heap_usage =
 509                         amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 510                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 511
 512                 return copy_to_user(out, &mem,
 513                                     min((size_t)size, sizeof(mem)))
 514                                     ? -EFAULT : 0;
 515         }
 516         case AMDGPU_INFO_READ_MMR_REG: {
 517                 unsigned n, alloc_size;
 518                 uint32_t *regs;
 519                 unsigned se_num = (info->read_mmr_reg.instance >>
 520                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 521                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 522                 unsigned sh_num = (info->read_mmr_reg.instance >>
 523                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 524                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 525
 526                 /* set full masks if the userspace set all bits
 527                  * in the bitfields */
 528                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 529                         se_num = 0xffffffff;
 530                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 531                         sh_num = 0xffffffff;
 532
 533                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 534                 if (!regs)
 535                         return -ENOMEM;
 536                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 537
 538                 for (i = 0; i < info->read_mmr_reg.count; i++)
 539                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 540                                                       info->read_mmr_reg.dword_offset + i,
 541                                                       &regs[i])) {
 542                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 543                                               info->read_mmr_reg.dword_offset + i);
 544                                 kfree(regs);
 545                                 return -EFAULT;
 546                         }
 547                 n = copy_to_user(out, regs, min(size, alloc_size));
 548                 kfree(regs);
 549                 return n ? -EFAULT : 0;
 550         }
 551         case AMDGPU_INFO_DEV_INFO: {
 552                 struct drm_amdgpu_info_device dev_info = {};
 553                 uint64_t vm_size;
 554
 555                 dev_info.device_id = dev->pdev->device;
 556                 dev_info.chip_rev = adev->rev_id;
 557                 dev_info.external_rev = adev->external_rev_id;
 558                 dev_info.pci_rev = dev->pdev->revision;
 559                 dev_info.family = adev->family;
 560                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 561                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 562                 /* return all clocks in KHz */
 563                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 564                 if (adev->pm.dpm_enabled) {
 565                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 566                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 567                 } else {
 568                         dev_info.max_engine_clock = adev->clock.default_sclk * 10;
 569                         dev_info.max_memory_clock = adev->clock.default_mclk * 10;
 570                 }
 571                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 572                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 573                         adev->gfx.config.max_shader_engines;
 574                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 575                 dev_info._pad = 0;
 576                 dev_info.ids_flags = 0;
 577                 if (adev->flags & AMD_IS_APU)
 578                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 579                 if (amdgpu_sriov_vf(adev))
 580                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 581
 582                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 583                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 584                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 585                 dev_info.virtual_address_max =
 586                         min(vm_size, AMDGPU_VA_HOLE_START);
 587
 588                 if (vm_size > AMDGPU_VA_HOLE_START) {
 589                         dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
 590                         dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;
 591                 }
 592                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 593                 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 594                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 595                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 596                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 597                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 598                 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 599                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 600                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 601                        sizeof(adev->gfx.cu_info.bitmap));
 602                 dev_info.vram_type = adev->gmc.vram_type;
 603                 dev_info.vram_bit_width = adev->gmc.vram_width;
 604                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 605                 dev_info.gc_double_offchip_lds_buf =
 606                         adev->gfx.config.double_offchip_lds_buf;
 607
 608                 if (amdgpu_ngg) {
 609                         dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
 610                         dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
 611                         dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
 612                         dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
 613                         dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
 614                         dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
 615                         dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
 616                         dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
 617                 }
 618                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
 619                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 620                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 621                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 622                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 623                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 624                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 625
 626                 return copy_to_user(out, &dev_info,
 627                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 628         }
 629         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 630                 unsigned i;
 631                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 632                 struct amd_vce_state *vce_state;
 633
 634                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 635                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 636                         if (vce_state) {
 637                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 638                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 639                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 640                                 vce_clk_table.num_valid_entries++;
 641                         }
 642                 }
 643
 644                 return copy_to_user(out, &vce_clk_table,
 645                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 646         }
 647         case AMDGPU_INFO_VBIOS: {
 648                 uint32_t bios_size = adev->bios_size;
 649
 650                 switch (info->vbios_info.type) {
 651                 case AMDGPU_INFO_VBIOS_SIZE:
 652                         return copy_to_user(out, &bios_size,
 653                                         min((size_t)size, sizeof(bios_size)))
 654                                         ? -EFAULT : 0;
 655                 case AMDGPU_INFO_VBIOS_IMAGE: {
 656                         uint8_t *bios;
 657                         uint32_t bios_offset = info->vbios_info.offset;
 658
 659                         if (bios_offset >= bios_size)
 660                                 return -EINVAL;
 661
 662                         bios = adev->bios + bios_offset;
 663                         return copy_to_user(out, bios,
 664                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 665                                         ? -EFAULT : 0;
 666                 }
 667                 default:
 668                         DRM_DEBUG_KMS("Invalid request %d\n",
 669                                         info->vbios_info.type);
 670                         return -EINVAL;
 671                 }
 672         }
 673         case AMDGPU_INFO_NUM_HANDLES: {
 674                 struct drm_amdgpu_info_num_handles handle;
 675
 676                 switch (info->query_hw_ip.type) {
 677                 case AMDGPU_HW_IP_UVD:
 678                         /* Starting Polaris, we support unlimited UVD handles */
 679                         if (adev->asic_type < CHIP_POLARIS10) {
 680                                 handle.uvd_max_handles = adev->uvd.max_handles;
 681                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 682
 683                                 return copy_to_user(out, &handle,
 684                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 685                         } else {
 686                                 return -ENODATA;
 687                         }
 688
 689                         break;
 690                 default:
 691                         return -EINVAL;
 692                 }
 693         }
 694         case AMDGPU_INFO_SENSOR: {
 695                 struct pp_gpu_power query = {0};
 696                 int query_size = sizeof(query);
 697
 698                 if (amdgpu_dpm == 0)
 699                         return -ENOENT;
 700
 701                 switch (info->sensor_info.type) {
 702                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 703                         /* get sclk in Mhz */
 704                         if (amdgpu_dpm_read_sensor(adev,
 705                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 706                                                    (void *)&ui32, &ui32_size)) {
 707                                 return -EINVAL;
 708                         }
 709                         ui32 /= 100;
 710                         break;
 711                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 712                         /* get mclk in Mhz */
 713                         if (amdgpu_dpm_read_sensor(adev,
 714                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 715                                                    (void *)&ui32, &ui32_size)) {
 716                                 return -EINVAL;
 717                         }
 718                         ui32 /= 100;
 719                         break;
 720                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 721                         /* get temperature in millidegrees C */
 722                         if (amdgpu_dpm_read_sensor(adev,
 723                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 724                                                    (void *)&ui32, &ui32_size)) {
 725                                 return -EINVAL;
 726                         }
 727                         break;
 728                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 729                         /* get GPU load */
 730                         if (amdgpu_dpm_read_sensor(adev,
 731                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 732                                                    (void *)&ui32, &ui32_size)) {
 733                                 return -EINVAL;
 734                         }
 735                         break;
 736                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 737                         /* get average GPU power */
 738                         if (amdgpu_dpm_read_sensor(adev,
 739                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 740                                                    (void *)&query, &query_size)) {
 741                                 return -EINVAL;
 742                         }
 743                         ui32 = query.average_gpu_power >> 8;
 744                         break;
 745                 case AMDGPU_INFO_SENSOR_VDDNB:
 746                         /* get VDDNB in millivolts */
 747                         if (amdgpu_dpm_read_sensor(adev,
 748                                                    AMDGPU_PP_SENSOR_VDDNB,
 749                                                    (void *)&ui32, &ui32_size)) {
 750                                 return -EINVAL;
 751                         }
 752                         break;
 753                 case AMDGPU_INFO_SENSOR_VDDGFX:
 754                         /* get VDDGFX in millivolts */
 755                         if (amdgpu_dpm_read_sensor(adev,
 756                                                    AMDGPU_PP_SENSOR_VDDGFX,
 757                                                    (void *)&ui32, &ui32_size)) {
 758                                 return -EINVAL;
 759                         }
 760                         break;
 761                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 762                         /* get stable pstate sclk in Mhz */
 763                         if (amdgpu_dpm_read_sensor(adev,
 764                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 765                                                    (void *)&ui32, &ui32_size)) {
 766                                 return -EINVAL;
 767                         }
 768                         ui32 /= 100;
 769                         break;
 770                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 771                         /* get stable pstate mclk in Mhz */
 772                         if (amdgpu_dpm_read_sensor(adev,
 773                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 774                                                    (void *)&ui32, &ui32_size)) {
 775                                 return -EINVAL;
 776                         }
 777                         ui32 /= 100;
 778                         break;
 779                 default:
 780                         DRM_DEBUG_KMS("Invalid request %d\n",
 781                                       info->sensor_info.type);
 782                         return -EINVAL;
 783                 }
 784                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 785         }
 786         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 787                 ui32 = atomic_read(&adev->vram_lost_counter);
 788                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 789         default:
 790                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 791                 return -EINVAL;
 792         }
 793         return 0;
 794 }
 795
 796
 797 /*
 798  * Outdated mess for old drm with Xorg being in charge (void function now).
 799  */
 800 /**
 801  * amdgpu_driver_lastclose_kms - drm callback for last close
 802  *
 803  * @dev: drm dev pointer
 804  *
 805  * Switch vga_switcheroo state after last close (all asics).
 806  */
 807 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 808 {
 809         drm_fb_helper_lastclose(dev);
 810         vga_switcheroo_process_delayed_switch();
 811 }
 812
 813 /**
 814  * amdgpu_driver_open_kms - drm callback for open
 815  *
 816  * @dev: drm dev pointer
 817  * @file_priv: drm file
 818  *
 819  * On device open, init vm on cayman+ (all asics).
 820  * Returns 0 on success, error on failure.
 821  */
 822 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 823 {
 824         struct amdgpu_device *adev = dev->dev_private;
 825         struct amdgpu_fpriv *fpriv;
 826         int r, pasid;
 827
 828         file_priv->driver_priv = NULL;
 829
 830         r = pm_runtime_get_sync(dev->dev);
 831         if (r < 0)
 832                 return r;
 833
 834         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 835         if (unlikely(!fpriv)) {
 836                 r = -ENOMEM;
 837                 goto out_suspend;
 838         }
 839
 840         pasid = amdgpu_pasid_alloc(16);
 841         if (pasid < 0) {
 842                 dev_warn(adev->dev, "No more PASIDs available!");
 843                 pasid = 0;
 844         }
 845         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
 846         if (r)
 847                 goto error_pasid;
 848
 849         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
 850         if (!fpriv->prt_va) {
 851                 r = -ENOMEM;
 852                 goto error_vm;
 853         }
 854
 855         if (amdgpu_sriov_vf(adev)) {
 856                 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
 857                 if (r)
 858                         goto error_vm;
 859         }
 860
 861         mutex_init(&fpriv->bo_list_lock);
 862         idr_init(&fpriv->bo_list_handles);
 863
 864         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
 865
 866         file_priv->driver_priv = fpriv;
 867         goto out_suspend;
 868
 869 error_vm:
 870         amdgpu_vm_fini(adev, &fpriv->vm);
 871
 872 error_pasid:
 873         if (pasid)
 874                 amdgpu_pasid_free(pasid);
 875
 876         kfree(fpriv);
 877
 878 out_suspend:
 879         pm_runtime_mark_last_busy(dev->dev);
 880         pm_runtime_put_autosuspend(dev->dev);
 881
 882         return r;
 883 }
 884
 885 /**
 886  * amdgpu_driver_postclose_kms - drm callback for post close
 887  *
 888  * @dev: drm dev pointer
 889  * @file_priv: drm file
 890  *
 891  * On device post close, tear down vm on cayman+ (all asics).
 892  */
 893 void amdgpu_driver_postclose_kms(struct drm_device *dev,
 894                                  struct drm_file *file_priv)
 895 {
 896         struct amdgpu_device *adev = dev->dev_private;
 897         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 898         struct amdgpu_bo_list *list;
 899         struct amdgpu_bo *pd;
 900         unsigned int pasid;
 901         int handle;
 902
 903         if (!fpriv)
 904                 return;
 905
 906         pm_runtime_get_sync(dev->dev);
 907
 908         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
 909
 910         if (adev->asic_type != CHIP_RAVEN) {
 911                 amdgpu_uvd_free_handles(adev, file_priv);
 912                 amdgpu_vce_free_handles(adev, file_priv);
 913         }
 914
 915         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
 916
 917         if (amdgpu_sriov_vf(adev)) {
 918                 /* TODO: how to handle reserve failure */
 919                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
 920                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
 921                 fpriv->csa_va = NULL;
 922                 amdgpu_bo_unreserve(adev->virt.csa_obj);
 923         }
 924
 925         pasid = fpriv->vm.pasid;
 926         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
 927
 928         amdgpu_vm_fini(adev, &fpriv->vm);
 929         if (pasid)
 930                 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
 931         amdgpu_bo_unref(&pd);
 932
 933         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
 934                 amdgpu_bo_list_free(list);
 935
 936         idr_destroy(&fpriv->bo_list_handles);
 937         mutex_destroy(&fpriv->bo_list_lock);
 938
 939         kfree(fpriv);
 940         file_priv->driver_priv = NULL;
 941
 942         pm_runtime_mark_last_busy(dev->dev);
 943         pm_runtime_put_autosuspend(dev->dev);
 944 }
 945
 946 /*
 947  * VBlank related functions.
 948  */
 949 /**
 950  * amdgpu_get_vblank_counter_kms - get frame count
 951  *
 952  * @dev: drm dev pointer
 953  * @pipe: crtc to get the frame count from
 954  *
 955  * Gets the frame count on the requested crtc (all asics).
 956  * Returns frame count on success, -EINVAL on failure.
 957  */
 958 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
 959 {
 960         struct amdgpu_device *adev = dev->dev_private;
 961         int vpos, hpos, stat;
 962         u32 count;
 963
 964         if (pipe >= adev->mode_info.num_crtc) {
 965                 DRM_ERROR("Invalid crtc %u\n", pipe);
 966                 return -EINVAL;
 967         }
 968
 969         /* The hw increments its frame counter at start of vsync, not at start
 970          * of vblank, as is required by DRM core vblank counter handling.
 971          * Cook the hw count here to make it appear to the caller as if it
 972          * incremented at start of vblank. We measure distance to start of
 973          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
 974          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
 975          * result by 1 to give the proper appearance to caller.
 976          */
 977         if (adev->mode_info.crtcs[pipe]) {
 978                 /* Repeat readout if needed to provide stable result if
 979                  * we cross start of vsync during the queries.
 980                  */
 981                 do {
 982                         count = amdgpu_display_vblank_get_counter(adev, pipe);
 983                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
 984                          * vpos as distance to start of vblank, instead of
 985                          * regular vertical scanout pos.
 986                          */
 987                         stat = amdgpu_display_get_crtc_scanoutpos(
 988                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
 989                                 &vpos, &hpos, NULL, NULL,
 990                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
 991                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
 992
 993                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
 994                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
 995                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
 996                 } else {
 997                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
 998                                       pipe, vpos);
 999
1000                         /* Bump counter if we are at >= leading edge of vblank,
1001                          * but before vsync where vpos would turn negative and
1002                          * the hw counter really increments.
1003                          */
1004                         if (vpos >= 0)
1005                                 count++;
1006                 }
1007         } else {
1008                 /* Fallback to use value as is. */
1009                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1010                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1011         }
1012
1013         return count;
1014 }
1015
1016 /**
1017  * amdgpu_enable_vblank_kms - enable vblank interrupt
1018  *
1019  * @dev: drm dev pointer
1020  * @pipe: crtc to enable vblank interrupt for
1021  *
1022  * Enable the interrupt on the requested crtc (all asics).
1023  * Returns 0 on success, -EINVAL on failure.
1024  */
1025 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1026 {
1027         struct amdgpu_device *adev = dev->dev_private;
1028         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1029
1030         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1031 }
1032
1033 /**
1034  * amdgpu_disable_vblank_kms - disable vblank interrupt
1035  *
1036  * @dev: drm dev pointer
1037  * @pipe: crtc to disable vblank interrupt for
1038  *
1039  * Disable the interrupt on the requested crtc (all asics).
1040  */
1041 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1042 {
1043         struct amdgpu_device *adev = dev->dev_private;
1044         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1045
1046         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1047 }
1048
1049 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1050         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1051         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1052         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1053         DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1054         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1055         DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1056         /* KMS */
1057         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1058         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1059         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1060         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1061         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1062         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1063         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1064         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1065         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1066         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1067 };
1068 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1069
1070 /*
1071  * Debugfs info
1072  */
1073 #if defined(CONFIG_DEBUG_FS)
1074
1075 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1076 {
1077         struct drm_info_node *node = (struct drm_info_node *) m->private;
1078         struct drm_device *dev = node->minor->dev;
1079         struct amdgpu_device *adev = dev->dev_private;
1080         struct drm_amdgpu_info_firmware fw_info;
1081         struct drm_amdgpu_query_fw query_fw;
1082         int ret, i;
1083
1084         /* VCE */
1085         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1086         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1087         if (ret)
1088                 return ret;
1089         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1090                    fw_info.feature, fw_info.ver);
1091
1092         /* UVD */
1093         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1094         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1095         if (ret)
1096                 return ret;
1097         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1098                    fw_info.feature, fw_info.ver);
1099
1100         /* GMC */
1101         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1102         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1103         if (ret)
1104                 return ret;
1105         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1106                    fw_info.feature, fw_info.ver);
1107
1108         /* ME */
1109         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1110         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1111         if (ret)
1112                 return ret;
1113         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1114                    fw_info.feature, fw_info.ver);
1115
1116         /* PFP */
1117         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1118         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1119         if (ret)
1120                 return ret;
1121         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1122                    fw_info.feature, fw_info.ver);
1123
1124         /* CE */
1125         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1126         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1127         if (ret)
1128                 return ret;
1129         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1130                    fw_info.feature, fw_info.ver);
1131
1132         /* RLC */
1133         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1134         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1135         if (ret)
1136                 return ret;
1137         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1138                    fw_info.feature, fw_info.ver);
1139
1140         /* MEC */
1141         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1142         query_fw.index = 0;
1143         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1144         if (ret)
1145                 return ret;
1146         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1147                    fw_info.feature, fw_info.ver);
1148
1149         /* MEC2 */
1150         if (adev->asic_type == CHIP_KAVERI ||
1151             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1152                 query_fw.index = 1;
1153                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1154                 if (ret)
1155                         return ret;
1156                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1157                            fw_info.feature, fw_info.ver);
1158         }
1159
1160         /* PSP SOS */
1161         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1162         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1163         if (ret)
1164                 return ret;
1165         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1166                    fw_info.feature, fw_info.ver);
1167
1168
1169         /* PSP ASD */
1170         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1171         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1172         if (ret)
1173                 return ret;
1174         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1175                    fw_info.feature, fw_info.ver);
1176
1177         /* SMC */
1178         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1179         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1180         if (ret)
1181                 return ret;
1182         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1183                    fw_info.feature, fw_info.ver);
1184
1185         /* SDMA */
1186         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1187         for (i = 0; i < adev->sdma.num_instances; i++) {
1188                 query_fw.index = i;
1189                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1190                 if (ret)
1191                         return ret;
1192                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1193                            i, fw_info.feature, fw_info.ver);
1194         }
1195
1196         return 0;
1197 }
1198
1199 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1200         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1201 };
1202 #endif
1203
1204 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1205 {
1206 #if defined(CONFIG_DEBUG_FS)
1207         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1208                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1209 #else
1210         return 0;
1211 #endif
1212 }