drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_drv.h>
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/uaccess.h>
  39 #include <linux/pci.h>
  40 #include <linux/pm_runtime.h>
  41 #include "amdgpu_amdkfd.h"
  42 #include "amdgpu_gem.h"
  43 #include "amdgpu_display.h"
  44 #include "amdgpu_ras.h"
  45
  46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  47 {
  48         struct amdgpu_gpu_instance *gpu_instance;
  49         int i;
  50
  51         mutex_lock(&mgpu_info.mutex);
  52
  53         for (i = 0; i < mgpu_info.num_gpu; i++) {
  54                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  55                 if (gpu_instance->adev == adev) {
  56                         mgpu_info.gpu_ins[i] =
  57                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  58                         mgpu_info.num_gpu--;
  59                         if (adev->flags & AMD_IS_APU)
  60                                 mgpu_info.num_apu--;
  61                         else
  62                                 mgpu_info.num_dgpu--;
  63                         break;
  64                 }
  65         }
  66
  67         mutex_unlock(&mgpu_info.mutex);
  68 }
  69
  70 /**
  71  * amdgpu_driver_unload_kms - Main unload function for KMS.
  72  *
  73  * @dev: drm dev pointer
  74  *
  75  * This is the main unload function for KMS (all asics).
  76  * Returns 0 on success.
  77  */
  78 void amdgpu_driver_unload_kms(struct drm_device *dev)
  79 {
  80         struct amdgpu_device *adev = drm_to_adev(dev);
  81
  82         if (adev == NULL)
  83                 return;
  84
  85         amdgpu_unregister_gpu_instance(adev);
  86
  87         if (adev->rmmio == NULL)
  88                 return;
  89
  90         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
  91                 DRM_WARN("smart shift update failed\n");
  92
  93         amdgpu_acpi_fini(adev);
  94         amdgpu_device_fini_hw(adev);
  95 }
  96
  97 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
  98 {
  99         struct amdgpu_gpu_instance *gpu_instance;
 100
 101         mutex_lock(&mgpu_info.mutex);
 102
 103         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 104                 DRM_ERROR("Cannot register more gpu instance\n");
 105                 mutex_unlock(&mgpu_info.mutex);
 106                 return;
 107         }
 108
 109         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 110         gpu_instance->adev = adev;
 111         gpu_instance->mgpu_fan_enabled = 0;
 112
 113         mgpu_info.num_gpu++;
 114         if (adev->flags & AMD_IS_APU)
 115                 mgpu_info.num_apu++;
 116         else
 117                 mgpu_info.num_dgpu++;
 118
 119         mutex_unlock(&mgpu_info.mutex);
 120 }
 121
 122 /**
 123  * amdgpu_driver_load_kms - Main load function for KMS.
 124  *
 125  * @adev: pointer to struct amdgpu_device
 126  * @flags: device flags
 127  *
 128  * This is the main load function for KMS (all asics).
 129  * Returns 0 on success, error on failure.
 130  */
 131 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 132 {
 133         struct drm_device *dev;
 134         int r, acpi_status;
 135
 136         dev = adev_to_drm(adev);
 137
 138         /* amdgpu_device_init should report only fatal error
 139          * like memory allocation failure or iomapping failure,
 140          * or memory manager initialization failure, it must
 141          * properly initialize the GPU MC controller and permit
 142          * VRAM allocation
 143          */
 144         r = amdgpu_device_init(adev, flags);
 145         if (r) {
 146                 dev_err(dev->dev, "Fatal error during GPU init\n");
 147                 goto out;
 148         }
 149
 150         adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
 151         if (amdgpu_device_supports_px(dev) &&
 152             (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */
 153                 adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
 154                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 155         } else if (amdgpu_device_supports_boco(dev) &&
 156                    (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */
 157                 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
 158                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 159         } else if (amdgpu_device_supports_baco(dev) &&
 160                    (amdgpu_runtime_pm != 0)) {
 161                 switch (adev->asic_type) {
 162                 case CHIP_VEGA20:
 163                 case CHIP_ARCTURUS:
 164                         /* enable BACO as runpm mode if runpm=1 */
 165                         if (amdgpu_runtime_pm > 0)
 166                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 167                         break;
 168                 case CHIP_VEGA10:
 169                         /* enable BACO as runpm mode if noretry=0 */
 170                         if (!adev->gmc.noretry)
 171                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 172                         break;
 173                 default:
 174                         /* enable BACO as runpm mode on CI+ */
 175                         adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 176                         break;
 177                 }
 178
 179                 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
 180                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 181         }
 182
 183         /* Call ACPI methods: require modeset init
 184          * but failure is not fatal
 185          */
 186
 187         acpi_status = amdgpu_acpi_init(adev);
 188         if (acpi_status)
 189                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 190
 191         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
 192                 DRM_WARN("smart shift update failed\n");
 193
 194 out:
 195         if (r)
 196                 amdgpu_driver_unload_kms(dev);
 197
 198         return r;
 199 }
 200
 201 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 202                                 struct drm_amdgpu_query_fw *query_fw,
 203                                 struct amdgpu_device *adev)
 204 {
 205         switch (query_fw->fw_type) {
 206         case AMDGPU_INFO_FW_VCE:
 207                 fw_info->ver = adev->vce.fw_version;
 208                 fw_info->feature = adev->vce.fb_version;
 209                 break;
 210         case AMDGPU_INFO_FW_UVD:
 211                 fw_info->ver = adev->uvd.fw_version;
 212                 fw_info->feature = 0;
 213                 break;
 214         case AMDGPU_INFO_FW_VCN:
 215                 fw_info->ver = adev->vcn.fw_version;
 216                 fw_info->feature = 0;
 217                 break;
 218         case AMDGPU_INFO_FW_GMC:
 219                 fw_info->ver = adev->gmc.fw_version;
 220                 fw_info->feature = 0;
 221                 break;
 222         case AMDGPU_INFO_FW_GFX_ME:
 223                 fw_info->ver = adev->gfx.me_fw_version;
 224                 fw_info->feature = adev->gfx.me_feature_version;
 225                 break;
 226         case AMDGPU_INFO_FW_GFX_PFP:
 227                 fw_info->ver = adev->gfx.pfp_fw_version;
 228                 fw_info->feature = adev->gfx.pfp_feature_version;
 229                 break;
 230         case AMDGPU_INFO_FW_GFX_CE:
 231                 fw_info->ver = adev->gfx.ce_fw_version;
 232                 fw_info->feature = adev->gfx.ce_feature_version;
 233                 break;
 234         case AMDGPU_INFO_FW_GFX_RLC:
 235                 fw_info->ver = adev->gfx.rlc_fw_version;
 236                 fw_info->feature = adev->gfx.rlc_feature_version;
 237                 break;
 238         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 239                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 240                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 241                 break;
 242         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 243                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 244                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 245                 break;
 246         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 247                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 248                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 249                 break;
 250         case AMDGPU_INFO_FW_GFX_RLCP:
 251                 fw_info->ver = adev->gfx.rlcp_ucode_version;
 252                 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
 253                 break;
 254         case AMDGPU_INFO_FW_GFX_RLCV:
 255                 fw_info->ver = adev->gfx.rlcv_ucode_version;
 256                 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
 257                 break;
 258         case AMDGPU_INFO_FW_GFX_MEC:
 259                 if (query_fw->index == 0) {
 260                         fw_info->ver = adev->gfx.mec_fw_version;
 261                         fw_info->feature = adev->gfx.mec_feature_version;
 262                 } else if (query_fw->index == 1) {
 263                         fw_info->ver = adev->gfx.mec2_fw_version;
 264                         fw_info->feature = adev->gfx.mec2_feature_version;
 265                 } else
 266                         return -EINVAL;
 267                 break;
 268         case AMDGPU_INFO_FW_SMC:
 269                 fw_info->ver = adev->pm.fw_version;
 270                 fw_info->feature = 0;
 271                 break;
 272         case AMDGPU_INFO_FW_TA:
 273                 switch (query_fw->index) {
 274                 case TA_FW_TYPE_PSP_XGMI:
 275                         fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
 276                         fw_info->feature = adev->psp.xgmi_context.context
 277                                                    .bin_desc.feature_version;
 278                         break;
 279                 case TA_FW_TYPE_PSP_RAS:
 280                         fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
 281                         fw_info->feature = adev->psp.ras_context.context
 282                                                    .bin_desc.feature_version;
 283                         break;
 284                 case TA_FW_TYPE_PSP_HDCP:
 285                         fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
 286                         fw_info->feature = adev->psp.hdcp_context.context
 287                                                    .bin_desc.feature_version;
 288                         break;
 289                 case TA_FW_TYPE_PSP_DTM:
 290                         fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
 291                         fw_info->feature = adev->psp.dtm_context.context
 292                                                    .bin_desc.feature_version;
 293                         break;
 294                 case TA_FW_TYPE_PSP_RAP:
 295                         fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
 296                         fw_info->feature = adev->psp.rap_context.context
 297                                                    .bin_desc.feature_version;
 298                         break;
 299                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 300                         fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
 301                         fw_info->feature =
 302                                 adev->psp.securedisplay_context.context.bin_desc
 303                                         .feature_version;
 304                         break;
 305                 default:
 306                         return -EINVAL;
 307                 }
 308                 break;
 309         case AMDGPU_INFO_FW_SDMA:
 310                 if (query_fw->index >= adev->sdma.num_instances)
 311                         return -EINVAL;
 312                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 313                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 314                 break;
 315         case AMDGPU_INFO_FW_SOS:
 316                 fw_info->ver = adev->psp.sos.fw_version;
 317                 fw_info->feature = adev->psp.sos.feature_version;
 318                 break;
 319         case AMDGPU_INFO_FW_ASD:
 320                 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
 321                 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
 322                 break;
 323         case AMDGPU_INFO_FW_DMCU:
 324                 fw_info->ver = adev->dm.dmcu_fw_version;
 325                 fw_info->feature = 0;
 326                 break;
 327         case AMDGPU_INFO_FW_DMCUB:
 328                 fw_info->ver = adev->dm.dmcub_fw_version;
 329                 fw_info->feature = 0;
 330                 break;
 331         case AMDGPU_INFO_FW_TOC:
 332                 fw_info->ver = adev->psp.toc.fw_version;
 333                 fw_info->feature = adev->psp.toc.feature_version;
 334                 break;
 335         case AMDGPU_INFO_FW_CAP:
 336                 fw_info->ver = adev->psp.cap_fw_version;
 337                 fw_info->feature = adev->psp.cap_feature_version;
 338                 break;
 339         case AMDGPU_INFO_FW_MES_KIQ:
 340                 fw_info->ver = adev->mes.ucode_fw_version[0];
 341                 fw_info->feature = 0;
 342                 break;
 343         case AMDGPU_INFO_FW_MES:
 344                 fw_info->ver = adev->mes.ucode_fw_version[1];
 345                 fw_info->feature = 0;
 346                 break;
 347         default:
 348                 return -EINVAL;
 349         }
 350         return 0;
 351 }
 352
 353 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 354                              struct drm_amdgpu_info *info,
 355                              struct drm_amdgpu_info_hw_ip *result)
 356 {
 357         uint32_t ib_start_alignment = 0;
 358         uint32_t ib_size_alignment = 0;
 359         enum amd_ip_block_type type;
 360         unsigned int num_rings = 0;
 361         unsigned int i, j;
 362
 363         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 364                 return -EINVAL;
 365
 366         switch (info->query_hw_ip.type) {
 367         case AMDGPU_HW_IP_GFX:
 368                 type = AMD_IP_BLOCK_TYPE_GFX;
 369                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 370                         if (adev->gfx.gfx_ring[i].sched.ready)
 371                                 ++num_rings;
 372                 ib_start_alignment = 32;
 373                 ib_size_alignment = 32;
 374                 break;
 375         case AMDGPU_HW_IP_COMPUTE:
 376                 type = AMD_IP_BLOCK_TYPE_GFX;
 377                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 378                         if (adev->gfx.compute_ring[i].sched.ready)
 379                                 ++num_rings;
 380                 ib_start_alignment = 32;
 381                 ib_size_alignment = 32;
 382                 break;
 383         case AMDGPU_HW_IP_DMA:
 384                 type = AMD_IP_BLOCK_TYPE_SDMA;
 385                 for (i = 0; i < adev->sdma.num_instances; i++)
 386                         if (adev->sdma.instance[i].ring.sched.ready)
 387                                 ++num_rings;
 388                 ib_start_alignment = 256;
 389                 ib_size_alignment = 4;
 390                 break;
 391         case AMDGPU_HW_IP_UVD:
 392                 type = AMD_IP_BLOCK_TYPE_UVD;
 393                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 394                         if (adev->uvd.harvest_config & (1 << i))
 395                                 continue;
 396
 397                         if (adev->uvd.inst[i].ring.sched.ready)
 398                                 ++num_rings;
 399                 }
 400                 ib_start_alignment = 64;
 401                 ib_size_alignment = 64;
 402                 break;
 403         case AMDGPU_HW_IP_VCE:
 404                 type = AMD_IP_BLOCK_TYPE_VCE;
 405                 for (i = 0; i < adev->vce.num_rings; i++)
 406                         if (adev->vce.ring[i].sched.ready)
 407                                 ++num_rings;
 408                 ib_start_alignment = 4;
 409                 ib_size_alignment = 1;
 410                 break;
 411         case AMDGPU_HW_IP_UVD_ENC:
 412                 type = AMD_IP_BLOCK_TYPE_UVD;
 413                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 414                         if (adev->uvd.harvest_config & (1 << i))
 415                                 continue;
 416
 417                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 418                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 419                                         ++num_rings;
 420                 }
 421                 ib_start_alignment = 64;
 422                 ib_size_alignment = 64;
 423                 break;
 424         case AMDGPU_HW_IP_VCN_DEC:
 425                 type = AMD_IP_BLOCK_TYPE_VCN;
 426                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 427                         if (adev->uvd.harvest_config & (1 << i))
 428                                 continue;
 429
 430                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 431                                 ++num_rings;
 432                 }
 433                 ib_start_alignment = 16;
 434                 ib_size_alignment = 16;
 435                 break;
 436         case AMDGPU_HW_IP_VCN_ENC:
 437                 type = AMD_IP_BLOCK_TYPE_VCN;
 438                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 439                         if (adev->uvd.harvest_config & (1 << i))
 440                                 continue;
 441
 442                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 443                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 444                                         ++num_rings;
 445                 }
 446                 ib_start_alignment = 64;
 447                 ib_size_alignment = 1;
 448                 break;
 449         case AMDGPU_HW_IP_VCN_JPEG:
 450                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 451                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 452
 453                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 454                         if (adev->jpeg.harvest_config & (1 << i))
 455                                 continue;
 456
 457                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 458                                 ++num_rings;
 459                 }
 460                 ib_start_alignment = 16;
 461                 ib_size_alignment = 16;
 462                 break;
 463         default:
 464                 return -EINVAL;
 465         }
 466
 467         for (i = 0; i < adev->num_ip_blocks; i++)
 468                 if (adev->ip_blocks[i].version->type == type &&
 469                     adev->ip_blocks[i].status.valid)
 470                         break;
 471
 472         if (i == adev->num_ip_blocks)
 473                 return 0;
 474
 475         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 476                         num_rings);
 477
 478         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 479         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 480
 481         if (adev->asic_type >= CHIP_VEGA10) {
 482                 switch (type) {
 483                 case AMD_IP_BLOCK_TYPE_GFX:
 484                         result->ip_discovery_version = adev->ip_versions[GC_HWIP][0];
 485                         break;
 486                 case AMD_IP_BLOCK_TYPE_SDMA:
 487                         result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0];
 488                         break;
 489                 case AMD_IP_BLOCK_TYPE_UVD:
 490                 case AMD_IP_BLOCK_TYPE_VCN:
 491                 case AMD_IP_BLOCK_TYPE_JPEG:
 492                         result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0];
 493                         break;
 494                 case AMD_IP_BLOCK_TYPE_VCE:
 495                         result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0];
 496                         break;
 497                 default:
 498                         result->ip_discovery_version = 0;
 499                         break;
 500                 }
 501         } else {
 502                 result->ip_discovery_version = 0;
 503         }
 504         result->capabilities_flags = 0;
 505         result->available_rings = (1 << num_rings) - 1;
 506         result->ib_start_alignment = ib_start_alignment;
 507         result->ib_size_alignment = ib_size_alignment;
 508         return 0;
 509 }
 510
 511 /*
 512  * Userspace get information ioctl
 513  */
 514 /**
 515  * amdgpu_info_ioctl - answer a device specific request.
 516  *
 517  * @dev: drm device pointer
 518  * @data: request object
 519  * @filp: drm filp
 520  *
 521  * This function is used to pass device specific parameters to the userspace
 522  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 523  * etc. (all asics).
 524  * Returns 0 on success, -EINVAL on failure.
 525  */
 526 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 527 {
 528         struct amdgpu_device *adev = drm_to_adev(dev);
 529         struct drm_amdgpu_info *info = data;
 530         struct amdgpu_mode_info *minfo = &adev->mode_info;
 531         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 532         uint32_t size = info->return_size;
 533         struct drm_crtc *crtc;
 534         uint32_t ui32 = 0;
 535         uint64_t ui64 = 0;
 536         int i, found;
 537         int ui32_size = sizeof(ui32);
 538
 539         if (!info->return_size || !info->return_pointer)
 540                 return -EINVAL;
 541
 542         switch (info->query) {
 543         case AMDGPU_INFO_ACCEL_WORKING:
 544                 ui32 = adev->accel_working;
 545                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 546         case AMDGPU_INFO_CRTC_FROM_ID:
 547                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 548                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 549                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 550                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 551                                 ui32 = amdgpu_crtc->crtc_id;
 552                                 found = 1;
 553                                 break;
 554                         }
 555                 }
 556                 if (!found) {
 557                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 558                         return -EINVAL;
 559                 }
 560                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 561         case AMDGPU_INFO_HW_IP_INFO: {
 562                 struct drm_amdgpu_info_hw_ip ip = {};
 563                 int ret;
 564
 565                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 566                 if (ret)
 567                         return ret;
 568
 569                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 570                 return ret ? -EFAULT : 0;
 571         }
 572         case AMDGPU_INFO_HW_IP_COUNT: {
 573                 enum amd_ip_block_type type;
 574                 uint32_t count = 0;
 575
 576                 switch (info->query_hw_ip.type) {
 577                 case AMDGPU_HW_IP_GFX:
 578                         type = AMD_IP_BLOCK_TYPE_GFX;
 579                         break;
 580                 case AMDGPU_HW_IP_COMPUTE:
 581                         type = AMD_IP_BLOCK_TYPE_GFX;
 582                         break;
 583                 case AMDGPU_HW_IP_DMA:
 584                         type = AMD_IP_BLOCK_TYPE_SDMA;
 585                         break;
 586                 case AMDGPU_HW_IP_UVD:
 587                         type = AMD_IP_BLOCK_TYPE_UVD;
 588                         break;
 589                 case AMDGPU_HW_IP_VCE:
 590                         type = AMD_IP_BLOCK_TYPE_VCE;
 591                         break;
 592                 case AMDGPU_HW_IP_UVD_ENC:
 593                         type = AMD_IP_BLOCK_TYPE_UVD;
 594                         break;
 595                 case AMDGPU_HW_IP_VCN_DEC:
 596                 case AMDGPU_HW_IP_VCN_ENC:
 597                         type = AMD_IP_BLOCK_TYPE_VCN;
 598                         break;
 599                 case AMDGPU_HW_IP_VCN_JPEG:
 600                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 601                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 602                         break;
 603                 default:
 604                         return -EINVAL;
 605                 }
 606
 607                 for (i = 0; i < adev->num_ip_blocks; i++)
 608                         if (adev->ip_blocks[i].version->type == type &&
 609                             adev->ip_blocks[i].status.valid &&
 610                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 611                                 count++;
 612
 613                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 614         }
 615         case AMDGPU_INFO_TIMESTAMP:
 616                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 617                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 618         case AMDGPU_INFO_FW_VERSION: {
 619                 struct drm_amdgpu_info_firmware fw_info;
 620                 int ret;
 621
 622                 /* We only support one instance of each IP block right now. */
 623                 if (info->query_fw.ip_instance != 0)
 624                         return -EINVAL;
 625
 626                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 627                 if (ret)
 628                         return ret;
 629
 630                 return copy_to_user(out, &fw_info,
 631                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 632         }
 633         case AMDGPU_INFO_NUM_BYTES_MOVED:
 634                 ui64 = atomic64_read(&adev->num_bytes_moved);
 635                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 636         case AMDGPU_INFO_NUM_EVICTIONS:
 637                 ui64 = atomic64_read(&adev->num_evictions);
 638                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 639         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 640                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 641                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 642         case AMDGPU_INFO_VRAM_USAGE:
 643                 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 644                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 645         case AMDGPU_INFO_VIS_VRAM_USAGE:
 646                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 647                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 648         case AMDGPU_INFO_GTT_USAGE:
 649                 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
 650                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 651         case AMDGPU_INFO_GDS_CONFIG: {
 652                 struct drm_amdgpu_info_gds gds_info;
 653
 654                 memset(&gds_info, 0, sizeof(gds_info));
 655                 gds_info.compute_partition_size = adev->gds.gds_size;
 656                 gds_info.gds_total_size = adev->gds.gds_size;
 657                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 658                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 659                 return copy_to_user(out, &gds_info,
 660                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 661         }
 662         case AMDGPU_INFO_VRAM_GTT: {
 663                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 664
 665                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 666                         atomic64_read(&adev->vram_pin_size) -
 667                         AMDGPU_VM_RESERVED_VRAM;
 668                 vram_gtt.vram_cpu_accessible_size =
 669                         min(adev->gmc.visible_vram_size -
 670                             atomic64_read(&adev->visible_pin_size),
 671                             vram_gtt.vram_size);
 672                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 673                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 674                 return copy_to_user(out, &vram_gtt,
 675                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 676         }
 677         case AMDGPU_INFO_MEMORY: {
 678                 struct drm_amdgpu_memory_info mem;
 679                 struct ttm_resource_manager *gtt_man =
 680                         &adev->mman.gtt_mgr.manager;
 681                 struct ttm_resource_manager *vram_man =
 682                         &adev->mman.vram_mgr.manager;
 683
 684                 memset(&mem, 0, sizeof(mem));
 685                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 686                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 687                         atomic64_read(&adev->vram_pin_size) -
 688                         AMDGPU_VM_RESERVED_VRAM;
 689                 mem.vram.heap_usage =
 690                         ttm_resource_manager_usage(vram_man);
 691                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 692
 693                 mem.cpu_accessible_vram.total_heap_size =
 694                         adev->gmc.visible_vram_size;
 695                 mem.cpu_accessible_vram.usable_heap_size =
 696                         min(adev->gmc.visible_vram_size -
 697                             atomic64_read(&adev->visible_pin_size),
 698                             mem.vram.usable_heap_size);
 699                 mem.cpu_accessible_vram.heap_usage =
 700                         amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 701                 mem.cpu_accessible_vram.max_allocation =
 702                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 703
 704                 mem.gtt.total_heap_size = gtt_man->size;
 705                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 706                         atomic64_read(&adev->gart_pin_size);
 707                 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
 708                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 709
 710                 return copy_to_user(out, &mem,
 711                                     min((size_t)size, sizeof(mem)))
 712                                     ? -EFAULT : 0;
 713         }
 714         case AMDGPU_INFO_READ_MMR_REG: {
 715                 unsigned n, alloc_size;
 716                 uint32_t *regs;
 717                 unsigned se_num = (info->read_mmr_reg.instance >>
 718                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 719                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 720                 unsigned sh_num = (info->read_mmr_reg.instance >>
 721                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 722                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 723
 724                 /* set full masks if the userspace set all bits
 725                  * in the bitfields */
 726                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 727                         se_num = 0xffffffff;
 728                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 729                         return -EINVAL;
 730                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 731                         sh_num = 0xffffffff;
 732                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 733                         return -EINVAL;
 734
 735                 if (info->read_mmr_reg.count > 128)
 736                         return -EINVAL;
 737
 738                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 739                 if (!regs)
 740                         return -ENOMEM;
 741                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 742
 743                 amdgpu_gfx_off_ctrl(adev, false);
 744                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 745                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 746                                                       info->read_mmr_reg.dword_offset + i,
 747                                                       &regs[i])) {
 748                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 749                                               info->read_mmr_reg.dword_offset + i);
 750                                 kfree(regs);
 751                                 amdgpu_gfx_off_ctrl(adev, true);
 752                                 return -EFAULT;
 753                         }
 754                 }
 755                 amdgpu_gfx_off_ctrl(adev, true);
 756                 n = copy_to_user(out, regs, min(size, alloc_size));
 757                 kfree(regs);
 758                 return n ? -EFAULT : 0;
 759         }
 760         case AMDGPU_INFO_DEV_INFO: {
 761                 struct drm_amdgpu_info_device *dev_info;
 762                 uint64_t vm_size;
 763                 int ret;
 764
 765                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 766                 if (!dev_info)
 767                         return -ENOMEM;
 768
 769                 dev_info->device_id = adev->pdev->device;
 770                 dev_info->chip_rev = adev->rev_id;
 771                 dev_info->external_rev = adev->external_rev_id;
 772                 dev_info->pci_rev = adev->pdev->revision;
 773                 dev_info->family = adev->family;
 774                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 775                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 776                 /* return all clocks in KHz */
 777                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 778                 if (adev->pm.dpm_enabled) {
 779                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 780                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 781                 } else {
 782                         dev_info->max_engine_clock = adev->clock.default_sclk * 10;
 783                         dev_info->max_memory_clock = adev->clock.default_mclk * 10;
 784                 }
 785                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 786                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 787                         adev->gfx.config.max_shader_engines;
 788                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 789                 dev_info->_pad = 0;
 790                 dev_info->ids_flags = 0;
 791                 if (adev->flags & AMD_IS_APU)
 792                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 793                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 794                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 795                 if (amdgpu_is_tmz(adev))
 796                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 797
 798                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 799                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 800
 801                 /* Older VCE FW versions are buggy and can handle only 40bits */
 802                 if (adev->vce.fw_version &&
 803                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 804                         vm_size = min(vm_size, 1ULL << 40);
 805
 806                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 807                 dev_info->virtual_address_max =
 808                         min(vm_size, AMDGPU_GMC_HOLE_START);
 809
 810                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 811                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 812                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 813                 }
 814                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 815                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 816                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 817                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 818                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 819                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 820                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 821                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 822                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 823                        sizeof(adev->gfx.cu_info.bitmap));
 824                 dev_info->vram_type = adev->gmc.vram_type;
 825                 dev_info->vram_bit_width = adev->gmc.vram_width;
 826                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 827                 dev_info->gc_double_offchip_lds_buf =
 828                         adev->gfx.config.double_offchip_lds_buf;
 829                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 830                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 831                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 832                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 833                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 834                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 835                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 836
 837                 if (adev->family >= AMDGPU_FAMILY_NV)
 838                         dev_info->pa_sc_tile_steering_override =
 839                                 adev->gfx.config.pa_sc_tile_steering_override;
 840
 841                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 842
 843                 ret = copy_to_user(out, dev_info,
 844                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 845                 kfree(dev_info);
 846                 return ret;
 847         }
 848         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 849                 unsigned i;
 850                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 851                 struct amd_vce_state *vce_state;
 852
 853                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 854                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 855                         if (vce_state) {
 856                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 857                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 858                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 859                                 vce_clk_table.num_valid_entries++;
 860                         }
 861                 }
 862
 863                 return copy_to_user(out, &vce_clk_table,
 864                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 865         }
 866         case AMDGPU_INFO_VBIOS: {
 867                 uint32_t bios_size = adev->bios_size;
 868
 869                 switch (info->vbios_info.type) {
 870                 case AMDGPU_INFO_VBIOS_SIZE:
 871                         return copy_to_user(out, &bios_size,
 872                                         min((size_t)size, sizeof(bios_size)))
 873                                         ? -EFAULT : 0;
 874                 case AMDGPU_INFO_VBIOS_IMAGE: {
 875                         uint8_t *bios;
 876                         uint32_t bios_offset = info->vbios_info.offset;
 877
 878                         if (bios_offset >= bios_size)
 879                                 return -EINVAL;
 880
 881                         bios = adev->bios + bios_offset;
 882                         return copy_to_user(out, bios,
 883                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 884                                         ? -EFAULT : 0;
 885                 }
 886                 case AMDGPU_INFO_VBIOS_INFO: {
 887                         struct drm_amdgpu_info_vbios vbios_info = {};
 888                         struct atom_context *atom_context;
 889
 890                         atom_context = adev->mode_info.atom_context;
 891                         memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
 892                         memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
 893                         vbios_info.version = atom_context->version;
 894                         memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
 895                                                 sizeof(atom_context->vbios_ver_str));
 896                         memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
 897
 898                         return copy_to_user(out, &vbios_info,
 899                                                 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
 900                 }
 901                 default:
 902                         DRM_DEBUG_KMS("Invalid request %d\n",
 903                                         info->vbios_info.type);
 904                         return -EINVAL;
 905                 }
 906         }
 907         case AMDGPU_INFO_NUM_HANDLES: {
 908                 struct drm_amdgpu_info_num_handles handle;
 909
 910                 switch (info->query_hw_ip.type) {
 911                 case AMDGPU_HW_IP_UVD:
 912                         /* Starting Polaris, we support unlimited UVD handles */
 913                         if (adev->asic_type < CHIP_POLARIS10) {
 914                                 handle.uvd_max_handles = adev->uvd.max_handles;
 915                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 916
 917                                 return copy_to_user(out, &handle,
 918                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 919                         } else {
 920                                 return -ENODATA;
 921                         }
 922
 923                         break;
 924                 default:
 925                         return -EINVAL;
 926                 }
 927         }
 928         case AMDGPU_INFO_SENSOR: {
 929                 if (!adev->pm.dpm_enabled)
 930                         return -ENOENT;
 931
 932                 switch (info->sensor_info.type) {
 933                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 934                         /* get sclk in Mhz */
 935                         if (amdgpu_dpm_read_sensor(adev,
 936                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 937                                                    (void *)&ui32, &ui32_size)) {
 938                                 return -EINVAL;
 939                         }
 940                         ui32 /= 100;
 941                         break;
 942                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 943                         /* get mclk in Mhz */
 944                         if (amdgpu_dpm_read_sensor(adev,
 945                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 946                                                    (void *)&ui32, &ui32_size)) {
 947                                 return -EINVAL;
 948                         }
 949                         ui32 /= 100;
 950                         break;
 951                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 952                         /* get temperature in millidegrees C */
 953                         if (amdgpu_dpm_read_sensor(adev,
 954                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 955                                                    (void *)&ui32, &ui32_size)) {
 956                                 return -EINVAL;
 957                         }
 958                         break;
 959                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 960                         /* get GPU load */
 961                         if (amdgpu_dpm_read_sensor(adev,
 962                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 963                                                    (void *)&ui32, &ui32_size)) {
 964                                 return -EINVAL;
 965                         }
 966                         break;
 967                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 968                         /* get average GPU power */
 969                         if (amdgpu_dpm_read_sensor(adev,
 970                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 971                                                    (void *)&ui32, &ui32_size)) {
 972                                 return -EINVAL;
 973                         }
 974                         ui32 >>= 8;
 975                         break;
 976                 case AMDGPU_INFO_SENSOR_VDDNB:
 977                         /* get VDDNB in millivolts */
 978                         if (amdgpu_dpm_read_sensor(adev,
 979                                                    AMDGPU_PP_SENSOR_VDDNB,
 980                                                    (void *)&ui32, &ui32_size)) {
 981                                 return -EINVAL;
 982                         }
 983                         break;
 984                 case AMDGPU_INFO_SENSOR_VDDGFX:
 985                         /* get VDDGFX in millivolts */
 986                         if (amdgpu_dpm_read_sensor(adev,
 987                                                    AMDGPU_PP_SENSOR_VDDGFX,
 988                                                    (void *)&ui32, &ui32_size)) {
 989                                 return -EINVAL;
 990                         }
 991                         break;
 992                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 993                         /* get stable pstate sclk in Mhz */
 994                         if (amdgpu_dpm_read_sensor(adev,
 995                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 996                                                    (void *)&ui32, &ui32_size)) {
 997                                 return -EINVAL;
 998                         }
 999                         ui32 /= 100;
1000                         break;
1001                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1002                         /* get stable pstate mclk in Mhz */
1003                         if (amdgpu_dpm_read_sensor(adev,
1004                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1005                                                    (void *)&ui32, &ui32_size)) {
1006                                 return -EINVAL;
1007                         }
1008                         ui32 /= 100;
1009                         break;
1010                 default:
1011                         DRM_DEBUG_KMS("Invalid request %d\n",
1012                                       info->sensor_info.type);
1013                         return -EINVAL;
1014                 }
1015                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1016         }
1017         case AMDGPU_INFO_VRAM_LOST_COUNTER:
1018                 ui32 = atomic_read(&adev->vram_lost_counter);
1019                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1020         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1021                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1022                 uint64_t ras_mask;
1023
1024                 if (!ras)
1025                         return -EINVAL;
1026                 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1027
1028                 return copy_to_user(out, &ras_mask,
1029                                 min_t(u64, size, sizeof(ras_mask))) ?
1030                         -EFAULT : 0;
1031         }
1032         case AMDGPU_INFO_VIDEO_CAPS: {
1033                 const struct amdgpu_video_codecs *codecs;
1034                 struct drm_amdgpu_info_video_caps *caps;
1035                 int r;
1036
1037                 switch (info->video_cap.type) {
1038                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1039                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1040                         if (r)
1041                                 return -EINVAL;
1042                         break;
1043                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1044                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1045                         if (r)
1046                                 return -EINVAL;
1047                         break;
1048                 default:
1049                         DRM_DEBUG_KMS("Invalid request %d\n",
1050                                       info->video_cap.type);
1051                         return -EINVAL;
1052                 }
1053
1054                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1055                 if (!caps)
1056                         return -ENOMEM;
1057
1058                 for (i = 0; i < codecs->codec_count; i++) {
1059                         int idx = codecs->codec_array[i].codec_type;
1060
1061                         switch (idx) {
1062                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1063                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1064                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1065                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1066                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1067                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1068                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1069                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1070                                 caps->codec_info[idx].valid = 1;
1071                                 caps->codec_info[idx].max_width =
1072                                         codecs->codec_array[i].max_width;
1073                                 caps->codec_info[idx].max_height =
1074                                         codecs->codec_array[i].max_height;
1075                                 caps->codec_info[idx].max_pixels_per_frame =
1076                                         codecs->codec_array[i].max_pixels_per_frame;
1077                                 caps->codec_info[idx].max_level =
1078                                         codecs->codec_array[i].max_level;
1079                                 break;
1080                         default:
1081                                 break;
1082                         }
1083                 }
1084                 r = copy_to_user(out, caps,
1085                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1086                 kfree(caps);
1087                 return r;
1088         }
1089         default:
1090                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1091                 return -EINVAL;
1092         }
1093         return 0;
1094 }
1095
1096
1097 /*
1098  * Outdated mess for old drm with Xorg being in charge (void function now).
1099  */
1100 /**
1101  * amdgpu_driver_lastclose_kms - drm callback for last close
1102  *
1103  * @dev: drm dev pointer
1104  *
1105  * Switch vga_switcheroo state after last close (all asics).
1106  */
1107 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1108 {
1109         drm_fb_helper_lastclose(dev);
1110         vga_switcheroo_process_delayed_switch();
1111 }
1112
1113 /**
1114  * amdgpu_driver_open_kms - drm callback for open
1115  *
1116  * @dev: drm dev pointer
1117  * @file_priv: drm file
1118  *
1119  * On device open, init vm on cayman+ (all asics).
1120  * Returns 0 on success, error on failure.
1121  */
1122 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1123 {
1124         struct amdgpu_device *adev = drm_to_adev(dev);
1125         struct amdgpu_fpriv *fpriv;
1126         int r, pasid;
1127
1128         /* Ensure IB tests are run on ring */
1129         flush_delayed_work(&adev->delayed_init_work);
1130
1131
1132         if (amdgpu_ras_intr_triggered()) {
1133                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1134                 return -EHWPOISON;
1135         }
1136
1137         file_priv->driver_priv = NULL;
1138
1139         r = pm_runtime_get_sync(dev->dev);
1140         if (r < 0)
1141                 goto pm_put;
1142
1143         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1144         if (unlikely(!fpriv)) {
1145                 r = -ENOMEM;
1146                 goto out_suspend;
1147         }
1148
1149         pasid = amdgpu_pasid_alloc(16);
1150         if (pasid < 0) {
1151                 dev_warn(adev->dev, "No more PASIDs available!");
1152                 pasid = 0;
1153         }
1154
1155         r = amdgpu_vm_init(adev, &fpriv->vm);
1156         if (r)
1157                 goto error_pasid;
1158
1159         r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1160         if (r)
1161                 goto error_vm;
1162
1163         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1164         if (!fpriv->prt_va) {
1165                 r = -ENOMEM;
1166                 goto error_vm;
1167         }
1168
1169         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1170                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1171
1172                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1173                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1174                 if (r)
1175                         goto error_vm;
1176         }
1177
1178         mutex_init(&fpriv->bo_list_lock);
1179         idr_init_base(&fpriv->bo_list_handles, 1);
1180
1181         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1182
1183         file_priv->driver_priv = fpriv;
1184         goto out_suspend;
1185
1186 error_vm:
1187         amdgpu_vm_fini(adev, &fpriv->vm);
1188
1189 error_pasid:
1190         if (pasid) {
1191                 amdgpu_pasid_free(pasid);
1192                 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1193         }
1194
1195         kfree(fpriv);
1196
1197 out_suspend:
1198         pm_runtime_mark_last_busy(dev->dev);
1199 pm_put:
1200         pm_runtime_put_autosuspend(dev->dev);
1201
1202         return r;
1203 }
1204
1205 /**
1206  * amdgpu_driver_postclose_kms - drm callback for post close
1207  *
1208  * @dev: drm dev pointer
1209  * @file_priv: drm file
1210  *
1211  * On device post close, tear down vm on cayman+ (all asics).
1212  */
1213 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1214                                  struct drm_file *file_priv)
1215 {
1216         struct amdgpu_device *adev = drm_to_adev(dev);
1217         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1218         struct amdgpu_bo_list *list;
1219         struct amdgpu_bo *pd;
1220         u32 pasid;
1221         int handle;
1222
1223         if (!fpriv)
1224                 return;
1225
1226         pm_runtime_get_sync(dev->dev);
1227
1228         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1229                 amdgpu_uvd_free_handles(adev, file_priv);
1230         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1231                 amdgpu_vce_free_handles(adev, file_priv);
1232
1233         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1234                 /* TODO: how to handle reserve failure */
1235                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1236                 amdgpu_vm_bo_del(adev, fpriv->csa_va);
1237                 fpriv->csa_va = NULL;
1238                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1239         }
1240
1241         pasid = fpriv->vm.pasid;
1242         pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1243         if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1244                 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1245                 amdgpu_bo_unreserve(pd);
1246         }
1247
1248         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1249         amdgpu_vm_fini(adev, &fpriv->vm);
1250
1251         if (pasid)
1252                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1253         amdgpu_bo_unref(&pd);
1254
1255         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1256                 amdgpu_bo_list_put(list);
1257
1258         idr_destroy(&fpriv->bo_list_handles);
1259         mutex_destroy(&fpriv->bo_list_lock);
1260
1261         kfree(fpriv);
1262         file_priv->driver_priv = NULL;
1263
1264         pm_runtime_mark_last_busy(dev->dev);
1265         pm_runtime_put_autosuspend(dev->dev);
1266 }
1267
1268
1269 void amdgpu_driver_release_kms(struct drm_device *dev)
1270 {
1271         struct amdgpu_device *adev = drm_to_adev(dev);
1272
1273         amdgpu_device_fini_sw(adev);
1274         pci_set_drvdata(adev->pdev, NULL);
1275 }
1276
1277 /*
1278  * VBlank related functions.
1279  */
1280 /**
1281  * amdgpu_get_vblank_counter_kms - get frame count
1282  *
1283  * @crtc: crtc to get the frame count from
1284  *
1285  * Gets the frame count on the requested crtc (all asics).
1286  * Returns frame count on success, -EINVAL on failure.
1287  */
1288 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1289 {
1290         struct drm_device *dev = crtc->dev;
1291         unsigned int pipe = crtc->index;
1292         struct amdgpu_device *adev = drm_to_adev(dev);
1293         int vpos, hpos, stat;
1294         u32 count;
1295
1296         if (pipe >= adev->mode_info.num_crtc) {
1297                 DRM_ERROR("Invalid crtc %u\n", pipe);
1298                 return -EINVAL;
1299         }
1300
1301         /* The hw increments its frame counter at start of vsync, not at start
1302          * of vblank, as is required by DRM core vblank counter handling.
1303          * Cook the hw count here to make it appear to the caller as if it
1304          * incremented at start of vblank. We measure distance to start of
1305          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1306          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1307          * result by 1 to give the proper appearance to caller.
1308          */
1309         if (adev->mode_info.crtcs[pipe]) {
1310                 /* Repeat readout if needed to provide stable result if
1311                  * we cross start of vsync during the queries.
1312                  */
1313                 do {
1314                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1315                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1316                          * vpos as distance to start of vblank, instead of
1317                          * regular vertical scanout pos.
1318                          */
1319                         stat = amdgpu_display_get_crtc_scanoutpos(
1320                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1321                                 &vpos, &hpos, NULL, NULL,
1322                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1323                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1324
1325                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1326                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1327                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1328                 } else {
1329                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1330                                       pipe, vpos);
1331
1332                         /* Bump counter if we are at >= leading edge of vblank,
1333                          * but before vsync where vpos would turn negative and
1334                          * the hw counter really increments.
1335                          */
1336                         if (vpos >= 0)
1337                                 count++;
1338                 }
1339         } else {
1340                 /* Fallback to use value as is. */
1341                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1342                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1343         }
1344
1345         return count;
1346 }
1347
1348 /**
1349  * amdgpu_enable_vblank_kms - enable vblank interrupt
1350  *
1351  * @crtc: crtc to enable vblank interrupt for
1352  *
1353  * Enable the interrupt on the requested crtc (all asics).
1354  * Returns 0 on success, -EINVAL on failure.
1355  */
1356 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1357 {
1358         struct drm_device *dev = crtc->dev;
1359         unsigned int pipe = crtc->index;
1360         struct amdgpu_device *adev = drm_to_adev(dev);
1361         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1362
1363         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1364 }
1365
1366 /**
1367  * amdgpu_disable_vblank_kms - disable vblank interrupt
1368  *
1369  * @crtc: crtc to disable vblank interrupt for
1370  *
1371  * Disable the interrupt on the requested crtc (all asics).
1372  */
1373 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1374 {
1375         struct drm_device *dev = crtc->dev;
1376         unsigned int pipe = crtc->index;
1377         struct amdgpu_device *adev = drm_to_adev(dev);
1378         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1379
1380         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1381 }
1382
1383 /*
1384  * Debugfs info
1385  */
1386 #if defined(CONFIG_DEBUG_FS)
1387
1388 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1389 {
1390         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1391         struct drm_amdgpu_info_firmware fw_info;
1392         struct drm_amdgpu_query_fw query_fw;
1393         struct atom_context *ctx = adev->mode_info.atom_context;
1394         uint8_t smu_program, smu_major, smu_minor, smu_debug;
1395         int ret, i;
1396
1397         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1398 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1399                 TA_FW_NAME(XGMI),
1400                 TA_FW_NAME(RAS),
1401                 TA_FW_NAME(HDCP),
1402                 TA_FW_NAME(DTM),
1403                 TA_FW_NAME(RAP),
1404                 TA_FW_NAME(SECUREDISPLAY),
1405 #undef TA_FW_NAME
1406         };
1407
1408         /* VCE */
1409         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1410         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1411         if (ret)
1412                 return ret;
1413         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1414                    fw_info.feature, fw_info.ver);
1415
1416         /* UVD */
1417         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1418         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1419         if (ret)
1420                 return ret;
1421         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1422                    fw_info.feature, fw_info.ver);
1423
1424         /* GMC */
1425         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1426         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1427         if (ret)
1428                 return ret;
1429         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1430                    fw_info.feature, fw_info.ver);
1431
1432         /* ME */
1433         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1434         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1435         if (ret)
1436                 return ret;
1437         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1438                    fw_info.feature, fw_info.ver);
1439
1440         /* PFP */
1441         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1442         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1443         if (ret)
1444                 return ret;
1445         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1446                    fw_info.feature, fw_info.ver);
1447
1448         /* CE */
1449         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1450         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1451         if (ret)
1452                 return ret;
1453         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1454                    fw_info.feature, fw_info.ver);
1455
1456         /* RLC */
1457         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1458         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1459         if (ret)
1460                 return ret;
1461         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1462                    fw_info.feature, fw_info.ver);
1463
1464         /* RLC SAVE RESTORE LIST CNTL */
1465         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1466         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1467         if (ret)
1468                 return ret;
1469         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1470                    fw_info.feature, fw_info.ver);
1471
1472         /* RLC SAVE RESTORE LIST GPM MEM */
1473         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1474         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1475         if (ret)
1476                 return ret;
1477         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1478                    fw_info.feature, fw_info.ver);
1479
1480         /* RLC SAVE RESTORE LIST SRM MEM */
1481         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1482         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1483         if (ret)
1484                 return ret;
1485         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1486                    fw_info.feature, fw_info.ver);
1487
1488         /* RLCP */
1489         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1490         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1491         if (ret)
1492                 return ret;
1493         seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1494                    fw_info.feature, fw_info.ver);
1495
1496         /* RLCV */
1497         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1498         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1499         if (ret)
1500                 return ret;
1501         seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1502                    fw_info.feature, fw_info.ver);
1503
1504         /* MEC */
1505         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1506         query_fw.index = 0;
1507         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1508         if (ret)
1509                 return ret;
1510         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1511                    fw_info.feature, fw_info.ver);
1512
1513         /* MEC2 */
1514         if (adev->gfx.mec2_fw) {
1515                 query_fw.index = 1;
1516                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1517                 if (ret)
1518                         return ret;
1519                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1520                            fw_info.feature, fw_info.ver);
1521         }
1522
1523         /* PSP SOS */
1524         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1525         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1526         if (ret)
1527                 return ret;
1528         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1529                    fw_info.feature, fw_info.ver);
1530
1531
1532         /* PSP ASD */
1533         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1534         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1535         if (ret)
1536                 return ret;
1537         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1538                    fw_info.feature, fw_info.ver);
1539
1540         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1541         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1542                 query_fw.index = i;
1543                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1544                 if (ret)
1545                         continue;
1546
1547                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1548                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1549         }
1550
1551         /* SMC */
1552         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1553         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1554         if (ret)
1555                 return ret;
1556         smu_program = (fw_info.ver >> 24) & 0xff;
1557         smu_major = (fw_info.ver >> 16) & 0xff;
1558         smu_minor = (fw_info.ver >> 8) & 0xff;
1559         smu_debug = (fw_info.ver >> 0) & 0xff;
1560         seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1561                    fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1562
1563         /* SDMA */
1564         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1565         for (i = 0; i < adev->sdma.num_instances; i++) {
1566                 query_fw.index = i;
1567                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1568                 if (ret)
1569                         return ret;
1570                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1571                            i, fw_info.feature, fw_info.ver);
1572         }
1573
1574         /* VCN */
1575         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1576         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1577         if (ret)
1578                 return ret;
1579         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1580                    fw_info.feature, fw_info.ver);
1581
1582         /* DMCU */
1583         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1584         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1585         if (ret)
1586                 return ret;
1587         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1588                    fw_info.feature, fw_info.ver);
1589
1590         /* DMCUB */
1591         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1592         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1593         if (ret)
1594                 return ret;
1595         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1596                    fw_info.feature, fw_info.ver);
1597
1598         /* TOC */
1599         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1600         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1601         if (ret)
1602                 return ret;
1603         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1604                    fw_info.feature, fw_info.ver);
1605
1606         /* CAP */
1607         if (adev->psp.cap_fw) {
1608                 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1609                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1610                 if (ret)
1611                         return ret;
1612                 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1613                                 fw_info.feature, fw_info.ver);
1614         }
1615
1616         /* MES_KIQ */
1617         query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1618         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1619         if (ret)
1620                 return ret;
1621         seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1622                    fw_info.feature, fw_info.ver);
1623
1624         /* MES */
1625         query_fw.fw_type = AMDGPU_INFO_FW_MES;
1626         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1627         if (ret)
1628                 return ret;
1629         seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1630                    fw_info.feature, fw_info.ver);
1631
1632         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1633
1634         return 0;
1635 }
1636
1637 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1638
1639 #endif
1640
1641 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1642 {
1643 #if defined(CONFIG_DEBUG_FS)
1644         struct drm_minor *minor = adev_to_drm(adev)->primary;
1645         struct dentry *root = minor->debugfs_root;
1646
1647         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1648                             adev, &amdgpu_debugfs_firmware_info_fops);
1649
1650 #endif
1651 }