2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
26 #include "amdgpu_ih.h"
27 #include "amdgpu_gfx.h"
30 #include "cik_structs.h"
32 #include "amdgpu_ucode.h"
33 #include "clearstate_ci.h"
35 #include "dce/dce_8_0_d.h"
36 #include "dce/dce_8_0_sh_mask.h"
38 #include "bif/bif_4_1_d.h"
39 #include "bif/bif_4_1_sh_mask.h"
41 #include "gca/gfx_7_0_d.h"
42 #include "gca/gfx_7_2_enum.h"
43 #include "gca/gfx_7_2_sh_mask.h"
45 #include "gmc/gmc_7_0_d.h"
46 #include "gmc/gmc_7_0_sh_mask.h"
48 #include "oss/oss_2_0_d.h"
49 #include "oss/oss_2_0_sh_mask.h"
51 #define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */
53 #define GFX7_NUM_GFX_RINGS 1
54 #define GFX7_MEC_HPD_SIZE 2048
56 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
57 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
58 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
60 MODULE_FIRMWARE("amdgpu/bonaire_pfp.bin");
61 MODULE_FIRMWARE("amdgpu/bonaire_me.bin");
62 MODULE_FIRMWARE("amdgpu/bonaire_ce.bin");
63 MODULE_FIRMWARE("amdgpu/bonaire_rlc.bin");
64 MODULE_FIRMWARE("amdgpu/bonaire_mec.bin");
66 MODULE_FIRMWARE("amdgpu/hawaii_pfp.bin");
67 MODULE_FIRMWARE("amdgpu/hawaii_me.bin");
68 MODULE_FIRMWARE("amdgpu/hawaii_ce.bin");
69 MODULE_FIRMWARE("amdgpu/hawaii_rlc.bin");
70 MODULE_FIRMWARE("amdgpu/hawaii_mec.bin");
72 MODULE_FIRMWARE("amdgpu/kaveri_pfp.bin");
73 MODULE_FIRMWARE("amdgpu/kaveri_me.bin");
74 MODULE_FIRMWARE("amdgpu/kaveri_ce.bin");
75 MODULE_FIRMWARE("amdgpu/kaveri_rlc.bin");
76 MODULE_FIRMWARE("amdgpu/kaveri_mec.bin");
77 MODULE_FIRMWARE("amdgpu/kaveri_mec2.bin");
79 MODULE_FIRMWARE("amdgpu/kabini_pfp.bin");
80 MODULE_FIRMWARE("amdgpu/kabini_me.bin");
81 MODULE_FIRMWARE("amdgpu/kabini_ce.bin");
82 MODULE_FIRMWARE("amdgpu/kabini_rlc.bin");
83 MODULE_FIRMWARE("amdgpu/kabini_mec.bin");
85 MODULE_FIRMWARE("amdgpu/mullins_pfp.bin");
86 MODULE_FIRMWARE("amdgpu/mullins_me.bin");
87 MODULE_FIRMWARE("amdgpu/mullins_ce.bin");
88 MODULE_FIRMWARE("amdgpu/mullins_rlc.bin");
89 MODULE_FIRMWARE("amdgpu/mullins_mec.bin");
91 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
93 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
94 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
95 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
96 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
97 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
98 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
99 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
100 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
101 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
102 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
103 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
104 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
105 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
106 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
107 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
108 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
111 static const u32 spectre_rlc_save_restore_register_list[] =
113 (0x0e00 << 16) | (0xc12c >> 2),
115 (0x0e00 << 16) | (0xc140 >> 2),
117 (0x0e00 << 16) | (0xc150 >> 2),
119 (0x0e00 << 16) | (0xc15c >> 2),
121 (0x0e00 << 16) | (0xc168 >> 2),
123 (0x0e00 << 16) | (0xc170 >> 2),
125 (0x0e00 << 16) | (0xc178 >> 2),
127 (0x0e00 << 16) | (0xc204 >> 2),
129 (0x0e00 << 16) | (0xc2b4 >> 2),
131 (0x0e00 << 16) | (0xc2b8 >> 2),
133 (0x0e00 << 16) | (0xc2bc >> 2),
135 (0x0e00 << 16) | (0xc2c0 >> 2),
137 (0x0e00 << 16) | (0x8228 >> 2),
139 (0x0e00 << 16) | (0x829c >> 2),
141 (0x0e00 << 16) | (0x869c >> 2),
143 (0x0600 << 16) | (0x98f4 >> 2),
145 (0x0e00 << 16) | (0x98f8 >> 2),
147 (0x0e00 << 16) | (0x9900 >> 2),
149 (0x0e00 << 16) | (0xc260 >> 2),
151 (0x0e00 << 16) | (0x90e8 >> 2),
153 (0x0e00 << 16) | (0x3c000 >> 2),
155 (0x0e00 << 16) | (0x3c00c >> 2),
157 (0x0e00 << 16) | (0x8c1c >> 2),
159 (0x0e00 << 16) | (0x9700 >> 2),
161 (0x0e00 << 16) | (0xcd20 >> 2),
163 (0x4e00 << 16) | (0xcd20 >> 2),
165 (0x5e00 << 16) | (0xcd20 >> 2),
167 (0x6e00 << 16) | (0xcd20 >> 2),
169 (0x7e00 << 16) | (0xcd20 >> 2),
171 (0x8e00 << 16) | (0xcd20 >> 2),
173 (0x9e00 << 16) | (0xcd20 >> 2),
175 (0xae00 << 16) | (0xcd20 >> 2),
177 (0xbe00 << 16) | (0xcd20 >> 2),
179 (0x0e00 << 16) | (0x89bc >> 2),
181 (0x0e00 << 16) | (0x8900 >> 2),
184 (0x0e00 << 16) | (0xc130 >> 2),
186 (0x0e00 << 16) | (0xc134 >> 2),
188 (0x0e00 << 16) | (0xc1fc >> 2),
190 (0x0e00 << 16) | (0xc208 >> 2),
192 (0x0e00 << 16) | (0xc264 >> 2),
194 (0x0e00 << 16) | (0xc268 >> 2),
196 (0x0e00 << 16) | (0xc26c >> 2),
198 (0x0e00 << 16) | (0xc270 >> 2),
200 (0x0e00 << 16) | (0xc274 >> 2),
202 (0x0e00 << 16) | (0xc278 >> 2),
204 (0x0e00 << 16) | (0xc27c >> 2),
206 (0x0e00 << 16) | (0xc280 >> 2),
208 (0x0e00 << 16) | (0xc284 >> 2),
210 (0x0e00 << 16) | (0xc288 >> 2),
212 (0x0e00 << 16) | (0xc28c >> 2),
214 (0x0e00 << 16) | (0xc290 >> 2),
216 (0x0e00 << 16) | (0xc294 >> 2),
218 (0x0e00 << 16) | (0xc298 >> 2),
220 (0x0e00 << 16) | (0xc29c >> 2),
222 (0x0e00 << 16) | (0xc2a0 >> 2),
224 (0x0e00 << 16) | (0xc2a4 >> 2),
226 (0x0e00 << 16) | (0xc2a8 >> 2),
228 (0x0e00 << 16) | (0xc2ac >> 2),
230 (0x0e00 << 16) | (0xc2b0 >> 2),
232 (0x0e00 << 16) | (0x301d0 >> 2),
234 (0x0e00 << 16) | (0x30238 >> 2),
236 (0x0e00 << 16) | (0x30250 >> 2),
238 (0x0e00 << 16) | (0x30254 >> 2),
240 (0x0e00 << 16) | (0x30258 >> 2),
242 (0x0e00 << 16) | (0x3025c >> 2),
244 (0x4e00 << 16) | (0xc900 >> 2),
246 (0x5e00 << 16) | (0xc900 >> 2),
248 (0x6e00 << 16) | (0xc900 >> 2),
250 (0x7e00 << 16) | (0xc900 >> 2),
252 (0x8e00 << 16) | (0xc900 >> 2),
254 (0x9e00 << 16) | (0xc900 >> 2),
256 (0xae00 << 16) | (0xc900 >> 2),
258 (0xbe00 << 16) | (0xc900 >> 2),
260 (0x4e00 << 16) | (0xc904 >> 2),
262 (0x5e00 << 16) | (0xc904 >> 2),
264 (0x6e00 << 16) | (0xc904 >> 2),
266 (0x7e00 << 16) | (0xc904 >> 2),
268 (0x8e00 << 16) | (0xc904 >> 2),
270 (0x9e00 << 16) | (0xc904 >> 2),
272 (0xae00 << 16) | (0xc904 >> 2),
274 (0xbe00 << 16) | (0xc904 >> 2),
276 (0x4e00 << 16) | (0xc908 >> 2),
278 (0x5e00 << 16) | (0xc908 >> 2),
280 (0x6e00 << 16) | (0xc908 >> 2),
282 (0x7e00 << 16) | (0xc908 >> 2),
284 (0x8e00 << 16) | (0xc908 >> 2),
286 (0x9e00 << 16) | (0xc908 >> 2),
288 (0xae00 << 16) | (0xc908 >> 2),
290 (0xbe00 << 16) | (0xc908 >> 2),
292 (0x4e00 << 16) | (0xc90c >> 2),
294 (0x5e00 << 16) | (0xc90c >> 2),
296 (0x6e00 << 16) | (0xc90c >> 2),
298 (0x7e00 << 16) | (0xc90c >> 2),
300 (0x8e00 << 16) | (0xc90c >> 2),
302 (0x9e00 << 16) | (0xc90c >> 2),
304 (0xae00 << 16) | (0xc90c >> 2),
306 (0xbe00 << 16) | (0xc90c >> 2),
308 (0x4e00 << 16) | (0xc910 >> 2),
310 (0x5e00 << 16) | (0xc910 >> 2),
312 (0x6e00 << 16) | (0xc910 >> 2),
314 (0x7e00 << 16) | (0xc910 >> 2),
316 (0x8e00 << 16) | (0xc910 >> 2),
318 (0x9e00 << 16) | (0xc910 >> 2),
320 (0xae00 << 16) | (0xc910 >> 2),
322 (0xbe00 << 16) | (0xc910 >> 2),
324 (0x0e00 << 16) | (0xc99c >> 2),
326 (0x0e00 << 16) | (0x9834 >> 2),
328 (0x0000 << 16) | (0x30f00 >> 2),
330 (0x0001 << 16) | (0x30f00 >> 2),
332 (0x0000 << 16) | (0x30f04 >> 2),
334 (0x0001 << 16) | (0x30f04 >> 2),
336 (0x0000 << 16) | (0x30f08 >> 2),
338 (0x0001 << 16) | (0x30f08 >> 2),
340 (0x0000 << 16) | (0x30f0c >> 2),
342 (0x0001 << 16) | (0x30f0c >> 2),
344 (0x0600 << 16) | (0x9b7c >> 2),
346 (0x0e00 << 16) | (0x8a14 >> 2),
348 (0x0e00 << 16) | (0x8a18 >> 2),
350 (0x0600 << 16) | (0x30a00 >> 2),
352 (0x0e00 << 16) | (0x8bf0 >> 2),
354 (0x0e00 << 16) | (0x8bcc >> 2),
356 (0x0e00 << 16) | (0x8b24 >> 2),
358 (0x0e00 << 16) | (0x30a04 >> 2),
360 (0x0600 << 16) | (0x30a10 >> 2),
362 (0x0600 << 16) | (0x30a14 >> 2),
364 (0x0600 << 16) | (0x30a18 >> 2),
366 (0x0600 << 16) | (0x30a2c >> 2),
368 (0x0e00 << 16) | (0xc700 >> 2),
370 (0x0e00 << 16) | (0xc704 >> 2),
372 (0x0e00 << 16) | (0xc708 >> 2),
374 (0x0e00 << 16) | (0xc768 >> 2),
376 (0x0400 << 16) | (0xc770 >> 2),
378 (0x0400 << 16) | (0xc774 >> 2),
380 (0x0400 << 16) | (0xc778 >> 2),
382 (0x0400 << 16) | (0xc77c >> 2),
384 (0x0400 << 16) | (0xc780 >> 2),
386 (0x0400 << 16) | (0xc784 >> 2),
388 (0x0400 << 16) | (0xc788 >> 2),
390 (0x0400 << 16) | (0xc78c >> 2),
392 (0x0400 << 16) | (0xc798 >> 2),
394 (0x0400 << 16) | (0xc79c >> 2),
396 (0x0400 << 16) | (0xc7a0 >> 2),
398 (0x0400 << 16) | (0xc7a4 >> 2),
400 (0x0400 << 16) | (0xc7a8 >> 2),
402 (0x0400 << 16) | (0xc7ac >> 2),
404 (0x0400 << 16) | (0xc7b0 >> 2),
406 (0x0400 << 16) | (0xc7b4 >> 2),
408 (0x0e00 << 16) | (0x9100 >> 2),
410 (0x0e00 << 16) | (0x3c010 >> 2),
412 (0x0e00 << 16) | (0x92a8 >> 2),
414 (0x0e00 << 16) | (0x92ac >> 2),
416 (0x0e00 << 16) | (0x92b4 >> 2),
418 (0x0e00 << 16) | (0x92b8 >> 2),
420 (0x0e00 << 16) | (0x92bc >> 2),
422 (0x0e00 << 16) | (0x92c0 >> 2),
424 (0x0e00 << 16) | (0x92c4 >> 2),
426 (0x0e00 << 16) | (0x92c8 >> 2),
428 (0x0e00 << 16) | (0x92cc >> 2),
430 (0x0e00 << 16) | (0x92d0 >> 2),
432 (0x0e00 << 16) | (0x8c00 >> 2),
434 (0x0e00 << 16) | (0x8c04 >> 2),
436 (0x0e00 << 16) | (0x8c20 >> 2),
438 (0x0e00 << 16) | (0x8c38 >> 2),
440 (0x0e00 << 16) | (0x8c3c >> 2),
442 (0x0e00 << 16) | (0xae00 >> 2),
444 (0x0e00 << 16) | (0x9604 >> 2),
446 (0x0e00 << 16) | (0xac08 >> 2),
448 (0x0e00 << 16) | (0xac0c >> 2),
450 (0x0e00 << 16) | (0xac10 >> 2),
452 (0x0e00 << 16) | (0xac14 >> 2),
454 (0x0e00 << 16) | (0xac58 >> 2),
456 (0x0e00 << 16) | (0xac68 >> 2),
458 (0x0e00 << 16) | (0xac6c >> 2),
460 (0x0e00 << 16) | (0xac70 >> 2),
462 (0x0e00 << 16) | (0xac74 >> 2),
464 (0x0e00 << 16) | (0xac78 >> 2),
466 (0x0e00 << 16) | (0xac7c >> 2),
468 (0x0e00 << 16) | (0xac80 >> 2),
470 (0x0e00 << 16) | (0xac84 >> 2),
472 (0x0e00 << 16) | (0xac88 >> 2),
474 (0x0e00 << 16) | (0xac8c >> 2),
476 (0x0e00 << 16) | (0x970c >> 2),
478 (0x0e00 << 16) | (0x9714 >> 2),
480 (0x0e00 << 16) | (0x9718 >> 2),
482 (0x0e00 << 16) | (0x971c >> 2),
484 (0x0e00 << 16) | (0x31068 >> 2),
486 (0x4e00 << 16) | (0x31068 >> 2),
488 (0x5e00 << 16) | (0x31068 >> 2),
490 (0x6e00 << 16) | (0x31068 >> 2),
492 (0x7e00 << 16) | (0x31068 >> 2),
494 (0x8e00 << 16) | (0x31068 >> 2),
496 (0x9e00 << 16) | (0x31068 >> 2),
498 (0xae00 << 16) | (0x31068 >> 2),
500 (0xbe00 << 16) | (0x31068 >> 2),
502 (0x0e00 << 16) | (0xcd10 >> 2),
504 (0x0e00 << 16) | (0xcd14 >> 2),
506 (0x0e00 << 16) | (0x88b0 >> 2),
508 (0x0e00 << 16) | (0x88b4 >> 2),
510 (0x0e00 << 16) | (0x88b8 >> 2),
512 (0x0e00 << 16) | (0x88bc >> 2),
514 (0x0400 << 16) | (0x89c0 >> 2),
516 (0x0e00 << 16) | (0x88c4 >> 2),
518 (0x0e00 << 16) | (0x88c8 >> 2),
520 (0x0e00 << 16) | (0x88d0 >> 2),
522 (0x0e00 << 16) | (0x88d4 >> 2),
524 (0x0e00 << 16) | (0x88d8 >> 2),
526 (0x0e00 << 16) | (0x8980 >> 2),
528 (0x0e00 << 16) | (0x30938 >> 2),
530 (0x0e00 << 16) | (0x3093c >> 2),
532 (0x0e00 << 16) | (0x30940 >> 2),
534 (0x0e00 << 16) | (0x89a0 >> 2),
536 (0x0e00 << 16) | (0x30900 >> 2),
538 (0x0e00 << 16) | (0x30904 >> 2),
540 (0x0e00 << 16) | (0x89b4 >> 2),
542 (0x0e00 << 16) | (0x3c210 >> 2),
544 (0x0e00 << 16) | (0x3c214 >> 2),
546 (0x0e00 << 16) | (0x3c218 >> 2),
548 (0x0e00 << 16) | (0x8904 >> 2),
551 (0x0e00 << 16) | (0x8c28 >> 2),
552 (0x0e00 << 16) | (0x8c2c >> 2),
553 (0x0e00 << 16) | (0x8c30 >> 2),
554 (0x0e00 << 16) | (0x8c34 >> 2),
555 (0x0e00 << 16) | (0x9600 >> 2),
558 static const u32 kalindi_rlc_save_restore_register_list[] =
560 (0x0e00 << 16) | (0xc12c >> 2),
562 (0x0e00 << 16) | (0xc140 >> 2),
564 (0x0e00 << 16) | (0xc150 >> 2),
566 (0x0e00 << 16) | (0xc15c >> 2),
568 (0x0e00 << 16) | (0xc168 >> 2),
570 (0x0e00 << 16) | (0xc170 >> 2),
572 (0x0e00 << 16) | (0xc204 >> 2),
574 (0x0e00 << 16) | (0xc2b4 >> 2),
576 (0x0e00 << 16) | (0xc2b8 >> 2),
578 (0x0e00 << 16) | (0xc2bc >> 2),
580 (0x0e00 << 16) | (0xc2c0 >> 2),
582 (0x0e00 << 16) | (0x8228 >> 2),
584 (0x0e00 << 16) | (0x829c >> 2),
586 (0x0e00 << 16) | (0x869c >> 2),
588 (0x0600 << 16) | (0x98f4 >> 2),
590 (0x0e00 << 16) | (0x98f8 >> 2),
592 (0x0e00 << 16) | (0x9900 >> 2),
594 (0x0e00 << 16) | (0xc260 >> 2),
596 (0x0e00 << 16) | (0x90e8 >> 2),
598 (0x0e00 << 16) | (0x3c000 >> 2),
600 (0x0e00 << 16) | (0x3c00c >> 2),
602 (0x0e00 << 16) | (0x8c1c >> 2),
604 (0x0e00 << 16) | (0x9700 >> 2),
606 (0x0e00 << 16) | (0xcd20 >> 2),
608 (0x4e00 << 16) | (0xcd20 >> 2),
610 (0x5e00 << 16) | (0xcd20 >> 2),
612 (0x6e00 << 16) | (0xcd20 >> 2),
614 (0x7e00 << 16) | (0xcd20 >> 2),
616 (0x0e00 << 16) | (0x89bc >> 2),
618 (0x0e00 << 16) | (0x8900 >> 2),
621 (0x0e00 << 16) | (0xc130 >> 2),
623 (0x0e00 << 16) | (0xc134 >> 2),
625 (0x0e00 << 16) | (0xc1fc >> 2),
627 (0x0e00 << 16) | (0xc208 >> 2),
629 (0x0e00 << 16) | (0xc264 >> 2),
631 (0x0e00 << 16) | (0xc268 >> 2),
633 (0x0e00 << 16) | (0xc26c >> 2),
635 (0x0e00 << 16) | (0xc270 >> 2),
637 (0x0e00 << 16) | (0xc274 >> 2),
639 (0x0e00 << 16) | (0xc28c >> 2),
641 (0x0e00 << 16) | (0xc290 >> 2),
643 (0x0e00 << 16) | (0xc294 >> 2),
645 (0x0e00 << 16) | (0xc298 >> 2),
647 (0x0e00 << 16) | (0xc2a0 >> 2),
649 (0x0e00 << 16) | (0xc2a4 >> 2),
651 (0x0e00 << 16) | (0xc2a8 >> 2),
653 (0x0e00 << 16) | (0xc2ac >> 2),
655 (0x0e00 << 16) | (0x301d0 >> 2),
657 (0x0e00 << 16) | (0x30238 >> 2),
659 (0x0e00 << 16) | (0x30250 >> 2),
661 (0x0e00 << 16) | (0x30254 >> 2),
663 (0x0e00 << 16) | (0x30258 >> 2),
665 (0x0e00 << 16) | (0x3025c >> 2),
667 (0x4e00 << 16) | (0xc900 >> 2),
669 (0x5e00 << 16) | (0xc900 >> 2),
671 (0x6e00 << 16) | (0xc900 >> 2),
673 (0x7e00 << 16) | (0xc900 >> 2),
675 (0x4e00 << 16) | (0xc904 >> 2),
677 (0x5e00 << 16) | (0xc904 >> 2),
679 (0x6e00 << 16) | (0xc904 >> 2),
681 (0x7e00 << 16) | (0xc904 >> 2),
683 (0x4e00 << 16) | (0xc908 >> 2),
685 (0x5e00 << 16) | (0xc908 >> 2),
687 (0x6e00 << 16) | (0xc908 >> 2),
689 (0x7e00 << 16) | (0xc908 >> 2),
691 (0x4e00 << 16) | (0xc90c >> 2),
693 (0x5e00 << 16) | (0xc90c >> 2),
695 (0x6e00 << 16) | (0xc90c >> 2),
697 (0x7e00 << 16) | (0xc90c >> 2),
699 (0x4e00 << 16) | (0xc910 >> 2),
701 (0x5e00 << 16) | (0xc910 >> 2),
703 (0x6e00 << 16) | (0xc910 >> 2),
705 (0x7e00 << 16) | (0xc910 >> 2),
707 (0x0e00 << 16) | (0xc99c >> 2),
709 (0x0e00 << 16) | (0x9834 >> 2),
711 (0x0000 << 16) | (0x30f00 >> 2),
713 (0x0000 << 16) | (0x30f04 >> 2),
715 (0x0000 << 16) | (0x30f08 >> 2),
717 (0x0000 << 16) | (0x30f0c >> 2),
719 (0x0600 << 16) | (0x9b7c >> 2),
721 (0x0e00 << 16) | (0x8a14 >> 2),
723 (0x0e00 << 16) | (0x8a18 >> 2),
725 (0x0600 << 16) | (0x30a00 >> 2),
727 (0x0e00 << 16) | (0x8bf0 >> 2),
729 (0x0e00 << 16) | (0x8bcc >> 2),
731 (0x0e00 << 16) | (0x8b24 >> 2),
733 (0x0e00 << 16) | (0x30a04 >> 2),
735 (0x0600 << 16) | (0x30a10 >> 2),
737 (0x0600 << 16) | (0x30a14 >> 2),
739 (0x0600 << 16) | (0x30a18 >> 2),
741 (0x0600 << 16) | (0x30a2c >> 2),
743 (0x0e00 << 16) | (0xc700 >> 2),
745 (0x0e00 << 16) | (0xc704 >> 2),
747 (0x0e00 << 16) | (0xc708 >> 2),
749 (0x0e00 << 16) | (0xc768 >> 2),
751 (0x0400 << 16) | (0xc770 >> 2),
753 (0x0400 << 16) | (0xc774 >> 2),
755 (0x0400 << 16) | (0xc798 >> 2),
757 (0x0400 << 16) | (0xc79c >> 2),
759 (0x0e00 << 16) | (0x9100 >> 2),
761 (0x0e00 << 16) | (0x3c010 >> 2),
763 (0x0e00 << 16) | (0x8c00 >> 2),
765 (0x0e00 << 16) | (0x8c04 >> 2),
767 (0x0e00 << 16) | (0x8c20 >> 2),
769 (0x0e00 << 16) | (0x8c38 >> 2),
771 (0x0e00 << 16) | (0x8c3c >> 2),
773 (0x0e00 << 16) | (0xae00 >> 2),
775 (0x0e00 << 16) | (0x9604 >> 2),
777 (0x0e00 << 16) | (0xac08 >> 2),
779 (0x0e00 << 16) | (0xac0c >> 2),
781 (0x0e00 << 16) | (0xac10 >> 2),
783 (0x0e00 << 16) | (0xac14 >> 2),
785 (0x0e00 << 16) | (0xac58 >> 2),
787 (0x0e00 << 16) | (0xac68 >> 2),
789 (0x0e00 << 16) | (0xac6c >> 2),
791 (0x0e00 << 16) | (0xac70 >> 2),
793 (0x0e00 << 16) | (0xac74 >> 2),
795 (0x0e00 << 16) | (0xac78 >> 2),
797 (0x0e00 << 16) | (0xac7c >> 2),
799 (0x0e00 << 16) | (0xac80 >> 2),
801 (0x0e00 << 16) | (0xac84 >> 2),
803 (0x0e00 << 16) | (0xac88 >> 2),
805 (0x0e00 << 16) | (0xac8c >> 2),
807 (0x0e00 << 16) | (0x970c >> 2),
809 (0x0e00 << 16) | (0x9714 >> 2),
811 (0x0e00 << 16) | (0x9718 >> 2),
813 (0x0e00 << 16) | (0x971c >> 2),
815 (0x0e00 << 16) | (0x31068 >> 2),
817 (0x4e00 << 16) | (0x31068 >> 2),
819 (0x5e00 << 16) | (0x31068 >> 2),
821 (0x6e00 << 16) | (0x31068 >> 2),
823 (0x7e00 << 16) | (0x31068 >> 2),
825 (0x0e00 << 16) | (0xcd10 >> 2),
827 (0x0e00 << 16) | (0xcd14 >> 2),
829 (0x0e00 << 16) | (0x88b0 >> 2),
831 (0x0e00 << 16) | (0x88b4 >> 2),
833 (0x0e00 << 16) | (0x88b8 >> 2),
835 (0x0e00 << 16) | (0x88bc >> 2),
837 (0x0400 << 16) | (0x89c0 >> 2),
839 (0x0e00 << 16) | (0x88c4 >> 2),
841 (0x0e00 << 16) | (0x88c8 >> 2),
843 (0x0e00 << 16) | (0x88d0 >> 2),
845 (0x0e00 << 16) | (0x88d4 >> 2),
847 (0x0e00 << 16) | (0x88d8 >> 2),
849 (0x0e00 << 16) | (0x8980 >> 2),
851 (0x0e00 << 16) | (0x30938 >> 2),
853 (0x0e00 << 16) | (0x3093c >> 2),
855 (0x0e00 << 16) | (0x30940 >> 2),
857 (0x0e00 << 16) | (0x89a0 >> 2),
859 (0x0e00 << 16) | (0x30900 >> 2),
861 (0x0e00 << 16) | (0x30904 >> 2),
863 (0x0e00 << 16) | (0x89b4 >> 2),
865 (0x0e00 << 16) | (0x3e1fc >> 2),
867 (0x0e00 << 16) | (0x3c210 >> 2),
869 (0x0e00 << 16) | (0x3c214 >> 2),
871 (0x0e00 << 16) | (0x3c218 >> 2),
873 (0x0e00 << 16) | (0x8904 >> 2),
876 (0x0e00 << 16) | (0x8c28 >> 2),
877 (0x0e00 << 16) | (0x8c2c >> 2),
878 (0x0e00 << 16) | (0x8c30 >> 2),
879 (0x0e00 << 16) | (0x8c34 >> 2),
880 (0x0e00 << 16) | (0x9600 >> 2),
883 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
884 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
885 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
886 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
887 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
893 * gfx_v7_0_init_microcode - load ucode images from disk
895 * @adev: amdgpu_device pointer
897 * Use the firmware interface to load the ucode images into
898 * the driver (not loaded into hw).
899 * Returns 0 on success, error on failure.
901 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
903 const char *chip_name;
909 switch (adev->asic_type) {
911 chip_name = "bonaire";
914 chip_name = "hawaii";
917 chip_name = "kaveri";
920 chip_name = "kabini";
923 chip_name = "mullins";
928 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
929 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
932 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
936 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
937 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
940 err = amdgpu_ucode_validate(adev->gfx.me_fw);
944 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
945 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
948 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
952 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
953 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
956 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
960 if (adev->asic_type == CHIP_KAVERI) {
961 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
962 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
965 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
970 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
971 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
974 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
978 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name);
979 release_firmware(adev->gfx.pfp_fw);
980 adev->gfx.pfp_fw = NULL;
981 release_firmware(adev->gfx.me_fw);
982 adev->gfx.me_fw = NULL;
983 release_firmware(adev->gfx.ce_fw);
984 adev->gfx.ce_fw = NULL;
985 release_firmware(adev->gfx.mec_fw);
986 adev->gfx.mec_fw = NULL;
987 release_firmware(adev->gfx.mec2_fw);
988 adev->gfx.mec2_fw = NULL;
989 release_firmware(adev->gfx.rlc_fw);
990 adev->gfx.rlc_fw = NULL;
995 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
997 release_firmware(adev->gfx.pfp_fw);
998 adev->gfx.pfp_fw = NULL;
999 release_firmware(adev->gfx.me_fw);
1000 adev->gfx.me_fw = NULL;
1001 release_firmware(adev->gfx.ce_fw);
1002 adev->gfx.ce_fw = NULL;
1003 release_firmware(adev->gfx.mec_fw);
1004 adev->gfx.mec_fw = NULL;
1005 release_firmware(adev->gfx.mec2_fw);
1006 adev->gfx.mec2_fw = NULL;
1007 release_firmware(adev->gfx.rlc_fw);
1008 adev->gfx.rlc_fw = NULL;
1012 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1014 * @adev: amdgpu_device pointer
1016 * Starting with SI, the tiling setup is done globally in a
1017 * set of 32 tiling modes. Rather than selecting each set of
1018 * parameters per surface as on older asics, we just select
1019 * which index in the tiling table we want to use, and the
1020 * surface uses those parameters (CIK).
1022 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1024 const u32 num_tile_mode_states =
1025 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1026 const u32 num_secondary_tile_mode_states =
1027 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1028 u32 reg_offset, split_equal_to_row_size;
1029 uint32_t *tile, *macrotile;
1031 tile = adev->gfx.config.tile_mode_array;
1032 macrotile = adev->gfx.config.macrotile_mode_array;
1034 switch (adev->gfx.config.mem_row_size_in_kb) {
1036 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1040 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1043 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1047 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1048 tile[reg_offset] = 0;
1049 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1050 macrotile[reg_offset] = 0;
1052 switch (adev->asic_type) {
1054 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1055 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1056 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1057 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1058 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1059 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1060 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1061 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1062 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1063 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1064 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1065 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1066 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1067 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1068 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1069 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1070 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1072 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1073 TILE_SPLIT(split_equal_to_row_size));
1074 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1075 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1076 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1077 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1078 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1079 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1080 TILE_SPLIT(split_equal_to_row_size));
1081 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1082 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1083 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1084 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1085 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1086 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1087 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1088 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1089 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1090 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1091 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1092 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1093 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1094 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1095 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1096 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1097 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1098 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1099 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1100 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1101 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1102 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1103 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1104 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1105 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1106 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1107 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1108 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1109 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1110 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1111 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1112 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1113 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1114 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1115 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1116 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1117 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1118 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1119 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1120 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1121 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1122 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1123 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1124 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1125 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1126 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1127 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1128 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1129 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1130 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1131 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1132 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1133 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1134 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1135 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1136 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1137 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1138 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1139 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1140 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1141 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1142 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1143 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1144 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1145 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1146 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1147 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1148 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1149 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1150 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1151 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1152 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1153 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1154 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1155 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1157 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1158 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1159 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1160 NUM_BANKS(ADDR_SURF_16_BANK));
1161 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1162 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1164 NUM_BANKS(ADDR_SURF_16_BANK));
1165 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1166 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1167 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1168 NUM_BANKS(ADDR_SURF_16_BANK));
1169 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1172 NUM_BANKS(ADDR_SURF_16_BANK));
1173 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1174 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1175 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1176 NUM_BANKS(ADDR_SURF_16_BANK));
1177 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1178 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1179 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1180 NUM_BANKS(ADDR_SURF_8_BANK));
1181 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1182 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1183 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1184 NUM_BANKS(ADDR_SURF_4_BANK));
1185 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1186 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1187 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1188 NUM_BANKS(ADDR_SURF_16_BANK));
1189 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1190 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1191 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1192 NUM_BANKS(ADDR_SURF_16_BANK));
1193 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1194 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1195 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1196 NUM_BANKS(ADDR_SURF_16_BANK));
1197 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1200 NUM_BANKS(ADDR_SURF_16_BANK));
1201 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1202 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1203 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1204 NUM_BANKS(ADDR_SURF_16_BANK));
1205 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1207 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1208 NUM_BANKS(ADDR_SURF_8_BANK));
1209 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1210 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1211 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1212 NUM_BANKS(ADDR_SURF_4_BANK));
1214 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1215 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1216 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1217 if (reg_offset != 7)
1218 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1221 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1222 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1223 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1224 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1225 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1226 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1227 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1228 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1229 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1230 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1231 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1232 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1233 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1234 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1235 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1236 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1237 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1238 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1239 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1240 TILE_SPLIT(split_equal_to_row_size));
1241 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1242 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1243 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1244 TILE_SPLIT(split_equal_to_row_size));
1245 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1246 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1247 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1248 TILE_SPLIT(split_equal_to_row_size));
1249 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1250 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1251 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1252 TILE_SPLIT(split_equal_to_row_size));
1253 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1254 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1255 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1256 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1257 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1258 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1259 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1260 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1261 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1262 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1263 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1264 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1265 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1266 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1267 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1268 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1269 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1270 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1271 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1272 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1273 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1274 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1275 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1276 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1277 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1278 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1279 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1280 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1281 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1282 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1283 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1284 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1285 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1286 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1287 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1288 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1289 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1290 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1291 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1292 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1293 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1294 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1295 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1296 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1297 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1298 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1299 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1300 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1301 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1302 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1303 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1304 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1305 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1306 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1307 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1308 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1309 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1310 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1311 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1312 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1313 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1314 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1315 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1316 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1317 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1318 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1319 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1320 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1321 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1322 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1323 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1324 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1325 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1326 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1327 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1328 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1329 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1330 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1331 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1332 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1333 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1334 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1335 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1336 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1337 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1338 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1340 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1341 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1342 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1343 NUM_BANKS(ADDR_SURF_16_BANK));
1344 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1345 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1346 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1347 NUM_BANKS(ADDR_SURF_16_BANK));
1348 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1349 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1350 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1351 NUM_BANKS(ADDR_SURF_16_BANK));
1352 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1353 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1354 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1355 NUM_BANKS(ADDR_SURF_16_BANK));
1356 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1357 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1358 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1359 NUM_BANKS(ADDR_SURF_8_BANK));
1360 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1361 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1362 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1363 NUM_BANKS(ADDR_SURF_4_BANK));
1364 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1365 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1366 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1367 NUM_BANKS(ADDR_SURF_4_BANK));
1368 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1369 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1370 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1371 NUM_BANKS(ADDR_SURF_16_BANK));
1372 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1373 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1374 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1375 NUM_BANKS(ADDR_SURF_16_BANK));
1376 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1377 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1378 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1379 NUM_BANKS(ADDR_SURF_16_BANK));
1380 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1381 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1382 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1383 NUM_BANKS(ADDR_SURF_8_BANK));
1384 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1385 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1386 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1387 NUM_BANKS(ADDR_SURF_16_BANK));
1388 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1389 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1390 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1391 NUM_BANKS(ADDR_SURF_8_BANK));
1392 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1393 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1394 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1395 NUM_BANKS(ADDR_SURF_4_BANK));
1397 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1398 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1399 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1400 if (reg_offset != 7)
1401 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1407 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1408 PIPE_CONFIG(ADDR_SURF_P2) |
1409 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1410 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1411 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1412 PIPE_CONFIG(ADDR_SURF_P2) |
1413 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1414 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1415 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1416 PIPE_CONFIG(ADDR_SURF_P2) |
1417 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1418 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1419 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1420 PIPE_CONFIG(ADDR_SURF_P2) |
1421 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1422 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1423 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1424 PIPE_CONFIG(ADDR_SURF_P2) |
1425 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1426 TILE_SPLIT(split_equal_to_row_size));
1427 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1428 PIPE_CONFIG(ADDR_SURF_P2) |
1429 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1430 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1431 PIPE_CONFIG(ADDR_SURF_P2) |
1432 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1433 TILE_SPLIT(split_equal_to_row_size));
1434 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1435 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1436 PIPE_CONFIG(ADDR_SURF_P2));
1437 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1438 PIPE_CONFIG(ADDR_SURF_P2) |
1439 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1440 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1441 PIPE_CONFIG(ADDR_SURF_P2) |
1442 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1443 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1444 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1445 PIPE_CONFIG(ADDR_SURF_P2) |
1446 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1447 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1448 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1449 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1450 PIPE_CONFIG(ADDR_SURF_P2) |
1451 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1452 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1453 PIPE_CONFIG(ADDR_SURF_P2) |
1454 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1455 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1456 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1457 PIPE_CONFIG(ADDR_SURF_P2) |
1458 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1459 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1460 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1461 PIPE_CONFIG(ADDR_SURF_P2) |
1462 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1463 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1464 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1465 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1466 PIPE_CONFIG(ADDR_SURF_P2) |
1467 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1468 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1469 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1470 PIPE_CONFIG(ADDR_SURF_P2) |
1471 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1472 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1473 PIPE_CONFIG(ADDR_SURF_P2) |
1474 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1475 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1476 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1477 PIPE_CONFIG(ADDR_SURF_P2) |
1478 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1479 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1480 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1481 PIPE_CONFIG(ADDR_SURF_P2) |
1482 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1483 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1484 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1485 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1486 PIPE_CONFIG(ADDR_SURF_P2) |
1487 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1488 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1489 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1490 PIPE_CONFIG(ADDR_SURF_P2) |
1491 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1492 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1493 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1494 PIPE_CONFIG(ADDR_SURF_P2) |
1495 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1496 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1497 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1498 PIPE_CONFIG(ADDR_SURF_P2) |
1499 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1500 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1501 PIPE_CONFIG(ADDR_SURF_P2) |
1502 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1503 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1504 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1505 PIPE_CONFIG(ADDR_SURF_P2) |
1506 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1507 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1508 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1510 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1511 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1512 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1513 NUM_BANKS(ADDR_SURF_8_BANK));
1514 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1515 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1516 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1517 NUM_BANKS(ADDR_SURF_8_BANK));
1518 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1519 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1520 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1521 NUM_BANKS(ADDR_SURF_8_BANK));
1522 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1523 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1524 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1525 NUM_BANKS(ADDR_SURF_8_BANK));
1526 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1529 NUM_BANKS(ADDR_SURF_8_BANK));
1530 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1531 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1532 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1533 NUM_BANKS(ADDR_SURF_8_BANK));
1534 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1535 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1536 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1537 NUM_BANKS(ADDR_SURF_8_BANK));
1538 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1539 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1540 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1541 NUM_BANKS(ADDR_SURF_16_BANK));
1542 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1543 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1544 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1545 NUM_BANKS(ADDR_SURF_16_BANK));
1546 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1547 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1548 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1549 NUM_BANKS(ADDR_SURF_16_BANK));
1550 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1551 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1552 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1553 NUM_BANKS(ADDR_SURF_16_BANK));
1554 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1555 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1556 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1557 NUM_BANKS(ADDR_SURF_16_BANK));
1558 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1559 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1560 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1561 NUM_BANKS(ADDR_SURF_16_BANK));
1562 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1563 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1564 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1565 NUM_BANKS(ADDR_SURF_8_BANK));
1567 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1568 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1569 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1570 if (reg_offset != 7)
1571 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1577 * gfx_v7_0_select_se_sh - select which SE, SH to address
1579 * @adev: amdgpu_device pointer
1580 * @se_num: shader engine to address
1581 * @sh_num: sh block to address
1583 * Select which SE, SH combinations to address. Certain
1584 * registers are instanced per SE or SH. 0xffffffff means
1585 * broadcast to all SEs or SHs (CIK).
1587 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
1588 u32 se_num, u32 sh_num, u32 instance)
1592 if (instance == 0xffffffff)
1593 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1595 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1597 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1598 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1599 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1600 else if (se_num == 0xffffffff)
1601 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1602 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1603 else if (sh_num == 0xffffffff)
1604 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1605 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1607 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1608 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1609 WREG32(mmGRBM_GFX_INDEX, data);
1613 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1615 * @adev: amdgpu_device pointer
1617 * Calculates the bitmask of enabled RBs (CIK).
1618 * Returns the enabled RB bitmask.
1620 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1624 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1625 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1627 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1628 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1630 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1631 adev->gfx.config.max_sh_per_se);
1633 return (~data) & mask;
1637 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1639 switch (adev->asic_type) {
1641 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1642 SE_XSEL(1) | SE_YSEL(1);
1646 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1647 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1648 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1650 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1654 *rconf |= RB_MAP_PKR0(2);
1663 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1669 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1670 u32 raster_config, u32 raster_config_1,
1671 unsigned rb_mask, unsigned num_rb)
1673 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1674 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1675 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1676 unsigned rb_per_se = num_rb / num_se;
1677 unsigned se_mask[4];
1680 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1681 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1682 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1683 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1685 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1686 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1687 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1689 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1690 (!se_mask[2] && !se_mask[3]))) {
1691 raster_config_1 &= ~SE_PAIR_MAP_MASK;
1693 if (!se_mask[0] && !se_mask[1]) {
1695 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1698 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1702 for (se = 0; se < num_se; se++) {
1703 unsigned raster_config_se = raster_config;
1704 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1705 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1706 int idx = (se / 2) * 2;
1708 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1709 raster_config_se &= ~SE_MAP_MASK;
1711 if (!se_mask[idx]) {
1712 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1714 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1718 pkr0_mask &= rb_mask;
1719 pkr1_mask &= rb_mask;
1720 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1721 raster_config_se &= ~PKR_MAP_MASK;
1724 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1726 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1730 if (rb_per_se >= 2) {
1731 unsigned rb0_mask = 1 << (se * rb_per_se);
1732 unsigned rb1_mask = rb0_mask << 1;
1734 rb0_mask &= rb_mask;
1735 rb1_mask &= rb_mask;
1736 if (!rb0_mask || !rb1_mask) {
1737 raster_config_se &= ~RB_MAP_PKR0_MASK;
1741 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1744 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1748 if (rb_per_se > 2) {
1749 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1750 rb1_mask = rb0_mask << 1;
1751 rb0_mask &= rb_mask;
1752 rb1_mask &= rb_mask;
1753 if (!rb0_mask || !rb1_mask) {
1754 raster_config_se &= ~RB_MAP_PKR1_MASK;
1758 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1761 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1767 /* GRBM_GFX_INDEX has a different offset on CI+ */
1768 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1769 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1770 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1773 /* GRBM_GFX_INDEX has a different offset on CI+ */
1774 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1778 * gfx_v7_0_setup_rb - setup the RBs on the asic
1780 * @adev: amdgpu_device pointer
1781 * @se_num: number of SEs (shader engines) for the asic
1782 * @sh_per_se: number of SH blocks per SE for the asic
1784 * Configures per-SE/SH RB registers (CIK).
1786 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1790 u32 raster_config = 0, raster_config_1 = 0;
1792 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1793 adev->gfx.config.max_sh_per_se;
1794 unsigned num_rb_pipes;
1796 mutex_lock(&adev->grbm_idx_mutex);
1797 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1798 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1799 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1800 data = gfx_v7_0_get_rb_active_bitmap(adev);
1801 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1802 rb_bitmap_width_per_sh);
1805 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1807 adev->gfx.config.backend_enable_mask = active_rbs;
1808 adev->gfx.config.num_rbs = hweight32(active_rbs);
1810 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1811 adev->gfx.config.max_shader_engines, 16);
1813 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1815 if (!adev->gfx.config.backend_enable_mask ||
1816 adev->gfx.config.num_rbs >= num_rb_pipes) {
1817 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1818 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1820 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1821 adev->gfx.config.backend_enable_mask,
1825 /* cache the values for userspace */
1826 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1827 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1828 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1829 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1830 RREG32(mmCC_RB_BACKEND_DISABLE);
1831 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1832 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1833 adev->gfx.config.rb_config[i][j].raster_config =
1834 RREG32(mmPA_SC_RASTER_CONFIG);
1835 adev->gfx.config.rb_config[i][j].raster_config_1 =
1836 RREG32(mmPA_SC_RASTER_CONFIG_1);
1839 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1840 mutex_unlock(&adev->grbm_idx_mutex);
1844 * gfx_v7_0_init_compute_vmid - gart enable
1846 * @adev: amdgpu_device pointer
1848 * Initialize compute vmid sh_mem registers
1851 #define DEFAULT_SH_MEM_BASES (0x6000)
1852 #define FIRST_COMPUTE_VMID (8)
1853 #define LAST_COMPUTE_VMID (16)
1854 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1857 uint32_t sh_mem_config;
1858 uint32_t sh_mem_bases;
1861 * Configure apertures:
1862 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1863 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1864 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1866 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1867 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1868 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1869 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1870 mutex_lock(&adev->srbm_mutex);
1871 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1872 cik_srbm_select(adev, 0, 0, 0, i);
1873 /* CP and shaders */
1874 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1875 WREG32(mmSH_MEM_APE1_BASE, 1);
1876 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1877 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1879 cik_srbm_select(adev, 0, 0, 0, 0);
1880 mutex_unlock(&adev->srbm_mutex);
1883 static void gfx_v7_0_config_init(struct amdgpu_device *adev)
1885 adev->gfx.config.double_offchip_lds_buf = 1;
1889 * gfx_v7_0_constants_init - setup the 3D engine
1891 * @adev: amdgpu_device pointer
1893 * init the gfx constants such as the 3D engine, tiling configuration
1894 * registers, maximum number of quad pipes, render backends...
1896 static void gfx_v7_0_constants_init(struct amdgpu_device *adev)
1898 u32 sh_mem_cfg, sh_static_mem_cfg, sh_mem_base;
1902 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1904 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1905 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1906 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1908 gfx_v7_0_tiling_mode_table_init(adev);
1910 gfx_v7_0_setup_rb(adev);
1911 gfx_v7_0_get_cu_info(adev);
1912 gfx_v7_0_config_init(adev);
1914 /* set HW defaults for 3D engine */
1915 WREG32(mmCP_MEQ_THRESHOLDS,
1916 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1917 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1919 mutex_lock(&adev->grbm_idx_mutex);
1921 * making sure that the following register writes will be broadcasted
1922 * to all the shaders
1924 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1926 /* XXX SH_MEM regs */
1927 /* where to put LDS, scratch, GPUVM in FSA64 space */
1928 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1929 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1930 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, DEFAULT_MTYPE,
1932 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, APE1_MTYPE,
1934 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0);
1936 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
1938 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1940 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
1942 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
1944 mutex_lock(&adev->srbm_mutex);
1945 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
1949 sh_mem_base = adev->gmc.shared_aperture_start >> 48;
1950 cik_srbm_select(adev, 0, 0, 0, i);
1951 /* CP and shaders */
1952 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1953 WREG32(mmSH_MEM_APE1_BASE, 1);
1954 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1955 WREG32(mmSH_MEM_BASES, sh_mem_base);
1957 cik_srbm_select(adev, 0, 0, 0, 0);
1958 mutex_unlock(&adev->srbm_mutex);
1960 gfx_v7_0_init_compute_vmid(adev);
1962 WREG32(mmSX_DEBUG_1, 0x20);
1964 WREG32(mmTA_CNTL_AUX, 0x00010000);
1966 tmp = RREG32(mmSPI_CONFIG_CNTL);
1968 WREG32(mmSPI_CONFIG_CNTL, tmp);
1970 WREG32(mmSQ_CONFIG, 1);
1972 WREG32(mmDB_DEBUG, 0);
1974 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1976 WREG32(mmDB_DEBUG2, tmp);
1978 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1980 WREG32(mmDB_DEBUG3, tmp);
1982 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1984 WREG32(mmCB_HW_CONTROL, tmp);
1986 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1988 WREG32(mmPA_SC_FIFO_SIZE,
1989 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1990 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1991 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1992 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1994 WREG32(mmVGT_NUM_INSTANCES, 1);
1996 WREG32(mmCP_PERFMON_CNTL, 0);
1998 WREG32(mmSQ_CONFIG, 0);
2000 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
2001 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
2002 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
2004 WREG32(mmVGT_CACHE_INVALIDATION,
2005 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
2006 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
2008 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
2009 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
2011 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
2012 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
2013 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
2015 tmp = RREG32(mmSPI_ARB_PRIORITY);
2016 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
2017 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
2018 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
2019 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
2020 WREG32(mmSPI_ARB_PRIORITY, tmp);
2022 mutex_unlock(&adev->grbm_idx_mutex);
2028 * GPU scratch registers helpers function.
2031 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
2033 * @adev: amdgpu_device pointer
2035 * Set up the number and offset of the CP scratch registers.
2036 * NOTE: use of CP scratch registers is a legacy inferface and
2037 * is not used by default on newer asics (r6xx+). On newer asics,
2038 * memory buffers are used for fences rather than scratch regs.
2040 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
2042 adev->gfx.scratch.num_reg = 8;
2043 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
2044 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
2048 * gfx_v7_0_ring_test_ring - basic gfx ring test
2050 * @adev: amdgpu_device pointer
2051 * @ring: amdgpu_ring structure holding ring information
2053 * Allocate a scratch register and write to it using the gfx ring (CIK).
2054 * Provides a basic gfx ring test to verify that the ring is working.
2055 * Used by gfx_v7_0_cp_gfx_resume();
2056 * Returns 0 on success, error on failure.
2058 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2060 struct amdgpu_device *adev = ring->adev;
2066 r = amdgpu_gfx_scratch_get(adev, &scratch);
2070 WREG32(scratch, 0xCAFEDEAD);
2071 r = amdgpu_ring_alloc(ring, 3);
2073 goto error_free_scratch;
2075 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2076 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2077 amdgpu_ring_write(ring, 0xDEADBEEF);
2078 amdgpu_ring_commit(ring);
2080 for (i = 0; i < adev->usec_timeout; i++) {
2081 tmp = RREG32(scratch);
2082 if (tmp == 0xDEADBEEF)
2086 if (i >= adev->usec_timeout)
2090 amdgpu_gfx_scratch_free(adev, scratch);
2095 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
2097 * @adev: amdgpu_device pointer
2098 * @ridx: amdgpu ring index
2100 * Emits an hdp flush on the cp.
2102 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2105 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
2107 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2110 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2113 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2119 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2122 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2123 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2124 WAIT_REG_MEM_FUNCTION(3) | /* == */
2125 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2126 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2127 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2128 amdgpu_ring_write(ring, ref_and_mask);
2129 amdgpu_ring_write(ring, ref_and_mask);
2130 amdgpu_ring_write(ring, 0x20); /* poll interval */
2133 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2135 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2136 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2139 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2140 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2145 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2147 * @adev: amdgpu_device pointer
2148 * @fence: amdgpu fence object
2150 * Emits a fence sequnce number on the gfx ring and flushes
2153 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2154 u64 seq, unsigned flags)
2156 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2157 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2158 /* Workaround for cache flush problems. First send a dummy EOP
2159 * event down the pipe with seq one below.
2161 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2162 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2164 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2166 amdgpu_ring_write(ring, addr & 0xfffffffc);
2167 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2168 DATA_SEL(1) | INT_SEL(0));
2169 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2170 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2172 /* Then send the real EOP event down the pipe. */
2173 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2174 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2176 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2178 amdgpu_ring_write(ring, addr & 0xfffffffc);
2179 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2180 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2181 amdgpu_ring_write(ring, lower_32_bits(seq));
2182 amdgpu_ring_write(ring, upper_32_bits(seq));
2186 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2188 * @adev: amdgpu_device pointer
2189 * @fence: amdgpu fence object
2191 * Emits a fence sequnce number on the compute ring and flushes
2194 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2198 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2199 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2201 /* RELEASE_MEM - flush caches, send int */
2202 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2203 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2205 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2207 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2208 amdgpu_ring_write(ring, addr & 0xfffffffc);
2209 amdgpu_ring_write(ring, upper_32_bits(addr));
2210 amdgpu_ring_write(ring, lower_32_bits(seq));
2211 amdgpu_ring_write(ring, upper_32_bits(seq));
2218 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2220 * @ring: amdgpu_ring structure holding ring information
2221 * @ib: amdgpu indirect buffer object
2223 * Emits an DE (drawing engine) or CE (constant engine) IB
2224 * on the gfx ring. IBs are usually generated by userspace
2225 * acceleration drivers and submitted to the kernel for
2226 * sheduling on the ring. This function schedules the IB
2227 * on the gfx ring for execution by the GPU.
2229 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2230 struct amdgpu_job *job,
2231 struct amdgpu_ib *ib,
2234 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2235 u32 header, control = 0;
2237 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2239 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2240 amdgpu_ring_write(ring, 0);
2243 if (ib->flags & AMDGPU_IB_FLAG_CE)
2244 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2246 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2248 control |= ib->length_dw | (vmid << 24);
2250 amdgpu_ring_write(ring, header);
2251 amdgpu_ring_write(ring,
2255 (ib->gpu_addr & 0xFFFFFFFC));
2256 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2257 amdgpu_ring_write(ring, control);
2260 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2261 struct amdgpu_job *job,
2262 struct amdgpu_ib *ib,
2265 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2266 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2268 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2269 amdgpu_ring_write(ring,
2273 (ib->gpu_addr & 0xFFFFFFFC));
2274 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2275 amdgpu_ring_write(ring, control);
2278 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2282 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2283 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2284 gfx_v7_0_ring_emit_vgt_flush(ring);
2285 /* set load_global_config & load_global_uconfig */
2287 /* set load_cs_sh_regs */
2289 /* set load_per_context_state & load_gfx_sh_regs */
2293 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2294 amdgpu_ring_write(ring, dw2);
2295 amdgpu_ring_write(ring, 0);
2299 * gfx_v7_0_ring_test_ib - basic ring IB test
2301 * @ring: amdgpu_ring structure holding ring information
2303 * Allocate an IB and execute it on the gfx ring (CIK).
2304 * Provides a basic gfx ring test to verify that IBs are working.
2305 * Returns 0 on success, error on failure.
2307 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
2309 struct amdgpu_device *adev = ring->adev;
2310 struct amdgpu_ib ib;
2311 struct dma_fence *f = NULL;
2316 r = amdgpu_gfx_scratch_get(adev, &scratch);
2320 WREG32(scratch, 0xCAFEDEAD);
2321 memset(&ib, 0, sizeof(ib));
2322 r = amdgpu_ib_get(adev, NULL, 256, &ib);
2326 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2327 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2328 ib.ptr[2] = 0xDEADBEEF;
2331 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
2335 r = dma_fence_wait_timeout(f, false, timeout);
2342 tmp = RREG32(scratch);
2343 if (tmp == 0xDEADBEEF)
2349 amdgpu_ib_free(adev, &ib, NULL);
2352 amdgpu_gfx_scratch_free(adev, scratch);
2358 * On CIK, gfx and compute now have independant command processors.
2361 * Gfx consists of a single ring and can process both gfx jobs and
2362 * compute jobs. The gfx CP consists of three microengines (ME):
2363 * PFP - Pre-Fetch Parser
2365 * CE - Constant Engine
2366 * The PFP and ME make up what is considered the Drawing Engine (DE).
2367 * The CE is an asynchronous engine used for updating buffer desciptors
2368 * used by the DE so that they can be loaded into cache in parallel
2369 * while the DE is processing state update packets.
2372 * The compute CP consists of two microengines (ME):
2373 * MEC1 - Compute MicroEngine 1
2374 * MEC2 - Compute MicroEngine 2
2375 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2376 * The queues are exposed to userspace and are programmed directly
2377 * by the compute runtime.
2380 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2382 * @adev: amdgpu_device pointer
2383 * @enable: enable or disable the MEs
2385 * Halts or unhalts the gfx MEs.
2387 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2392 WREG32(mmCP_ME_CNTL, 0);
2394 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2395 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2396 adev->gfx.gfx_ring[i].sched.ready = false;
2402 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2404 * @adev: amdgpu_device pointer
2406 * Loads the gfx PFP, ME, and CE ucode.
2407 * Returns 0 for success, -EINVAL if the ucode is not available.
2409 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2411 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2412 const struct gfx_firmware_header_v1_0 *ce_hdr;
2413 const struct gfx_firmware_header_v1_0 *me_hdr;
2414 const __le32 *fw_data;
2415 unsigned i, fw_size;
2417 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2420 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2421 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2422 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2424 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2425 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2426 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2427 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2428 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2429 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2430 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2431 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2432 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2434 gfx_v7_0_cp_gfx_enable(adev, false);
2437 fw_data = (const __le32 *)
2438 (adev->gfx.pfp_fw->data +
2439 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2440 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2441 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2442 for (i = 0; i < fw_size; i++)
2443 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2444 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2447 fw_data = (const __le32 *)
2448 (adev->gfx.ce_fw->data +
2449 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2450 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2451 WREG32(mmCP_CE_UCODE_ADDR, 0);
2452 for (i = 0; i < fw_size; i++)
2453 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2454 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2457 fw_data = (const __le32 *)
2458 (adev->gfx.me_fw->data +
2459 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2460 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2461 WREG32(mmCP_ME_RAM_WADDR, 0);
2462 for (i = 0; i < fw_size; i++)
2463 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2464 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2470 * gfx_v7_0_cp_gfx_start - start the gfx ring
2472 * @adev: amdgpu_device pointer
2474 * Enables the ring and loads the clear state context and other
2475 * packets required to init the ring.
2476 * Returns 0 for success, error for failure.
2478 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2480 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2481 const struct cs_section_def *sect = NULL;
2482 const struct cs_extent_def *ext = NULL;
2486 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2487 WREG32(mmCP_ENDIAN_SWAP, 0);
2488 WREG32(mmCP_DEVICE_ID, 1);
2490 gfx_v7_0_cp_gfx_enable(adev, true);
2492 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2494 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2498 /* init the CE partitions. CE only used for gfx on CIK */
2499 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2500 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2501 amdgpu_ring_write(ring, 0x8000);
2502 amdgpu_ring_write(ring, 0x8000);
2504 /* clear state buffer */
2505 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2506 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2508 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2509 amdgpu_ring_write(ring, 0x80000000);
2510 amdgpu_ring_write(ring, 0x80000000);
2512 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2513 for (ext = sect->section; ext->extent != NULL; ++ext) {
2514 if (sect->id == SECT_CONTEXT) {
2515 amdgpu_ring_write(ring,
2516 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2517 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2518 for (i = 0; i < ext->reg_count; i++)
2519 amdgpu_ring_write(ring, ext->extent[i]);
2524 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2525 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2526 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
2527 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
2529 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2530 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2532 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2533 amdgpu_ring_write(ring, 0);
2535 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2536 amdgpu_ring_write(ring, 0x00000316);
2537 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2538 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2540 amdgpu_ring_commit(ring);
2546 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2548 * @adev: amdgpu_device pointer
2550 * Program the location and size of the gfx ring buffer
2551 * and test it to make sure it's working.
2552 * Returns 0 for success, error for failure.
2554 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2556 struct amdgpu_ring *ring;
2559 u64 rb_addr, rptr_addr;
2562 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2563 if (adev->asic_type != CHIP_HAWAII)
2564 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2566 /* Set the write pointer delay */
2567 WREG32(mmCP_RB_WPTR_DELAY, 0);
2569 /* set the RB to use vmid 0 */
2570 WREG32(mmCP_RB_VMID, 0);
2572 WREG32(mmSCRATCH_ADDR, 0);
2574 /* ring 0 - compute and gfx */
2575 /* Set ring buffer size */
2576 ring = &adev->gfx.gfx_ring[0];
2577 rb_bufsz = order_base_2(ring->ring_size / 8);
2578 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2580 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2582 WREG32(mmCP_RB0_CNTL, tmp);
2584 /* Initialize the ring buffer's read and write pointers */
2585 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2587 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2589 /* set the wb address wether it's enabled or not */
2590 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2591 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2592 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2594 /* scratch register shadowing is no longer supported */
2595 WREG32(mmSCRATCH_UMSK, 0);
2598 WREG32(mmCP_RB0_CNTL, tmp);
2600 rb_addr = ring->gpu_addr >> 8;
2601 WREG32(mmCP_RB0_BASE, rb_addr);
2602 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2604 /* start the ring */
2605 gfx_v7_0_cp_gfx_start(adev);
2606 r = amdgpu_ring_test_helper(ring);
2613 static u64 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
2615 return ring->adev->wb.wb[ring->rptr_offs];
2618 static u64 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2620 struct amdgpu_device *adev = ring->adev;
2622 return RREG32(mmCP_RB0_WPTR);
2625 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2627 struct amdgpu_device *adev = ring->adev;
2629 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2630 (void)RREG32(mmCP_RB0_WPTR);
2633 static u64 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2635 /* XXX check if swapping is necessary on BE */
2636 return ring->adev->wb.wb[ring->wptr_offs];
2639 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2641 struct amdgpu_device *adev = ring->adev;
2643 /* XXX check if swapping is necessary on BE */
2644 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2645 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2649 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2651 * @adev: amdgpu_device pointer
2652 * @enable: enable or disable the MEs
2654 * Halts or unhalts the compute MEs.
2656 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2661 WREG32(mmCP_MEC_CNTL, 0);
2663 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2664 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2665 adev->gfx.compute_ring[i].sched.ready = false;
2671 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2673 * @adev: amdgpu_device pointer
2675 * Loads the compute MEC1&2 ucode.
2676 * Returns 0 for success, -EINVAL if the ucode is not available.
2678 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2680 const struct gfx_firmware_header_v1_0 *mec_hdr;
2681 const __le32 *fw_data;
2682 unsigned i, fw_size;
2684 if (!adev->gfx.mec_fw)
2687 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2688 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2689 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2690 adev->gfx.mec_feature_version = le32_to_cpu(
2691 mec_hdr->ucode_feature_version);
2693 gfx_v7_0_cp_compute_enable(adev, false);
2696 fw_data = (const __le32 *)
2697 (adev->gfx.mec_fw->data +
2698 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2699 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2700 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2701 for (i = 0; i < fw_size; i++)
2702 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2703 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2705 if (adev->asic_type == CHIP_KAVERI) {
2706 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2708 if (!adev->gfx.mec2_fw)
2711 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2712 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2713 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2714 adev->gfx.mec2_feature_version = le32_to_cpu(
2715 mec2_hdr->ucode_feature_version);
2718 fw_data = (const __le32 *)
2719 (adev->gfx.mec2_fw->data +
2720 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2721 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2722 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2723 for (i = 0; i < fw_size; i++)
2724 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2725 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2732 * gfx_v7_0_cp_compute_fini - stop the compute queues
2734 * @adev: amdgpu_device pointer
2736 * Stop the compute queues and tear down the driver queue
2739 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2743 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2744 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2746 amdgpu_bo_free_kernel(&ring->mqd_obj, NULL, NULL);
2750 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2752 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
2755 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2759 size_t mec_hpd_size;
2761 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2763 /* take ownership of the relevant compute queues */
2764 amdgpu_gfx_compute_queue_acquire(adev);
2766 /* allocate space for ALL pipes (even the ones we don't own) */
2767 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec
2768 * GFX7_MEC_HPD_SIZE * 2;
2770 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
2771 AMDGPU_GEM_DOMAIN_VRAM,
2772 &adev->gfx.mec.hpd_eop_obj,
2773 &adev->gfx.mec.hpd_eop_gpu_addr,
2776 dev_warn(adev->dev, "(%d) create, pin or map of HDP EOP bo failed\n", r);
2777 gfx_v7_0_mec_fini(adev);
2781 /* clear memory. Not sure if this is required or not */
2782 memset(hpd, 0, mec_hpd_size);
2784 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2785 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2790 struct hqd_registers
2792 u32 cp_mqd_base_addr;
2793 u32 cp_mqd_base_addr_hi;
2796 u32 cp_hqd_persistent_state;
2797 u32 cp_hqd_pipe_priority;
2798 u32 cp_hqd_queue_priority;
2801 u32 cp_hqd_pq_base_hi;
2803 u32 cp_hqd_pq_rptr_report_addr;
2804 u32 cp_hqd_pq_rptr_report_addr_hi;
2805 u32 cp_hqd_pq_wptr_poll_addr;
2806 u32 cp_hqd_pq_wptr_poll_addr_hi;
2807 u32 cp_hqd_pq_doorbell_control;
2809 u32 cp_hqd_pq_control;
2810 u32 cp_hqd_ib_base_addr;
2811 u32 cp_hqd_ib_base_addr_hi;
2813 u32 cp_hqd_ib_control;
2814 u32 cp_hqd_iq_timer;
2816 u32 cp_hqd_dequeue_request;
2817 u32 cp_hqd_dma_offload;
2818 u32 cp_hqd_sema_cmd;
2819 u32 cp_hqd_msg_type;
2820 u32 cp_hqd_atomic0_preop_lo;
2821 u32 cp_hqd_atomic0_preop_hi;
2822 u32 cp_hqd_atomic1_preop_lo;
2823 u32 cp_hqd_atomic1_preop_hi;
2824 u32 cp_hqd_hq_scheduler0;
2825 u32 cp_hqd_hq_scheduler1;
2829 static void gfx_v7_0_compute_pipe_init(struct amdgpu_device *adev,
2834 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)
2835 * GFX7_MEC_HPD_SIZE * 2;
2837 mutex_lock(&adev->srbm_mutex);
2838 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset;
2840 cik_srbm_select(adev, mec + 1, pipe, 0, 0);
2842 /* write the EOP addr */
2843 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2844 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2846 /* set the VMID assigned */
2847 WREG32(mmCP_HPD_EOP_VMID, 0);
2849 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2850 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2851 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2852 tmp |= order_base_2(GFX7_MEC_HPD_SIZE / 8);
2853 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2855 cik_srbm_select(adev, 0, 0, 0, 0);
2856 mutex_unlock(&adev->srbm_mutex);
2859 static int gfx_v7_0_mqd_deactivate(struct amdgpu_device *adev)
2863 /* disable the queue if it's active */
2864 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2865 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2866 for (i = 0; i < adev->usec_timeout; i++) {
2867 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2872 if (i == adev->usec_timeout)
2875 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
2876 WREG32(mmCP_HQD_PQ_RPTR, 0);
2877 WREG32(mmCP_HQD_PQ_WPTR, 0);
2883 static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
2884 struct cik_mqd *mqd,
2885 uint64_t mqd_gpu_addr,
2886 struct amdgpu_ring *ring)
2891 /* init the mqd struct */
2892 memset(mqd, 0, sizeof(struct cik_mqd));
2894 mqd->header = 0xC0310800;
2895 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2896 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2897 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2898 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2900 /* enable doorbell? */
2901 mqd->cp_hqd_pq_doorbell_control =
2902 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2903 if (ring->use_doorbell)
2904 mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2906 mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2908 /* set the pointer to the MQD */
2909 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
2910 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2912 /* set MQD vmid to 0 */
2913 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2914 mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2916 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2917 hqd_gpu_addr = ring->gpu_addr >> 8;
2918 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2919 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2921 /* set up the HQD, this is similar to CP_RB0_CNTL */
2922 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2923 mqd->cp_hqd_pq_control &=
2924 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2925 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2927 mqd->cp_hqd_pq_control |=
2928 order_base_2(ring->ring_size / 8);
2929 mqd->cp_hqd_pq_control |=
2930 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2932 mqd->cp_hqd_pq_control |=
2933 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
2935 mqd->cp_hqd_pq_control &=
2936 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2937 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2938 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2939 mqd->cp_hqd_pq_control |=
2940 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2941 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2943 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2944 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2945 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2946 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2948 /* set the wb address wether it's enabled or not */
2949 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2950 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2951 mqd->cp_hqd_pq_rptr_report_addr_hi =
2952 upper_32_bits(wb_gpu_addr) & 0xffff;
2954 /* enable the doorbell if requested */
2955 if (ring->use_doorbell) {
2956 mqd->cp_hqd_pq_doorbell_control =
2957 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2958 mqd->cp_hqd_pq_doorbell_control &=
2959 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2960 mqd->cp_hqd_pq_doorbell_control |=
2961 (ring->doorbell_index <<
2962 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2963 mqd->cp_hqd_pq_doorbell_control |=
2964 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2965 mqd->cp_hqd_pq_doorbell_control &=
2966 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2967 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2970 mqd->cp_hqd_pq_doorbell_control = 0;
2973 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2975 mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
2976 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2978 /* set the vmid for the queue */
2979 mqd->cp_hqd_vmid = 0;
2982 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
2983 mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
2984 mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
2985 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
2986 mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
2987 mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
2988 mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
2989 mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
2990 mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
2991 mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
2992 mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
2993 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2994 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
2995 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
2996 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
2997 mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
2999 /* activate the queue */
3000 mqd->cp_hqd_active = 1;
3003 int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
3009 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_MQD_CONTROL */
3010 mqd_data = &mqd->cp_mqd_base_addr_lo;
3012 /* disable wptr polling */
3013 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3014 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3015 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3017 /* program all HQD registers */
3018 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++)
3019 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
3021 /* activate the HQD */
3022 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
3023 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
3028 static int gfx_v7_0_compute_queue_init(struct amdgpu_device *adev, int ring_id)
3032 struct cik_mqd *mqd;
3033 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
3035 r = amdgpu_bo_create_reserved(adev, sizeof(struct cik_mqd), PAGE_SIZE,
3036 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
3037 &mqd_gpu_addr, (void **)&mqd);
3039 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3043 mutex_lock(&adev->srbm_mutex);
3044 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3046 gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring);
3047 gfx_v7_0_mqd_deactivate(adev);
3048 gfx_v7_0_mqd_commit(adev, mqd);
3050 cik_srbm_select(adev, 0, 0, 0, 0);
3051 mutex_unlock(&adev->srbm_mutex);
3053 amdgpu_bo_kunmap(ring->mqd_obj);
3054 amdgpu_bo_unreserve(ring->mqd_obj);
3059 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
3061 * @adev: amdgpu_device pointer
3063 * Program the compute queues and test them to make sure they
3065 * Returns 0 for success, error for failure.
3067 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
3071 struct amdgpu_ring *ring;
3073 /* fix up chicken bits */
3074 tmp = RREG32(mmCP_CPF_DEBUG);
3076 WREG32(mmCP_CPF_DEBUG, tmp);
3078 /* init all pipes (even the ones we don't own) */
3079 for (i = 0; i < adev->gfx.mec.num_mec; i++)
3080 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++)
3081 gfx_v7_0_compute_pipe_init(adev, i, j);
3083 /* init the queues */
3084 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3085 r = gfx_v7_0_compute_queue_init(adev, i);
3087 gfx_v7_0_cp_compute_fini(adev);
3092 gfx_v7_0_cp_compute_enable(adev, true);
3094 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3095 ring = &adev->gfx.compute_ring[i];
3096 amdgpu_ring_test_helper(ring);
3102 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3104 gfx_v7_0_cp_gfx_enable(adev, enable);
3105 gfx_v7_0_cp_compute_enable(adev, enable);
3108 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3112 r = gfx_v7_0_cp_gfx_load_microcode(adev);
3115 r = gfx_v7_0_cp_compute_load_microcode(adev);
3122 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3125 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3128 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3129 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3131 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3132 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3133 WREG32(mmCP_INT_CNTL_RING0, tmp);
3136 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3140 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3142 r = gfx_v7_0_cp_load_microcode(adev);
3146 r = gfx_v7_0_cp_gfx_resume(adev);
3149 r = gfx_v7_0_cp_compute_resume(adev);
3153 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3159 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3161 * @ring: the ring to emmit the commands to
3163 * Sync the command pipeline with the PFP. E.g. wait for everything
3166 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3168 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3169 uint32_t seq = ring->fence_drv.sync_seq;
3170 uint64_t addr = ring->fence_drv.gpu_addr;
3172 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3173 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3174 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3175 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3176 amdgpu_ring_write(ring, addr & 0xfffffffc);
3177 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3178 amdgpu_ring_write(ring, seq);
3179 amdgpu_ring_write(ring, 0xffffffff);
3180 amdgpu_ring_write(ring, 4); /* poll interval */
3183 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3184 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3185 amdgpu_ring_write(ring, 0);
3186 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3187 amdgpu_ring_write(ring, 0);
3193 * VMID 0 is the physical GPU addresses as used by the kernel.
3194 * VMIDs 1-15 are used for userspace clients and are handled
3195 * by the amdgpu vm/hsa code.
3198 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3200 * @adev: amdgpu_device pointer
3202 * Update the page table base and flush the VM TLB
3203 * using the CP (CIK).
3205 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3206 unsigned vmid, uint64_t pd_addr)
3208 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3210 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
3212 /* wait for the invalidate to complete */
3213 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3214 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3215 WAIT_REG_MEM_FUNCTION(0) | /* always */
3216 WAIT_REG_MEM_ENGINE(0))); /* me */
3217 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3218 amdgpu_ring_write(ring, 0);
3219 amdgpu_ring_write(ring, 0); /* ref */
3220 amdgpu_ring_write(ring, 0); /* mask */
3221 amdgpu_ring_write(ring, 0x20); /* poll interval */
3223 /* compute doesn't have PFP */
3225 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3226 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3227 amdgpu_ring_write(ring, 0x0);
3229 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3230 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3231 amdgpu_ring_write(ring, 0);
3232 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3233 amdgpu_ring_write(ring, 0);
3237 static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
3238 uint32_t reg, uint32_t val)
3240 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3242 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3243 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3244 WRITE_DATA_DST_SEL(0)));
3245 amdgpu_ring_write(ring, reg);
3246 amdgpu_ring_write(ring, 0);
3247 amdgpu_ring_write(ring, val);
3252 * The RLC is a multi-purpose microengine that handles a
3253 * variety of functions.
3255 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3258 volatile u32 *dst_ptr;
3260 const struct cs_section_def *cs_data;
3263 /* allocate rlc buffers */
3264 if (adev->flags & AMD_IS_APU) {
3265 if (adev->asic_type == CHIP_KAVERI) {
3266 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3267 adev->gfx.rlc.reg_list_size =
3268 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3270 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3271 adev->gfx.rlc.reg_list_size =
3272 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3275 adev->gfx.rlc.cs_data = ci_cs_data;
3276 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3277 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3279 src_ptr = adev->gfx.rlc.reg_list;
3280 dws = adev->gfx.rlc.reg_list_size;
3281 dws += (5 * 16) + 48 + 48 + 64;
3283 cs_data = adev->gfx.rlc.cs_data;
3286 /* save restore block */
3287 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
3288 AMDGPU_GEM_DOMAIN_VRAM,
3289 &adev->gfx.rlc.save_restore_obj,
3290 &adev->gfx.rlc.save_restore_gpu_addr,
3291 (void **)&adev->gfx.rlc.sr_ptr);
3293 dev_warn(adev->dev, "(%d) create, pin or map of RLC sr bo failed\n", r);
3294 amdgpu_gfx_rlc_fini(adev);
3298 /* write the sr buffer */
3299 dst_ptr = adev->gfx.rlc.sr_ptr;
3300 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3301 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3302 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3303 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3307 /* clear state block */
3308 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3310 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
3311 AMDGPU_GEM_DOMAIN_VRAM,
3312 &adev->gfx.rlc.clear_state_obj,
3313 &adev->gfx.rlc.clear_state_gpu_addr,
3314 (void **)&adev->gfx.rlc.cs_ptr);
3316 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3317 amdgpu_gfx_rlc_fini(adev);
3321 /* set up the cs buffer */
3322 dst_ptr = adev->gfx.rlc.cs_ptr;
3323 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3324 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3325 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3328 if (adev->gfx.rlc.cp_table_size) {
3330 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
3331 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
3332 &adev->gfx.rlc.cp_table_obj,
3333 &adev->gfx.rlc.cp_table_gpu_addr,
3334 (void **)&adev->gfx.rlc.cp_table_ptr);
3336 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3337 amdgpu_gfx_rlc_fini(adev);
3341 gfx_v7_0_init_cp_pg_table(adev);
3343 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3344 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3351 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3355 tmp = RREG32(mmRLC_LB_CNTL);
3357 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3359 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3360 WREG32(mmRLC_LB_CNTL, tmp);
3363 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3368 mutex_lock(&adev->grbm_idx_mutex);
3369 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3370 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3371 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
3372 for (k = 0; k < adev->usec_timeout; k++) {
3373 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3379 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3380 mutex_unlock(&adev->grbm_idx_mutex);
3382 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3383 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3384 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3385 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3386 for (k = 0; k < adev->usec_timeout; k++) {
3387 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3393 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3397 tmp = RREG32(mmRLC_CNTL);
3399 WREG32(mmRLC_CNTL, rlc);
3402 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3406 orig = data = RREG32(mmRLC_CNTL);
3408 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3411 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3412 WREG32(mmRLC_CNTL, data);
3414 for (i = 0; i < adev->usec_timeout; i++) {
3415 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3420 gfx_v7_0_wait_for_rlc_serdes(adev);
3426 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3430 tmp = 0x1 | (1 << 1);
3431 WREG32(mmRLC_GPR_REG2, tmp);
3433 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3434 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3435 for (i = 0; i < adev->usec_timeout; i++) {
3436 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3441 for (i = 0; i < adev->usec_timeout; i++) {
3442 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3448 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3452 tmp = 0x1 | (0 << 1);
3453 WREG32(mmRLC_GPR_REG2, tmp);
3457 * gfx_v7_0_rlc_stop - stop the RLC ME
3459 * @adev: amdgpu_device pointer
3461 * Halt the RLC ME (MicroEngine) (CIK).
3463 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3465 WREG32(mmRLC_CNTL, 0);
3467 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3469 gfx_v7_0_wait_for_rlc_serdes(adev);
3473 * gfx_v7_0_rlc_start - start the RLC ME
3475 * @adev: amdgpu_device pointer
3477 * Unhalt the RLC ME (MicroEngine) (CIK).
3479 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3481 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3483 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3488 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3490 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3492 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3493 WREG32(mmGRBM_SOFT_RESET, tmp);
3495 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3496 WREG32(mmGRBM_SOFT_RESET, tmp);
3501 * gfx_v7_0_rlc_resume - setup the RLC hw
3503 * @adev: amdgpu_device pointer
3505 * Initialize the RLC registers, load the ucode,
3506 * and start the RLC (CIK).
3507 * Returns 0 for success, -EINVAL if the ucode is not available.
3509 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3511 const struct rlc_firmware_header_v1_0 *hdr;
3512 const __le32 *fw_data;
3513 unsigned i, fw_size;
3516 if (!adev->gfx.rlc_fw)
3519 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3520 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3521 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3522 adev->gfx.rlc_feature_version = le32_to_cpu(
3523 hdr->ucode_feature_version);
3525 adev->gfx.rlc.funcs->stop(adev);
3528 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3529 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3531 adev->gfx.rlc.funcs->reset(adev);
3533 gfx_v7_0_init_pg(adev);
3535 WREG32(mmRLC_LB_CNTR_INIT, 0);
3536 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3538 mutex_lock(&adev->grbm_idx_mutex);
3539 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3540 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3541 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3542 WREG32(mmRLC_LB_CNTL, 0x80000004);
3543 mutex_unlock(&adev->grbm_idx_mutex);
3545 WREG32(mmRLC_MC_CNTL, 0);
3546 WREG32(mmRLC_UCODE_CNTL, 0);
3548 fw_data = (const __le32 *)
3549 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3550 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3551 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3552 for (i = 0; i < fw_size; i++)
3553 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3554 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3556 /* XXX - find out what chips support lbpw */
3557 gfx_v7_0_enable_lbpw(adev, false);
3559 if (adev->asic_type == CHIP_BONAIRE)
3560 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3562 adev->gfx.rlc.funcs->start(adev);
3567 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3569 u32 data, orig, tmp, tmp2;
3571 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3573 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3574 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3576 tmp = gfx_v7_0_halt_rlc(adev);
3578 mutex_lock(&adev->grbm_idx_mutex);
3579 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3580 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3581 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3582 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3583 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3584 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3585 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3586 mutex_unlock(&adev->grbm_idx_mutex);
3588 gfx_v7_0_update_rlc(adev, tmp);
3590 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3592 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3595 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3597 RREG32(mmCB_CGTT_SCLK_CTRL);
3598 RREG32(mmCB_CGTT_SCLK_CTRL);
3599 RREG32(mmCB_CGTT_SCLK_CTRL);
3600 RREG32(mmCB_CGTT_SCLK_CTRL);
3602 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3604 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3606 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3610 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3612 u32 data, orig, tmp = 0;
3614 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3615 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3616 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3617 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3618 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3620 WREG32(mmCP_MEM_SLP_CNTL, data);
3624 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3628 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3630 tmp = gfx_v7_0_halt_rlc(adev);
3632 mutex_lock(&adev->grbm_idx_mutex);
3633 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3634 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3635 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3636 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3637 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3638 WREG32(mmRLC_SERDES_WR_CTRL, data);
3639 mutex_unlock(&adev->grbm_idx_mutex);
3641 gfx_v7_0_update_rlc(adev, tmp);
3643 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3644 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3645 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3646 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3647 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3648 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3649 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3650 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3651 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3652 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3653 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3654 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3656 WREG32(mmCGTS_SM_CTRL_REG, data);
3659 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3662 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3664 data = RREG32(mmRLC_MEM_SLP_CNTL);
3665 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3666 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3667 WREG32(mmRLC_MEM_SLP_CNTL, data);
3670 data = RREG32(mmCP_MEM_SLP_CNTL);
3671 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3672 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3673 WREG32(mmCP_MEM_SLP_CNTL, data);
3676 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3677 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3679 WREG32(mmCGTS_SM_CTRL_REG, data);
3681 tmp = gfx_v7_0_halt_rlc(adev);
3683 mutex_lock(&adev->grbm_idx_mutex);
3684 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3685 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3686 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3687 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3688 WREG32(mmRLC_SERDES_WR_CTRL, data);
3689 mutex_unlock(&adev->grbm_idx_mutex);
3691 gfx_v7_0_update_rlc(adev, tmp);
3695 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3698 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3699 /* order matters! */
3701 gfx_v7_0_enable_mgcg(adev, true);
3702 gfx_v7_0_enable_cgcg(adev, true);
3704 gfx_v7_0_enable_cgcg(adev, false);
3705 gfx_v7_0_enable_mgcg(adev, false);
3707 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3710 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3715 orig = data = RREG32(mmRLC_PG_CNTL);
3716 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3717 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3719 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3721 WREG32(mmRLC_PG_CNTL, data);
3724 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3729 orig = data = RREG32(mmRLC_PG_CNTL);
3730 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3731 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3733 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3735 WREG32(mmRLC_PG_CNTL, data);
3738 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3742 orig = data = RREG32(mmRLC_PG_CNTL);
3743 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3748 WREG32(mmRLC_PG_CNTL, data);
3751 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3755 orig = data = RREG32(mmRLC_PG_CNTL);
3756 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3761 WREG32(mmRLC_PG_CNTL, data);
3764 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3766 const __le32 *fw_data;
3767 volatile u32 *dst_ptr;
3768 int me, i, max_me = 4;
3770 u32 table_offset, table_size;
3772 if (adev->asic_type == CHIP_KAVERI)
3775 if (adev->gfx.rlc.cp_table_ptr == NULL)
3778 /* write the cp table buffer */
3779 dst_ptr = adev->gfx.rlc.cp_table_ptr;
3780 for (me = 0; me < max_me; me++) {
3782 const struct gfx_firmware_header_v1_0 *hdr =
3783 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3784 fw_data = (const __le32 *)
3785 (adev->gfx.ce_fw->data +
3786 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3787 table_offset = le32_to_cpu(hdr->jt_offset);
3788 table_size = le32_to_cpu(hdr->jt_size);
3789 } else if (me == 1) {
3790 const struct gfx_firmware_header_v1_0 *hdr =
3791 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3792 fw_data = (const __le32 *)
3793 (adev->gfx.pfp_fw->data +
3794 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3795 table_offset = le32_to_cpu(hdr->jt_offset);
3796 table_size = le32_to_cpu(hdr->jt_size);
3797 } else if (me == 2) {
3798 const struct gfx_firmware_header_v1_0 *hdr =
3799 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3800 fw_data = (const __le32 *)
3801 (adev->gfx.me_fw->data +
3802 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3803 table_offset = le32_to_cpu(hdr->jt_offset);
3804 table_size = le32_to_cpu(hdr->jt_size);
3805 } else if (me == 3) {
3806 const struct gfx_firmware_header_v1_0 *hdr =
3807 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3808 fw_data = (const __le32 *)
3809 (adev->gfx.mec_fw->data +
3810 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3811 table_offset = le32_to_cpu(hdr->jt_offset);
3812 table_size = le32_to_cpu(hdr->jt_size);
3814 const struct gfx_firmware_header_v1_0 *hdr =
3815 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3816 fw_data = (const __le32 *)
3817 (adev->gfx.mec2_fw->data +
3818 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3819 table_offset = le32_to_cpu(hdr->jt_offset);
3820 table_size = le32_to_cpu(hdr->jt_size);
3823 for (i = 0; i < table_size; i ++) {
3824 dst_ptr[bo_offset + i] =
3825 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3828 bo_offset += table_size;
3832 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3837 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3838 orig = data = RREG32(mmRLC_PG_CNTL);
3839 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3841 WREG32(mmRLC_PG_CNTL, data);
3843 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3844 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3846 WREG32(mmRLC_AUTO_PG_CTRL, data);
3848 orig = data = RREG32(mmRLC_PG_CNTL);
3849 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3851 WREG32(mmRLC_PG_CNTL, data);
3853 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3854 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3856 WREG32(mmRLC_AUTO_PG_CTRL, data);
3858 data = RREG32(mmDB_RENDER_CONTROL);
3862 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
3870 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3871 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3873 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
3876 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3880 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3881 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
3883 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3884 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3886 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
3888 return (~data) & mask;
3891 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3895 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
3897 tmp = RREG32(mmRLC_MAX_PG_CU);
3898 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3899 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3900 WREG32(mmRLC_MAX_PG_CU, tmp);
3903 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3908 orig = data = RREG32(mmRLC_PG_CNTL);
3909 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
3910 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3912 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3914 WREG32(mmRLC_PG_CNTL, data);
3917 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3922 orig = data = RREG32(mmRLC_PG_CNTL);
3923 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
3924 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3926 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3928 WREG32(mmRLC_PG_CNTL, data);
3931 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3932 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
3934 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3939 if (adev->gfx.rlc.cs_data) {
3940 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3941 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3942 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3943 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3945 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3946 for (i = 0; i < 3; i++)
3947 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3949 if (adev->gfx.rlc.reg_list) {
3950 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3951 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3952 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3955 orig = data = RREG32(mmRLC_PG_CNTL);
3956 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3958 WREG32(mmRLC_PG_CNTL, data);
3960 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3961 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3963 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3964 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3965 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3966 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3969 WREG32(mmRLC_PG_DELAY, data);
3971 data = RREG32(mmRLC_PG_DELAY_2);
3974 WREG32(mmRLC_PG_DELAY_2, data);
3976 data = RREG32(mmRLC_AUTO_PG_CTRL);
3977 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3978 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3979 WREG32(mmRLC_AUTO_PG_CTRL, data);
3983 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3985 gfx_v7_0_enable_gfx_cgpg(adev, enable);
3986 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
3987 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
3990 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
3993 const struct cs_section_def *sect = NULL;
3994 const struct cs_extent_def *ext = NULL;
3996 if (adev->gfx.rlc.cs_data == NULL)
3999 /* begin clear state */
4001 /* context control state */
4004 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4005 for (ext = sect->section; ext->extent != NULL; ++ext) {
4006 if (sect->id == SECT_CONTEXT)
4007 count += 2 + ext->reg_count;
4012 /* pa_sc_raster_config/pa_sc_raster_config1 */
4014 /* end clear state */
4022 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4023 volatile u32 *buffer)
4026 const struct cs_section_def *sect = NULL;
4027 const struct cs_extent_def *ext = NULL;
4029 if (adev->gfx.rlc.cs_data == NULL)
4034 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4035 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4037 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4038 buffer[count++] = cpu_to_le32(0x80000000);
4039 buffer[count++] = cpu_to_le32(0x80000000);
4041 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4042 for (ext = sect->section; ext->extent != NULL; ++ext) {
4043 if (sect->id == SECT_CONTEXT) {
4045 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4046 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4047 for (i = 0; i < ext->reg_count; i++)
4048 buffer[count++] = cpu_to_le32(ext->extent[i]);
4055 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4056 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4057 switch (adev->asic_type) {
4059 buffer[count++] = cpu_to_le32(0x16000012);
4060 buffer[count++] = cpu_to_le32(0x00000000);
4063 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4064 buffer[count++] = cpu_to_le32(0x00000000);
4068 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4069 buffer[count++] = cpu_to_le32(0x00000000);
4072 buffer[count++] = cpu_to_le32(0x3a00161a);
4073 buffer[count++] = cpu_to_le32(0x0000002e);
4076 buffer[count++] = cpu_to_le32(0x00000000);
4077 buffer[count++] = cpu_to_le32(0x00000000);
4081 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4082 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4084 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4085 buffer[count++] = cpu_to_le32(0);
4088 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4090 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4091 AMD_PG_SUPPORT_GFX_SMG |
4092 AMD_PG_SUPPORT_GFX_DMG |
4094 AMD_PG_SUPPORT_GDS |
4095 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4096 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4097 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4098 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4099 gfx_v7_0_init_gfx_cgpg(adev);
4100 gfx_v7_0_enable_cp_pg(adev, true);
4101 gfx_v7_0_enable_gds_pg(adev, true);
4103 gfx_v7_0_init_ao_cu_mask(adev);
4104 gfx_v7_0_update_gfx_pg(adev, true);
4108 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4110 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4111 AMD_PG_SUPPORT_GFX_SMG |
4112 AMD_PG_SUPPORT_GFX_DMG |
4114 AMD_PG_SUPPORT_GDS |
4115 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4116 gfx_v7_0_update_gfx_pg(adev, false);
4117 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4118 gfx_v7_0_enable_cp_pg(adev, false);
4119 gfx_v7_0_enable_gds_pg(adev, false);
4125 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4127 * @adev: amdgpu_device pointer
4129 * Fetches a GPU clock counter snapshot (SI).
4130 * Returns the 64 bit clock counter snapshot.
4132 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4136 mutex_lock(&adev->gfx.gpu_clock_mutex);
4137 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4138 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4139 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4140 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4144 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4146 uint32_t gds_base, uint32_t gds_size,
4147 uint32_t gws_base, uint32_t gws_size,
4148 uint32_t oa_base, uint32_t oa_size)
4151 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4152 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4153 WRITE_DATA_DST_SEL(0)));
4154 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4155 amdgpu_ring_write(ring, 0);
4156 amdgpu_ring_write(ring, gds_base);
4159 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4160 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4161 WRITE_DATA_DST_SEL(0)));
4162 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4163 amdgpu_ring_write(ring, 0);
4164 amdgpu_ring_write(ring, gds_size);
4167 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4168 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4169 WRITE_DATA_DST_SEL(0)));
4170 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4171 amdgpu_ring_write(ring, 0);
4172 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4175 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4176 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4177 WRITE_DATA_DST_SEL(0)));
4178 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4179 amdgpu_ring_write(ring, 0);
4180 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4183 static void gfx_v7_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
4185 struct amdgpu_device *adev = ring->adev;
4188 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
4189 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
4190 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
4191 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
4192 WREG32(mmSQ_CMD, value);
4195 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4197 WREG32(mmSQ_IND_INDEX,
4198 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4199 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4200 (address << SQ_IND_INDEX__INDEX__SHIFT) |
4201 (SQ_IND_INDEX__FORCE_READ_MASK));
4202 return RREG32(mmSQ_IND_DATA);
4205 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4206 uint32_t wave, uint32_t thread,
4207 uint32_t regno, uint32_t num, uint32_t *out)
4209 WREG32(mmSQ_IND_INDEX,
4210 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4211 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4212 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4213 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4214 (SQ_IND_INDEX__FORCE_READ_MASK) |
4215 (SQ_IND_INDEX__AUTO_INCR_MASK));
4217 *(out++) = RREG32(mmSQ_IND_DATA);
4220 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4222 /* type 0 wave data */
4223 dst[(*no_fields)++] = 0;
4224 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
4225 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
4226 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
4227 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
4228 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
4229 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
4230 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
4231 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
4232 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
4233 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
4234 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
4235 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
4236 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
4237 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
4238 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
4239 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
4240 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
4241 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
4244 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4245 uint32_t wave, uint32_t start,
4246 uint32_t size, uint32_t *dst)
4249 adev, simd, wave, 0,
4250 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4253 static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev,
4254 u32 me, u32 pipe, u32 q)
4256 cik_srbm_select(adev, me, pipe, q, 0);
4259 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4260 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4261 .select_se_sh = &gfx_v7_0_select_se_sh,
4262 .read_wave_data = &gfx_v7_0_read_wave_data,
4263 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4264 .select_me_pipe_q = &gfx_v7_0_select_me_pipe_q
4267 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4268 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4269 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode,
4270 .init = gfx_v7_0_rlc_init,
4271 .resume = gfx_v7_0_rlc_resume,
4272 .stop = gfx_v7_0_rlc_stop,
4273 .reset = gfx_v7_0_rlc_reset,
4274 .start = gfx_v7_0_rlc_start
4277 static int gfx_v7_0_early_init(void *handle)
4279 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4281 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4282 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
4283 adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
4284 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
4285 gfx_v7_0_set_ring_funcs(adev);
4286 gfx_v7_0_set_irq_funcs(adev);
4287 gfx_v7_0_set_gds_init(adev);
4292 static int gfx_v7_0_late_init(void *handle)
4294 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4297 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4301 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4308 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4311 u32 mc_shared_chmap, mc_arb_ramcfg;
4312 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4315 switch (adev->asic_type) {
4317 adev->gfx.config.max_shader_engines = 2;
4318 adev->gfx.config.max_tile_pipes = 4;
4319 adev->gfx.config.max_cu_per_sh = 7;
4320 adev->gfx.config.max_sh_per_se = 1;
4321 adev->gfx.config.max_backends_per_se = 2;
4322 adev->gfx.config.max_texture_channel_caches = 4;
4323 adev->gfx.config.max_gprs = 256;
4324 adev->gfx.config.max_gs_threads = 32;
4325 adev->gfx.config.max_hw_contexts = 8;
4327 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4328 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4329 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4330 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4331 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4334 adev->gfx.config.max_shader_engines = 4;
4335 adev->gfx.config.max_tile_pipes = 16;
4336 adev->gfx.config.max_cu_per_sh = 11;
4337 adev->gfx.config.max_sh_per_se = 1;
4338 adev->gfx.config.max_backends_per_se = 4;
4339 adev->gfx.config.max_texture_channel_caches = 16;
4340 adev->gfx.config.max_gprs = 256;
4341 adev->gfx.config.max_gs_threads = 32;
4342 adev->gfx.config.max_hw_contexts = 8;
4344 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4345 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4346 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4347 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4348 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4351 adev->gfx.config.max_shader_engines = 1;
4352 adev->gfx.config.max_tile_pipes = 4;
4353 adev->gfx.config.max_cu_per_sh = 8;
4354 adev->gfx.config.max_backends_per_se = 2;
4355 adev->gfx.config.max_sh_per_se = 1;
4356 adev->gfx.config.max_texture_channel_caches = 4;
4357 adev->gfx.config.max_gprs = 256;
4358 adev->gfx.config.max_gs_threads = 16;
4359 adev->gfx.config.max_hw_contexts = 8;
4361 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4362 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4363 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4364 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4365 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4370 adev->gfx.config.max_shader_engines = 1;
4371 adev->gfx.config.max_tile_pipes = 2;
4372 adev->gfx.config.max_cu_per_sh = 2;
4373 adev->gfx.config.max_sh_per_se = 1;
4374 adev->gfx.config.max_backends_per_se = 1;
4375 adev->gfx.config.max_texture_channel_caches = 2;
4376 adev->gfx.config.max_gprs = 256;
4377 adev->gfx.config.max_gs_threads = 16;
4378 adev->gfx.config.max_hw_contexts = 8;
4380 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4381 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4382 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4383 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4384 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4388 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4389 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4390 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4392 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4393 adev->gfx.config.mem_max_burst_length_bytes = 256;
4394 if (adev->flags & AMD_IS_APU) {
4395 /* Get memory bank mapping mode. */
4396 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4397 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4398 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4400 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4401 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4402 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4404 /* Validate settings in case only one DIMM installed. */
4405 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4406 dimm00_addr_map = 0;
4407 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4408 dimm01_addr_map = 0;
4409 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4410 dimm10_addr_map = 0;
4411 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4412 dimm11_addr_map = 0;
4414 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4415 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4416 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4417 adev->gfx.config.mem_row_size_in_kb = 2;
4419 adev->gfx.config.mem_row_size_in_kb = 1;
4421 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4422 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4423 if (adev->gfx.config.mem_row_size_in_kb > 4)
4424 adev->gfx.config.mem_row_size_in_kb = 4;
4426 /* XXX use MC settings? */
4427 adev->gfx.config.shader_engine_tile_size = 32;
4428 adev->gfx.config.num_gpus = 1;
4429 adev->gfx.config.multi_gpu_tile_size = 64;
4431 /* fix up row size */
4432 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4433 switch (adev->gfx.config.mem_row_size_in_kb) {
4436 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4439 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4442 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4445 adev->gfx.config.gb_addr_config = gb_addr_config;
4448 static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4449 int mec, int pipe, int queue)
4453 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
4458 ring->queue = queue;
4460 ring->ring_obj = NULL;
4461 ring->use_doorbell = true;
4462 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + ring_id;
4463 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4465 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4466 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4469 /* type-2 packets are deprecated on MEC, use type-3 instead */
4470 r = amdgpu_ring_init(adev, ring, 1024,
4471 &adev->gfx.eop_irq, irq_type);
4479 static int gfx_v7_0_sw_init(void *handle)
4481 struct amdgpu_ring *ring;
4482 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4483 int i, j, k, r, ring_id;
4485 switch (adev->asic_type) {
4487 adev->gfx.mec.num_mec = 2;
4494 adev->gfx.mec.num_mec = 1;
4497 adev->gfx.mec.num_pipe_per_mec = 4;
4498 adev->gfx.mec.num_queue_per_pipe = 8;
4501 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
4505 /* Privileged reg */
4506 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184,
4507 &adev->gfx.priv_reg_irq);
4511 /* Privileged inst */
4512 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185,
4513 &adev->gfx.priv_inst_irq);
4517 gfx_v7_0_scratch_init(adev);
4519 r = gfx_v7_0_init_microcode(adev);
4521 DRM_ERROR("Failed to load gfx firmware!\n");
4525 r = adev->gfx.rlc.funcs->init(adev);
4527 DRM_ERROR("Failed to init rlc BOs!\n");
4531 /* allocate mec buffers */
4532 r = gfx_v7_0_mec_init(adev);
4534 DRM_ERROR("Failed to init MEC BOs!\n");
4538 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4539 ring = &adev->gfx.gfx_ring[i];
4540 ring->ring_obj = NULL;
4541 sprintf(ring->name, "gfx");
4542 r = amdgpu_ring_init(adev, ring, 1024,
4543 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
4548 /* set up the compute queues - allocate horizontally across pipes */
4550 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4551 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4552 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4553 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
4556 r = gfx_v7_0_compute_ring_init(adev,
4567 adev->gfx.ce_ram_size = 0x8000;
4569 gfx_v7_0_gpu_early_init(adev);
4574 static int gfx_v7_0_sw_fini(void *handle)
4577 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4579 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
4580 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
4581 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
4583 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4584 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4585 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4586 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4588 gfx_v7_0_cp_compute_fini(adev);
4589 amdgpu_gfx_rlc_fini(adev);
4590 gfx_v7_0_mec_fini(adev);
4591 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4592 &adev->gfx.rlc.clear_state_gpu_addr,
4593 (void **)&adev->gfx.rlc.cs_ptr);
4594 if (adev->gfx.rlc.cp_table_size) {
4595 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4596 &adev->gfx.rlc.cp_table_gpu_addr,
4597 (void **)&adev->gfx.rlc.cp_table_ptr);
4599 gfx_v7_0_free_microcode(adev);
4604 static int gfx_v7_0_hw_init(void *handle)
4607 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4609 gfx_v7_0_constants_init(adev);
4612 r = adev->gfx.rlc.funcs->resume(adev);
4616 r = gfx_v7_0_cp_resume(adev);
4623 static int gfx_v7_0_hw_fini(void *handle)
4625 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4627 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4628 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4629 gfx_v7_0_cp_enable(adev, false);
4630 adev->gfx.rlc.funcs->stop(adev);
4631 gfx_v7_0_fini_pg(adev);
4636 static int gfx_v7_0_suspend(void *handle)
4638 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4640 return gfx_v7_0_hw_fini(adev);
4643 static int gfx_v7_0_resume(void *handle)
4645 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4647 return gfx_v7_0_hw_init(adev);
4650 static bool gfx_v7_0_is_idle(void *handle)
4652 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4654 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4660 static int gfx_v7_0_wait_for_idle(void *handle)
4664 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4666 for (i = 0; i < adev->usec_timeout; i++) {
4667 /* read MC_STATUS */
4668 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4677 static int gfx_v7_0_soft_reset(void *handle)
4679 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4681 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4684 tmp = RREG32(mmGRBM_STATUS);
4685 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4686 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4687 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4688 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4689 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4690 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4691 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4692 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4694 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4695 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4696 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4700 tmp = RREG32(mmGRBM_STATUS2);
4701 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4702 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4705 tmp = RREG32(mmSRBM_STATUS);
4706 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4707 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4709 if (grbm_soft_reset || srbm_soft_reset) {
4711 gfx_v7_0_fini_pg(adev);
4712 gfx_v7_0_update_cg(adev, false);
4715 adev->gfx.rlc.funcs->stop(adev);
4717 /* Disable GFX parsing/prefetching */
4718 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4720 /* Disable MEC parsing/prefetching */
4721 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4723 if (grbm_soft_reset) {
4724 tmp = RREG32(mmGRBM_SOFT_RESET);
4725 tmp |= grbm_soft_reset;
4726 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4727 WREG32(mmGRBM_SOFT_RESET, tmp);
4728 tmp = RREG32(mmGRBM_SOFT_RESET);
4732 tmp &= ~grbm_soft_reset;
4733 WREG32(mmGRBM_SOFT_RESET, tmp);
4734 tmp = RREG32(mmGRBM_SOFT_RESET);
4737 if (srbm_soft_reset) {
4738 tmp = RREG32(mmSRBM_SOFT_RESET);
4739 tmp |= srbm_soft_reset;
4740 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4741 WREG32(mmSRBM_SOFT_RESET, tmp);
4742 tmp = RREG32(mmSRBM_SOFT_RESET);
4746 tmp &= ~srbm_soft_reset;
4747 WREG32(mmSRBM_SOFT_RESET, tmp);
4748 tmp = RREG32(mmSRBM_SOFT_RESET);
4750 /* Wait a little for things to settle down */
4756 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4757 enum amdgpu_interrupt_state state)
4762 case AMDGPU_IRQ_STATE_DISABLE:
4763 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4764 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4765 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4767 case AMDGPU_IRQ_STATE_ENABLE:
4768 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4769 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4770 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4777 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4779 enum amdgpu_interrupt_state state)
4781 u32 mec_int_cntl, mec_int_cntl_reg;
4784 * amdgpu controls only the first MEC. That's why this function only
4785 * handles the setting of interrupts for this specific MEC. All other
4786 * pipes' interrupts are set by amdkfd.
4792 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4795 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
4798 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
4801 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
4804 DRM_DEBUG("invalid pipe %d\n", pipe);
4808 DRM_DEBUG("invalid me %d\n", me);
4813 case AMDGPU_IRQ_STATE_DISABLE:
4814 mec_int_cntl = RREG32(mec_int_cntl_reg);
4815 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4816 WREG32(mec_int_cntl_reg, mec_int_cntl);
4818 case AMDGPU_IRQ_STATE_ENABLE:
4819 mec_int_cntl = RREG32(mec_int_cntl_reg);
4820 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4821 WREG32(mec_int_cntl_reg, mec_int_cntl);
4828 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4829 struct amdgpu_irq_src *src,
4831 enum amdgpu_interrupt_state state)
4836 case AMDGPU_IRQ_STATE_DISABLE:
4837 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4838 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4839 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4841 case AMDGPU_IRQ_STATE_ENABLE:
4842 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4843 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4844 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4853 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4854 struct amdgpu_irq_src *src,
4856 enum amdgpu_interrupt_state state)
4861 case AMDGPU_IRQ_STATE_DISABLE:
4862 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4863 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4864 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4866 case AMDGPU_IRQ_STATE_ENABLE:
4867 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4868 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4869 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4878 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4879 struct amdgpu_irq_src *src,
4881 enum amdgpu_interrupt_state state)
4884 case AMDGPU_CP_IRQ_GFX_EOP:
4885 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4887 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4888 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4890 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4891 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4893 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4894 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4896 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4897 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4899 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4900 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4902 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4903 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4905 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4906 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4908 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4909 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4917 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4918 struct amdgpu_irq_src *source,
4919 struct amdgpu_iv_entry *entry)
4922 struct amdgpu_ring *ring;
4925 DRM_DEBUG("IH: CP EOP\n");
4926 me_id = (entry->ring_id & 0x0c) >> 2;
4927 pipe_id = (entry->ring_id & 0x03) >> 0;
4930 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4934 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4935 ring = &adev->gfx.compute_ring[i];
4936 if ((ring->me == me_id) && (ring->pipe == pipe_id))
4937 amdgpu_fence_process(ring);
4944 static void gfx_v7_0_fault(struct amdgpu_device *adev,
4945 struct amdgpu_iv_entry *entry)
4947 struct amdgpu_ring *ring;
4951 me_id = (entry->ring_id & 0x0c) >> 2;
4952 pipe_id = (entry->ring_id & 0x03) >> 0;
4955 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
4959 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4960 ring = &adev->gfx.compute_ring[i];
4961 if ((ring->me == me_id) && (ring->pipe == pipe_id))
4962 drm_sched_fault(&ring->sched);
4968 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
4969 struct amdgpu_irq_src *source,
4970 struct amdgpu_iv_entry *entry)
4972 DRM_ERROR("Illegal register access in command stream\n");
4973 gfx_v7_0_fault(adev, entry);
4977 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
4978 struct amdgpu_irq_src *source,
4979 struct amdgpu_iv_entry *entry)
4981 DRM_ERROR("Illegal instruction in command stream\n");
4982 // XXX soft reset the gfx block only
4983 gfx_v7_0_fault(adev, entry);
4987 static int gfx_v7_0_set_clockgating_state(void *handle,
4988 enum amd_clockgating_state state)
4991 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4993 if (state == AMD_CG_STATE_GATE)
4996 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4997 /* order matters! */
4999 gfx_v7_0_enable_mgcg(adev, true);
5000 gfx_v7_0_enable_cgcg(adev, true);
5002 gfx_v7_0_enable_cgcg(adev, false);
5003 gfx_v7_0_enable_mgcg(adev, false);
5005 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5010 static int gfx_v7_0_set_powergating_state(void *handle,
5011 enum amd_powergating_state state)
5014 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5016 if (state == AMD_PG_STATE_GATE)
5019 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
5020 AMD_PG_SUPPORT_GFX_SMG |
5021 AMD_PG_SUPPORT_GFX_DMG |
5023 AMD_PG_SUPPORT_GDS |
5024 AMD_PG_SUPPORT_RLC_SMU_HS)) {
5025 gfx_v7_0_update_gfx_pg(adev, gate);
5026 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
5027 gfx_v7_0_enable_cp_pg(adev, gate);
5028 gfx_v7_0_enable_gds_pg(adev, gate);
5035 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5037 .early_init = gfx_v7_0_early_init,
5038 .late_init = gfx_v7_0_late_init,
5039 .sw_init = gfx_v7_0_sw_init,
5040 .sw_fini = gfx_v7_0_sw_fini,
5041 .hw_init = gfx_v7_0_hw_init,
5042 .hw_fini = gfx_v7_0_hw_fini,
5043 .suspend = gfx_v7_0_suspend,
5044 .resume = gfx_v7_0_resume,
5045 .is_idle = gfx_v7_0_is_idle,
5046 .wait_for_idle = gfx_v7_0_wait_for_idle,
5047 .soft_reset = gfx_v7_0_soft_reset,
5048 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5049 .set_powergating_state = gfx_v7_0_set_powergating_state,
5052 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5053 .type = AMDGPU_RING_TYPE_GFX,
5055 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5056 .support_64bit_ptrs = false,
5057 .get_rptr = gfx_v7_0_ring_get_rptr,
5058 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5059 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5061 20 + /* gfx_v7_0_ring_emit_gds_switch */
5062 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5063 5 + /* hdp invalidate */
5064 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5065 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5066 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
5067 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5068 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
5069 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
5070 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
5071 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5072 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5073 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5074 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5075 .test_ring = gfx_v7_0_ring_test_ring,
5076 .test_ib = gfx_v7_0_ring_test_ib,
5077 .insert_nop = amdgpu_ring_insert_nop,
5078 .pad_ib = amdgpu_ring_generic_pad_ib,
5079 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
5080 .emit_wreg = gfx_v7_0_ring_emit_wreg,
5081 .soft_recovery = gfx_v7_0_ring_soft_recovery,
5084 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5085 .type = AMDGPU_RING_TYPE_COMPUTE,
5087 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5088 .support_64bit_ptrs = false,
5089 .get_rptr = gfx_v7_0_ring_get_rptr,
5090 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5091 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5093 20 + /* gfx_v7_0_ring_emit_gds_switch */
5094 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5095 5 + /* hdp invalidate */
5096 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
5097 CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */
5098 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5099 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
5100 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
5101 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
5102 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5103 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5104 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5105 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5106 .test_ring = gfx_v7_0_ring_test_ring,
5107 .test_ib = gfx_v7_0_ring_test_ib,
5108 .insert_nop = amdgpu_ring_insert_nop,
5109 .pad_ib = amdgpu_ring_generic_pad_ib,
5110 .emit_wreg = gfx_v7_0_ring_emit_wreg,
5113 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5117 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5118 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5119 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5120 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5123 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5124 .set = gfx_v7_0_set_eop_interrupt_state,
5125 .process = gfx_v7_0_eop_irq,
5128 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5129 .set = gfx_v7_0_set_priv_reg_fault_state,
5130 .process = gfx_v7_0_priv_reg_irq,
5133 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5134 .set = gfx_v7_0_set_priv_inst_fault_state,
5135 .process = gfx_v7_0_priv_inst_irq,
5138 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5140 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5141 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5143 adev->gfx.priv_reg_irq.num_types = 1;
5144 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5146 adev->gfx.priv_inst_irq.num_types = 1;
5147 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5150 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5152 /* init asci gds info */
5153 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5154 adev->gds.gws.total_size = 64;
5155 adev->gds.oa.total_size = 16;
5157 if (adev->gds.mem.total_size == 64 * 1024) {
5158 adev->gds.mem.gfx_partition_size = 4096;
5159 adev->gds.mem.cs_partition_size = 4096;
5161 adev->gds.gws.gfx_partition_size = 4;
5162 adev->gds.gws.cs_partition_size = 4;
5164 adev->gds.oa.gfx_partition_size = 4;
5165 adev->gds.oa.cs_partition_size = 1;
5167 adev->gds.mem.gfx_partition_size = 1024;
5168 adev->gds.mem.cs_partition_size = 1024;
5170 adev->gds.gws.gfx_partition_size = 16;
5171 adev->gds.gws.cs_partition_size = 16;
5173 adev->gds.oa.gfx_partition_size = 4;
5174 adev->gds.oa.cs_partition_size = 4;
5179 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5181 int i, j, k, counter, active_cu_number = 0;
5182 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5183 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5184 unsigned disable_masks[4 * 2];
5187 if (adev->flags & AMD_IS_APU)
5190 ao_cu_num = adev->gfx.config.max_cu_per_sh;
5192 memset(cu_info, 0, sizeof(*cu_info));
5194 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5196 mutex_lock(&adev->grbm_idx_mutex);
5197 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5198 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5202 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
5204 gfx_v7_0_set_user_cu_inactive_bitmap(
5205 adev, disable_masks[i * 2 + j]);
5206 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5207 cu_info->bitmap[i][j] = bitmap;
5209 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
5210 if (bitmap & mask) {
5211 if (counter < ao_cu_num)
5217 active_cu_number += counter;
5219 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5220 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5223 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5224 mutex_unlock(&adev->grbm_idx_mutex);
5226 cu_info->number = active_cu_number;
5227 cu_info->ao_cu_mask = ao_cu_mask;
5228 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5229 cu_info->max_waves_per_simd = 10;
5230 cu_info->max_scratch_slots_per_cu = 32;
5231 cu_info->wave_front_size = 64;
5232 cu_info->lds_size = 64;
5235 const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
5237 .type = AMD_IP_BLOCK_TYPE_GFX,
5241 .funcs = &gfx_v7_0_ip_funcs,
5244 const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
5246 .type = AMD_IP_BLOCK_TYPE_GFX,
5250 .funcs = &gfx_v7_0_ip_funcs,
5253 const struct amdgpu_ip_block_version gfx_v7_2_ip_block =
5255 .type = AMD_IP_BLOCK_TYPE_GFX,
5259 .funcs = &gfx_v7_0_ip_funcs,
5262 const struct amdgpu_ip_block_version gfx_v7_3_ip_block =
5264 .type = AMD_IP_BLOCK_TYPE_GFX,
5268 .funcs = &gfx_v7_0_ip_funcs,
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