drivers/gpu/drm/i915/display/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <[email protected]>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <[email protected]>
  26  *      Dave Airlie <[email protected]>
  27  *      Jesse Barnes <[email protected]>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/acpi.h>
  32 #include <linux/dmi.h>
  33 #include <linux/i2c.h>
  34 #include <linux/slab.h>
  35 #include <linux/vga_switcheroo.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_edid.h>
  40
  41 #include "i915_drv.h"
  42 #include "i915_reg.h"
  43 #include "intel_atomic.h"
  44 #include "intel_backlight.h"
  45 #include "intel_connector.h"
  46 #include "intel_de.h"
  47 #include "intel_display_types.h"
  48 #include "intel_dpll.h"
  49 #include "intel_fdi.h"
  50 #include "intel_gmbus.h"
  51 #include "intel_lvds.h"
  52 #include "intel_lvds_regs.h"
  53 #include "intel_panel.h"
  54 #include "intel_pps_regs.h"
  55
  56 /* Private structure for the integrated LVDS support */
  57 struct intel_lvds_pps {
  58         /* 100us units */
  59         int t1_t2;
  60         int t3;
  61         int t4;
  62         int t5;
  63         int tx;
  64
  65         int divider;
  66
  67         int port;
  68         bool powerdown_on_reset;
  69 };
  70
  71 struct intel_lvds_encoder {
  72         struct intel_encoder base;
  73
  74         bool is_dual_link;
  75         i915_reg_t reg;
  76         u32 a3_power;
  77
  78         struct intel_lvds_pps init_pps;
  79         u32 init_lvds_val;
  80
  81         struct intel_connector *attached_connector;
  82 };
  83
  84 static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder)
  85 {
  86         return container_of(encoder, struct intel_lvds_encoder, base);
  87 }
  88
  89 bool intel_lvds_port_enabled(struct drm_i915_private *i915,
  90                              i915_reg_t lvds_reg, enum pipe *pipe)
  91 {
  92         u32 val;
  93
  94         val = intel_de_read(i915, lvds_reg);
  95
  96         /* asserts want to know the pipe even if the port is disabled */
  97         if (HAS_PCH_CPT(i915))
  98                 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val);
  99         else
 100                 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val);
 101
 102         return val & LVDS_PORT_EN;
 103 }
 104
 105 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
 106                                     enum pipe *pipe)
 107 {
 108         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 109         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 110         intel_wakeref_t wakeref;
 111         bool ret;
 112
 113         wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain);
 114         if (!wakeref)
 115                 return false;
 116
 117         ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe);
 118
 119         intel_display_power_put(i915, encoder->power_domain, wakeref);
 120
 121         return ret;
 122 }
 123
 124 static void intel_lvds_get_config(struct intel_encoder *encoder,
 125                                   struct intel_crtc_state *crtc_state)
 126 {
 127         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 128         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 129         u32 tmp, flags = 0;
 130
 131         crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS);
 132
 133         tmp = intel_de_read(dev_priv, lvds_encoder->reg);
 134         if (tmp & LVDS_HSYNC_POLARITY)
 135                 flags |= DRM_MODE_FLAG_NHSYNC;
 136         else
 137                 flags |= DRM_MODE_FLAG_PHSYNC;
 138         if (tmp & LVDS_VSYNC_POLARITY)
 139                 flags |= DRM_MODE_FLAG_NVSYNC;
 140         else
 141                 flags |= DRM_MODE_FLAG_PVSYNC;
 142
 143         crtc_state->hw.adjusted_mode.flags |= flags;
 144
 145         if (DISPLAY_VER(dev_priv) < 5)
 146                 crtc_state->gmch_pfit.lvds_border_bits =
 147                         tmp & LVDS_BORDER_ENABLE;
 148
 149         /* gen2/3 store dither state in pfit control, needs to match */
 150         if (DISPLAY_VER(dev_priv) < 4) {
 151                 tmp = intel_de_read(dev_priv, PFIT_CONTROL);
 152
 153                 crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
 154         }
 155
 156         crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
 157 }
 158
 159 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 160                                         struct intel_lvds_pps *pps)
 161 {
 162         u32 val;
 163
 164         pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET;
 165
 166         val = intel_de_read(dev_priv, PP_ON_DELAYS(0));
 167         pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
 168         pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
 169         pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
 170
 171         val = intel_de_read(dev_priv, PP_OFF_DELAYS(0));
 172         pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
 173         pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
 174
 175         val = intel_de_read(dev_priv, PP_DIVISOR(0));
 176         pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
 177         val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
 178         /*
 179          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 180          * too short power-cycle delay due to the asynchronous programming of
 181          * the register.
 182          */
 183         if (val)
 184                 val--;
 185         /* Convert from 100ms to 100us units */
 186         pps->t4 = val * 1000;
 187
 188         if (DISPLAY_VER(dev_priv) <= 4 &&
 189             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 190                 drm_dbg_kms(&dev_priv->drm,
 191                             "Panel power timings uninitialized, "
 192                             "setting defaults\n");
 193                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 194                 pps->t1_t2 = 40 * 10;
 195                 pps->t5 = 200 * 10;
 196                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 197                 pps->t3 = 35 * 10;
 198                 pps->tx = 200 * 10;
 199         }
 200
 201         drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 202                 "divider %d port %d powerdown_on_reset %d\n",
 203                 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 204                 pps->divider, pps->port, pps->powerdown_on_reset);
 205 }
 206
 207 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 208                                    struct intel_lvds_pps *pps)
 209 {
 210         u32 val;
 211
 212         val = intel_de_read(dev_priv, PP_CONTROL(0));
 213         drm_WARN_ON(&dev_priv->drm,
 214                     (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 215         if (pps->powerdown_on_reset)
 216                 val |= PANEL_POWER_RESET;
 217         intel_de_write(dev_priv, PP_CONTROL(0), val);
 218
 219         intel_de_write(dev_priv, PP_ON_DELAYS(0),
 220                        REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |
 221                        REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) |
 222                        REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5));
 223
 224         intel_de_write(dev_priv, PP_OFF_DELAYS(0),
 225                        REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) |
 226                        REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx));
 227
 228         intel_de_write(dev_priv, PP_DIVISOR(0),
 229                        REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
 230                        REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1));
 231 }
 232
 233 static void intel_pre_enable_lvds(struct intel_atomic_state *state,
 234                                   struct intel_encoder *encoder,
 235                                   const struct intel_crtc_state *crtc_state,
 236                                   const struct drm_connector_state *conn_state)
 237 {
 238         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 239         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 240         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 241         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 242         enum pipe pipe = crtc->pipe;
 243         u32 temp;
 244
 245         if (HAS_PCH_SPLIT(i915)) {
 246                 assert_fdi_rx_pll_disabled(i915, pipe);
 247                 assert_shared_dpll_disabled(i915, crtc_state->shared_dpll);
 248         } else {
 249                 assert_pll_disabled(i915, pipe);
 250         }
 251
 252         intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps);
 253
 254         temp = lvds_encoder->init_lvds_val;
 255         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 256
 257         if (HAS_PCH_CPT(i915)) {
 258                 temp &= ~LVDS_PIPE_SEL_MASK_CPT;
 259                 temp |= LVDS_PIPE_SEL_CPT(pipe);
 260         } else {
 261                 temp &= ~LVDS_PIPE_SEL_MASK;
 262                 temp |= LVDS_PIPE_SEL(pipe);
 263         }
 264
 265         /* set the corresponsding LVDS_BORDER bit */
 266         temp &= ~LVDS_BORDER_ENABLE;
 267         temp |= crtc_state->gmch_pfit.lvds_border_bits;
 268
 269         /*
 270          * Set the B0-B3 data pairs corresponding to whether we're going to
 271          * set the DPLLs for dual-channel mode or not.
 272          */
 273         if (lvds_encoder->is_dual_link)
 274                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 275         else
 276                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 277
 278         /*
 279          * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 280          * appropriately here, but we need to look more thoroughly into how
 281          * panels behave in the two modes. For now, let's just maintain the
 282          * value we got from the BIOS.
 283          */
 284         temp &= ~LVDS_A3_POWER_MASK;
 285         temp |= lvds_encoder->a3_power;
 286
 287         /*
 288          * Set the dithering flag on LVDS as needed, note that there is no
 289          * special lvds dither control bit on pch-split platforms, dithering is
 290          * only controlled through the TRANSCONF reg.
 291          */
 292         if (DISPLAY_VER(i915) == 4) {
 293                 /*
 294                  * Bspec wording suggests that LVDS port dithering only exists
 295                  * for 18bpp panels.
 296                  */
 297                 if (crtc_state->dither && crtc_state->pipe_bpp == 18)
 298                         temp |= LVDS_ENABLE_DITHER;
 299                 else
 300                         temp &= ~LVDS_ENABLE_DITHER;
 301         }
 302         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 303         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 304                 temp |= LVDS_HSYNC_POLARITY;
 305         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 306                 temp |= LVDS_VSYNC_POLARITY;
 307
 308         intel_de_write(i915, lvds_encoder->reg, temp);
 309 }
 310
 311 /*
 312  * Sets the power state for the panel.
 313  */
 314 static void intel_enable_lvds(struct intel_atomic_state *state,
 315                               struct intel_encoder *encoder,
 316                               const struct intel_crtc_state *crtc_state,
 317                               const struct drm_connector_state *conn_state)
 318 {
 319         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 320         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 321
 322         intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN);
 323
 324         intel_de_rmw(dev_priv, PP_CONTROL(0), 0, PANEL_POWER_ON);
 325         intel_de_posting_read(dev_priv, lvds_encoder->reg);
 326
 327         if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000))
 328                 drm_err(&dev_priv->drm,
 329                         "timed out waiting for panel to power on\n");
 330
 331         intel_backlight_enable(crtc_state, conn_state);
 332 }
 333
 334 static void intel_disable_lvds(struct intel_atomic_state *state,
 335                                struct intel_encoder *encoder,
 336                                const struct intel_crtc_state *old_crtc_state,
 337                                const struct drm_connector_state *old_conn_state)
 338 {
 339         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 340         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 341
 342         intel_de_rmw(dev_priv, PP_CONTROL(0), PANEL_POWER_ON, 0);
 343         if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000))
 344                 drm_err(&dev_priv->drm,
 345                         "timed out waiting for panel to power off\n");
 346
 347         intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0);
 348         intel_de_posting_read(dev_priv, lvds_encoder->reg);
 349 }
 350
 351 static void gmch_disable_lvds(struct intel_atomic_state *state,
 352                               struct intel_encoder *encoder,
 353                               const struct intel_crtc_state *old_crtc_state,
 354                               const struct drm_connector_state *old_conn_state)
 355
 356 {
 357         intel_backlight_disable(old_conn_state);
 358
 359         intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
 360 }
 361
 362 static void pch_disable_lvds(struct intel_atomic_state *state,
 363                              struct intel_encoder *encoder,
 364                              const struct intel_crtc_state *old_crtc_state,
 365                              const struct drm_connector_state *old_conn_state)
 366 {
 367         intel_backlight_disable(old_conn_state);
 368 }
 369
 370 static void pch_post_disable_lvds(struct intel_atomic_state *state,
 371                                   struct intel_encoder *encoder,
 372                                   const struct intel_crtc_state *old_crtc_state,
 373                                   const struct drm_connector_state *old_conn_state)
 374 {
 375         intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
 376 }
 377
 378 static void intel_lvds_shutdown(struct intel_encoder *encoder)
 379 {
 380         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 381
 382         if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000))
 383                 drm_err(&dev_priv->drm,
 384                         "timed out waiting for panel power cycle delay\n");
 385 }
 386
 387 static enum drm_mode_status
 388 intel_lvds_mode_valid(struct drm_connector *_connector,
 389                       struct drm_display_mode *mode)
 390 {
 391         struct intel_connector *connector = to_intel_connector(_connector);
 392         const struct drm_display_mode *fixed_mode =
 393                 intel_panel_fixed_mode(connector, mode);
 394         int max_pixclk = to_i915(connector->base.dev)->max_dotclk_freq;
 395         enum drm_mode_status status;
 396
 397         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 398                 return MODE_NO_DBLESCAN;
 399
 400         status = intel_panel_mode_valid(connector, mode);
 401         if (status != MODE_OK)
 402                 return status;
 403
 404         if (fixed_mode->clock > max_pixclk)
 405                 return MODE_CLOCK_HIGH;
 406
 407         return MODE_OK;
 408 }
 409
 410 static int intel_lvds_compute_config(struct intel_encoder *encoder,
 411                                      struct intel_crtc_state *crtc_state,
 412                                      struct drm_connector_state *conn_state)
 413 {
 414         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 415         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 416         struct intel_connector *connector = lvds_encoder->attached_connector;
 417         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 418         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 419         unsigned int lvds_bpp;
 420         int ret;
 421
 422         /* Should never happen!! */
 423         if (DISPLAY_VER(i915) < 4 && crtc->pipe == 0) {
 424                 drm_err(&i915->drm, "Can't support LVDS on pipe A\n");
 425                 return -EINVAL;
 426         }
 427
 428         if (HAS_PCH_SPLIT(i915)) {
 429                 crtc_state->has_pch_encoder = true;
 430                 if (!intel_fdi_compute_pipe_bpp(crtc_state))
 431                         return -EINVAL;
 432         }
 433
 434         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 435                 lvds_bpp = 8*3;
 436         else
 437                 lvds_bpp = 6*3;
 438
 439         /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
 440         if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) {
 441                 drm_dbg_kms(&i915->drm,
 442                             "forcing display bpp (was %d) to LVDS (%d)\n",
 443                             crtc_state->pipe_bpp, lvds_bpp);
 444                 crtc_state->pipe_bpp = lvds_bpp;
 445         }
 446
 447         crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
 448         crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
 449
 450         /*
 451          * We have timings from the BIOS for the panel, put them in
 452          * to the adjusted mode.  The CRTC will be set up for this mode,
 453          * with the panel scaling set up to source from the H/VDisplay
 454          * of the original mode.
 455          */
 456         ret = intel_panel_compute_config(connector, adjusted_mode);
 457         if (ret)
 458                 return ret;
 459
 460         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 461                 return -EINVAL;
 462
 463         ret = intel_panel_fitting(crtc_state, conn_state);
 464         if (ret)
 465                 return ret;
 466
 467         /*
 468          * XXX: It would be nice to support lower refresh rates on the
 469          * panels to reduce power consumption, and perhaps match the
 470          * user's requested refresh rate.
 471          */
 472
 473         return 0;
 474 }
 475
 476 /*
 477  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 478  */
 479 static int intel_lvds_get_modes(struct drm_connector *_connector)
 480 {
 481         struct intel_connector *connector = to_intel_connector(_connector);
 482         const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
 483
 484         /* Use panel fixed edid if we have one */
 485         if (!IS_ERR_OR_NULL(fixed_edid)) {
 486                 drm_edid_connector_update(&connector->base, fixed_edid);
 487
 488                 return drm_edid_connector_add_modes(&connector->base);
 489         }
 490
 491         return intel_panel_get_modes(connector);
 492 }
 493
 494 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 495         .get_modes = intel_lvds_get_modes,
 496         .mode_valid = intel_lvds_mode_valid,
 497         .atomic_check = intel_digital_connector_atomic_check,
 498 };
 499
 500 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 501         .detect = intel_panel_detect,
 502         .fill_modes = drm_helper_probe_single_connector_modes,
 503         .atomic_get_property = intel_digital_connector_atomic_get_property,
 504         .atomic_set_property = intel_digital_connector_atomic_set_property,
 505         .late_register = intel_connector_register,
 506         .early_unregister = intel_connector_unregister,
 507         .destroy = intel_connector_destroy,
 508         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 509         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 510 };
 511
 512 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 513         .destroy = intel_encoder_destroy,
 514 };
 515
 516 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 517 {
 518         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 519         return 1;
 520 }
 521
 522 /* These systems claim to have LVDS, but really don't */
 523 static const struct dmi_system_id intel_no_lvds[] = {
 524         {
 525                 .callback = intel_no_lvds_dmi_callback,
 526                 .ident = "Apple Mac Mini (Core series)",
 527                 .matches = {
 528                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 529                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 530                 },
 531         },
 532         {
 533                 .callback = intel_no_lvds_dmi_callback,
 534                 .ident = "Apple Mac Mini (Core 2 series)",
 535                 .matches = {
 536                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 537                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 538                 },
 539         },
 540         {
 541                 .callback = intel_no_lvds_dmi_callback,
 542                 .ident = "MSI IM-945GSE-A",
 543                 .matches = {
 544                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 545                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 546                 },
 547         },
 548         {
 549                 .callback = intel_no_lvds_dmi_callback,
 550                 .ident = "Dell Studio Hybrid",
 551                 .matches = {
 552                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 553                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 554                 },
 555         },
 556         {
 557                 .callback = intel_no_lvds_dmi_callback,
 558                 .ident = "Dell OptiPlex FX170",
 559                 .matches = {
 560                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 561                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 562                 },
 563         },
 564         {
 565                 .callback = intel_no_lvds_dmi_callback,
 566                 .ident = "AOpen Mini PC",
 567                 .matches = {
 568                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 569                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 570                 },
 571         },
 572         {
 573                 .callback = intel_no_lvds_dmi_callback,
 574                 .ident = "AOpen Mini PC MP915",
 575                 .matches = {
 576                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 577                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 578                 },
 579         },
 580         {
 581                 .callback = intel_no_lvds_dmi_callback,
 582                 .ident = "AOpen i915GMm-HFS",
 583                 .matches = {
 584                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 585                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 586                 },
 587         },
 588         {
 589                 .callback = intel_no_lvds_dmi_callback,
 590                 .ident = "AOpen i45GMx-I",
 591                 .matches = {
 592                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 593                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 594                 },
 595         },
 596         {
 597                 .callback = intel_no_lvds_dmi_callback,
 598                 .ident = "Aopen i945GTt-VFA",
 599                 .matches = {
 600                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 601                 },
 602         },
 603         {
 604                 .callback = intel_no_lvds_dmi_callback,
 605                 .ident = "Clientron U800",
 606                 .matches = {
 607                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 608                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 609                 },
 610         },
 611         {
 612                 .callback = intel_no_lvds_dmi_callback,
 613                 .ident = "Clientron E830",
 614                 .matches = {
 615                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 616                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 617                 },
 618         },
 619         {
 620                 .callback = intel_no_lvds_dmi_callback,
 621                 .ident = "Asus EeeBox PC EB1007",
 622                 .matches = {
 623                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 624                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 625                 },
 626         },
 627         {
 628                 .callback = intel_no_lvds_dmi_callback,
 629                 .ident = "Asus AT5NM10T-I",
 630                 .matches = {
 631                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 632                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 633                 },
 634         },
 635         {
 636                 .callback = intel_no_lvds_dmi_callback,
 637                 .ident = "Hewlett-Packard HP t5740",
 638                 .matches = {
 639                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 640                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 641                 },
 642         },
 643         {
 644                 .callback = intel_no_lvds_dmi_callback,
 645                 .ident = "Hewlett-Packard t5745",
 646                 .matches = {
 647                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 648                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 649                 },
 650         },
 651         {
 652                 .callback = intel_no_lvds_dmi_callback,
 653                 .ident = "Hewlett-Packard st5747",
 654                 .matches = {
 655                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 656                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 657                 },
 658         },
 659         {
 660                 .callback = intel_no_lvds_dmi_callback,
 661                 .ident = "MSI Wind Box DC500",
 662                 .matches = {
 663                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 664                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 665                 },
 666         },
 667         {
 668                 .callback = intel_no_lvds_dmi_callback,
 669                 .ident = "Gigabyte GA-D525TUD",
 670                 .matches = {
 671                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 672                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 673                 },
 674         },
 675         {
 676                 .callback = intel_no_lvds_dmi_callback,
 677                 .ident = "Supermicro X7SPA-H",
 678                 .matches = {
 679                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 680                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 681                 },
 682         },
 683         {
 684                 .callback = intel_no_lvds_dmi_callback,
 685                 .ident = "Fujitsu Esprimo Q900",
 686                 .matches = {
 687                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 688                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 689                 },
 690         },
 691         {
 692                 .callback = intel_no_lvds_dmi_callback,
 693                 .ident = "Intel D410PT",
 694                 .matches = {
 695                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 696                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 697                 },
 698         },
 699         {
 700                 .callback = intel_no_lvds_dmi_callback,
 701                 .ident = "Intel D425KT",
 702                 .matches = {
 703                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 704                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 705                 },
 706         },
 707         {
 708                 .callback = intel_no_lvds_dmi_callback,
 709                 .ident = "Intel D510MO",
 710                 .matches = {
 711                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 712                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 713                 },
 714         },
 715         {
 716                 .callback = intel_no_lvds_dmi_callback,
 717                 .ident = "Intel D525MW",
 718                 .matches = {
 719                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 720                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 721                 },
 722         },
 723         {
 724                 .callback = intel_no_lvds_dmi_callback,
 725                 .ident = "Radiant P845",
 726                 .matches = {
 727                         DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
 728                         DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
 729                 },
 730         },
 731
 732         { }     /* terminating entry */
 733 };
 734
 735 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 736 {
 737         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 738         return 1;
 739 }
 740
 741 static const struct dmi_system_id intel_dual_link_lvds[] = {
 742         {
 743                 .callback = intel_dual_link_lvds_callback,
 744                 .ident = "Apple MacBook Pro 15\" (2010)",
 745                 .matches = {
 746                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 747                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 748                 },
 749         },
 750         {
 751                 .callback = intel_dual_link_lvds_callback,
 752                 .ident = "Apple MacBook Pro 15\" (2011)",
 753                 .matches = {
 754                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 755                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 756                 },
 757         },
 758         {
 759                 .callback = intel_dual_link_lvds_callback,
 760                 .ident = "Apple MacBook Pro 15\" (2012)",
 761                 .matches = {
 762                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 763                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 764                 },
 765         },
 766         { }     /* terminating entry */
 767 };
 768
 769 struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *i915)
 770 {
 771         struct intel_encoder *encoder;
 772
 773         for_each_intel_encoder(&i915->drm, encoder) {
 774                 if (encoder->type == INTEL_OUTPUT_LVDS)
 775                         return encoder;
 776         }
 777
 778         return NULL;
 779 }
 780
 781 bool intel_is_dual_link_lvds(struct drm_i915_private *i915)
 782 {
 783         struct intel_encoder *encoder = intel_get_lvds_encoder(i915);
 784
 785         return encoder && to_lvds_encoder(encoder)->is_dual_link;
 786 }
 787
 788 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 789 {
 790         struct drm_i915_private *i915 = to_i915(lvds_encoder->base.base.dev);
 791         struct intel_connector *connector = lvds_encoder->attached_connector;
 792         const struct drm_display_mode *fixed_mode =
 793                 intel_panel_preferred_fixed_mode(connector);
 794         unsigned int val;
 795
 796         /* use the module option value if specified */
 797         if (i915->params.lvds_channel_mode > 0)
 798                 return i915->params.lvds_channel_mode == 2;
 799
 800         /* single channel LVDS is limited to 112 MHz */
 801         if (fixed_mode->clock > 112999)
 802                 return true;
 803
 804         if (dmi_check_system(intel_dual_link_lvds))
 805                 return true;
 806
 807         /*
 808          * BIOS should set the proper LVDS register value at boot, but
 809          * in reality, it doesn't set the value when the lid is closed;
 810          * we need to check "the value to be set" in VBT when LVDS
 811          * register is uninitialized.
 812          */
 813         val = intel_de_read(i915, lvds_encoder->reg);
 814         if (HAS_PCH_CPT(i915))
 815                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
 816         else
 817                 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
 818         if (val == 0)
 819                 val = connector->panel.vbt.bios_lvds_val;
 820
 821         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 822 }
 823
 824 static void intel_lvds_add_properties(struct drm_connector *connector)
 825 {
 826         intel_attach_scaling_mode_property(connector);
 827 }
 828
 829 /**
 830  * intel_lvds_init - setup LVDS connectors on this device
 831  * @i915: i915 device
 832  *
 833  * Create the connector, register the LVDS DDC bus, and try to figure out what
 834  * modes we can display on the LVDS panel (if present).
 835  */
 836 void intel_lvds_init(struct drm_i915_private *i915)
 837 {
 838         struct intel_lvds_encoder *lvds_encoder;
 839         struct intel_connector *connector;
 840         const struct drm_edid *drm_edid;
 841         struct intel_encoder *encoder;
 842         i915_reg_t lvds_reg;
 843         u32 lvds;
 844         u8 ddc_pin;
 845
 846         /* Skip init on machines we know falsely report LVDS */
 847         if (dmi_check_system(intel_no_lvds)) {
 848                 drm_WARN(&i915->drm, !i915->display.vbt.int_lvds_support,
 849                          "Useless DMI match. Internal LVDS support disabled by VBT\n");
 850                 return;
 851         }
 852
 853         if (!i915->display.vbt.int_lvds_support) {
 854                 drm_dbg_kms(&i915->drm,
 855                             "Internal LVDS support disabled by VBT\n");
 856                 return;
 857         }
 858
 859         if (HAS_PCH_SPLIT(i915))
 860                 lvds_reg = PCH_LVDS;
 861         else
 862                 lvds_reg = LVDS;
 863
 864         lvds = intel_de_read(i915, lvds_reg);
 865
 866         if (HAS_PCH_SPLIT(i915)) {
 867                 if ((lvds & LVDS_DETECTED) == 0)
 868                         return;
 869         }
 870
 871         ddc_pin = GMBUS_PIN_PANEL;
 872         if (!intel_bios_is_lvds_present(i915, &ddc_pin)) {
 873                 if ((lvds & LVDS_PORT_EN) == 0) {
 874                         drm_dbg_kms(&i915->drm,
 875                                     "LVDS is not present in VBT\n");
 876                         return;
 877                 }
 878                 drm_dbg_kms(&i915->drm,
 879                             "LVDS is not present in VBT, but enabled anyway\n");
 880         }
 881
 882         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
 883         if (!lvds_encoder)
 884                 return;
 885
 886         connector = intel_connector_alloc();
 887         if (!connector) {
 888                 kfree(lvds_encoder);
 889                 return;
 890         }
 891
 892         lvds_encoder->attached_connector = connector;
 893         encoder = &lvds_encoder->base;
 894
 895         drm_connector_init_with_ddc(&i915->drm, &connector->base,
 896                                     &intel_lvds_connector_funcs,
 897                                     DRM_MODE_CONNECTOR_LVDS,
 898                                     intel_gmbus_get_adapter(i915, ddc_pin));
 899
 900         drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs,
 901                          DRM_MODE_ENCODER_LVDS, "LVDS");
 902
 903         encoder->enable = intel_enable_lvds;
 904         encoder->pre_enable = intel_pre_enable_lvds;
 905         encoder->compute_config = intel_lvds_compute_config;
 906         if (HAS_PCH_SPLIT(i915)) {
 907                 encoder->disable = pch_disable_lvds;
 908                 encoder->post_disable = pch_post_disable_lvds;
 909         } else {
 910                 encoder->disable = gmch_disable_lvds;
 911         }
 912         encoder->get_hw_state = intel_lvds_get_hw_state;
 913         encoder->get_config = intel_lvds_get_config;
 914         encoder->update_pipe = intel_backlight_update;
 915         encoder->shutdown = intel_lvds_shutdown;
 916         connector->get_hw_state = intel_connector_get_hw_state;
 917
 918         intel_connector_attach_encoder(connector, encoder);
 919
 920         encoder->type = INTEL_OUTPUT_LVDS;
 921         encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
 922         encoder->port = PORT_NONE;
 923         encoder->cloneable = 0;
 924         if (DISPLAY_VER(i915) < 4)
 925                 encoder->pipe_mask = BIT(PIPE_B);
 926         else
 927                 encoder->pipe_mask = ~0;
 928
 929         drm_connector_helper_add(&connector->base, &intel_lvds_connector_helper_funcs);
 930         connector->base.display_info.subpixel_order = SubPixelHorizontalRGB;
 931
 932         lvds_encoder->reg = lvds_reg;
 933
 934         intel_lvds_add_properties(&connector->base);
 935
 936         intel_lvds_pps_get_hw_state(i915, &lvds_encoder->init_pps);
 937         lvds_encoder->init_lvds_val = lvds;
 938
 939         /*
 940          * LVDS discovery:
 941          * 1) check for EDID on DDC
 942          * 2) check for VBT data
 943          * 3) check to see if LVDS is already on
 944          *    if none of the above, no panel
 945          */
 946
 947         /*
 948          * Attempt to get the fixed panel mode from DDC.  Assume that the
 949          * preferred mode is the right one.
 950          */
 951         mutex_lock(&i915->drm.mode_config.mutex);
 952         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
 953                 drm_edid = drm_edid_read_switcheroo(&connector->base, connector->base.ddc);
 954         else
 955                 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);
 956         if (drm_edid) {
 957                 if (drm_edid_connector_update(&connector->base, drm_edid) ||
 958                     !drm_edid_connector_add_modes(&connector->base)) {
 959                         drm_edid_connector_update(&connector->base, NULL);
 960                         drm_edid_free(drm_edid);
 961                         drm_edid = ERR_PTR(-EINVAL);
 962                 }
 963         } else {
 964                 drm_edid = ERR_PTR(-ENOENT);
 965         }
 966         intel_bios_init_panel_late(i915, &connector->panel, NULL,
 967                                    IS_ERR(drm_edid) ? NULL : drm_edid);
 968
 969         /* Try EDID first */
 970         intel_panel_add_edid_fixed_modes(connector, true);
 971
 972         /* Failed to get EDID, what about VBT? */
 973         if (!intel_panel_preferred_fixed_mode(connector))
 974                 intel_panel_add_vbt_lfp_fixed_mode(connector);
 975
 976         /*
 977          * If we didn't get a fixed mode from EDID or VBT, try checking
 978          * if the panel is already turned on.  If so, assume that
 979          * whatever is currently programmed is the correct mode.
 980          */
 981         if (!intel_panel_preferred_fixed_mode(connector))
 982                 intel_panel_add_encoder_fixed_mode(connector, encoder);
 983
 984         mutex_unlock(&i915->drm.mode_config.mutex);
 985
 986         /* If we still don't have a mode after all that, give up. */
 987         if (!intel_panel_preferred_fixed_mode(connector))
 988                 goto failed;
 989
 990         intel_panel_init(connector, drm_edid);
 991
 992         intel_backlight_setup(connector, INVALID_PIPE);
 993
 994         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
 995         drm_dbg_kms(&i915->drm, "detected %s-link lvds configuration\n",
 996                     lvds_encoder->is_dual_link ? "dual" : "single");
 997
 998         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
 999
1000         return;
1001
1002 failed:
1003         drm_dbg_kms(&i915->drm, "No LVDS modes found, disabling.\n");
1004         drm_connector_cleanup(&connector->base);
1005         drm_encoder_cleanup(&encoder->base);
1006         kfree(lvds_encoder);
1007         intel_connector_free(connector);
1008         return;
1009 }