2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
26 #include "amdgpu_ih.h"
27 #include "amdgpu_gfx.h"
31 #include "amdgpu_ucode.h"
32 #include "clearstate_ci.h"
34 #include "dce/dce_8_0_d.h"
35 #include "dce/dce_8_0_sh_mask.h"
37 #include "bif/bif_4_1_d.h"
38 #include "bif/bif_4_1_sh_mask.h"
40 #include "gca/gfx_7_0_d.h"
41 #include "gca/gfx_7_2_enum.h"
42 #include "gca/gfx_7_2_sh_mask.h"
44 #include "gmc/gmc_7_0_d.h"
45 #include "gmc/gmc_7_0_sh_mask.h"
47 #include "oss/oss_2_0_d.h"
48 #include "oss/oss_2_0_sh_mask.h"
50 #define GFX7_NUM_GFX_RINGS 1
51 #define GFX7_NUM_COMPUTE_RINGS 8
53 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
54 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
57 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
58 MODULE_FIRMWARE("radeon/bonaire_me.bin");
59 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
60 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
61 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
63 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
64 MODULE_FIRMWARE("radeon/hawaii_me.bin");
65 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
66 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
67 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
69 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
70 MODULE_FIRMWARE("radeon/kaveri_me.bin");
71 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
72 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
73 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
74 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
76 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
77 MODULE_FIRMWARE("radeon/kabini_me.bin");
78 MODULE_FIRMWARE("radeon/kabini_ce.bin");
79 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
80 MODULE_FIRMWARE("radeon/kabini_mec.bin");
82 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
83 MODULE_FIRMWARE("radeon/mullins_me.bin");
84 MODULE_FIRMWARE("radeon/mullins_ce.bin");
85 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
86 MODULE_FIRMWARE("radeon/mullins_mec.bin");
88 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
90 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
91 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
92 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
93 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
94 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
95 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
96 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
97 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
98 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
99 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
100 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
101 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
102 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
103 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
104 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
105 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
108 static const u32 spectre_rlc_save_restore_register_list[] =
110 (0x0e00 << 16) | (0xc12c >> 2),
112 (0x0e00 << 16) | (0xc140 >> 2),
114 (0x0e00 << 16) | (0xc150 >> 2),
116 (0x0e00 << 16) | (0xc15c >> 2),
118 (0x0e00 << 16) | (0xc168 >> 2),
120 (0x0e00 << 16) | (0xc170 >> 2),
122 (0x0e00 << 16) | (0xc178 >> 2),
124 (0x0e00 << 16) | (0xc204 >> 2),
126 (0x0e00 << 16) | (0xc2b4 >> 2),
128 (0x0e00 << 16) | (0xc2b8 >> 2),
130 (0x0e00 << 16) | (0xc2bc >> 2),
132 (0x0e00 << 16) | (0xc2c0 >> 2),
134 (0x0e00 << 16) | (0x8228 >> 2),
136 (0x0e00 << 16) | (0x829c >> 2),
138 (0x0e00 << 16) | (0x869c >> 2),
140 (0x0600 << 16) | (0x98f4 >> 2),
142 (0x0e00 << 16) | (0x98f8 >> 2),
144 (0x0e00 << 16) | (0x9900 >> 2),
146 (0x0e00 << 16) | (0xc260 >> 2),
148 (0x0e00 << 16) | (0x90e8 >> 2),
150 (0x0e00 << 16) | (0x3c000 >> 2),
152 (0x0e00 << 16) | (0x3c00c >> 2),
154 (0x0e00 << 16) | (0x8c1c >> 2),
156 (0x0e00 << 16) | (0x9700 >> 2),
158 (0x0e00 << 16) | (0xcd20 >> 2),
160 (0x4e00 << 16) | (0xcd20 >> 2),
162 (0x5e00 << 16) | (0xcd20 >> 2),
164 (0x6e00 << 16) | (0xcd20 >> 2),
166 (0x7e00 << 16) | (0xcd20 >> 2),
168 (0x8e00 << 16) | (0xcd20 >> 2),
170 (0x9e00 << 16) | (0xcd20 >> 2),
172 (0xae00 << 16) | (0xcd20 >> 2),
174 (0xbe00 << 16) | (0xcd20 >> 2),
176 (0x0e00 << 16) | (0x89bc >> 2),
178 (0x0e00 << 16) | (0x8900 >> 2),
181 (0x0e00 << 16) | (0xc130 >> 2),
183 (0x0e00 << 16) | (0xc134 >> 2),
185 (0x0e00 << 16) | (0xc1fc >> 2),
187 (0x0e00 << 16) | (0xc208 >> 2),
189 (0x0e00 << 16) | (0xc264 >> 2),
191 (0x0e00 << 16) | (0xc268 >> 2),
193 (0x0e00 << 16) | (0xc26c >> 2),
195 (0x0e00 << 16) | (0xc270 >> 2),
197 (0x0e00 << 16) | (0xc274 >> 2),
199 (0x0e00 << 16) | (0xc278 >> 2),
201 (0x0e00 << 16) | (0xc27c >> 2),
203 (0x0e00 << 16) | (0xc280 >> 2),
205 (0x0e00 << 16) | (0xc284 >> 2),
207 (0x0e00 << 16) | (0xc288 >> 2),
209 (0x0e00 << 16) | (0xc28c >> 2),
211 (0x0e00 << 16) | (0xc290 >> 2),
213 (0x0e00 << 16) | (0xc294 >> 2),
215 (0x0e00 << 16) | (0xc298 >> 2),
217 (0x0e00 << 16) | (0xc29c >> 2),
219 (0x0e00 << 16) | (0xc2a0 >> 2),
221 (0x0e00 << 16) | (0xc2a4 >> 2),
223 (0x0e00 << 16) | (0xc2a8 >> 2),
225 (0x0e00 << 16) | (0xc2ac >> 2),
227 (0x0e00 << 16) | (0xc2b0 >> 2),
229 (0x0e00 << 16) | (0x301d0 >> 2),
231 (0x0e00 << 16) | (0x30238 >> 2),
233 (0x0e00 << 16) | (0x30250 >> 2),
235 (0x0e00 << 16) | (0x30254 >> 2),
237 (0x0e00 << 16) | (0x30258 >> 2),
239 (0x0e00 << 16) | (0x3025c >> 2),
241 (0x4e00 << 16) | (0xc900 >> 2),
243 (0x5e00 << 16) | (0xc900 >> 2),
245 (0x6e00 << 16) | (0xc900 >> 2),
247 (0x7e00 << 16) | (0xc900 >> 2),
249 (0x8e00 << 16) | (0xc900 >> 2),
251 (0x9e00 << 16) | (0xc900 >> 2),
253 (0xae00 << 16) | (0xc900 >> 2),
255 (0xbe00 << 16) | (0xc900 >> 2),
257 (0x4e00 << 16) | (0xc904 >> 2),
259 (0x5e00 << 16) | (0xc904 >> 2),
261 (0x6e00 << 16) | (0xc904 >> 2),
263 (0x7e00 << 16) | (0xc904 >> 2),
265 (0x8e00 << 16) | (0xc904 >> 2),
267 (0x9e00 << 16) | (0xc904 >> 2),
269 (0xae00 << 16) | (0xc904 >> 2),
271 (0xbe00 << 16) | (0xc904 >> 2),
273 (0x4e00 << 16) | (0xc908 >> 2),
275 (0x5e00 << 16) | (0xc908 >> 2),
277 (0x6e00 << 16) | (0xc908 >> 2),
279 (0x7e00 << 16) | (0xc908 >> 2),
281 (0x8e00 << 16) | (0xc908 >> 2),
283 (0x9e00 << 16) | (0xc908 >> 2),
285 (0xae00 << 16) | (0xc908 >> 2),
287 (0xbe00 << 16) | (0xc908 >> 2),
289 (0x4e00 << 16) | (0xc90c >> 2),
291 (0x5e00 << 16) | (0xc90c >> 2),
293 (0x6e00 << 16) | (0xc90c >> 2),
295 (0x7e00 << 16) | (0xc90c >> 2),
297 (0x8e00 << 16) | (0xc90c >> 2),
299 (0x9e00 << 16) | (0xc90c >> 2),
301 (0xae00 << 16) | (0xc90c >> 2),
303 (0xbe00 << 16) | (0xc90c >> 2),
305 (0x4e00 << 16) | (0xc910 >> 2),
307 (0x5e00 << 16) | (0xc910 >> 2),
309 (0x6e00 << 16) | (0xc910 >> 2),
311 (0x7e00 << 16) | (0xc910 >> 2),
313 (0x8e00 << 16) | (0xc910 >> 2),
315 (0x9e00 << 16) | (0xc910 >> 2),
317 (0xae00 << 16) | (0xc910 >> 2),
319 (0xbe00 << 16) | (0xc910 >> 2),
321 (0x0e00 << 16) | (0xc99c >> 2),
323 (0x0e00 << 16) | (0x9834 >> 2),
325 (0x0000 << 16) | (0x30f00 >> 2),
327 (0x0001 << 16) | (0x30f00 >> 2),
329 (0x0000 << 16) | (0x30f04 >> 2),
331 (0x0001 << 16) | (0x30f04 >> 2),
333 (0x0000 << 16) | (0x30f08 >> 2),
335 (0x0001 << 16) | (0x30f08 >> 2),
337 (0x0000 << 16) | (0x30f0c >> 2),
339 (0x0001 << 16) | (0x30f0c >> 2),
341 (0x0600 << 16) | (0x9b7c >> 2),
343 (0x0e00 << 16) | (0x8a14 >> 2),
345 (0x0e00 << 16) | (0x8a18 >> 2),
347 (0x0600 << 16) | (0x30a00 >> 2),
349 (0x0e00 << 16) | (0x8bf0 >> 2),
351 (0x0e00 << 16) | (0x8bcc >> 2),
353 (0x0e00 << 16) | (0x8b24 >> 2),
355 (0x0e00 << 16) | (0x30a04 >> 2),
357 (0x0600 << 16) | (0x30a10 >> 2),
359 (0x0600 << 16) | (0x30a14 >> 2),
361 (0x0600 << 16) | (0x30a18 >> 2),
363 (0x0600 << 16) | (0x30a2c >> 2),
365 (0x0e00 << 16) | (0xc700 >> 2),
367 (0x0e00 << 16) | (0xc704 >> 2),
369 (0x0e00 << 16) | (0xc708 >> 2),
371 (0x0e00 << 16) | (0xc768 >> 2),
373 (0x0400 << 16) | (0xc770 >> 2),
375 (0x0400 << 16) | (0xc774 >> 2),
377 (0x0400 << 16) | (0xc778 >> 2),
379 (0x0400 << 16) | (0xc77c >> 2),
381 (0x0400 << 16) | (0xc780 >> 2),
383 (0x0400 << 16) | (0xc784 >> 2),
385 (0x0400 << 16) | (0xc788 >> 2),
387 (0x0400 << 16) | (0xc78c >> 2),
389 (0x0400 << 16) | (0xc798 >> 2),
391 (0x0400 << 16) | (0xc79c >> 2),
393 (0x0400 << 16) | (0xc7a0 >> 2),
395 (0x0400 << 16) | (0xc7a4 >> 2),
397 (0x0400 << 16) | (0xc7a8 >> 2),
399 (0x0400 << 16) | (0xc7ac >> 2),
401 (0x0400 << 16) | (0xc7b0 >> 2),
403 (0x0400 << 16) | (0xc7b4 >> 2),
405 (0x0e00 << 16) | (0x9100 >> 2),
407 (0x0e00 << 16) | (0x3c010 >> 2),
409 (0x0e00 << 16) | (0x92a8 >> 2),
411 (0x0e00 << 16) | (0x92ac >> 2),
413 (0x0e00 << 16) | (0x92b4 >> 2),
415 (0x0e00 << 16) | (0x92b8 >> 2),
417 (0x0e00 << 16) | (0x92bc >> 2),
419 (0x0e00 << 16) | (0x92c0 >> 2),
421 (0x0e00 << 16) | (0x92c4 >> 2),
423 (0x0e00 << 16) | (0x92c8 >> 2),
425 (0x0e00 << 16) | (0x92cc >> 2),
427 (0x0e00 << 16) | (0x92d0 >> 2),
429 (0x0e00 << 16) | (0x8c00 >> 2),
431 (0x0e00 << 16) | (0x8c04 >> 2),
433 (0x0e00 << 16) | (0x8c20 >> 2),
435 (0x0e00 << 16) | (0x8c38 >> 2),
437 (0x0e00 << 16) | (0x8c3c >> 2),
439 (0x0e00 << 16) | (0xae00 >> 2),
441 (0x0e00 << 16) | (0x9604 >> 2),
443 (0x0e00 << 16) | (0xac08 >> 2),
445 (0x0e00 << 16) | (0xac0c >> 2),
447 (0x0e00 << 16) | (0xac10 >> 2),
449 (0x0e00 << 16) | (0xac14 >> 2),
451 (0x0e00 << 16) | (0xac58 >> 2),
453 (0x0e00 << 16) | (0xac68 >> 2),
455 (0x0e00 << 16) | (0xac6c >> 2),
457 (0x0e00 << 16) | (0xac70 >> 2),
459 (0x0e00 << 16) | (0xac74 >> 2),
461 (0x0e00 << 16) | (0xac78 >> 2),
463 (0x0e00 << 16) | (0xac7c >> 2),
465 (0x0e00 << 16) | (0xac80 >> 2),
467 (0x0e00 << 16) | (0xac84 >> 2),
469 (0x0e00 << 16) | (0xac88 >> 2),
471 (0x0e00 << 16) | (0xac8c >> 2),
473 (0x0e00 << 16) | (0x970c >> 2),
475 (0x0e00 << 16) | (0x9714 >> 2),
477 (0x0e00 << 16) | (0x9718 >> 2),
479 (0x0e00 << 16) | (0x971c >> 2),
481 (0x0e00 << 16) | (0x31068 >> 2),
483 (0x4e00 << 16) | (0x31068 >> 2),
485 (0x5e00 << 16) | (0x31068 >> 2),
487 (0x6e00 << 16) | (0x31068 >> 2),
489 (0x7e00 << 16) | (0x31068 >> 2),
491 (0x8e00 << 16) | (0x31068 >> 2),
493 (0x9e00 << 16) | (0x31068 >> 2),
495 (0xae00 << 16) | (0x31068 >> 2),
497 (0xbe00 << 16) | (0x31068 >> 2),
499 (0x0e00 << 16) | (0xcd10 >> 2),
501 (0x0e00 << 16) | (0xcd14 >> 2),
503 (0x0e00 << 16) | (0x88b0 >> 2),
505 (0x0e00 << 16) | (0x88b4 >> 2),
507 (0x0e00 << 16) | (0x88b8 >> 2),
509 (0x0e00 << 16) | (0x88bc >> 2),
511 (0x0400 << 16) | (0x89c0 >> 2),
513 (0x0e00 << 16) | (0x88c4 >> 2),
515 (0x0e00 << 16) | (0x88c8 >> 2),
517 (0x0e00 << 16) | (0x88d0 >> 2),
519 (0x0e00 << 16) | (0x88d4 >> 2),
521 (0x0e00 << 16) | (0x88d8 >> 2),
523 (0x0e00 << 16) | (0x8980 >> 2),
525 (0x0e00 << 16) | (0x30938 >> 2),
527 (0x0e00 << 16) | (0x3093c >> 2),
529 (0x0e00 << 16) | (0x30940 >> 2),
531 (0x0e00 << 16) | (0x89a0 >> 2),
533 (0x0e00 << 16) | (0x30900 >> 2),
535 (0x0e00 << 16) | (0x30904 >> 2),
537 (0x0e00 << 16) | (0x89b4 >> 2),
539 (0x0e00 << 16) | (0x3c210 >> 2),
541 (0x0e00 << 16) | (0x3c214 >> 2),
543 (0x0e00 << 16) | (0x3c218 >> 2),
545 (0x0e00 << 16) | (0x8904 >> 2),
548 (0x0e00 << 16) | (0x8c28 >> 2),
549 (0x0e00 << 16) | (0x8c2c >> 2),
550 (0x0e00 << 16) | (0x8c30 >> 2),
551 (0x0e00 << 16) | (0x8c34 >> 2),
552 (0x0e00 << 16) | (0x9600 >> 2),
555 static const u32 kalindi_rlc_save_restore_register_list[] =
557 (0x0e00 << 16) | (0xc12c >> 2),
559 (0x0e00 << 16) | (0xc140 >> 2),
561 (0x0e00 << 16) | (0xc150 >> 2),
563 (0x0e00 << 16) | (0xc15c >> 2),
565 (0x0e00 << 16) | (0xc168 >> 2),
567 (0x0e00 << 16) | (0xc170 >> 2),
569 (0x0e00 << 16) | (0xc204 >> 2),
571 (0x0e00 << 16) | (0xc2b4 >> 2),
573 (0x0e00 << 16) | (0xc2b8 >> 2),
575 (0x0e00 << 16) | (0xc2bc >> 2),
577 (0x0e00 << 16) | (0xc2c0 >> 2),
579 (0x0e00 << 16) | (0x8228 >> 2),
581 (0x0e00 << 16) | (0x829c >> 2),
583 (0x0e00 << 16) | (0x869c >> 2),
585 (0x0600 << 16) | (0x98f4 >> 2),
587 (0x0e00 << 16) | (0x98f8 >> 2),
589 (0x0e00 << 16) | (0x9900 >> 2),
591 (0x0e00 << 16) | (0xc260 >> 2),
593 (0x0e00 << 16) | (0x90e8 >> 2),
595 (0x0e00 << 16) | (0x3c000 >> 2),
597 (0x0e00 << 16) | (0x3c00c >> 2),
599 (0x0e00 << 16) | (0x8c1c >> 2),
601 (0x0e00 << 16) | (0x9700 >> 2),
603 (0x0e00 << 16) | (0xcd20 >> 2),
605 (0x4e00 << 16) | (0xcd20 >> 2),
607 (0x5e00 << 16) | (0xcd20 >> 2),
609 (0x6e00 << 16) | (0xcd20 >> 2),
611 (0x7e00 << 16) | (0xcd20 >> 2),
613 (0x0e00 << 16) | (0x89bc >> 2),
615 (0x0e00 << 16) | (0x8900 >> 2),
618 (0x0e00 << 16) | (0xc130 >> 2),
620 (0x0e00 << 16) | (0xc134 >> 2),
622 (0x0e00 << 16) | (0xc1fc >> 2),
624 (0x0e00 << 16) | (0xc208 >> 2),
626 (0x0e00 << 16) | (0xc264 >> 2),
628 (0x0e00 << 16) | (0xc268 >> 2),
630 (0x0e00 << 16) | (0xc26c >> 2),
632 (0x0e00 << 16) | (0xc270 >> 2),
634 (0x0e00 << 16) | (0xc274 >> 2),
636 (0x0e00 << 16) | (0xc28c >> 2),
638 (0x0e00 << 16) | (0xc290 >> 2),
640 (0x0e00 << 16) | (0xc294 >> 2),
642 (0x0e00 << 16) | (0xc298 >> 2),
644 (0x0e00 << 16) | (0xc2a0 >> 2),
646 (0x0e00 << 16) | (0xc2a4 >> 2),
648 (0x0e00 << 16) | (0xc2a8 >> 2),
650 (0x0e00 << 16) | (0xc2ac >> 2),
652 (0x0e00 << 16) | (0x301d0 >> 2),
654 (0x0e00 << 16) | (0x30238 >> 2),
656 (0x0e00 << 16) | (0x30250 >> 2),
658 (0x0e00 << 16) | (0x30254 >> 2),
660 (0x0e00 << 16) | (0x30258 >> 2),
662 (0x0e00 << 16) | (0x3025c >> 2),
664 (0x4e00 << 16) | (0xc900 >> 2),
666 (0x5e00 << 16) | (0xc900 >> 2),
668 (0x6e00 << 16) | (0xc900 >> 2),
670 (0x7e00 << 16) | (0xc900 >> 2),
672 (0x4e00 << 16) | (0xc904 >> 2),
674 (0x5e00 << 16) | (0xc904 >> 2),
676 (0x6e00 << 16) | (0xc904 >> 2),
678 (0x7e00 << 16) | (0xc904 >> 2),
680 (0x4e00 << 16) | (0xc908 >> 2),
682 (0x5e00 << 16) | (0xc908 >> 2),
684 (0x6e00 << 16) | (0xc908 >> 2),
686 (0x7e00 << 16) | (0xc908 >> 2),
688 (0x4e00 << 16) | (0xc90c >> 2),
690 (0x5e00 << 16) | (0xc90c >> 2),
692 (0x6e00 << 16) | (0xc90c >> 2),
694 (0x7e00 << 16) | (0xc90c >> 2),
696 (0x4e00 << 16) | (0xc910 >> 2),
698 (0x5e00 << 16) | (0xc910 >> 2),
700 (0x6e00 << 16) | (0xc910 >> 2),
702 (0x7e00 << 16) | (0xc910 >> 2),
704 (0x0e00 << 16) | (0xc99c >> 2),
706 (0x0e00 << 16) | (0x9834 >> 2),
708 (0x0000 << 16) | (0x30f00 >> 2),
710 (0x0000 << 16) | (0x30f04 >> 2),
712 (0x0000 << 16) | (0x30f08 >> 2),
714 (0x0000 << 16) | (0x30f0c >> 2),
716 (0x0600 << 16) | (0x9b7c >> 2),
718 (0x0e00 << 16) | (0x8a14 >> 2),
720 (0x0e00 << 16) | (0x8a18 >> 2),
722 (0x0600 << 16) | (0x30a00 >> 2),
724 (0x0e00 << 16) | (0x8bf0 >> 2),
726 (0x0e00 << 16) | (0x8bcc >> 2),
728 (0x0e00 << 16) | (0x8b24 >> 2),
730 (0x0e00 << 16) | (0x30a04 >> 2),
732 (0x0600 << 16) | (0x30a10 >> 2),
734 (0x0600 << 16) | (0x30a14 >> 2),
736 (0x0600 << 16) | (0x30a18 >> 2),
738 (0x0600 << 16) | (0x30a2c >> 2),
740 (0x0e00 << 16) | (0xc700 >> 2),
742 (0x0e00 << 16) | (0xc704 >> 2),
744 (0x0e00 << 16) | (0xc708 >> 2),
746 (0x0e00 << 16) | (0xc768 >> 2),
748 (0x0400 << 16) | (0xc770 >> 2),
750 (0x0400 << 16) | (0xc774 >> 2),
752 (0x0400 << 16) | (0xc798 >> 2),
754 (0x0400 << 16) | (0xc79c >> 2),
756 (0x0e00 << 16) | (0x9100 >> 2),
758 (0x0e00 << 16) | (0x3c010 >> 2),
760 (0x0e00 << 16) | (0x8c00 >> 2),
762 (0x0e00 << 16) | (0x8c04 >> 2),
764 (0x0e00 << 16) | (0x8c20 >> 2),
766 (0x0e00 << 16) | (0x8c38 >> 2),
768 (0x0e00 << 16) | (0x8c3c >> 2),
770 (0x0e00 << 16) | (0xae00 >> 2),
772 (0x0e00 << 16) | (0x9604 >> 2),
774 (0x0e00 << 16) | (0xac08 >> 2),
776 (0x0e00 << 16) | (0xac0c >> 2),
778 (0x0e00 << 16) | (0xac10 >> 2),
780 (0x0e00 << 16) | (0xac14 >> 2),
782 (0x0e00 << 16) | (0xac58 >> 2),
784 (0x0e00 << 16) | (0xac68 >> 2),
786 (0x0e00 << 16) | (0xac6c >> 2),
788 (0x0e00 << 16) | (0xac70 >> 2),
790 (0x0e00 << 16) | (0xac74 >> 2),
792 (0x0e00 << 16) | (0xac78 >> 2),
794 (0x0e00 << 16) | (0xac7c >> 2),
796 (0x0e00 << 16) | (0xac80 >> 2),
798 (0x0e00 << 16) | (0xac84 >> 2),
800 (0x0e00 << 16) | (0xac88 >> 2),
802 (0x0e00 << 16) | (0xac8c >> 2),
804 (0x0e00 << 16) | (0x970c >> 2),
806 (0x0e00 << 16) | (0x9714 >> 2),
808 (0x0e00 << 16) | (0x9718 >> 2),
810 (0x0e00 << 16) | (0x971c >> 2),
812 (0x0e00 << 16) | (0x31068 >> 2),
814 (0x4e00 << 16) | (0x31068 >> 2),
816 (0x5e00 << 16) | (0x31068 >> 2),
818 (0x6e00 << 16) | (0x31068 >> 2),
820 (0x7e00 << 16) | (0x31068 >> 2),
822 (0x0e00 << 16) | (0xcd10 >> 2),
824 (0x0e00 << 16) | (0xcd14 >> 2),
826 (0x0e00 << 16) | (0x88b0 >> 2),
828 (0x0e00 << 16) | (0x88b4 >> 2),
830 (0x0e00 << 16) | (0x88b8 >> 2),
832 (0x0e00 << 16) | (0x88bc >> 2),
834 (0x0400 << 16) | (0x89c0 >> 2),
836 (0x0e00 << 16) | (0x88c4 >> 2),
838 (0x0e00 << 16) | (0x88c8 >> 2),
840 (0x0e00 << 16) | (0x88d0 >> 2),
842 (0x0e00 << 16) | (0x88d4 >> 2),
844 (0x0e00 << 16) | (0x88d8 >> 2),
846 (0x0e00 << 16) | (0x8980 >> 2),
848 (0x0e00 << 16) | (0x30938 >> 2),
850 (0x0e00 << 16) | (0x3093c >> 2),
852 (0x0e00 << 16) | (0x30940 >> 2),
854 (0x0e00 << 16) | (0x89a0 >> 2),
856 (0x0e00 << 16) | (0x30900 >> 2),
858 (0x0e00 << 16) | (0x30904 >> 2),
860 (0x0e00 << 16) | (0x89b4 >> 2),
862 (0x0e00 << 16) | (0x3e1fc >> 2),
864 (0x0e00 << 16) | (0x3c210 >> 2),
866 (0x0e00 << 16) | (0x3c214 >> 2),
868 (0x0e00 << 16) | (0x3c218 >> 2),
870 (0x0e00 << 16) | (0x8904 >> 2),
873 (0x0e00 << 16) | (0x8c28 >> 2),
874 (0x0e00 << 16) | (0x8c2c >> 2),
875 (0x0e00 << 16) | (0x8c30 >> 2),
876 (0x0e00 << 16) | (0x8c34 >> 2),
877 (0x0e00 << 16) | (0x9600 >> 2),
880 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
881 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
882 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
883 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
884 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
890 * gfx_v7_0_init_microcode - load ucode images from disk
892 * @adev: amdgpu_device pointer
894 * Use the firmware interface to load the ucode images into
895 * the driver (not loaded into hw).
896 * Returns 0 on success, error on failure.
898 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
900 const char *chip_name;
906 switch (adev->asic_type) {
908 chip_name = "bonaire";
911 chip_name = "hawaii";
914 chip_name = "kaveri";
917 chip_name = "kabini";
920 chip_name = "mullins";
925 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
926 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
929 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
933 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
934 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
937 err = amdgpu_ucode_validate(adev->gfx.me_fw);
941 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
942 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
945 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
949 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
950 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
953 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
957 if (adev->asic_type == CHIP_KAVERI) {
958 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
959 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
962 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
967 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
968 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
971 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
975 pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name);
976 release_firmware(adev->gfx.pfp_fw);
977 adev->gfx.pfp_fw = NULL;
978 release_firmware(adev->gfx.me_fw);
979 adev->gfx.me_fw = NULL;
980 release_firmware(adev->gfx.ce_fw);
981 adev->gfx.ce_fw = NULL;
982 release_firmware(adev->gfx.mec_fw);
983 adev->gfx.mec_fw = NULL;
984 release_firmware(adev->gfx.mec2_fw);
985 adev->gfx.mec2_fw = NULL;
986 release_firmware(adev->gfx.rlc_fw);
987 adev->gfx.rlc_fw = NULL;
992 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
994 release_firmware(adev->gfx.pfp_fw);
995 adev->gfx.pfp_fw = NULL;
996 release_firmware(adev->gfx.me_fw);
997 adev->gfx.me_fw = NULL;
998 release_firmware(adev->gfx.ce_fw);
999 adev->gfx.ce_fw = NULL;
1000 release_firmware(adev->gfx.mec_fw);
1001 adev->gfx.mec_fw = NULL;
1002 release_firmware(adev->gfx.mec2_fw);
1003 adev->gfx.mec2_fw = NULL;
1004 release_firmware(adev->gfx.rlc_fw);
1005 adev->gfx.rlc_fw = NULL;
1009 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1011 * @adev: amdgpu_device pointer
1013 * Starting with SI, the tiling setup is done globally in a
1014 * set of 32 tiling modes. Rather than selecting each set of
1015 * parameters per surface as on older asics, we just select
1016 * which index in the tiling table we want to use, and the
1017 * surface uses those parameters (CIK).
1019 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1021 const u32 num_tile_mode_states =
1022 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1023 const u32 num_secondary_tile_mode_states =
1024 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1025 u32 reg_offset, split_equal_to_row_size;
1026 uint32_t *tile, *macrotile;
1028 tile = adev->gfx.config.tile_mode_array;
1029 macrotile = adev->gfx.config.macrotile_mode_array;
1031 switch (adev->gfx.config.mem_row_size_in_kb) {
1033 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1037 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1040 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1044 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1045 tile[reg_offset] = 0;
1046 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1047 macrotile[reg_offset] = 0;
1049 switch (adev->asic_type) {
1051 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1052 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1053 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1054 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1055 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1056 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1057 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1058 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1059 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1060 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1062 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1063 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1064 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1065 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1066 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1067 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1068 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1069 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1070 TILE_SPLIT(split_equal_to_row_size));
1071 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1072 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1073 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1074 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1075 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1076 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1077 TILE_SPLIT(split_equal_to_row_size));
1078 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1079 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1080 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1081 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1082 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1083 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1084 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1085 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1086 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1087 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1088 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1089 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1090 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1091 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1092 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1093 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1094 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1095 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1096 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1097 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1098 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1099 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1100 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1101 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1102 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1103 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1104 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1105 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1106 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1107 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1108 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1109 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1110 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1111 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1112 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1113 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1114 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1115 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1116 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1117 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1118 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1119 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1120 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1121 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1122 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1123 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1124 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1125 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1126 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1127 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1128 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1129 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1130 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1131 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1132 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1133 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1134 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1135 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1136 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1137 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1138 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1139 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1140 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1141 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1142 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1143 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1144 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1145 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1146 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1147 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1148 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1149 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1150 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1151 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1152 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1154 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1157 NUM_BANKS(ADDR_SURF_16_BANK));
1158 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1159 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1160 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1161 NUM_BANKS(ADDR_SURF_16_BANK));
1162 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1163 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1164 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1165 NUM_BANKS(ADDR_SURF_16_BANK));
1166 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1167 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1168 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1169 NUM_BANKS(ADDR_SURF_16_BANK));
1170 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1171 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1172 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1173 NUM_BANKS(ADDR_SURF_16_BANK));
1174 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1175 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1176 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1177 NUM_BANKS(ADDR_SURF_8_BANK));
1178 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1179 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1180 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1181 NUM_BANKS(ADDR_SURF_4_BANK));
1182 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1183 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1184 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1185 NUM_BANKS(ADDR_SURF_16_BANK));
1186 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1187 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1188 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1189 NUM_BANKS(ADDR_SURF_16_BANK));
1190 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1193 NUM_BANKS(ADDR_SURF_16_BANK));
1194 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1195 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1196 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1197 NUM_BANKS(ADDR_SURF_16_BANK));
1198 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1199 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1200 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1201 NUM_BANKS(ADDR_SURF_16_BANK));
1202 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1203 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1204 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1205 NUM_BANKS(ADDR_SURF_8_BANK));
1206 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1207 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1208 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1209 NUM_BANKS(ADDR_SURF_4_BANK));
1211 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1212 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1213 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1214 if (reg_offset != 7)
1215 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1218 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1219 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1220 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1221 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1222 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1223 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1224 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1225 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1226 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1227 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1228 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1229 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1230 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1231 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1232 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1233 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1234 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1235 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1236 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1237 TILE_SPLIT(split_equal_to_row_size));
1238 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1239 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1240 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1241 TILE_SPLIT(split_equal_to_row_size));
1242 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1243 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1244 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1245 TILE_SPLIT(split_equal_to_row_size));
1246 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1247 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1248 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1249 TILE_SPLIT(split_equal_to_row_size));
1250 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1251 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1252 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1253 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1254 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1255 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1256 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1257 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1258 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1259 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1260 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1261 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1262 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1263 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1264 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1265 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1266 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1267 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1268 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1269 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1270 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1271 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1272 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1273 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1274 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1275 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1276 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1277 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1278 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1279 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1280 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1281 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1282 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1283 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1284 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1285 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1286 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1287 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1288 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1289 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1290 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1291 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1292 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1293 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1294 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1295 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1296 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1297 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1298 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1299 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1300 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1301 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1302 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1303 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1304 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1305 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1306 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1307 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1308 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1309 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1310 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1311 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1312 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1313 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1314 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1315 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1316 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1317 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1318 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1319 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1320 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1321 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1322 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1323 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1324 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1325 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1326 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1327 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1328 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1329 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1330 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1331 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1332 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1333 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1334 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1335 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1337 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1338 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1339 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1340 NUM_BANKS(ADDR_SURF_16_BANK));
1341 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1342 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1343 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1344 NUM_BANKS(ADDR_SURF_16_BANK));
1345 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1346 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1347 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1348 NUM_BANKS(ADDR_SURF_16_BANK));
1349 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1350 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1351 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1352 NUM_BANKS(ADDR_SURF_16_BANK));
1353 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1354 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1355 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1356 NUM_BANKS(ADDR_SURF_8_BANK));
1357 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1358 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1359 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1360 NUM_BANKS(ADDR_SURF_4_BANK));
1361 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1362 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1363 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1364 NUM_BANKS(ADDR_SURF_4_BANK));
1365 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1366 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1367 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1368 NUM_BANKS(ADDR_SURF_16_BANK));
1369 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1370 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1371 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1372 NUM_BANKS(ADDR_SURF_16_BANK));
1373 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1374 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1375 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1376 NUM_BANKS(ADDR_SURF_16_BANK));
1377 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1378 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1379 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1380 NUM_BANKS(ADDR_SURF_8_BANK));
1381 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1382 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1383 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1384 NUM_BANKS(ADDR_SURF_16_BANK));
1385 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1386 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1387 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1388 NUM_BANKS(ADDR_SURF_8_BANK));
1389 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1390 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1391 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1392 NUM_BANKS(ADDR_SURF_4_BANK));
1394 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1395 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1396 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1397 if (reg_offset != 7)
1398 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1404 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1405 PIPE_CONFIG(ADDR_SURF_P2) |
1406 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1407 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1408 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1409 PIPE_CONFIG(ADDR_SURF_P2) |
1410 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1411 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1412 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1413 PIPE_CONFIG(ADDR_SURF_P2) |
1414 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1415 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1416 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1417 PIPE_CONFIG(ADDR_SURF_P2) |
1418 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1419 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1420 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1421 PIPE_CONFIG(ADDR_SURF_P2) |
1422 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1423 TILE_SPLIT(split_equal_to_row_size));
1424 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1425 PIPE_CONFIG(ADDR_SURF_P2) |
1426 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1427 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1428 PIPE_CONFIG(ADDR_SURF_P2) |
1429 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1430 TILE_SPLIT(split_equal_to_row_size));
1431 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1432 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1433 PIPE_CONFIG(ADDR_SURF_P2));
1434 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1435 PIPE_CONFIG(ADDR_SURF_P2) |
1436 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1437 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1438 PIPE_CONFIG(ADDR_SURF_P2) |
1439 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1440 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1441 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1442 PIPE_CONFIG(ADDR_SURF_P2) |
1443 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1444 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1445 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1446 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1447 PIPE_CONFIG(ADDR_SURF_P2) |
1448 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1449 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1450 PIPE_CONFIG(ADDR_SURF_P2) |
1451 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1452 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1453 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1454 PIPE_CONFIG(ADDR_SURF_P2) |
1455 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1456 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1457 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1458 PIPE_CONFIG(ADDR_SURF_P2) |
1459 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1460 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1461 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1462 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1463 PIPE_CONFIG(ADDR_SURF_P2) |
1464 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1465 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1466 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1467 PIPE_CONFIG(ADDR_SURF_P2) |
1468 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1469 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1470 PIPE_CONFIG(ADDR_SURF_P2) |
1471 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1472 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1473 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1474 PIPE_CONFIG(ADDR_SURF_P2) |
1475 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1476 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1477 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1478 PIPE_CONFIG(ADDR_SURF_P2) |
1479 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1480 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1481 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1482 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1483 PIPE_CONFIG(ADDR_SURF_P2) |
1484 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1485 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1486 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1487 PIPE_CONFIG(ADDR_SURF_P2) |
1488 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1489 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1490 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1491 PIPE_CONFIG(ADDR_SURF_P2) |
1492 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1493 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1494 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1495 PIPE_CONFIG(ADDR_SURF_P2) |
1496 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1497 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1498 PIPE_CONFIG(ADDR_SURF_P2) |
1499 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1500 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1501 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1502 PIPE_CONFIG(ADDR_SURF_P2) |
1503 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1504 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1505 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1507 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1508 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1509 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1510 NUM_BANKS(ADDR_SURF_8_BANK));
1511 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1513 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1514 NUM_BANKS(ADDR_SURF_8_BANK));
1515 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1518 NUM_BANKS(ADDR_SURF_8_BANK));
1519 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1520 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1521 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1522 NUM_BANKS(ADDR_SURF_8_BANK));
1523 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1524 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1525 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1526 NUM_BANKS(ADDR_SURF_8_BANK));
1527 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1528 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1529 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1530 NUM_BANKS(ADDR_SURF_8_BANK));
1531 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1532 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1533 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1534 NUM_BANKS(ADDR_SURF_8_BANK));
1535 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1536 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1537 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1538 NUM_BANKS(ADDR_SURF_16_BANK));
1539 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1540 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1541 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1542 NUM_BANKS(ADDR_SURF_16_BANK));
1543 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1544 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1545 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1546 NUM_BANKS(ADDR_SURF_16_BANK));
1547 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1549 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1550 NUM_BANKS(ADDR_SURF_16_BANK));
1551 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1552 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1553 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1554 NUM_BANKS(ADDR_SURF_16_BANK));
1555 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1556 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1557 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1558 NUM_BANKS(ADDR_SURF_16_BANK));
1559 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1560 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1561 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1562 NUM_BANKS(ADDR_SURF_8_BANK));
1564 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1565 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1566 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1567 if (reg_offset != 7)
1568 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1574 * gfx_v7_0_select_se_sh - select which SE, SH to address
1576 * @adev: amdgpu_device pointer
1577 * @se_num: shader engine to address
1578 * @sh_num: sh block to address
1580 * Select which SE, SH combinations to address. Certain
1581 * registers are instanced per SE or SH. 0xffffffff means
1582 * broadcast to all SEs or SHs (CIK).
1584 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
1585 u32 se_num, u32 sh_num, u32 instance)
1589 if (instance == 0xffffffff)
1590 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1592 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1594 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1595 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1596 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1597 else if (se_num == 0xffffffff)
1598 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1599 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1600 else if (sh_num == 0xffffffff)
1601 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1602 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1604 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1605 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1606 WREG32(mmGRBM_GFX_INDEX, data);
1610 * gfx_v7_0_create_bitmask - create a bitmask
1612 * @bit_width: length of the mask
1614 * create a variable length bit mask (CIK).
1615 * Returns the bitmask.
1617 static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1619 return (u32)((1ULL << bit_width) - 1);
1623 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1625 * @adev: amdgpu_device pointer
1627 * Calculates the bitmask of enabled RBs (CIK).
1628 * Returns the enabled RB bitmask.
1630 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1634 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1635 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1637 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1638 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1640 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1641 adev->gfx.config.max_sh_per_se);
1643 return (~data) & mask;
1647 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1649 switch (adev->asic_type) {
1651 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1652 SE_XSEL(1) | SE_YSEL(1);
1656 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1657 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1658 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1660 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1664 *rconf |= RB_MAP_PKR0(2);
1673 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1679 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1680 u32 raster_config, u32 raster_config_1,
1681 unsigned rb_mask, unsigned num_rb)
1683 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1684 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1685 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1686 unsigned rb_per_se = num_rb / num_se;
1687 unsigned se_mask[4];
1690 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1691 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1692 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1693 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1695 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1696 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1697 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1699 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1700 (!se_mask[2] && !se_mask[3]))) {
1701 raster_config_1 &= ~SE_PAIR_MAP_MASK;
1703 if (!se_mask[0] && !se_mask[1]) {
1705 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1708 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1712 for (se = 0; se < num_se; se++) {
1713 unsigned raster_config_se = raster_config;
1714 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1715 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1716 int idx = (se / 2) * 2;
1718 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1719 raster_config_se &= ~SE_MAP_MASK;
1721 if (!se_mask[idx]) {
1722 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1724 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1728 pkr0_mask &= rb_mask;
1729 pkr1_mask &= rb_mask;
1730 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1731 raster_config_se &= ~PKR_MAP_MASK;
1734 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1736 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1740 if (rb_per_se >= 2) {
1741 unsigned rb0_mask = 1 << (se * rb_per_se);
1742 unsigned rb1_mask = rb0_mask << 1;
1744 rb0_mask &= rb_mask;
1745 rb1_mask &= rb_mask;
1746 if (!rb0_mask || !rb1_mask) {
1747 raster_config_se &= ~RB_MAP_PKR0_MASK;
1751 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1754 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1758 if (rb_per_se > 2) {
1759 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1760 rb1_mask = rb0_mask << 1;
1761 rb0_mask &= rb_mask;
1762 rb1_mask &= rb_mask;
1763 if (!rb0_mask || !rb1_mask) {
1764 raster_config_se &= ~RB_MAP_PKR1_MASK;
1768 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1771 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1777 /* GRBM_GFX_INDEX has a different offset on CI+ */
1778 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1779 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1780 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1783 /* GRBM_GFX_INDEX has a different offset on CI+ */
1784 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1788 * gfx_v7_0_setup_rb - setup the RBs on the asic
1790 * @adev: amdgpu_device pointer
1791 * @se_num: number of SEs (shader engines) for the asic
1792 * @sh_per_se: number of SH blocks per SE for the asic
1794 * Configures per-SE/SH RB registers (CIK).
1796 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1800 u32 raster_config = 0, raster_config_1 = 0;
1802 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1803 adev->gfx.config.max_sh_per_se;
1804 unsigned num_rb_pipes;
1806 mutex_lock(&adev->grbm_idx_mutex);
1807 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1808 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1809 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1810 data = gfx_v7_0_get_rb_active_bitmap(adev);
1811 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1812 rb_bitmap_width_per_sh);
1815 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1817 adev->gfx.config.backend_enable_mask = active_rbs;
1818 adev->gfx.config.num_rbs = hweight32(active_rbs);
1820 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1821 adev->gfx.config.max_shader_engines, 16);
1823 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1825 if (!adev->gfx.config.backend_enable_mask ||
1826 adev->gfx.config.num_rbs >= num_rb_pipes) {
1827 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1828 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1830 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1831 adev->gfx.config.backend_enable_mask,
1834 mutex_unlock(&adev->grbm_idx_mutex);
1838 * gmc_v7_0_init_compute_vmid - gart enable
1840 * @rdev: amdgpu_device pointer
1842 * Initialize compute vmid sh_mem registers
1845 #define DEFAULT_SH_MEM_BASES (0x6000)
1846 #define FIRST_COMPUTE_VMID (8)
1847 #define LAST_COMPUTE_VMID (16)
1848 static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1851 uint32_t sh_mem_config;
1852 uint32_t sh_mem_bases;
1855 * Configure apertures:
1856 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1857 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1858 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1860 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1861 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1862 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1863 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1864 mutex_lock(&adev->srbm_mutex);
1865 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1866 cik_srbm_select(adev, 0, 0, 0, i);
1867 /* CP and shaders */
1868 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1869 WREG32(mmSH_MEM_APE1_BASE, 1);
1870 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1871 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1873 cik_srbm_select(adev, 0, 0, 0, 0);
1874 mutex_unlock(&adev->srbm_mutex);
1877 static void gfx_v7_0_config_init(struct amdgpu_device *adev)
1879 adev->gfx.config.double_offchip_lds_buf = 1;
1883 * gfx_v7_0_gpu_init - setup the 3D engine
1885 * @adev: amdgpu_device pointer
1887 * Configures the 3D engine and tiling configuration
1888 * registers so that the 3D engine is usable.
1890 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1892 u32 tmp, sh_mem_cfg;
1895 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1897 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1898 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1899 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1901 gfx_v7_0_tiling_mode_table_init(adev);
1903 gfx_v7_0_setup_rb(adev);
1904 gfx_v7_0_get_cu_info(adev);
1905 gfx_v7_0_config_init(adev);
1907 /* set HW defaults for 3D engine */
1908 WREG32(mmCP_MEQ_THRESHOLDS,
1909 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1910 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1912 mutex_lock(&adev->grbm_idx_mutex);
1914 * making sure that the following register writes will be broadcasted
1915 * to all the shaders
1917 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1919 /* XXX SH_MEM regs */
1920 /* where to put LDS, scratch, GPUVM in FSA64 space */
1921 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1922 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1924 mutex_lock(&adev->srbm_mutex);
1925 for (i = 0; i < 16; i++) {
1926 cik_srbm_select(adev, 0, 0, 0, i);
1927 /* CP and shaders */
1928 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1929 WREG32(mmSH_MEM_APE1_BASE, 1);
1930 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1931 WREG32(mmSH_MEM_BASES, 0);
1933 cik_srbm_select(adev, 0, 0, 0, 0);
1934 mutex_unlock(&adev->srbm_mutex);
1936 gmc_v7_0_init_compute_vmid(adev);
1938 WREG32(mmSX_DEBUG_1, 0x20);
1940 WREG32(mmTA_CNTL_AUX, 0x00010000);
1942 tmp = RREG32(mmSPI_CONFIG_CNTL);
1944 WREG32(mmSPI_CONFIG_CNTL, tmp);
1946 WREG32(mmSQ_CONFIG, 1);
1948 WREG32(mmDB_DEBUG, 0);
1950 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1952 WREG32(mmDB_DEBUG2, tmp);
1954 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1956 WREG32(mmDB_DEBUG3, tmp);
1958 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1960 WREG32(mmCB_HW_CONTROL, tmp);
1962 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1964 WREG32(mmPA_SC_FIFO_SIZE,
1965 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1966 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1967 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1968 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1970 WREG32(mmVGT_NUM_INSTANCES, 1);
1972 WREG32(mmCP_PERFMON_CNTL, 0);
1974 WREG32(mmSQ_CONFIG, 0);
1976 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1977 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1978 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1980 WREG32(mmVGT_CACHE_INVALIDATION,
1981 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1982 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1984 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1985 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1987 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1988 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1989 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1991 tmp = RREG32(mmSPI_ARB_PRIORITY);
1992 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
1993 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
1994 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
1995 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
1996 WREG32(mmSPI_ARB_PRIORITY, tmp);
1998 mutex_unlock(&adev->grbm_idx_mutex);
2004 * GPU scratch registers helpers function.
2007 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
2009 * @adev: amdgpu_device pointer
2011 * Set up the number and offset of the CP scratch registers.
2012 * NOTE: use of CP scratch registers is a legacy inferface and
2013 * is not used by default on newer asics (r6xx+). On newer asics,
2014 * memory buffers are used for fences rather than scratch regs.
2016 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
2018 adev->gfx.scratch.num_reg = 7;
2019 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
2020 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
2024 * gfx_v7_0_ring_test_ring - basic gfx ring test
2026 * @adev: amdgpu_device pointer
2027 * @ring: amdgpu_ring structure holding ring information
2029 * Allocate a scratch register and write to it using the gfx ring (CIK).
2030 * Provides a basic gfx ring test to verify that the ring is working.
2031 * Used by gfx_v7_0_cp_gfx_resume();
2032 * Returns 0 on success, error on failure.
2034 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2036 struct amdgpu_device *adev = ring->adev;
2042 r = amdgpu_gfx_scratch_get(adev, &scratch);
2044 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
2047 WREG32(scratch, 0xCAFEDEAD);
2048 r = amdgpu_ring_alloc(ring, 3);
2050 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
2051 amdgpu_gfx_scratch_free(adev, scratch);
2054 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2055 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2056 amdgpu_ring_write(ring, 0xDEADBEEF);
2057 amdgpu_ring_commit(ring);
2059 for (i = 0; i < adev->usec_timeout; i++) {
2060 tmp = RREG32(scratch);
2061 if (tmp == 0xDEADBEEF)
2065 if (i < adev->usec_timeout) {
2066 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2068 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2069 ring->idx, scratch, tmp);
2072 amdgpu_gfx_scratch_free(adev, scratch);
2077 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
2079 * @adev: amdgpu_device pointer
2080 * @ridx: amdgpu ring index
2082 * Emits an hdp flush on the cp.
2084 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2087 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
2089 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2092 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2095 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2101 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2104 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2105 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2106 WAIT_REG_MEM_FUNCTION(3) | /* == */
2107 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2108 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2109 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2110 amdgpu_ring_write(ring, ref_and_mask);
2111 amdgpu_ring_write(ring, ref_and_mask);
2112 amdgpu_ring_write(ring, 0x20); /* poll interval */
2115 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2117 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2118 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2121 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2122 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2128 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
2130 * @adev: amdgpu_device pointer
2131 * @ridx: amdgpu ring index
2133 * Emits an hdp invalidate on the cp.
2135 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2137 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2138 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2139 WRITE_DATA_DST_SEL(0) |
2141 amdgpu_ring_write(ring, mmHDP_DEBUG0);
2142 amdgpu_ring_write(ring, 0);
2143 amdgpu_ring_write(ring, 1);
2147 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2149 * @adev: amdgpu_device pointer
2150 * @fence: amdgpu fence object
2152 * Emits a fence sequnce number on the gfx ring and flushes
2155 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2156 u64 seq, unsigned flags)
2158 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2159 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2160 /* Workaround for cache flush problems. First send a dummy EOP
2161 * event down the pipe with seq one below.
2163 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2164 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2166 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2168 amdgpu_ring_write(ring, addr & 0xfffffffc);
2169 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2170 DATA_SEL(1) | INT_SEL(0));
2171 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2172 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2174 /* Then send the real EOP event down the pipe. */
2175 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2176 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2178 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2180 amdgpu_ring_write(ring, addr & 0xfffffffc);
2181 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2182 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2183 amdgpu_ring_write(ring, lower_32_bits(seq));
2184 amdgpu_ring_write(ring, upper_32_bits(seq));
2188 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2190 * @adev: amdgpu_device pointer
2191 * @fence: amdgpu fence object
2193 * Emits a fence sequnce number on the compute ring and flushes
2196 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2200 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2201 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2203 /* RELEASE_MEM - flush caches, send int */
2204 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2205 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2207 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2209 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2210 amdgpu_ring_write(ring, addr & 0xfffffffc);
2211 amdgpu_ring_write(ring, upper_32_bits(addr));
2212 amdgpu_ring_write(ring, lower_32_bits(seq));
2213 amdgpu_ring_write(ring, upper_32_bits(seq));
2220 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2222 * @ring: amdgpu_ring structure holding ring information
2223 * @ib: amdgpu indirect buffer object
2225 * Emits an DE (drawing engine) or CE (constant engine) IB
2226 * on the gfx ring. IBs are usually generated by userspace
2227 * acceleration drivers and submitted to the kernel for
2228 * sheduling on the ring. This function schedules the IB
2229 * on the gfx ring for execution by the GPU.
2231 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2232 struct amdgpu_ib *ib,
2233 unsigned vm_id, bool ctx_switch)
2235 u32 header, control = 0;
2237 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2239 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2240 amdgpu_ring_write(ring, 0);
2243 if (ib->flags & AMDGPU_IB_FLAG_CE)
2244 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2246 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2248 control |= ib->length_dw | (vm_id << 24);
2250 amdgpu_ring_write(ring, header);
2251 amdgpu_ring_write(ring,
2255 (ib->gpu_addr & 0xFFFFFFFC));
2256 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2257 amdgpu_ring_write(ring, control);
2260 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2261 struct amdgpu_ib *ib,
2262 unsigned vm_id, bool ctx_switch)
2264 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
2266 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2267 amdgpu_ring_write(ring,
2271 (ib->gpu_addr & 0xFFFFFFFC));
2272 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2273 amdgpu_ring_write(ring, control);
2276 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2280 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2281 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2282 gfx_v7_0_ring_emit_vgt_flush(ring);
2283 /* set load_global_config & load_global_uconfig */
2285 /* set load_cs_sh_regs */
2287 /* set load_per_context_state & load_gfx_sh_regs */
2291 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2292 amdgpu_ring_write(ring, dw2);
2293 amdgpu_ring_write(ring, 0);
2297 * gfx_v7_0_ring_test_ib - basic ring IB test
2299 * @ring: amdgpu_ring structure holding ring information
2301 * Allocate an IB and execute it on the gfx ring (CIK).
2302 * Provides a basic gfx ring test to verify that IBs are working.
2303 * Returns 0 on success, error on failure.
2305 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
2307 struct amdgpu_device *adev = ring->adev;
2308 struct amdgpu_ib ib;
2309 struct dma_fence *f = NULL;
2314 r = amdgpu_gfx_scratch_get(adev, &scratch);
2316 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
2319 WREG32(scratch, 0xCAFEDEAD);
2320 memset(&ib, 0, sizeof(ib));
2321 r = amdgpu_ib_get(adev, NULL, 256, &ib);
2323 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
2326 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2327 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2328 ib.ptr[2] = 0xDEADBEEF;
2331 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
2335 r = dma_fence_wait_timeout(f, false, timeout);
2337 DRM_ERROR("amdgpu: IB test timed out\n");
2341 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
2344 tmp = RREG32(scratch);
2345 if (tmp == 0xDEADBEEF) {
2346 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
2349 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2355 amdgpu_ib_free(adev, &ib, NULL);
2358 amdgpu_gfx_scratch_free(adev, scratch);
2364 * On CIK, gfx and compute now have independant command processors.
2367 * Gfx consists of a single ring and can process both gfx jobs and
2368 * compute jobs. The gfx CP consists of three microengines (ME):
2369 * PFP - Pre-Fetch Parser
2371 * CE - Constant Engine
2372 * The PFP and ME make up what is considered the Drawing Engine (DE).
2373 * The CE is an asynchronous engine used for updating buffer desciptors
2374 * used by the DE so that they can be loaded into cache in parallel
2375 * while the DE is processing state update packets.
2378 * The compute CP consists of two microengines (ME):
2379 * MEC1 - Compute MicroEngine 1
2380 * MEC2 - Compute MicroEngine 2
2381 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2382 * The queues are exposed to userspace and are programmed directly
2383 * by the compute runtime.
2386 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2388 * @adev: amdgpu_device pointer
2389 * @enable: enable or disable the MEs
2391 * Halts or unhalts the gfx MEs.
2393 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2398 WREG32(mmCP_ME_CNTL, 0);
2400 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2401 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2402 adev->gfx.gfx_ring[i].ready = false;
2408 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2410 * @adev: amdgpu_device pointer
2412 * Loads the gfx PFP, ME, and CE ucode.
2413 * Returns 0 for success, -EINVAL if the ucode is not available.
2415 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2417 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2418 const struct gfx_firmware_header_v1_0 *ce_hdr;
2419 const struct gfx_firmware_header_v1_0 *me_hdr;
2420 const __le32 *fw_data;
2421 unsigned i, fw_size;
2423 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2426 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2427 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2428 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2430 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2431 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2432 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2433 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2434 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2435 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2436 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2437 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2438 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2440 gfx_v7_0_cp_gfx_enable(adev, false);
2443 fw_data = (const __le32 *)
2444 (adev->gfx.pfp_fw->data +
2445 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2446 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2447 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2448 for (i = 0; i < fw_size; i++)
2449 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2450 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2453 fw_data = (const __le32 *)
2454 (adev->gfx.ce_fw->data +
2455 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2456 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2457 WREG32(mmCP_CE_UCODE_ADDR, 0);
2458 for (i = 0; i < fw_size; i++)
2459 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2460 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2463 fw_data = (const __le32 *)
2464 (adev->gfx.me_fw->data +
2465 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2466 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2467 WREG32(mmCP_ME_RAM_WADDR, 0);
2468 for (i = 0; i < fw_size; i++)
2469 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2470 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2476 * gfx_v7_0_cp_gfx_start - start the gfx ring
2478 * @adev: amdgpu_device pointer
2480 * Enables the ring and loads the clear state context and other
2481 * packets required to init the ring.
2482 * Returns 0 for success, error for failure.
2484 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2486 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2487 const struct cs_section_def *sect = NULL;
2488 const struct cs_extent_def *ext = NULL;
2492 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2493 WREG32(mmCP_ENDIAN_SWAP, 0);
2494 WREG32(mmCP_DEVICE_ID, 1);
2496 gfx_v7_0_cp_gfx_enable(adev, true);
2498 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2500 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2504 /* init the CE partitions. CE only used for gfx on CIK */
2505 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2506 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2507 amdgpu_ring_write(ring, 0x8000);
2508 amdgpu_ring_write(ring, 0x8000);
2510 /* clear state buffer */
2511 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2512 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2514 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2515 amdgpu_ring_write(ring, 0x80000000);
2516 amdgpu_ring_write(ring, 0x80000000);
2518 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2519 for (ext = sect->section; ext->extent != NULL; ++ext) {
2520 if (sect->id == SECT_CONTEXT) {
2521 amdgpu_ring_write(ring,
2522 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2523 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2524 for (i = 0; i < ext->reg_count; i++)
2525 amdgpu_ring_write(ring, ext->extent[i]);
2530 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2531 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2532 switch (adev->asic_type) {
2534 amdgpu_ring_write(ring, 0x16000012);
2535 amdgpu_ring_write(ring, 0x00000000);
2538 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2539 amdgpu_ring_write(ring, 0x00000000);
2543 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2544 amdgpu_ring_write(ring, 0x00000000);
2547 amdgpu_ring_write(ring, 0x3a00161a);
2548 amdgpu_ring_write(ring, 0x0000002e);
2551 amdgpu_ring_write(ring, 0x00000000);
2552 amdgpu_ring_write(ring, 0x00000000);
2556 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2557 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2559 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2560 amdgpu_ring_write(ring, 0);
2562 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2563 amdgpu_ring_write(ring, 0x00000316);
2564 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2565 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2567 amdgpu_ring_commit(ring);
2573 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2575 * @adev: amdgpu_device pointer
2577 * Program the location and size of the gfx ring buffer
2578 * and test it to make sure it's working.
2579 * Returns 0 for success, error for failure.
2581 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2583 struct amdgpu_ring *ring;
2586 u64 rb_addr, rptr_addr;
2589 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2590 if (adev->asic_type != CHIP_HAWAII)
2591 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2593 /* Set the write pointer delay */
2594 WREG32(mmCP_RB_WPTR_DELAY, 0);
2596 /* set the RB to use vmid 0 */
2597 WREG32(mmCP_RB_VMID, 0);
2599 WREG32(mmSCRATCH_ADDR, 0);
2601 /* ring 0 - compute and gfx */
2602 /* Set ring buffer size */
2603 ring = &adev->gfx.gfx_ring[0];
2604 rb_bufsz = order_base_2(ring->ring_size / 8);
2605 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2607 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2609 WREG32(mmCP_RB0_CNTL, tmp);
2611 /* Initialize the ring buffer's read and write pointers */
2612 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2614 WREG32(mmCP_RB0_WPTR, ring->wptr);
2616 /* set the wb address wether it's enabled or not */
2617 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2618 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2619 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2621 /* scratch register shadowing is no longer supported */
2622 WREG32(mmSCRATCH_UMSK, 0);
2625 WREG32(mmCP_RB0_CNTL, tmp);
2627 rb_addr = ring->gpu_addr >> 8;
2628 WREG32(mmCP_RB0_BASE, rb_addr);
2629 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2631 /* start the ring */
2632 gfx_v7_0_cp_gfx_start(adev);
2634 r = amdgpu_ring_test_ring(ring);
2636 ring->ready = false;
2643 static u32 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
2645 return ring->adev->wb.wb[ring->rptr_offs];
2648 static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2650 struct amdgpu_device *adev = ring->adev;
2652 return RREG32(mmCP_RB0_WPTR);
2655 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2657 struct amdgpu_device *adev = ring->adev;
2659 WREG32(mmCP_RB0_WPTR, ring->wptr);
2660 (void)RREG32(mmCP_RB0_WPTR);
2663 static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2665 /* XXX check if swapping is necessary on BE */
2666 return ring->adev->wb.wb[ring->wptr_offs];
2669 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2671 struct amdgpu_device *adev = ring->adev;
2673 /* XXX check if swapping is necessary on BE */
2674 adev->wb.wb[ring->wptr_offs] = ring->wptr;
2675 WDOORBELL32(ring->doorbell_index, ring->wptr);
2679 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2681 * @adev: amdgpu_device pointer
2682 * @enable: enable or disable the MEs
2684 * Halts or unhalts the compute MEs.
2686 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2691 WREG32(mmCP_MEC_CNTL, 0);
2693 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2694 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2695 adev->gfx.compute_ring[i].ready = false;
2701 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2703 * @adev: amdgpu_device pointer
2705 * Loads the compute MEC1&2 ucode.
2706 * Returns 0 for success, -EINVAL if the ucode is not available.
2708 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2710 const struct gfx_firmware_header_v1_0 *mec_hdr;
2711 const __le32 *fw_data;
2712 unsigned i, fw_size;
2714 if (!adev->gfx.mec_fw)
2717 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2718 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2719 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2720 adev->gfx.mec_feature_version = le32_to_cpu(
2721 mec_hdr->ucode_feature_version);
2723 gfx_v7_0_cp_compute_enable(adev, false);
2726 fw_data = (const __le32 *)
2727 (adev->gfx.mec_fw->data +
2728 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2729 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2730 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2731 for (i = 0; i < fw_size; i++)
2732 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2733 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2735 if (adev->asic_type == CHIP_KAVERI) {
2736 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2738 if (!adev->gfx.mec2_fw)
2741 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2742 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2743 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2744 adev->gfx.mec2_feature_version = le32_to_cpu(
2745 mec2_hdr->ucode_feature_version);
2748 fw_data = (const __le32 *)
2749 (adev->gfx.mec2_fw->data +
2750 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2751 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2752 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2753 for (i = 0; i < fw_size; i++)
2754 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2755 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2762 * gfx_v7_0_cp_compute_fini - stop the compute queues
2764 * @adev: amdgpu_device pointer
2766 * Stop the compute queues and tear down the driver queue
2769 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2773 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2774 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2776 if (ring->mqd_obj) {
2777 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2778 if (unlikely(r != 0))
2779 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2781 amdgpu_bo_unpin(ring->mqd_obj);
2782 amdgpu_bo_unreserve(ring->mqd_obj);
2784 amdgpu_bo_unref(&ring->mqd_obj);
2785 ring->mqd_obj = NULL;
2790 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2794 if (adev->gfx.mec.hpd_eop_obj) {
2795 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2796 if (unlikely(r != 0))
2797 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2798 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2799 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2801 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2802 adev->gfx.mec.hpd_eop_obj = NULL;
2806 #define MEC_HPD_SIZE 2048
2808 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2814 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2815 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2816 * Nonetheless, we assign only 1 pipe because all other pipes will
2819 adev->gfx.mec.num_mec = 1;
2820 adev->gfx.mec.num_pipe = 1;
2821 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
2823 if (adev->gfx.mec.hpd_eop_obj == NULL) {
2824 r = amdgpu_bo_create(adev,
2825 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
2827 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2828 &adev->gfx.mec.hpd_eop_obj);
2830 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2835 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2836 if (unlikely(r != 0)) {
2837 gfx_v7_0_mec_fini(adev);
2840 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2841 &adev->gfx.mec.hpd_eop_gpu_addr);
2843 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2844 gfx_v7_0_mec_fini(adev);
2847 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2849 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2850 gfx_v7_0_mec_fini(adev);
2854 /* clear memory. Not sure if this is required or not */
2855 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
2857 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2858 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2863 struct hqd_registers
2865 u32 cp_mqd_base_addr;
2866 u32 cp_mqd_base_addr_hi;
2869 u32 cp_hqd_persistent_state;
2870 u32 cp_hqd_pipe_priority;
2871 u32 cp_hqd_queue_priority;
2874 u32 cp_hqd_pq_base_hi;
2876 u32 cp_hqd_pq_rptr_report_addr;
2877 u32 cp_hqd_pq_rptr_report_addr_hi;
2878 u32 cp_hqd_pq_wptr_poll_addr;
2879 u32 cp_hqd_pq_wptr_poll_addr_hi;
2880 u32 cp_hqd_pq_doorbell_control;
2882 u32 cp_hqd_pq_control;
2883 u32 cp_hqd_ib_base_addr;
2884 u32 cp_hqd_ib_base_addr_hi;
2886 u32 cp_hqd_ib_control;
2887 u32 cp_hqd_iq_timer;
2889 u32 cp_hqd_dequeue_request;
2890 u32 cp_hqd_dma_offload;
2891 u32 cp_hqd_sema_cmd;
2892 u32 cp_hqd_msg_type;
2893 u32 cp_hqd_atomic0_preop_lo;
2894 u32 cp_hqd_atomic0_preop_hi;
2895 u32 cp_hqd_atomic1_preop_lo;
2896 u32 cp_hqd_atomic1_preop_hi;
2897 u32 cp_hqd_hq_scheduler0;
2898 u32 cp_hqd_hq_scheduler1;
2905 u32 dispatch_initiator;
2909 u32 pipeline_stat_enable;
2910 u32 perf_counter_enable;
2916 u32 resource_limits;
2917 u32 static_thread_mgmt01[2];
2919 u32 static_thread_mgmt23[2];
2921 u32 thread_trace_enable;
2924 u32 vgtcs_invoke_count[2];
2925 struct hqd_registers queue_state;
2927 u32 interrupt_queue[64];
2931 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2933 * @adev: amdgpu_device pointer
2935 * Program the compute queues and test them to make sure they
2937 * Returns 0 for success, error for failure.
2939 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
2943 bool use_doorbell = true;
2949 struct bonaire_mqd *mqd;
2950 struct amdgpu_ring *ring;
2952 /* fix up chicken bits */
2953 tmp = RREG32(mmCP_CPF_DEBUG);
2955 WREG32(mmCP_CPF_DEBUG, tmp);
2957 /* init the pipes */
2958 mutex_lock(&adev->srbm_mutex);
2959 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2960 int me = (i < 4) ? 1 : 2;
2961 int pipe = (i < 4) ? i : (i - 4);
2963 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
2965 cik_srbm_select(adev, me, pipe, 0, 0);
2967 /* write the EOP addr */
2968 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2969 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2971 /* set the VMID assigned */
2972 WREG32(mmCP_HPD_EOP_VMID, 0);
2974 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2975 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2976 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2977 tmp |= order_base_2(MEC_HPD_SIZE / 8);
2978 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2980 cik_srbm_select(adev, 0, 0, 0, 0);
2981 mutex_unlock(&adev->srbm_mutex);
2983 /* init the queues. Just two for now. */
2984 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2985 ring = &adev->gfx.compute_ring[i];
2987 if (ring->mqd_obj == NULL) {
2988 r = amdgpu_bo_create(adev,
2989 sizeof(struct bonaire_mqd),
2991 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2994 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2999 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3000 if (unlikely(r != 0)) {
3001 gfx_v7_0_cp_compute_fini(adev);
3004 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3007 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3008 gfx_v7_0_cp_compute_fini(adev);
3011 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3013 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3014 gfx_v7_0_cp_compute_fini(adev);
3018 /* init the mqd struct */
3019 memset(buf, 0, sizeof(struct bonaire_mqd));
3021 mqd = (struct bonaire_mqd *)buf;
3022 mqd->header = 0xC0310800;
3023 mqd->static_thread_mgmt01[0] = 0xffffffff;
3024 mqd->static_thread_mgmt01[1] = 0xffffffff;
3025 mqd->static_thread_mgmt23[0] = 0xffffffff;
3026 mqd->static_thread_mgmt23[1] = 0xffffffff;
3028 mutex_lock(&adev->srbm_mutex);
3029 cik_srbm_select(adev, ring->me,
3033 /* disable wptr polling */
3034 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3035 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
3036 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3038 /* enable doorbell? */
3039 mqd->queue_state.cp_hqd_pq_doorbell_control =
3040 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3042 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3044 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3045 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3046 mqd->queue_state.cp_hqd_pq_doorbell_control);
3048 /* disable the queue if it's active */
3049 mqd->queue_state.cp_hqd_dequeue_request = 0;
3050 mqd->queue_state.cp_hqd_pq_rptr = 0;
3051 mqd->queue_state.cp_hqd_pq_wptr= 0;
3052 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3053 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3054 for (j = 0; j < adev->usec_timeout; j++) {
3055 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3059 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
3060 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
3061 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3064 /* set the pointer to the MQD */
3065 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
3066 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3067 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
3068 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
3069 /* set MQD vmid to 0 */
3070 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
3071 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
3072 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
3074 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3075 hqd_gpu_addr = ring->gpu_addr >> 8;
3076 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
3077 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3078 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
3079 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
3081 /* set up the HQD, this is similar to CP_RB0_CNTL */
3082 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
3083 mqd->queue_state.cp_hqd_pq_control &=
3084 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
3085 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
3087 mqd->queue_state.cp_hqd_pq_control |=
3088 order_base_2(ring->ring_size / 8);
3089 mqd->queue_state.cp_hqd_pq_control |=
3090 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
3092 mqd->queue_state.cp_hqd_pq_control |=
3093 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
3095 mqd->queue_state.cp_hqd_pq_control &=
3096 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
3097 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
3098 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
3099 mqd->queue_state.cp_hqd_pq_control |=
3100 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
3101 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
3102 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
3104 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3105 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3106 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3107 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3108 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
3109 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3110 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
3112 /* set the wb address wether it's enabled or not */
3113 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3114 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
3115 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
3116 upper_32_bits(wb_gpu_addr) & 0xffff;
3117 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3118 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
3119 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3120 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
3122 /* enable the doorbell if requested */
3124 mqd->queue_state.cp_hqd_pq_doorbell_control =
3125 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3126 mqd->queue_state.cp_hqd_pq_doorbell_control &=
3127 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
3128 mqd->queue_state.cp_hqd_pq_doorbell_control |=
3129 (ring->doorbell_index <<
3130 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
3131 mqd->queue_state.cp_hqd_pq_doorbell_control |=
3132 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3133 mqd->queue_state.cp_hqd_pq_doorbell_control &=
3134 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
3135 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
3138 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
3140 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3141 mqd->queue_state.cp_hqd_pq_doorbell_control);
3143 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3145 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
3146 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3147 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3149 /* set the vmid for the queue */
3150 mqd->queue_state.cp_hqd_vmid = 0;
3151 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
3153 /* activate the queue */
3154 mqd->queue_state.cp_hqd_active = 1;
3155 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
3157 cik_srbm_select(adev, 0, 0, 0, 0);
3158 mutex_unlock(&adev->srbm_mutex);
3160 amdgpu_bo_kunmap(ring->mqd_obj);
3161 amdgpu_bo_unreserve(ring->mqd_obj);
3166 gfx_v7_0_cp_compute_enable(adev, true);
3168 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3169 ring = &adev->gfx.compute_ring[i];
3171 r = amdgpu_ring_test_ring(ring);
3173 ring->ready = false;
3179 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3181 gfx_v7_0_cp_gfx_enable(adev, enable);
3182 gfx_v7_0_cp_compute_enable(adev, enable);
3185 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3189 r = gfx_v7_0_cp_gfx_load_microcode(adev);
3192 r = gfx_v7_0_cp_compute_load_microcode(adev);
3199 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3202 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3205 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3206 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3208 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3209 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3210 WREG32(mmCP_INT_CNTL_RING0, tmp);
3213 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3217 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3219 r = gfx_v7_0_cp_load_microcode(adev);
3223 r = gfx_v7_0_cp_gfx_resume(adev);
3226 r = gfx_v7_0_cp_compute_resume(adev);
3230 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3236 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3238 * @ring: the ring to emmit the commands to
3240 * Sync the command pipeline with the PFP. E.g. wait for everything
3243 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3245 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3246 uint32_t seq = ring->fence_drv.sync_seq;
3247 uint64_t addr = ring->fence_drv.gpu_addr;
3249 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3250 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3251 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3252 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3253 amdgpu_ring_write(ring, addr & 0xfffffffc);
3254 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3255 amdgpu_ring_write(ring, seq);
3256 amdgpu_ring_write(ring, 0xffffffff);
3257 amdgpu_ring_write(ring, 4); /* poll interval */
3260 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3261 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3262 amdgpu_ring_write(ring, 0);
3263 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3264 amdgpu_ring_write(ring, 0);
3270 * VMID 0 is the physical GPU addresses as used by the kernel.
3271 * VMIDs 1-15 are used for userspace clients and are handled
3272 * by the amdgpu vm/hsa code.
3275 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3277 * @adev: amdgpu_device pointer
3279 * Update the page table base and flush the VM TLB
3280 * using the CP (CIK).
3282 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3283 unsigned vm_id, uint64_t pd_addr)
3285 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3287 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3288 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3289 WRITE_DATA_DST_SEL(0)));
3291 amdgpu_ring_write(ring,
3292 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3294 amdgpu_ring_write(ring,
3295 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3297 amdgpu_ring_write(ring, 0);
3298 amdgpu_ring_write(ring, pd_addr >> 12);
3300 /* bits 0-15 are the VM contexts0-15 */
3301 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3302 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3303 WRITE_DATA_DST_SEL(0)));
3304 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3305 amdgpu_ring_write(ring, 0);
3306 amdgpu_ring_write(ring, 1 << vm_id);
3308 /* wait for the invalidate to complete */
3309 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3310 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3311 WAIT_REG_MEM_FUNCTION(0) | /* always */
3312 WAIT_REG_MEM_ENGINE(0))); /* me */
3313 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3314 amdgpu_ring_write(ring, 0);
3315 amdgpu_ring_write(ring, 0); /* ref */
3316 amdgpu_ring_write(ring, 0); /* mask */
3317 amdgpu_ring_write(ring, 0x20); /* poll interval */
3319 /* compute doesn't have PFP */
3321 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3322 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3323 amdgpu_ring_write(ring, 0x0);
3325 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3326 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3327 amdgpu_ring_write(ring, 0);
3328 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3329 amdgpu_ring_write(ring, 0);
3335 * The RLC is a multi-purpose microengine that handles a
3336 * variety of functions.
3338 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3342 /* save restore block */
3343 if (adev->gfx.rlc.save_restore_obj) {
3344 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3345 if (unlikely(r != 0))
3346 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3347 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3348 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3350 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3351 adev->gfx.rlc.save_restore_obj = NULL;
3354 /* clear state block */
3355 if (adev->gfx.rlc.clear_state_obj) {
3356 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3357 if (unlikely(r != 0))
3358 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3359 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3360 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3362 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3363 adev->gfx.rlc.clear_state_obj = NULL;
3366 /* clear state block */
3367 if (adev->gfx.rlc.cp_table_obj) {
3368 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3369 if (unlikely(r != 0))
3370 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3371 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3372 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3374 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3375 adev->gfx.rlc.cp_table_obj = NULL;
3379 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3382 volatile u32 *dst_ptr;
3384 const struct cs_section_def *cs_data;
3387 /* allocate rlc buffers */
3388 if (adev->flags & AMD_IS_APU) {
3389 if (adev->asic_type == CHIP_KAVERI) {
3390 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3391 adev->gfx.rlc.reg_list_size =
3392 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3394 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3395 adev->gfx.rlc.reg_list_size =
3396 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3399 adev->gfx.rlc.cs_data = ci_cs_data;
3400 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3401 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3403 src_ptr = adev->gfx.rlc.reg_list;
3404 dws = adev->gfx.rlc.reg_list_size;
3405 dws += (5 * 16) + 48 + 48 + 64;
3407 cs_data = adev->gfx.rlc.cs_data;
3410 /* save restore block */
3411 if (adev->gfx.rlc.save_restore_obj == NULL) {
3412 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3413 AMDGPU_GEM_DOMAIN_VRAM,
3414 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
3415 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
3417 &adev->gfx.rlc.save_restore_obj);
3419 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3424 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3425 if (unlikely(r != 0)) {
3426 gfx_v7_0_rlc_fini(adev);
3429 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3430 &adev->gfx.rlc.save_restore_gpu_addr);
3432 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3433 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3434 gfx_v7_0_rlc_fini(adev);
3438 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3440 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3441 gfx_v7_0_rlc_fini(adev);
3444 /* write the sr buffer */
3445 dst_ptr = adev->gfx.rlc.sr_ptr;
3446 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3447 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3448 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3449 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3453 /* clear state block */
3454 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3456 if (adev->gfx.rlc.clear_state_obj == NULL) {
3457 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3458 AMDGPU_GEM_DOMAIN_VRAM,
3459 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
3460 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
3462 &adev->gfx.rlc.clear_state_obj);
3464 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3465 gfx_v7_0_rlc_fini(adev);
3469 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3470 if (unlikely(r != 0)) {
3471 gfx_v7_0_rlc_fini(adev);
3474 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3475 &adev->gfx.rlc.clear_state_gpu_addr);
3477 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3478 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3479 gfx_v7_0_rlc_fini(adev);
3483 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3485 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3486 gfx_v7_0_rlc_fini(adev);
3489 /* set up the cs buffer */
3490 dst_ptr = adev->gfx.rlc.cs_ptr;
3491 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3492 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3493 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3496 if (adev->gfx.rlc.cp_table_size) {
3497 if (adev->gfx.rlc.cp_table_obj == NULL) {
3498 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
3499 AMDGPU_GEM_DOMAIN_VRAM,
3500 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
3501 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
3503 &adev->gfx.rlc.cp_table_obj);
3505 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3506 gfx_v7_0_rlc_fini(adev);
3511 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3512 if (unlikely(r != 0)) {
3513 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3514 gfx_v7_0_rlc_fini(adev);
3517 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3518 &adev->gfx.rlc.cp_table_gpu_addr);
3520 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3521 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3522 gfx_v7_0_rlc_fini(adev);
3525 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3527 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3528 gfx_v7_0_rlc_fini(adev);
3532 gfx_v7_0_init_cp_pg_table(adev);
3534 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3535 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3542 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3546 tmp = RREG32(mmRLC_LB_CNTL);
3548 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3550 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3551 WREG32(mmRLC_LB_CNTL, tmp);
3554 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3559 mutex_lock(&adev->grbm_idx_mutex);
3560 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3561 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3562 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
3563 for (k = 0; k < adev->usec_timeout; k++) {
3564 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3570 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3571 mutex_unlock(&adev->grbm_idx_mutex);
3573 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3574 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3575 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3576 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3577 for (k = 0; k < adev->usec_timeout; k++) {
3578 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3584 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3588 tmp = RREG32(mmRLC_CNTL);
3590 WREG32(mmRLC_CNTL, rlc);
3593 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3597 orig = data = RREG32(mmRLC_CNTL);
3599 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3602 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3603 WREG32(mmRLC_CNTL, data);
3605 for (i = 0; i < adev->usec_timeout; i++) {
3606 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3611 gfx_v7_0_wait_for_rlc_serdes(adev);
3617 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3621 tmp = 0x1 | (1 << 1);
3622 WREG32(mmRLC_GPR_REG2, tmp);
3624 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3625 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3626 for (i = 0; i < adev->usec_timeout; i++) {
3627 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3632 for (i = 0; i < adev->usec_timeout; i++) {
3633 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3639 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3643 tmp = 0x1 | (0 << 1);
3644 WREG32(mmRLC_GPR_REG2, tmp);
3648 * gfx_v7_0_rlc_stop - stop the RLC ME
3650 * @adev: amdgpu_device pointer
3652 * Halt the RLC ME (MicroEngine) (CIK).
3654 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3656 WREG32(mmRLC_CNTL, 0);
3658 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3660 gfx_v7_0_wait_for_rlc_serdes(adev);
3664 * gfx_v7_0_rlc_start - start the RLC ME
3666 * @adev: amdgpu_device pointer
3668 * Unhalt the RLC ME (MicroEngine) (CIK).
3670 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3672 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3674 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3679 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3681 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3683 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3684 WREG32(mmGRBM_SOFT_RESET, tmp);
3686 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3687 WREG32(mmGRBM_SOFT_RESET, tmp);
3692 * gfx_v7_0_rlc_resume - setup the RLC hw
3694 * @adev: amdgpu_device pointer
3696 * Initialize the RLC registers, load the ucode,
3697 * and start the RLC (CIK).
3698 * Returns 0 for success, -EINVAL if the ucode is not available.
3700 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3702 const struct rlc_firmware_header_v1_0 *hdr;
3703 const __le32 *fw_data;
3704 unsigned i, fw_size;
3707 if (!adev->gfx.rlc_fw)
3710 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3711 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3712 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3713 adev->gfx.rlc_feature_version = le32_to_cpu(
3714 hdr->ucode_feature_version);
3716 gfx_v7_0_rlc_stop(adev);
3719 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3720 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3722 gfx_v7_0_rlc_reset(adev);
3724 gfx_v7_0_init_pg(adev);
3726 WREG32(mmRLC_LB_CNTR_INIT, 0);
3727 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3729 mutex_lock(&adev->grbm_idx_mutex);
3730 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3731 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3732 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3733 WREG32(mmRLC_LB_CNTL, 0x80000004);
3734 mutex_unlock(&adev->grbm_idx_mutex);
3736 WREG32(mmRLC_MC_CNTL, 0);
3737 WREG32(mmRLC_UCODE_CNTL, 0);
3739 fw_data = (const __le32 *)
3740 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3741 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3742 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3743 for (i = 0; i < fw_size; i++)
3744 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3745 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3747 /* XXX - find out what chips support lbpw */
3748 gfx_v7_0_enable_lbpw(adev, false);
3750 if (adev->asic_type == CHIP_BONAIRE)
3751 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3753 gfx_v7_0_rlc_start(adev);
3758 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3760 u32 data, orig, tmp, tmp2;
3762 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3764 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3765 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3767 tmp = gfx_v7_0_halt_rlc(adev);
3769 mutex_lock(&adev->grbm_idx_mutex);
3770 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3771 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3772 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3773 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3774 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3775 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3776 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3777 mutex_unlock(&adev->grbm_idx_mutex);
3779 gfx_v7_0_update_rlc(adev, tmp);
3781 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3783 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3785 RREG32(mmCB_CGTT_SCLK_CTRL);
3786 RREG32(mmCB_CGTT_SCLK_CTRL);
3787 RREG32(mmCB_CGTT_SCLK_CTRL);
3788 RREG32(mmCB_CGTT_SCLK_CTRL);
3790 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3794 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3798 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3800 u32 data, orig, tmp = 0;
3802 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3803 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3804 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3805 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3806 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3808 WREG32(mmCP_MEM_SLP_CNTL, data);
3812 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3816 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3818 tmp = gfx_v7_0_halt_rlc(adev);
3820 mutex_lock(&adev->grbm_idx_mutex);
3821 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3822 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3823 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3824 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3825 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3826 WREG32(mmRLC_SERDES_WR_CTRL, data);
3827 mutex_unlock(&adev->grbm_idx_mutex);
3829 gfx_v7_0_update_rlc(adev, tmp);
3831 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3832 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3833 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3834 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3835 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3836 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3837 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3838 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3839 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3840 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3841 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3842 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3844 WREG32(mmCGTS_SM_CTRL_REG, data);
3847 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3850 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3852 data = RREG32(mmRLC_MEM_SLP_CNTL);
3853 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3854 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3855 WREG32(mmRLC_MEM_SLP_CNTL, data);
3858 data = RREG32(mmCP_MEM_SLP_CNTL);
3859 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3860 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3861 WREG32(mmCP_MEM_SLP_CNTL, data);
3864 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3865 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3867 WREG32(mmCGTS_SM_CTRL_REG, data);
3869 tmp = gfx_v7_0_halt_rlc(adev);
3871 mutex_lock(&adev->grbm_idx_mutex);
3872 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3873 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3874 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3875 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3876 WREG32(mmRLC_SERDES_WR_CTRL, data);
3877 mutex_unlock(&adev->grbm_idx_mutex);
3879 gfx_v7_0_update_rlc(adev, tmp);
3883 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3886 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3887 /* order matters! */
3889 gfx_v7_0_enable_mgcg(adev, true);
3890 gfx_v7_0_enable_cgcg(adev, true);
3892 gfx_v7_0_enable_cgcg(adev, false);
3893 gfx_v7_0_enable_mgcg(adev, false);
3895 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3898 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3903 orig = data = RREG32(mmRLC_PG_CNTL);
3904 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3905 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3907 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3909 WREG32(mmRLC_PG_CNTL, data);
3912 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3917 orig = data = RREG32(mmRLC_PG_CNTL);
3918 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3919 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3921 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3923 WREG32(mmRLC_PG_CNTL, data);
3926 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3930 orig = data = RREG32(mmRLC_PG_CNTL);
3931 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3936 WREG32(mmRLC_PG_CNTL, data);
3939 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3943 orig = data = RREG32(mmRLC_PG_CNTL);
3944 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3949 WREG32(mmRLC_PG_CNTL, data);
3952 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3954 const __le32 *fw_data;
3955 volatile u32 *dst_ptr;
3956 int me, i, max_me = 4;
3958 u32 table_offset, table_size;
3960 if (adev->asic_type == CHIP_KAVERI)
3963 if (adev->gfx.rlc.cp_table_ptr == NULL)
3966 /* write the cp table buffer */
3967 dst_ptr = adev->gfx.rlc.cp_table_ptr;
3968 for (me = 0; me < max_me; me++) {
3970 const struct gfx_firmware_header_v1_0 *hdr =
3971 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3972 fw_data = (const __le32 *)
3973 (adev->gfx.ce_fw->data +
3974 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3975 table_offset = le32_to_cpu(hdr->jt_offset);
3976 table_size = le32_to_cpu(hdr->jt_size);
3977 } else if (me == 1) {
3978 const struct gfx_firmware_header_v1_0 *hdr =
3979 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3980 fw_data = (const __le32 *)
3981 (adev->gfx.pfp_fw->data +
3982 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3983 table_offset = le32_to_cpu(hdr->jt_offset);
3984 table_size = le32_to_cpu(hdr->jt_size);
3985 } else if (me == 2) {
3986 const struct gfx_firmware_header_v1_0 *hdr =
3987 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3988 fw_data = (const __le32 *)
3989 (adev->gfx.me_fw->data +
3990 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3991 table_offset = le32_to_cpu(hdr->jt_offset);
3992 table_size = le32_to_cpu(hdr->jt_size);
3993 } else if (me == 3) {
3994 const struct gfx_firmware_header_v1_0 *hdr =
3995 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3996 fw_data = (const __le32 *)
3997 (adev->gfx.mec_fw->data +
3998 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3999 table_offset = le32_to_cpu(hdr->jt_offset);
4000 table_size = le32_to_cpu(hdr->jt_size);
4002 const struct gfx_firmware_header_v1_0 *hdr =
4003 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
4004 fw_data = (const __le32 *)
4005 (adev->gfx.mec2_fw->data +
4006 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4007 table_offset = le32_to_cpu(hdr->jt_offset);
4008 table_size = le32_to_cpu(hdr->jt_size);
4011 for (i = 0; i < table_size; i ++) {
4012 dst_ptr[bo_offset + i] =
4013 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
4016 bo_offset += table_size;
4020 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
4025 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
4026 orig = data = RREG32(mmRLC_PG_CNTL);
4027 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4029 WREG32(mmRLC_PG_CNTL, data);
4031 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4032 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4034 WREG32(mmRLC_AUTO_PG_CTRL, data);
4036 orig = data = RREG32(mmRLC_PG_CNTL);
4037 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4039 WREG32(mmRLC_PG_CNTL, data);
4041 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4042 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4044 WREG32(mmRLC_AUTO_PG_CTRL, data);
4046 data = RREG32(mmDB_RENDER_CONTROL);
4050 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4058 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4059 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4061 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
4064 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4068 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4069 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4071 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4072 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4074 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
4076 return (~data) & mask;
4079 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
4083 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4085 tmp = RREG32(mmRLC_MAX_PG_CU);
4086 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
4087 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
4088 WREG32(mmRLC_MAX_PG_CU, tmp);
4091 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
4096 orig = data = RREG32(mmRLC_PG_CNTL);
4097 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
4098 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4100 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4102 WREG32(mmRLC_PG_CNTL, data);
4105 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
4110 orig = data = RREG32(mmRLC_PG_CNTL);
4111 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
4112 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4114 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4116 WREG32(mmRLC_PG_CNTL, data);
4119 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
4120 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
4122 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
4127 if (adev->gfx.rlc.cs_data) {
4128 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4129 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4130 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4131 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
4133 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4134 for (i = 0; i < 3; i++)
4135 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
4137 if (adev->gfx.rlc.reg_list) {
4138 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
4139 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
4140 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
4143 orig = data = RREG32(mmRLC_PG_CNTL);
4144 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
4146 WREG32(mmRLC_PG_CNTL, data);
4148 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
4149 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4151 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
4152 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
4153 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4154 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
4157 WREG32(mmRLC_PG_DELAY, data);
4159 data = RREG32(mmRLC_PG_DELAY_2);
4162 WREG32(mmRLC_PG_DELAY_2, data);
4164 data = RREG32(mmRLC_AUTO_PG_CTRL);
4165 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
4166 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
4167 WREG32(mmRLC_AUTO_PG_CTRL, data);
4171 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
4173 gfx_v7_0_enable_gfx_cgpg(adev, enable);
4174 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
4175 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
4178 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4181 const struct cs_section_def *sect = NULL;
4182 const struct cs_extent_def *ext = NULL;
4184 if (adev->gfx.rlc.cs_data == NULL)
4187 /* begin clear state */
4189 /* context control state */
4192 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4193 for (ext = sect->section; ext->extent != NULL; ++ext) {
4194 if (sect->id == SECT_CONTEXT)
4195 count += 2 + ext->reg_count;
4200 /* pa_sc_raster_config/pa_sc_raster_config1 */
4202 /* end clear state */
4210 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4211 volatile u32 *buffer)
4214 const struct cs_section_def *sect = NULL;
4215 const struct cs_extent_def *ext = NULL;
4217 if (adev->gfx.rlc.cs_data == NULL)
4222 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4223 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4225 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4226 buffer[count++] = cpu_to_le32(0x80000000);
4227 buffer[count++] = cpu_to_le32(0x80000000);
4229 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4230 for (ext = sect->section; ext->extent != NULL; ++ext) {
4231 if (sect->id == SECT_CONTEXT) {
4233 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4234 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4235 for (i = 0; i < ext->reg_count; i++)
4236 buffer[count++] = cpu_to_le32(ext->extent[i]);
4243 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4244 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4245 switch (adev->asic_type) {
4247 buffer[count++] = cpu_to_le32(0x16000012);
4248 buffer[count++] = cpu_to_le32(0x00000000);
4251 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4252 buffer[count++] = cpu_to_le32(0x00000000);
4256 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4257 buffer[count++] = cpu_to_le32(0x00000000);
4260 buffer[count++] = cpu_to_le32(0x3a00161a);
4261 buffer[count++] = cpu_to_le32(0x0000002e);
4264 buffer[count++] = cpu_to_le32(0x00000000);
4265 buffer[count++] = cpu_to_le32(0x00000000);
4269 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4270 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4272 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4273 buffer[count++] = cpu_to_le32(0);
4276 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4278 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4279 AMD_PG_SUPPORT_GFX_SMG |
4280 AMD_PG_SUPPORT_GFX_DMG |
4282 AMD_PG_SUPPORT_GDS |
4283 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4284 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4285 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4286 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4287 gfx_v7_0_init_gfx_cgpg(adev);
4288 gfx_v7_0_enable_cp_pg(adev, true);
4289 gfx_v7_0_enable_gds_pg(adev, true);
4291 gfx_v7_0_init_ao_cu_mask(adev);
4292 gfx_v7_0_update_gfx_pg(adev, true);
4296 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4298 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4299 AMD_PG_SUPPORT_GFX_SMG |
4300 AMD_PG_SUPPORT_GFX_DMG |
4302 AMD_PG_SUPPORT_GDS |
4303 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4304 gfx_v7_0_update_gfx_pg(adev, false);
4305 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4306 gfx_v7_0_enable_cp_pg(adev, false);
4307 gfx_v7_0_enable_gds_pg(adev, false);
4313 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4315 * @adev: amdgpu_device pointer
4317 * Fetches a GPU clock counter snapshot (SI).
4318 * Returns the 64 bit clock counter snapshot.
4320 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4324 mutex_lock(&adev->gfx.gpu_clock_mutex);
4325 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4326 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4327 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4328 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4332 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4334 uint32_t gds_base, uint32_t gds_size,
4335 uint32_t gws_base, uint32_t gws_size,
4336 uint32_t oa_base, uint32_t oa_size)
4338 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4339 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4341 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4342 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4344 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4345 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4348 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4349 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4350 WRITE_DATA_DST_SEL(0)));
4351 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4352 amdgpu_ring_write(ring, 0);
4353 amdgpu_ring_write(ring, gds_base);
4356 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4357 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4358 WRITE_DATA_DST_SEL(0)));
4359 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4360 amdgpu_ring_write(ring, 0);
4361 amdgpu_ring_write(ring, gds_size);
4364 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4365 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4366 WRITE_DATA_DST_SEL(0)));
4367 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4368 amdgpu_ring_write(ring, 0);
4369 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4372 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4373 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4374 WRITE_DATA_DST_SEL(0)));
4375 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4376 amdgpu_ring_write(ring, 0);
4377 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4380 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4382 WREG32(mmSQ_IND_INDEX,
4383 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4384 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4385 (address << SQ_IND_INDEX__INDEX__SHIFT) |
4386 (SQ_IND_INDEX__FORCE_READ_MASK));
4387 return RREG32(mmSQ_IND_DATA);
4390 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4391 uint32_t wave, uint32_t thread,
4392 uint32_t regno, uint32_t num, uint32_t *out)
4394 WREG32(mmSQ_IND_INDEX,
4395 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4396 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4397 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4398 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4399 (SQ_IND_INDEX__FORCE_READ_MASK) |
4400 (SQ_IND_INDEX__AUTO_INCR_MASK));
4402 *(out++) = RREG32(mmSQ_IND_DATA);
4405 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4407 /* type 0 wave data */
4408 dst[(*no_fields)++] = 0;
4409 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
4410 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
4411 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
4412 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
4413 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
4414 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
4415 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
4416 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
4417 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
4418 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
4419 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
4420 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
4421 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
4422 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
4423 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
4424 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
4425 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
4426 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
4429 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4430 uint32_t wave, uint32_t start,
4431 uint32_t size, uint32_t *dst)
4434 adev, simd, wave, 0,
4435 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4438 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4439 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4440 .select_se_sh = &gfx_v7_0_select_se_sh,
4441 .read_wave_data = &gfx_v7_0_read_wave_data,
4442 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4445 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4446 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4447 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode
4450 static int gfx_v7_0_early_init(void *handle)
4452 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4454 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4455 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
4456 adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
4457 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
4458 gfx_v7_0_set_ring_funcs(adev);
4459 gfx_v7_0_set_irq_funcs(adev);
4460 gfx_v7_0_set_gds_init(adev);
4465 static int gfx_v7_0_late_init(void *handle)
4467 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4470 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4474 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4481 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4484 u32 mc_shared_chmap, mc_arb_ramcfg;
4485 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4488 switch (adev->asic_type) {
4490 adev->gfx.config.max_shader_engines = 2;
4491 adev->gfx.config.max_tile_pipes = 4;
4492 adev->gfx.config.max_cu_per_sh = 7;
4493 adev->gfx.config.max_sh_per_se = 1;
4494 adev->gfx.config.max_backends_per_se = 2;
4495 adev->gfx.config.max_texture_channel_caches = 4;
4496 adev->gfx.config.max_gprs = 256;
4497 adev->gfx.config.max_gs_threads = 32;
4498 adev->gfx.config.max_hw_contexts = 8;
4500 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4501 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4502 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4503 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4504 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4507 adev->gfx.config.max_shader_engines = 4;
4508 adev->gfx.config.max_tile_pipes = 16;
4509 adev->gfx.config.max_cu_per_sh = 11;
4510 adev->gfx.config.max_sh_per_se = 1;
4511 adev->gfx.config.max_backends_per_se = 4;
4512 adev->gfx.config.max_texture_channel_caches = 16;
4513 adev->gfx.config.max_gprs = 256;
4514 adev->gfx.config.max_gs_threads = 32;
4515 adev->gfx.config.max_hw_contexts = 8;
4517 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4518 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4519 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4520 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4521 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4524 adev->gfx.config.max_shader_engines = 1;
4525 adev->gfx.config.max_tile_pipes = 4;
4526 if ((adev->pdev->device == 0x1304) ||
4527 (adev->pdev->device == 0x1305) ||
4528 (adev->pdev->device == 0x130C) ||
4529 (adev->pdev->device == 0x130F) ||
4530 (adev->pdev->device == 0x1310) ||
4531 (adev->pdev->device == 0x1311) ||
4532 (adev->pdev->device == 0x131C)) {
4533 adev->gfx.config.max_cu_per_sh = 8;
4534 adev->gfx.config.max_backends_per_se = 2;
4535 } else if ((adev->pdev->device == 0x1309) ||
4536 (adev->pdev->device == 0x130A) ||
4537 (adev->pdev->device == 0x130D) ||
4538 (adev->pdev->device == 0x1313) ||
4539 (adev->pdev->device == 0x131D)) {
4540 adev->gfx.config.max_cu_per_sh = 6;
4541 adev->gfx.config.max_backends_per_se = 2;
4542 } else if ((adev->pdev->device == 0x1306) ||
4543 (adev->pdev->device == 0x1307) ||
4544 (adev->pdev->device == 0x130B) ||
4545 (adev->pdev->device == 0x130E) ||
4546 (adev->pdev->device == 0x1315) ||
4547 (adev->pdev->device == 0x131B)) {
4548 adev->gfx.config.max_cu_per_sh = 4;
4549 adev->gfx.config.max_backends_per_se = 1;
4551 adev->gfx.config.max_cu_per_sh = 3;
4552 adev->gfx.config.max_backends_per_se = 1;
4554 adev->gfx.config.max_sh_per_se = 1;
4555 adev->gfx.config.max_texture_channel_caches = 4;
4556 adev->gfx.config.max_gprs = 256;
4557 adev->gfx.config.max_gs_threads = 16;
4558 adev->gfx.config.max_hw_contexts = 8;
4560 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4561 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4562 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4563 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4564 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4569 adev->gfx.config.max_shader_engines = 1;
4570 adev->gfx.config.max_tile_pipes = 2;
4571 adev->gfx.config.max_cu_per_sh = 2;
4572 adev->gfx.config.max_sh_per_se = 1;
4573 adev->gfx.config.max_backends_per_se = 1;
4574 adev->gfx.config.max_texture_channel_caches = 2;
4575 adev->gfx.config.max_gprs = 256;
4576 adev->gfx.config.max_gs_threads = 16;
4577 adev->gfx.config.max_hw_contexts = 8;
4579 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4580 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4581 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4582 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4583 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4587 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4588 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4589 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4591 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4592 adev->gfx.config.mem_max_burst_length_bytes = 256;
4593 if (adev->flags & AMD_IS_APU) {
4594 /* Get memory bank mapping mode. */
4595 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4596 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4597 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4599 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4600 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4601 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4603 /* Validate settings in case only one DIMM installed. */
4604 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4605 dimm00_addr_map = 0;
4606 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4607 dimm01_addr_map = 0;
4608 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4609 dimm10_addr_map = 0;
4610 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4611 dimm11_addr_map = 0;
4613 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4614 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4615 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4616 adev->gfx.config.mem_row_size_in_kb = 2;
4618 adev->gfx.config.mem_row_size_in_kb = 1;
4620 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4621 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4622 if (adev->gfx.config.mem_row_size_in_kb > 4)
4623 adev->gfx.config.mem_row_size_in_kb = 4;
4625 /* XXX use MC settings? */
4626 adev->gfx.config.shader_engine_tile_size = 32;
4627 adev->gfx.config.num_gpus = 1;
4628 adev->gfx.config.multi_gpu_tile_size = 64;
4630 /* fix up row size */
4631 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4632 switch (adev->gfx.config.mem_row_size_in_kb) {
4635 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4638 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4641 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4644 adev->gfx.config.gb_addr_config = gb_addr_config;
4647 static int gfx_v7_0_sw_init(void *handle)
4649 struct amdgpu_ring *ring;
4650 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4654 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4658 /* Privileged reg */
4659 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4663 /* Privileged inst */
4664 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4668 gfx_v7_0_scratch_init(adev);
4670 r = gfx_v7_0_init_microcode(adev);
4672 DRM_ERROR("Failed to load gfx firmware!\n");
4676 r = gfx_v7_0_rlc_init(adev);
4678 DRM_ERROR("Failed to init rlc BOs!\n");
4682 /* allocate mec buffers */
4683 r = gfx_v7_0_mec_init(adev);
4685 DRM_ERROR("Failed to init MEC BOs!\n");
4689 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4690 ring = &adev->gfx.gfx_ring[i];
4691 ring->ring_obj = NULL;
4692 sprintf(ring->name, "gfx");
4693 r = amdgpu_ring_init(adev, ring, 1024,
4694 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
4699 /* set up the compute queues */
4700 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4703 /* max 32 queues per MEC */
4704 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4705 DRM_ERROR("Too many (%d) compute rings!\n", i);
4708 ring = &adev->gfx.compute_ring[i];
4709 ring->ring_obj = NULL;
4710 ring->use_doorbell = true;
4711 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4712 ring->me = 1; /* first MEC */
4714 ring->queue = i % 8;
4715 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4716 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4717 /* type-2 packets are deprecated on MEC, use type-3 instead */
4718 r = amdgpu_ring_init(adev, ring, 1024,
4719 &adev->gfx.eop_irq, irq_type);
4724 /* reserve GDS, GWS and OA resource for gfx */
4725 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
4726 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
4727 &adev->gds.gds_gfx_bo, NULL, NULL);
4731 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
4732 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
4733 &adev->gds.gws_gfx_bo, NULL, NULL);
4737 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
4738 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
4739 &adev->gds.oa_gfx_bo, NULL, NULL);
4743 adev->gfx.ce_ram_size = 0x8000;
4745 gfx_v7_0_gpu_early_init(adev);
4750 static int gfx_v7_0_sw_fini(void *handle)
4753 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4755 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
4756 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
4757 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
4759 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4760 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4761 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4762 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4764 gfx_v7_0_cp_compute_fini(adev);
4765 gfx_v7_0_rlc_fini(adev);
4766 gfx_v7_0_mec_fini(adev);
4767 gfx_v7_0_free_microcode(adev);
4772 static int gfx_v7_0_hw_init(void *handle)
4775 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4777 gfx_v7_0_gpu_init(adev);
4780 r = gfx_v7_0_rlc_resume(adev);
4784 r = gfx_v7_0_cp_resume(adev);
4791 static int gfx_v7_0_hw_fini(void *handle)
4793 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4795 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4796 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4797 gfx_v7_0_cp_enable(adev, false);
4798 gfx_v7_0_rlc_stop(adev);
4799 gfx_v7_0_fini_pg(adev);
4804 static int gfx_v7_0_suspend(void *handle)
4806 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4808 return gfx_v7_0_hw_fini(adev);
4811 static int gfx_v7_0_resume(void *handle)
4813 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4815 return gfx_v7_0_hw_init(adev);
4818 static bool gfx_v7_0_is_idle(void *handle)
4820 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4822 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4828 static int gfx_v7_0_wait_for_idle(void *handle)
4832 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4834 for (i = 0; i < adev->usec_timeout; i++) {
4835 /* read MC_STATUS */
4836 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4845 static int gfx_v7_0_soft_reset(void *handle)
4847 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4849 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4852 tmp = RREG32(mmGRBM_STATUS);
4853 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4854 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4855 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4856 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4857 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4858 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4859 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4860 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4862 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4863 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4864 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4868 tmp = RREG32(mmGRBM_STATUS2);
4869 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4870 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4873 tmp = RREG32(mmSRBM_STATUS);
4874 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4875 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4877 if (grbm_soft_reset || srbm_soft_reset) {
4879 gfx_v7_0_fini_pg(adev);
4880 gfx_v7_0_update_cg(adev, false);
4883 gfx_v7_0_rlc_stop(adev);
4885 /* Disable GFX parsing/prefetching */
4886 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4888 /* Disable MEC parsing/prefetching */
4889 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4891 if (grbm_soft_reset) {
4892 tmp = RREG32(mmGRBM_SOFT_RESET);
4893 tmp |= grbm_soft_reset;
4894 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4895 WREG32(mmGRBM_SOFT_RESET, tmp);
4896 tmp = RREG32(mmGRBM_SOFT_RESET);
4900 tmp &= ~grbm_soft_reset;
4901 WREG32(mmGRBM_SOFT_RESET, tmp);
4902 tmp = RREG32(mmGRBM_SOFT_RESET);
4905 if (srbm_soft_reset) {
4906 tmp = RREG32(mmSRBM_SOFT_RESET);
4907 tmp |= srbm_soft_reset;
4908 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4909 WREG32(mmSRBM_SOFT_RESET, tmp);
4910 tmp = RREG32(mmSRBM_SOFT_RESET);
4914 tmp &= ~srbm_soft_reset;
4915 WREG32(mmSRBM_SOFT_RESET, tmp);
4916 tmp = RREG32(mmSRBM_SOFT_RESET);
4918 /* Wait a little for things to settle down */
4924 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4925 enum amdgpu_interrupt_state state)
4930 case AMDGPU_IRQ_STATE_DISABLE:
4931 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4932 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4933 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4935 case AMDGPU_IRQ_STATE_ENABLE:
4936 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4937 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4938 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4945 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4947 enum amdgpu_interrupt_state state)
4949 u32 mec_int_cntl, mec_int_cntl_reg;
4952 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4953 * handles the setting of interrupts for this specific pipe. All other
4954 * pipes' interrupts are set by amdkfd.
4960 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4963 DRM_DEBUG("invalid pipe %d\n", pipe);
4967 DRM_DEBUG("invalid me %d\n", me);
4972 case AMDGPU_IRQ_STATE_DISABLE:
4973 mec_int_cntl = RREG32(mec_int_cntl_reg);
4974 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4975 WREG32(mec_int_cntl_reg, mec_int_cntl);
4977 case AMDGPU_IRQ_STATE_ENABLE:
4978 mec_int_cntl = RREG32(mec_int_cntl_reg);
4979 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4980 WREG32(mec_int_cntl_reg, mec_int_cntl);
4987 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4988 struct amdgpu_irq_src *src,
4990 enum amdgpu_interrupt_state state)
4995 case AMDGPU_IRQ_STATE_DISABLE:
4996 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4997 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4998 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5000 case AMDGPU_IRQ_STATE_ENABLE:
5001 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5002 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
5003 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5012 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5013 struct amdgpu_irq_src *src,
5015 enum amdgpu_interrupt_state state)
5020 case AMDGPU_IRQ_STATE_DISABLE:
5021 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5022 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5023 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5025 case AMDGPU_IRQ_STATE_ENABLE:
5026 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5027 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5028 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5037 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5038 struct amdgpu_irq_src *src,
5040 enum amdgpu_interrupt_state state)
5043 case AMDGPU_CP_IRQ_GFX_EOP:
5044 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
5046 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5047 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5049 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5050 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5052 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5053 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5055 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5056 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5058 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5059 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5061 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5062 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5064 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5065 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5067 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5068 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5076 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
5077 struct amdgpu_irq_src *source,
5078 struct amdgpu_iv_entry *entry)
5081 struct amdgpu_ring *ring;
5084 DRM_DEBUG("IH: CP EOP\n");
5085 me_id = (entry->ring_id & 0x0c) >> 2;
5086 pipe_id = (entry->ring_id & 0x03) >> 0;
5089 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5093 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5094 ring = &adev->gfx.compute_ring[i];
5095 if ((ring->me == me_id) && (ring->pipe == pipe_id))
5096 amdgpu_fence_process(ring);
5103 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
5104 struct amdgpu_irq_src *source,
5105 struct amdgpu_iv_entry *entry)
5107 DRM_ERROR("Illegal register access in command stream\n");
5108 schedule_work(&adev->reset_work);
5112 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5113 struct amdgpu_irq_src *source,
5114 struct amdgpu_iv_entry *entry)
5116 DRM_ERROR("Illegal instruction in command stream\n");
5117 // XXX soft reset the gfx block only
5118 schedule_work(&adev->reset_work);
5122 static int gfx_v7_0_set_clockgating_state(void *handle,
5123 enum amd_clockgating_state state)
5126 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5128 if (state == AMD_CG_STATE_GATE)
5131 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
5132 /* order matters! */
5134 gfx_v7_0_enable_mgcg(adev, true);
5135 gfx_v7_0_enable_cgcg(adev, true);
5137 gfx_v7_0_enable_cgcg(adev, false);
5138 gfx_v7_0_enable_mgcg(adev, false);
5140 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5145 static int gfx_v7_0_set_powergating_state(void *handle,
5146 enum amd_powergating_state state)
5149 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5151 if (state == AMD_PG_STATE_GATE)
5154 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
5155 AMD_PG_SUPPORT_GFX_SMG |
5156 AMD_PG_SUPPORT_GFX_DMG |
5158 AMD_PG_SUPPORT_GDS |
5159 AMD_PG_SUPPORT_RLC_SMU_HS)) {
5160 gfx_v7_0_update_gfx_pg(adev, gate);
5161 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
5162 gfx_v7_0_enable_cp_pg(adev, gate);
5163 gfx_v7_0_enable_gds_pg(adev, gate);
5170 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5172 .early_init = gfx_v7_0_early_init,
5173 .late_init = gfx_v7_0_late_init,
5174 .sw_init = gfx_v7_0_sw_init,
5175 .sw_fini = gfx_v7_0_sw_fini,
5176 .hw_init = gfx_v7_0_hw_init,
5177 .hw_fini = gfx_v7_0_hw_fini,
5178 .suspend = gfx_v7_0_suspend,
5179 .resume = gfx_v7_0_resume,
5180 .is_idle = gfx_v7_0_is_idle,
5181 .wait_for_idle = gfx_v7_0_wait_for_idle,
5182 .soft_reset = gfx_v7_0_soft_reset,
5183 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5184 .set_powergating_state = gfx_v7_0_set_powergating_state,
5187 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5188 .type = AMDGPU_RING_TYPE_GFX,
5190 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5191 .get_rptr = gfx_v7_0_ring_get_rptr,
5192 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5193 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5195 20 + /* gfx_v7_0_ring_emit_gds_switch */
5196 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5197 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5198 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5199 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5200 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
5201 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5202 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
5203 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
5204 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
5205 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5206 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5207 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5208 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5209 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
5210 .test_ring = gfx_v7_0_ring_test_ring,
5211 .test_ib = gfx_v7_0_ring_test_ib,
5212 .insert_nop = amdgpu_ring_insert_nop,
5213 .pad_ib = amdgpu_ring_generic_pad_ib,
5214 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
5217 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5218 .type = AMDGPU_RING_TYPE_COMPUTE,
5220 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5221 .get_rptr = gfx_v7_0_ring_get_rptr,
5222 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5223 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5225 20 + /* gfx_v7_0_ring_emit_gds_switch */
5226 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5227 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5228 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
5229 17 + /* gfx_v7_0_ring_emit_vm_flush */
5230 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5231 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
5232 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
5233 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
5234 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5235 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5236 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5237 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5238 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
5239 .test_ring = gfx_v7_0_ring_test_ring,
5240 .test_ib = gfx_v7_0_ring_test_ib,
5241 .insert_nop = amdgpu_ring_insert_nop,
5242 .pad_ib = amdgpu_ring_generic_pad_ib,
5245 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5249 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5250 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5251 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5252 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5255 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5256 .set = gfx_v7_0_set_eop_interrupt_state,
5257 .process = gfx_v7_0_eop_irq,
5260 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5261 .set = gfx_v7_0_set_priv_reg_fault_state,
5262 .process = gfx_v7_0_priv_reg_irq,
5265 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5266 .set = gfx_v7_0_set_priv_inst_fault_state,
5267 .process = gfx_v7_0_priv_inst_irq,
5270 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5272 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5273 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5275 adev->gfx.priv_reg_irq.num_types = 1;
5276 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5278 adev->gfx.priv_inst_irq.num_types = 1;
5279 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5282 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5284 /* init asci gds info */
5285 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5286 adev->gds.gws.total_size = 64;
5287 adev->gds.oa.total_size = 16;
5289 if (adev->gds.mem.total_size == 64 * 1024) {
5290 adev->gds.mem.gfx_partition_size = 4096;
5291 adev->gds.mem.cs_partition_size = 4096;
5293 adev->gds.gws.gfx_partition_size = 4;
5294 adev->gds.gws.cs_partition_size = 4;
5296 adev->gds.oa.gfx_partition_size = 4;
5297 adev->gds.oa.cs_partition_size = 1;
5299 adev->gds.mem.gfx_partition_size = 1024;
5300 adev->gds.mem.cs_partition_size = 1024;
5302 adev->gds.gws.gfx_partition_size = 16;
5303 adev->gds.gws.cs_partition_size = 16;
5305 adev->gds.oa.gfx_partition_size = 4;
5306 adev->gds.oa.cs_partition_size = 4;
5311 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5313 int i, j, k, counter, active_cu_number = 0;
5314 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5315 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5316 unsigned disable_masks[4 * 2];
5318 memset(cu_info, 0, sizeof(*cu_info));
5320 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5322 mutex_lock(&adev->grbm_idx_mutex);
5323 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5324 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5328 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
5330 gfx_v7_0_set_user_cu_inactive_bitmap(
5331 adev, disable_masks[i * 2 + j]);
5332 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5333 cu_info->bitmap[i][j] = bitmap;
5335 for (k = 0; k < 16; k ++) {
5336 if (bitmap & mask) {
5343 active_cu_number += counter;
5344 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5347 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5348 mutex_unlock(&adev->grbm_idx_mutex);
5350 cu_info->number = active_cu_number;
5351 cu_info->ao_cu_mask = ao_cu_mask;
5354 const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
5356 .type = AMD_IP_BLOCK_TYPE_GFX,
5360 .funcs = &gfx_v7_0_ip_funcs,
5363 const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
5365 .type = AMD_IP_BLOCK_TYPE_GFX,
5369 .funcs = &gfx_v7_0_ip_funcs,
5372 const struct amdgpu_ip_block_version gfx_v7_2_ip_block =
5374 .type = AMD_IP_BLOCK_TYPE_GFX,
5378 .funcs = &gfx_v7_0_ip_funcs,
5381 const struct amdgpu_ip_block_version gfx_v7_3_ip_block =
5383 .type = AMD_IP_BLOCK_TYPE_GFX,
5387 .funcs = &gfx_v7_0_ip_funcs,
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