drivers/gpu/drm/ast/ast_post.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  16  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  17  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  18  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * The above copyright notice and this permission notice (including the
  21  * next paragraph) shall be included in all copies or substantial portions
  22  * of the Software.
  23  *
  24  */
  25 /*
  26  * Authors: Dave Airlie <[email protected]>
  27  */
  28
  29 #include <linux/delay.h>
  30 #include <linux/pci.h>
  31
  32 #include <drm/drm_print.h>
  33
  34 #include "ast_dram_tables.h"
  35 #include "ast_drv.h"
  36
  37 static void ast_post_chip_2300(struct drm_device *dev);
  38 static void ast_post_chip_2500(struct drm_device *dev);
  39
  40 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
  41 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
  42
  43 static void
  44 ast_set_def_ext_reg(struct drm_device *dev)
  45 {
  46         struct ast_device *ast = to_ast_device(dev);
  47         u8 i, index, reg;
  48         const u8 *ext_reg_info;
  49
  50         /* reset scratch */
  51         for (i = 0x81; i <= 0x9f; i++)
  52                 ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
  53
  54         if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
  55                 ext_reg_info = extreginfo_ast2300;
  56         else
  57                 ext_reg_info = extreginfo;
  58
  59         index = 0xa0;
  60         while (*ext_reg_info != 0xff) {
  61                 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
  62                 index++;
  63                 ext_reg_info++;
  64         }
  65
  66         /* disable standard IO/MEM decode if secondary */
  67         /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
  68
  69         /* Set Ext. Default */
  70         ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
  71         ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
  72
  73         /* Enable RAMDAC for A1 */
  74         reg = 0x04;
  75         if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
  76                 reg |= 0x20;
  77         ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
  78 }
  79
  80 u32 ast_mindwm(struct ast_device *ast, u32 r)
  81 {
  82         uint32_t data;
  83
  84         ast_write32(ast, 0xf004, r & 0xffff0000);
  85         ast_write32(ast, 0xf000, 0x1);
  86
  87         do {
  88                 data = ast_read32(ast, 0xf004) & 0xffff0000;
  89         } while (data != (r & 0xffff0000));
  90         return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
  91 }
  92
  93 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v)
  94 {
  95         uint32_t data;
  96         ast_write32(ast, 0xf004, r & 0xffff0000);
  97         ast_write32(ast, 0xf000, 0x1);
  98         do {
  99                 data = ast_read32(ast, 0xf004) & 0xffff0000;
 100         } while (data != (r & 0xffff0000));
 101         ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
 102 }
 103
 104 /*
 105  * AST2100/2150 DLL CBR Setting
 106  */
 107 #define CBR_SIZE_AST2150             ((16 << 10) - 1)
 108 #define CBR_PASSNUM_AST2150          5
 109 #define CBR_THRESHOLD_AST2150        10
 110 #define CBR_THRESHOLD2_AST2150       10
 111 #define TIMEOUT_AST2150              5000000
 112
 113 #define CBR_PATNUM_AST2150           8
 114
 115 static const u32 pattern_AST2150[14] = {
 116         0xFF00FF00,
 117         0xCC33CC33,
 118         0xAA55AA55,
 119         0xFFFE0001,
 120         0x683501FE,
 121         0x0F1929B0,
 122         0x2D0B4346,
 123         0x60767F02,
 124         0x6FBE36A6,
 125         0x3A253035,
 126         0x3019686D,
 127         0x41C6167E,
 128         0x620152BF,
 129         0x20F050E0
 130 };
 131
 132 static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen)
 133 {
 134         u32 data, timeout;
 135
 136         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 137         ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
 138         timeout = 0;
 139         do {
 140                 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
 141                 if (++timeout > TIMEOUT_AST2150) {
 142                         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 143                         return 0xffffffff;
 144                 }
 145         } while (!data);
 146         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 147         ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
 148         timeout = 0;
 149         do {
 150                 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
 151                 if (++timeout > TIMEOUT_AST2150) {
 152                         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 153                         return 0xffffffff;
 154                 }
 155         } while (!data);
 156         data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
 157         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 158         return data;
 159 }
 160
 161 #if 0 /* unused in DDX driver - here for completeness */
 162 static u32 mmctestsingle2_ast2150(struct ast_device *ast, u32 datagen)
 163 {
 164         u32 data, timeout;
 165
 166         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 167         ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
 168         timeout = 0;
 169         do {
 170                 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
 171                 if (++timeout > TIMEOUT_AST2150) {
 172                         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 173                         return 0xffffffff;
 174                 }
 175         } while (!data);
 176         data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
 177         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 178         return data;
 179 }
 180 #endif
 181
 182 static int cbrtest_ast2150(struct ast_device *ast)
 183 {
 184         int i;
 185
 186         for (i = 0; i < 8; i++)
 187                 if (mmctestburst2_ast2150(ast, i))
 188                         return 0;
 189         return 1;
 190 }
 191
 192 static int cbrscan_ast2150(struct ast_device *ast, int busw)
 193 {
 194         u32 patcnt, loop;
 195
 196         for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
 197                 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
 198                 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
 199                         if (cbrtest_ast2150(ast))
 200                                 break;
 201                 }
 202                 if (loop == CBR_PASSNUM_AST2150)
 203                         return 0;
 204         }
 205         return 1;
 206 }
 207
 208
 209 static void cbrdlli_ast2150(struct ast_device *ast, int busw)
 210 {
 211         u32 dll_min[4], dll_max[4], dlli, data, passcnt;
 212
 213 cbr_start:
 214         dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff;
 215         dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0;
 216         passcnt = 0;
 217
 218         for (dlli = 0; dlli < 100; dlli++) {
 219                 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
 220                 data = cbrscan_ast2150(ast, busw);
 221                 if (data != 0) {
 222                         if (data & 0x1) {
 223                                 if (dll_min[0] > dlli)
 224                                         dll_min[0] = dlli;
 225                                 if (dll_max[0] < dlli)
 226                                         dll_max[0] = dlli;
 227                         }
 228                         passcnt++;
 229                 } else if (passcnt >= CBR_THRESHOLD_AST2150)
 230                         goto cbr_start;
 231         }
 232         if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
 233                 goto cbr_start;
 234
 235         dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
 236         ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
 237 }
 238
 239
 240
 241 static void ast_init_dram_reg(struct drm_device *dev)
 242 {
 243         struct ast_device *ast = to_ast_device(dev);
 244         u8 j;
 245         u32 data, temp, i;
 246         const struct ast_dramstruct *dram_reg_info;
 247
 248         j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
 249
 250         if ((j & 0x80) == 0) { /* VGA only */
 251                 if (IS_AST_GEN1(ast)) {
 252                         dram_reg_info = ast2000_dram_table_data;
 253                         ast_write32(ast, 0xf004, 0x1e6e0000);
 254                         ast_write32(ast, 0xf000, 0x1);
 255                         ast_write32(ast, 0x10100, 0xa8);
 256
 257                         do {
 258                                 ;
 259                         } while (ast_read32(ast, 0x10100) != 0xa8);
 260                 } else { /* GEN2/GEN3 */
 261                         if (ast->chip == AST2100 || ast->chip == AST2200)
 262                                 dram_reg_info = ast2100_dram_table_data;
 263                         else
 264                                 dram_reg_info = ast1100_dram_table_data;
 265
 266                         ast_write32(ast, 0xf004, 0x1e6e0000);
 267                         ast_write32(ast, 0xf000, 0x1);
 268                         ast_write32(ast, 0x12000, 0x1688A8A8);
 269                         do {
 270                                 ;
 271                         } while (ast_read32(ast, 0x12000) != 0x01);
 272
 273                         ast_write32(ast, 0x10000, 0xfc600309);
 274                         do {
 275                                 ;
 276                         } while (ast_read32(ast, 0x10000) != 0x01);
 277                 }
 278
 279                 while (dram_reg_info->index != 0xffff) {
 280                         if (dram_reg_info->index == 0xff00) {/* delay fn */
 281                                 for (i = 0; i < 15; i++)
 282                                         udelay(dram_reg_info->data);
 283                         } else if (dram_reg_info->index == 0x4 && !IS_AST_GEN1(ast)) {
 284                                 data = dram_reg_info->data;
 285                                 if (ast->dram_type == AST_DRAM_1Gx16)
 286                                         data = 0x00000d89;
 287                                 else if (ast->dram_type == AST_DRAM_1Gx32)
 288                                         data = 0x00000c8d;
 289
 290                                 temp = ast_read32(ast, 0x12070);
 291                                 temp &= 0xc;
 292                                 temp <<= 2;
 293                                 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
 294                         } else
 295                                 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
 296                         dram_reg_info++;
 297                 }
 298
 299                 /* AST 2100/2150 DRAM calibration */
 300                 data = ast_read32(ast, 0x10120);
 301                 if (data == 0x5061) { /* 266Mhz */
 302                         data = ast_read32(ast, 0x10004);
 303                         if (data & 0x40)
 304                                 cbrdlli_ast2150(ast, 16); /* 16 bits */
 305                         else
 306                                 cbrdlli_ast2150(ast, 32); /* 32 bits */
 307                 }
 308
 309                 switch (AST_GEN(ast)) {
 310                 case 1:
 311                         temp = ast_read32(ast, 0x10140);
 312                         ast_write32(ast, 0x10140, temp | 0x40);
 313                         break;
 314                 case 2:
 315                 case 3:
 316                         temp = ast_read32(ast, 0x1200c);
 317                         ast_write32(ast, 0x1200c, temp & 0xfffffffd);
 318                         temp = ast_read32(ast, 0x12040);
 319                         ast_write32(ast, 0x12040, temp | 0x40);
 320                         break;
 321                 default:
 322                         break;
 323                 }
 324         }
 325
 326         /* wait ready */
 327         do {
 328                 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
 329         } while ((j & 0x40) == 0);
 330 }
 331
 332 void ast_post_gpu(struct drm_device *dev)
 333 {
 334         struct ast_device *ast = to_ast_device(dev);
 335
 336         ast_set_def_ext_reg(dev);
 337
 338         if (IS_AST_GEN7(ast)) {
 339                 if (ast->tx_chip_types & AST_TX_ASTDP_BIT)
 340                         ast_dp_launch(dev);
 341         } else if (ast->config_mode == ast_use_p2a) {
 342                 if (IS_AST_GEN6(ast))
 343                         ast_post_chip_2500(dev);
 344                 else if (IS_AST_GEN5(ast) || IS_AST_GEN4(ast))
 345                         ast_post_chip_2300(dev);
 346                 else
 347                         ast_init_dram_reg(dev);
 348
 349                 ast_init_3rdtx(dev);
 350         } else {
 351                 if (ast->tx_chip_types & AST_TX_SIL164_BIT)
 352                         ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);   /* Enable DVO */
 353         }
 354 }
 355
 356 /* AST 2300 DRAM settings */
 357 #define AST_DDR3 0
 358 #define AST_DDR2 1
 359
 360 struct ast2300_dram_param {
 361         u32 dram_type;
 362         u32 dram_chipid;
 363         u32 dram_freq;
 364         u32 vram_size;
 365         u32 odt;
 366         u32 wodt;
 367         u32 rodt;
 368         u32 dram_config;
 369         u32 reg_PERIOD;
 370         u32 reg_MADJ;
 371         u32 reg_SADJ;
 372         u32 reg_MRS;
 373         u32 reg_EMRS;
 374         u32 reg_AC1;
 375         u32 reg_AC2;
 376         u32 reg_DQSIC;
 377         u32 reg_DRV;
 378         u32 reg_IOZ;
 379         u32 reg_DQIDLY;
 380         u32 reg_FREQ;
 381         u32 madj_max;
 382         u32 dll2_finetune_step;
 383 };
 384
 385 /*
 386  * DQSI DLL CBR Setting
 387  */
 388 #define CBR_SIZE0            ((1  << 10) - 1)
 389 #define CBR_SIZE1            ((4  << 10) - 1)
 390 #define CBR_SIZE2            ((64 << 10) - 1)
 391 #define CBR_PASSNUM          5
 392 #define CBR_PASSNUM2         5
 393 #define CBR_THRESHOLD        10
 394 #define CBR_THRESHOLD2       10
 395 #define TIMEOUT              5000000
 396 #define CBR_PATNUM           8
 397
 398 static const u32 pattern[8] = {
 399         0xFF00FF00,
 400         0xCC33CC33,
 401         0xAA55AA55,
 402         0x88778877,
 403         0x92CC4D6E,
 404         0x543D3CDE,
 405         0xF1E843C7,
 406         0x7C61D253
 407 };
 408
 409 static bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl)
 410 {
 411         u32 data, timeout;
 412
 413         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 414         ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
 415         timeout = 0;
 416         do {
 417                 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
 418                 if (data & 0x2000)
 419                         return false;
 420                 if (++timeout > TIMEOUT) {
 421                         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 422                         return false;
 423                 }
 424         } while (!data);
 425         ast_moutdwm(ast, 0x1e6e0070, 0x0);
 426         return true;
 427 }
 428
 429 static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl)
 430 {
 431         u32 data, timeout;
 432
 433         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 434         ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
 435         timeout = 0;
 436         do {
 437                 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
 438                 if (++timeout > TIMEOUT) {
 439                         ast_moutdwm(ast, 0x1e6e0070, 0x0);
 440                         return 0xffffffff;
 441                 }
 442         } while (!data);
 443         data = ast_mindwm(ast, 0x1e6e0078);
 444         data = (data | (data >> 16)) & 0xffff;
 445         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 446         return data;
 447 }
 448
 449
 450 static bool mmc_test_burst(struct ast_device *ast, u32 datagen)
 451 {
 452         return mmc_test(ast, datagen, 0xc1);
 453 }
 454
 455 static u32 mmc_test_burst2(struct ast_device *ast, u32 datagen)
 456 {
 457         return mmc_test2(ast, datagen, 0x41);
 458 }
 459
 460 static bool mmc_test_single(struct ast_device *ast, u32 datagen)
 461 {
 462         return mmc_test(ast, datagen, 0xc5);
 463 }
 464
 465 static u32 mmc_test_single2(struct ast_device *ast, u32 datagen)
 466 {
 467         return mmc_test2(ast, datagen, 0x05);
 468 }
 469
 470 static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen)
 471 {
 472         return mmc_test(ast, datagen, 0x85);
 473 }
 474
 475 static int cbr_test(struct ast_device *ast)
 476 {
 477         u32 data;
 478         int i;
 479         data = mmc_test_single2(ast, 0);
 480         if ((data & 0xff) && (data & 0xff00))
 481                 return 0;
 482         for (i = 0; i < 8; i++) {
 483                 data = mmc_test_burst2(ast, i);
 484                 if ((data & 0xff) && (data & 0xff00))
 485                         return 0;
 486         }
 487         if (!data)
 488                 return 3;
 489         else if (data & 0xff)
 490                 return 2;
 491         return 1;
 492 }
 493
 494 static int cbr_scan(struct ast_device *ast)
 495 {
 496         u32 data, data2, patcnt, loop;
 497
 498         data2 = 3;
 499         for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
 500                 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
 501                 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
 502                         if ((data = cbr_test(ast)) != 0) {
 503                                 data2 &= data;
 504                                 if (!data2)
 505                                         return 0;
 506                                 break;
 507                         }
 508                 }
 509                 if (loop == CBR_PASSNUM2)
 510                         return 0;
 511         }
 512         return data2;
 513 }
 514
 515 static u32 cbr_test2(struct ast_device *ast)
 516 {
 517         u32 data;
 518
 519         data = mmc_test_burst2(ast, 0);
 520         if (data == 0xffff)
 521                 return 0;
 522         data |= mmc_test_single2(ast, 0);
 523         if (data == 0xffff)
 524                 return 0;
 525
 526         return ~data & 0xffff;
 527 }
 528
 529 static u32 cbr_scan2(struct ast_device *ast)
 530 {
 531         u32 data, data2, patcnt, loop;
 532
 533         data2 = 0xffff;
 534         for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
 535                 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
 536                 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
 537                         if ((data = cbr_test2(ast)) != 0) {
 538                                 data2 &= data;
 539                                 if (!data2)
 540                                         return 0;
 541                                 break;
 542                         }
 543                 }
 544                 if (loop == CBR_PASSNUM2)
 545                         return 0;
 546         }
 547         return data2;
 548 }
 549
 550 static bool cbr_test3(struct ast_device *ast)
 551 {
 552         if (!mmc_test_burst(ast, 0))
 553                 return false;
 554         if (!mmc_test_single(ast, 0))
 555                 return false;
 556         return true;
 557 }
 558
 559 static bool cbr_scan3(struct ast_device *ast)
 560 {
 561         u32 patcnt, loop;
 562
 563         for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
 564                 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
 565                 for (loop = 0; loop < 2; loop++) {
 566                         if (cbr_test3(ast))
 567                                 break;
 568                 }
 569                 if (loop == 2)
 570                         return false;
 571         }
 572         return true;
 573 }
 574
 575 static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param)
 576 {
 577         u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
 578         bool status = false;
 579 FINETUNE_START:
 580         for (cnt = 0; cnt < 16; cnt++) {
 581                 dllmin[cnt] = 0xff;
 582                 dllmax[cnt] = 0x0;
 583         }
 584         passcnt = 0;
 585         for (dlli = 0; dlli < 76; dlli++) {
 586                 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
 587                 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
 588                 data = cbr_scan2(ast);
 589                 if (data != 0) {
 590                         mask = 0x00010001;
 591                         for (cnt = 0; cnt < 16; cnt++) {
 592                                 if (data & mask) {
 593                                         if (dllmin[cnt] > dlli) {
 594                                                 dllmin[cnt] = dlli;
 595                                         }
 596                                         if (dllmax[cnt] < dlli) {
 597                                                 dllmax[cnt] = dlli;
 598                                         }
 599                                 }
 600                                 mask <<= 1;
 601                         }
 602                         passcnt++;
 603                 } else if (passcnt >= CBR_THRESHOLD2) {
 604                         break;
 605                 }
 606         }
 607         gold_sadj[0] = 0x0;
 608         passcnt = 0;
 609         for (cnt = 0; cnt < 16; cnt++) {
 610                 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
 611                         gold_sadj[0] += dllmin[cnt];
 612                         passcnt++;
 613                 }
 614         }
 615         if (retry++ > 10)
 616                 goto FINETUNE_DONE;
 617         if (passcnt != 16) {
 618                 goto FINETUNE_START;
 619         }
 620         status = true;
 621 FINETUNE_DONE:
 622         gold_sadj[0] = gold_sadj[0] >> 4;
 623         gold_sadj[1] = gold_sadj[0];
 624
 625         data = 0;
 626         for (cnt = 0; cnt < 8; cnt++) {
 627                 data >>= 3;
 628                 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
 629                         dlli = dllmin[cnt];
 630                         if (gold_sadj[0] >= dlli) {
 631                                 dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
 632                                 if (dlli > 3) {
 633                                         dlli = 3;
 634                                 }
 635                         } else {
 636                                 dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
 637                                 if (dlli > 4) {
 638                                         dlli = 4;
 639                                 }
 640                                 dlli = (8 - dlli) & 0x7;
 641                         }
 642                         data |= dlli << 21;
 643                 }
 644         }
 645         ast_moutdwm(ast, 0x1E6E0080, data);
 646
 647         data = 0;
 648         for (cnt = 8; cnt < 16; cnt++) {
 649                 data >>= 3;
 650                 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
 651                         dlli = dllmin[cnt];
 652                         if (gold_sadj[1] >= dlli) {
 653                                 dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
 654                                 if (dlli > 3) {
 655                                         dlli = 3;
 656                                 } else {
 657                                         dlli = (dlli - 1) & 0x7;
 658                                 }
 659                         } else {
 660                                 dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
 661                                 dlli += 1;
 662                                 if (dlli > 4) {
 663                                         dlli = 4;
 664                                 }
 665                                 dlli = (8 - dlli) & 0x7;
 666                         }
 667                         data |= dlli << 21;
 668                 }
 669         }
 670         ast_moutdwm(ast, 0x1E6E0084, data);
 671         return status;
 672 } /* finetuneDQI_L */
 673
 674 static void finetuneDQSI(struct ast_device *ast)
 675 {
 676         u32 dlli, dqsip, dqidly;
 677         u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
 678         u32 g_dqidly, g_dqsip, g_margin, g_side;
 679         u16 pass[32][2][2];
 680         char tag[2][76];
 681
 682         /* Disable DQI CBR */
 683         reg_mcr0c  = ast_mindwm(ast, 0x1E6E000C);
 684         reg_mcr18  = ast_mindwm(ast, 0x1E6E0018);
 685         reg_mcr18 &= 0x0000ffff;
 686         ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
 687
 688         for (dlli = 0; dlli < 76; dlli++) {
 689                 tag[0][dlli] = 0x0;
 690                 tag[1][dlli] = 0x0;
 691         }
 692         for (dqidly = 0; dqidly < 32; dqidly++) {
 693                 pass[dqidly][0][0] = 0xff;
 694                 pass[dqidly][0][1] = 0x0;
 695                 pass[dqidly][1][0] = 0xff;
 696                 pass[dqidly][1][1] = 0x0;
 697         }
 698         for (dqidly = 0; dqidly < 32; dqidly++) {
 699                 passcnt[0] = passcnt[1] = 0;
 700                 for (dqsip = 0; dqsip < 2; dqsip++) {
 701                         ast_moutdwm(ast, 0x1E6E000C, 0);
 702                         ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
 703                         ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
 704                         for (dlli = 0; dlli < 76; dlli++) {
 705                                 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
 706                                 ast_moutdwm(ast, 0x1E6E0070, 0);
 707                                 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
 708                                 if (cbr_scan3(ast)) {
 709                                         if (dlli == 0)
 710                                                 break;
 711                                         passcnt[dqsip]++;
 712                                         tag[dqsip][dlli] = 'P';
 713                                         if (dlli < pass[dqidly][dqsip][0])
 714                                                 pass[dqidly][dqsip][0] = (u16) dlli;
 715                                         if (dlli > pass[dqidly][dqsip][1])
 716                                                 pass[dqidly][dqsip][1] = (u16) dlli;
 717                                 } else if (passcnt[dqsip] >= 5)
 718                                         break;
 719                                 else {
 720                                         pass[dqidly][dqsip][0] = 0xff;
 721                                         pass[dqidly][dqsip][1] = 0x0;
 722                                 }
 723                         }
 724                 }
 725                 if (passcnt[0] == 0 && passcnt[1] == 0)
 726                         dqidly++;
 727         }
 728         /* Search margin */
 729         g_dqidly = g_dqsip = g_margin = g_side = 0;
 730
 731         for (dqidly = 0; dqidly < 32; dqidly++) {
 732                 for (dqsip = 0; dqsip < 2; dqsip++) {
 733                         if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
 734                                 continue;
 735                         diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
 736                         if ((diff+2) < g_margin)
 737                                 continue;
 738                         passcnt[0] = passcnt[1] = 0;
 739                         for (dlli = pass[dqidly][dqsip][0]; dlli > 0  && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
 740                         for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
 741                         if (passcnt[0] > passcnt[1])
 742                                 passcnt[0] = passcnt[1];
 743                         passcnt[1] = 0;
 744                         if (passcnt[0] > g_side)
 745                                 passcnt[1] = passcnt[0] - g_side;
 746                         if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
 747                                 g_margin = diff;
 748                                 g_dqidly = dqidly;
 749                                 g_dqsip  = dqsip;
 750                                 g_side   = passcnt[0];
 751                         } else if (passcnt[1] > 1 && g_side < 8) {
 752                                 if (diff > g_margin)
 753                                         g_margin = diff;
 754                                 g_dqidly = dqidly;
 755                                 g_dqsip  = dqsip;
 756                                 g_side   = passcnt[0];
 757                         }
 758                 }
 759         }
 760         reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
 761         ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
 762
 763 }
 764 static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param)
 765 {
 766         u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
 767         bool status = false;
 768
 769         finetuneDQSI(ast);
 770         if (finetuneDQI_L(ast, param) == false)
 771                 return status;
 772
 773 CBR_START2:
 774         dllmin[0] = dllmin[1] = 0xff;
 775         dllmax[0] = dllmax[1] = 0x0;
 776         passcnt = 0;
 777         for (dlli = 0; dlli < 76; dlli++) {
 778                 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
 779                 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
 780                 data = cbr_scan(ast);
 781                 if (data != 0) {
 782                         if (data & 0x1) {
 783                                 if (dllmin[0] > dlli) {
 784                                         dllmin[0] = dlli;
 785                                 }
 786                                 if (dllmax[0] < dlli) {
 787                                         dllmax[0] = dlli;
 788                                 }
 789                         }
 790                         if (data & 0x2) {
 791                                 if (dllmin[1] > dlli) {
 792                                         dllmin[1] = dlli;
 793                                 }
 794                                 if (dllmax[1] < dlli) {
 795                                         dllmax[1] = dlli;
 796                                 }
 797                         }
 798                         passcnt++;
 799                 } else if (passcnt >= CBR_THRESHOLD) {
 800                         break;
 801                 }
 802         }
 803         if (retry++ > 10)
 804                 goto CBR_DONE2;
 805         if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
 806                 goto CBR_START2;
 807         }
 808         if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
 809                 goto CBR_START2;
 810         }
 811         status = true;
 812 CBR_DONE2:
 813         dlli  = (dllmin[1] + dllmax[1]) >> 1;
 814         dlli <<= 8;
 815         dlli += (dllmin[0] + dllmax[0]) >> 1;
 816         ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
 817         return status;
 818 } /* CBRDLL2 */
 819
 820 static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param)
 821 {
 822         u32 trap, trap_AC2, trap_MRS;
 823
 824         ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
 825
 826         /* Ger trap info */
 827         trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
 828         trap_AC2  = 0x00020000 + (trap << 16);
 829         trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
 830         trap_MRS  = 0x00000010 + (trap << 4);
 831         trap_MRS |= ((trap & 0x2) << 18);
 832
 833         param->reg_MADJ       = 0x00034C4C;
 834         param->reg_SADJ       = 0x00001800;
 835         param->reg_DRV        = 0x000000F0;
 836         param->reg_PERIOD     = param->dram_freq;
 837         param->rodt           = 0;
 838
 839         switch (param->dram_freq) {
 840         case 336:
 841                 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
 842                 param->wodt          = 0;
 843                 param->reg_AC1       = 0x22202725;
 844                 param->reg_AC2       = 0xAA007613 | trap_AC2;
 845                 param->reg_DQSIC     = 0x000000BA;
 846                 param->reg_MRS       = 0x04001400 | trap_MRS;
 847                 param->reg_EMRS      = 0x00000000;
 848                 param->reg_IOZ       = 0x00000023;
 849                 param->reg_DQIDLY    = 0x00000074;
 850                 param->reg_FREQ      = 0x00004DC0;
 851                 param->madj_max      = 96;
 852                 param->dll2_finetune_step = 3;
 853                 switch (param->dram_chipid) {
 854                 default:
 855                 case AST_DRAM_512Mx16:
 856                 case AST_DRAM_1Gx16:
 857                         param->reg_AC2   = 0xAA007613 | trap_AC2;
 858                         break;
 859                 case AST_DRAM_2Gx16:
 860                         param->reg_AC2   = 0xAA00761C | trap_AC2;
 861                         break;
 862                 case AST_DRAM_4Gx16:
 863                         param->reg_AC2   = 0xAA007636 | trap_AC2;
 864                         break;
 865                 }
 866                 break;
 867         default:
 868         case 396:
 869                 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
 870                 param->wodt          = 1;
 871                 param->reg_AC1       = 0x33302825;
 872                 param->reg_AC2       = 0xCC009617 | trap_AC2;
 873                 param->reg_DQSIC     = 0x000000E2;
 874                 param->reg_MRS       = 0x04001600 | trap_MRS;
 875                 param->reg_EMRS      = 0x00000000;
 876                 param->reg_IOZ       = 0x00000034;
 877                 param->reg_DRV       = 0x000000FA;
 878                 param->reg_DQIDLY    = 0x00000089;
 879                 param->reg_FREQ      = 0x00005040;
 880                 param->madj_max      = 96;
 881                 param->dll2_finetune_step = 4;
 882
 883                 switch (param->dram_chipid) {
 884                 default:
 885                 case AST_DRAM_512Mx16:
 886                 case AST_DRAM_1Gx16:
 887                         param->reg_AC2   = 0xCC009617 | trap_AC2;
 888                         break;
 889                 case AST_DRAM_2Gx16:
 890                         param->reg_AC2   = 0xCC009622 | trap_AC2;
 891                         break;
 892                 case AST_DRAM_4Gx16:
 893                         param->reg_AC2   = 0xCC00963F | trap_AC2;
 894                         break;
 895                 }
 896                 break;
 897
 898         case 408:
 899                 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
 900                 param->wodt          = 1;
 901                 param->reg_AC1       = 0x33302825;
 902                 param->reg_AC2       = 0xCC009617 | trap_AC2;
 903                 param->reg_DQSIC     = 0x000000E2;
 904                 param->reg_MRS       = 0x04001600 | trap_MRS;
 905                 param->reg_EMRS      = 0x00000000;
 906                 param->reg_IOZ       = 0x00000023;
 907                 param->reg_DRV       = 0x000000FA;
 908                 param->reg_DQIDLY    = 0x00000089;
 909                 param->reg_FREQ      = 0x000050C0;
 910                 param->madj_max      = 96;
 911                 param->dll2_finetune_step = 4;
 912
 913                 switch (param->dram_chipid) {
 914                 default:
 915                 case AST_DRAM_512Mx16:
 916                 case AST_DRAM_1Gx16:
 917                         param->reg_AC2   = 0xCC009617 | trap_AC2;
 918                         break;
 919                 case AST_DRAM_2Gx16:
 920                         param->reg_AC2   = 0xCC009622 | trap_AC2;
 921                         break;
 922                 case AST_DRAM_4Gx16:
 923                         param->reg_AC2   = 0xCC00963F | trap_AC2;
 924                         break;
 925                 }
 926
 927                 break;
 928         case 456:
 929                 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
 930                 param->wodt          = 0;
 931                 param->reg_AC1       = 0x33302926;
 932                 param->reg_AC2       = 0xCD44961A;
 933                 param->reg_DQSIC     = 0x000000FC;
 934                 param->reg_MRS       = 0x00081830;
 935                 param->reg_EMRS      = 0x00000000;
 936                 param->reg_IOZ       = 0x00000045;
 937                 param->reg_DQIDLY    = 0x00000097;
 938                 param->reg_FREQ      = 0x000052C0;
 939                 param->madj_max      = 88;
 940                 param->dll2_finetune_step = 4;
 941                 break;
 942         case 504:
 943                 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
 944                 param->wodt          = 1;
 945                 param->reg_AC1       = 0x33302926;
 946                 param->reg_AC2       = 0xDE44A61D;
 947                 param->reg_DQSIC     = 0x00000117;
 948                 param->reg_MRS       = 0x00081A30;
 949                 param->reg_EMRS      = 0x00000000;
 950                 param->reg_IOZ       = 0x070000BB;
 951                 param->reg_DQIDLY    = 0x000000A0;
 952                 param->reg_FREQ      = 0x000054C0;
 953                 param->madj_max      = 79;
 954                 param->dll2_finetune_step = 4;
 955                 break;
 956         case 528:
 957                 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
 958                 param->wodt          = 1;
 959                 param->rodt          = 1;
 960                 param->reg_AC1       = 0x33302926;
 961                 param->reg_AC2       = 0xEF44B61E;
 962                 param->reg_DQSIC     = 0x00000125;
 963                 param->reg_MRS       = 0x00081A30;
 964                 param->reg_EMRS      = 0x00000040;
 965                 param->reg_DRV       = 0x000000F5;
 966                 param->reg_IOZ       = 0x00000023;
 967                 param->reg_DQIDLY    = 0x00000088;
 968                 param->reg_FREQ      = 0x000055C0;
 969                 param->madj_max      = 76;
 970                 param->dll2_finetune_step = 3;
 971                 break;
 972         case 576:
 973                 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
 974                 param->reg_MADJ      = 0x00136868;
 975                 param->reg_SADJ      = 0x00004534;
 976                 param->wodt          = 1;
 977                 param->rodt          = 1;
 978                 param->reg_AC1       = 0x33302A37;
 979                 param->reg_AC2       = 0xEF56B61E;
 980                 param->reg_DQSIC     = 0x0000013F;
 981                 param->reg_MRS       = 0x00101A50;
 982                 param->reg_EMRS      = 0x00000040;
 983                 param->reg_DRV       = 0x000000FA;
 984                 param->reg_IOZ       = 0x00000023;
 985                 param->reg_DQIDLY    = 0x00000078;
 986                 param->reg_FREQ      = 0x000057C0;
 987                 param->madj_max      = 136;
 988                 param->dll2_finetune_step = 3;
 989                 break;
 990         case 600:
 991                 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
 992                 param->reg_MADJ      = 0x00136868;
 993                 param->reg_SADJ      = 0x00004534;
 994                 param->wodt          = 1;
 995                 param->rodt          = 1;
 996                 param->reg_AC1       = 0x32302A37;
 997                 param->reg_AC2       = 0xDF56B61F;
 998                 param->reg_DQSIC     = 0x0000014D;
 999                 param->reg_MRS       = 0x00101A50;
1000                 param->reg_EMRS      = 0x00000004;
1001                 param->reg_DRV       = 0x000000F5;
1002                 param->reg_IOZ       = 0x00000023;
1003                 param->reg_DQIDLY    = 0x00000078;
1004                 param->reg_FREQ      = 0x000058C0;
1005                 param->madj_max      = 132;
1006                 param->dll2_finetune_step = 3;
1007                 break;
1008         case 624:
1009                 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1010                 param->reg_MADJ      = 0x00136868;
1011                 param->reg_SADJ      = 0x00004534;
1012                 param->wodt          = 1;
1013                 param->rodt          = 1;
1014                 param->reg_AC1       = 0x32302A37;
1015                 param->reg_AC2       = 0xEF56B621;
1016                 param->reg_DQSIC     = 0x0000015A;
1017                 param->reg_MRS       = 0x02101A50;
1018                 param->reg_EMRS      = 0x00000004;
1019                 param->reg_DRV       = 0x000000F5;
1020                 param->reg_IOZ       = 0x00000034;
1021                 param->reg_DQIDLY    = 0x00000078;
1022                 param->reg_FREQ      = 0x000059C0;
1023                 param->madj_max      = 128;
1024                 param->dll2_finetune_step = 3;
1025                 break;
1026         } /* switch freq */
1027
1028         switch (param->dram_chipid) {
1029         case AST_DRAM_512Mx16:
1030                 param->dram_config = 0x130;
1031                 break;
1032         default:
1033         case AST_DRAM_1Gx16:
1034                 param->dram_config = 0x131;
1035                 break;
1036         case AST_DRAM_2Gx16:
1037                 param->dram_config = 0x132;
1038                 break;
1039         case AST_DRAM_4Gx16:
1040                 param->dram_config = 0x133;
1041                 break;
1042         } /* switch size */
1043
1044         switch (param->vram_size) {
1045         default:
1046         case AST_VIDMEM_SIZE_8M:
1047                 param->dram_config |= 0x00;
1048                 break;
1049         case AST_VIDMEM_SIZE_16M:
1050                 param->dram_config |= 0x04;
1051                 break;
1052         case AST_VIDMEM_SIZE_32M:
1053                 param->dram_config |= 0x08;
1054                 break;
1055         case AST_VIDMEM_SIZE_64M:
1056                 param->dram_config |= 0x0c;
1057                 break;
1058         }
1059
1060 }
1061
1062 static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param)
1063 {
1064         u32 data, data2, retry = 0;
1065
1066 ddr3_init_start:
1067         ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1068         ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1069         ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1070         ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1071         udelay(10);
1072         ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1073         ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1074         udelay(10);
1075         ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1076         udelay(10);
1077
1078         ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1079         ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1080         ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1081         ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1082         ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1083         ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1084         ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1085         ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1086         ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1087         ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1088         ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1089         ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1090         ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1091         ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1092         ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1093         ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1094         ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1095         ast_moutdwm(ast, 0x1E6E0054, 0);
1096         ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1097         ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1098         ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1099         ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1100         ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1101         ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1102         /* Wait MCLK2X lock to MCLK */
1103         do {
1104                 data = ast_mindwm(ast, 0x1E6E001C);
1105         } while (!(data & 0x08000000));
1106         data = ast_mindwm(ast, 0x1E6E001C);
1107         data = (data >> 8) & 0xff;
1108         while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1109                 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1110                 if ((data2 & 0xff) > param->madj_max) {
1111                         break;
1112                 }
1113                 ast_moutdwm(ast, 0x1E6E0064, data2);
1114                 if (data2 & 0x00100000) {
1115                         data2 = ((data2 & 0xff) >> 3) + 3;
1116                 } else {
1117                         data2 = ((data2 & 0xff) >> 2) + 5;
1118                 }
1119                 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1120                 data2 += data & 0xff;
1121                 data = data | (data2 << 8);
1122                 ast_moutdwm(ast, 0x1E6E0068, data);
1123                 udelay(10);
1124                 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1125                 udelay(10);
1126                 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1127                 ast_moutdwm(ast, 0x1E6E0018, data);
1128                 data = data | 0x200;
1129                 ast_moutdwm(ast, 0x1E6E0018, data);
1130                 do {
1131                         data = ast_mindwm(ast, 0x1E6E001C);
1132                 } while (!(data & 0x08000000));
1133
1134                 data = ast_mindwm(ast, 0x1E6E001C);
1135                 data = (data >> 8) & 0xff;
1136         }
1137         ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1138         data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1139         ast_moutdwm(ast, 0x1E6E0018, data);
1140
1141         ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1142         ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1143         udelay(50);
1144         /* Mode Register Setting */
1145         ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1146         ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1147         ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1148         ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1149         ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1150         ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1151         ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1152         ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1153         ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1154
1155         ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1156         data = 0;
1157         if (param->wodt) {
1158                 data = 0x300;
1159         }
1160         if (param->rodt) {
1161                 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1162         }
1163         ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1164
1165         /* Calibrate the DQSI delay */
1166         if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1167                 goto ddr3_init_start;
1168
1169         ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1170         /* ECC Memory Initialization */
1171 #ifdef ECC
1172         ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1173         ast_moutdwm(ast, 0x1E6E0070, 0x221);
1174         do {
1175                 data = ast_mindwm(ast, 0x1E6E0070);
1176         } while (!(data & 0x00001000));
1177         ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1178         ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1179         ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1180 #endif
1181
1182
1183 }
1184
1185 static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param)
1186 {
1187         u32 trap, trap_AC2, trap_MRS;
1188
1189         ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1190
1191         /* Ger trap info */
1192         trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1193         trap_AC2  = (trap << 20) | (trap << 16);
1194         trap_AC2 += 0x00110000;
1195         trap_MRS  = 0x00000040 | (trap << 4);
1196
1197
1198         param->reg_MADJ       = 0x00034C4C;
1199         param->reg_SADJ       = 0x00001800;
1200         param->reg_DRV        = 0x000000F0;
1201         param->reg_PERIOD     = param->dram_freq;
1202         param->rodt           = 0;
1203
1204         switch (param->dram_freq) {
1205         case 264:
1206                 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1207                 param->wodt          = 0;
1208                 param->reg_AC1       = 0x11101513;
1209                 param->reg_AC2       = 0x78117011;
1210                 param->reg_DQSIC     = 0x00000092;
1211                 param->reg_MRS       = 0x00000842;
1212                 param->reg_EMRS      = 0x00000000;
1213                 param->reg_DRV       = 0x000000F0;
1214                 param->reg_IOZ       = 0x00000034;
1215                 param->reg_DQIDLY    = 0x0000005A;
1216                 param->reg_FREQ      = 0x00004AC0;
1217                 param->madj_max      = 138;
1218                 param->dll2_finetune_step = 3;
1219                 break;
1220         case 336:
1221                 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1222                 param->wodt          = 1;
1223                 param->reg_AC1       = 0x22202613;
1224                 param->reg_AC2       = 0xAA009016 | trap_AC2;
1225                 param->reg_DQSIC     = 0x000000BA;
1226                 param->reg_MRS       = 0x00000A02 | trap_MRS;
1227                 param->reg_EMRS      = 0x00000040;
1228                 param->reg_DRV       = 0x000000FA;
1229                 param->reg_IOZ       = 0x00000034;
1230                 param->reg_DQIDLY    = 0x00000074;
1231                 param->reg_FREQ      = 0x00004DC0;
1232                 param->madj_max      = 96;
1233                 param->dll2_finetune_step = 3;
1234                 switch (param->dram_chipid) {
1235                 default:
1236                 case AST_DRAM_512Mx16:
1237                         param->reg_AC2   = 0xAA009012 | trap_AC2;
1238                         break;
1239                 case AST_DRAM_1Gx16:
1240                         param->reg_AC2   = 0xAA009016 | trap_AC2;
1241                         break;
1242                 case AST_DRAM_2Gx16:
1243                         param->reg_AC2   = 0xAA009023 | trap_AC2;
1244                         break;
1245                 case AST_DRAM_4Gx16:
1246                         param->reg_AC2   = 0xAA00903B | trap_AC2;
1247                         break;
1248                 }
1249                 break;
1250         default:
1251         case 396:
1252                 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1253                 param->wodt          = 1;
1254                 param->rodt          = 0;
1255                 param->reg_AC1       = 0x33302714;
1256                 param->reg_AC2       = 0xCC00B01B | trap_AC2;
1257                 param->reg_DQSIC     = 0x000000E2;
1258                 param->reg_MRS       = 0x00000C02 | trap_MRS;
1259                 param->reg_EMRS      = 0x00000040;
1260                 param->reg_DRV       = 0x000000FA;
1261                 param->reg_IOZ       = 0x00000034;
1262                 param->reg_DQIDLY    = 0x00000089;
1263                 param->reg_FREQ      = 0x00005040;
1264                 param->madj_max      = 96;
1265                 param->dll2_finetune_step = 4;
1266
1267                 switch (param->dram_chipid) {
1268                 case AST_DRAM_512Mx16:
1269                         param->reg_AC2   = 0xCC00B016 | trap_AC2;
1270                         break;
1271                 default:
1272                 case AST_DRAM_1Gx16:
1273                         param->reg_AC2   = 0xCC00B01B | trap_AC2;
1274                         break;
1275                 case AST_DRAM_2Gx16:
1276                         param->reg_AC2   = 0xCC00B02B | trap_AC2;
1277                         break;
1278                 case AST_DRAM_4Gx16:
1279                         param->reg_AC2   = 0xCC00B03F | trap_AC2;
1280                         break;
1281                 }
1282
1283                 break;
1284
1285         case 408:
1286                 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1287                 param->wodt          = 1;
1288                 param->rodt          = 0;
1289                 param->reg_AC1       = 0x33302714;
1290                 param->reg_AC2       = 0xCC00B01B | trap_AC2;
1291                 param->reg_DQSIC     = 0x000000E2;
1292                 param->reg_MRS       = 0x00000C02 | trap_MRS;
1293                 param->reg_EMRS      = 0x00000040;
1294                 param->reg_DRV       = 0x000000FA;
1295                 param->reg_IOZ       = 0x00000034;
1296                 param->reg_DQIDLY    = 0x00000089;
1297                 param->reg_FREQ      = 0x000050C0;
1298                 param->madj_max      = 96;
1299                 param->dll2_finetune_step = 4;
1300
1301                 switch (param->dram_chipid) {
1302                 case AST_DRAM_512Mx16:
1303                         param->reg_AC2   = 0xCC00B016 | trap_AC2;
1304                         break;
1305                 default:
1306                 case AST_DRAM_1Gx16:
1307                         param->reg_AC2   = 0xCC00B01B | trap_AC2;
1308                         break;
1309                 case AST_DRAM_2Gx16:
1310                         param->reg_AC2   = 0xCC00B02B | trap_AC2;
1311                         break;
1312                 case AST_DRAM_4Gx16:
1313                         param->reg_AC2   = 0xCC00B03F | trap_AC2;
1314                         break;
1315                 }
1316
1317                 break;
1318         case 456:
1319                 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1320                 param->wodt          = 0;
1321                 param->reg_AC1       = 0x33302815;
1322                 param->reg_AC2       = 0xCD44B01E;
1323                 param->reg_DQSIC     = 0x000000FC;
1324                 param->reg_MRS       = 0x00000E72;
1325                 param->reg_EMRS      = 0x00000000;
1326                 param->reg_DRV       = 0x00000000;
1327                 param->reg_IOZ       = 0x00000034;
1328                 param->reg_DQIDLY    = 0x00000097;
1329                 param->reg_FREQ      = 0x000052C0;
1330                 param->madj_max      = 88;
1331                 param->dll2_finetune_step = 3;
1332                 break;
1333         case 504:
1334                 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1335                 param->wodt          = 1;
1336                 param->rodt          = 1;
1337                 param->reg_AC1       = 0x33302815;
1338                 param->reg_AC2       = 0xDE44C022;
1339                 param->reg_DQSIC     = 0x00000117;
1340                 param->reg_MRS       = 0x00000E72;
1341                 param->reg_EMRS      = 0x00000040;
1342                 param->reg_DRV       = 0x0000000A;
1343                 param->reg_IOZ       = 0x00000045;
1344                 param->reg_DQIDLY    = 0x000000A0;
1345                 param->reg_FREQ      = 0x000054C0;
1346                 param->madj_max      = 79;
1347                 param->dll2_finetune_step = 3;
1348                 break;
1349         case 528:
1350                 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1351                 param->wodt          = 1;
1352                 param->rodt          = 1;
1353                 param->reg_AC1       = 0x33302815;
1354                 param->reg_AC2       = 0xEF44D024;
1355                 param->reg_DQSIC     = 0x00000125;
1356                 param->reg_MRS       = 0x00000E72;
1357                 param->reg_EMRS      = 0x00000004;
1358                 param->reg_DRV       = 0x000000F9;
1359                 param->reg_IOZ       = 0x00000045;
1360                 param->reg_DQIDLY    = 0x000000A7;
1361                 param->reg_FREQ      = 0x000055C0;
1362                 param->madj_max      = 76;
1363                 param->dll2_finetune_step = 3;
1364                 break;
1365         case 552:
1366                 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1367                 param->wodt          = 1;
1368                 param->rodt          = 1;
1369                 param->reg_AC1       = 0x43402915;
1370                 param->reg_AC2       = 0xFF44E025;
1371                 param->reg_DQSIC     = 0x00000132;
1372                 param->reg_MRS       = 0x00000E72;
1373                 param->reg_EMRS      = 0x00000040;
1374                 param->reg_DRV       = 0x0000000A;
1375                 param->reg_IOZ       = 0x00000045;
1376                 param->reg_DQIDLY    = 0x000000AD;
1377                 param->reg_FREQ      = 0x000056C0;
1378                 param->madj_max      = 76;
1379                 param->dll2_finetune_step = 3;
1380                 break;
1381         case 576:
1382                 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1383                 param->wodt          = 1;
1384                 param->rodt          = 1;
1385                 param->reg_AC1       = 0x43402915;
1386                 param->reg_AC2       = 0xFF44E027;
1387                 param->reg_DQSIC     = 0x0000013F;
1388                 param->reg_MRS       = 0x00000E72;
1389                 param->reg_EMRS      = 0x00000004;
1390                 param->reg_DRV       = 0x000000F5;
1391                 param->reg_IOZ       = 0x00000045;
1392                 param->reg_DQIDLY    = 0x000000B3;
1393                 param->reg_FREQ      = 0x000057C0;
1394                 param->madj_max      = 76;
1395                 param->dll2_finetune_step = 3;
1396                 break;
1397         }
1398
1399         switch (param->dram_chipid) {
1400         case AST_DRAM_512Mx16:
1401                 param->dram_config = 0x100;
1402                 break;
1403         default:
1404         case AST_DRAM_1Gx16:
1405                 param->dram_config = 0x121;
1406                 break;
1407         case AST_DRAM_2Gx16:
1408                 param->dram_config = 0x122;
1409                 break;
1410         case AST_DRAM_4Gx16:
1411                 param->dram_config = 0x123;
1412                 break;
1413         } /* switch size */
1414
1415         switch (param->vram_size) {
1416         default:
1417         case AST_VIDMEM_SIZE_8M:
1418                 param->dram_config |= 0x00;
1419                 break;
1420         case AST_VIDMEM_SIZE_16M:
1421                 param->dram_config |= 0x04;
1422                 break;
1423         case AST_VIDMEM_SIZE_32M:
1424                 param->dram_config |= 0x08;
1425                 break;
1426         case AST_VIDMEM_SIZE_64M:
1427                 param->dram_config |= 0x0c;
1428                 break;
1429         }
1430 }
1431
1432 static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param)
1433 {
1434         u32 data, data2, retry = 0;
1435
1436 ddr2_init_start:
1437         ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1438         ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1439         ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1440         ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1441         ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1442         udelay(10);
1443         ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1444         udelay(10);
1445
1446         ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1447         ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1448         ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1449         ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1450         ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1451         ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1452         ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1453         ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1454         ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1455         ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1456         ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1457         ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1458         ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1459         ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1460         ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1461         ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1462         ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1463         ast_moutdwm(ast, 0x1E6E0054, 0);
1464         ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1465         ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1466         ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1467         ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1468         ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1469         ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1470
1471         /* Wait MCLK2X lock to MCLK */
1472         do {
1473                 data = ast_mindwm(ast, 0x1E6E001C);
1474         } while (!(data & 0x08000000));
1475         data = ast_mindwm(ast, 0x1E6E001C);
1476         data = (data >> 8) & 0xff;
1477         while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1478                 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1479                 if ((data2 & 0xff) > param->madj_max) {
1480                         break;
1481                 }
1482                 ast_moutdwm(ast, 0x1E6E0064, data2);
1483                 if (data2 & 0x00100000) {
1484                         data2 = ((data2 & 0xff) >> 3) + 3;
1485                 } else {
1486                         data2 = ((data2 & 0xff) >> 2) + 5;
1487                 }
1488                 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1489                 data2 += data & 0xff;
1490                 data = data | (data2 << 8);
1491                 ast_moutdwm(ast, 0x1E6E0068, data);
1492                 udelay(10);
1493                 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1494                 udelay(10);
1495                 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1496                 ast_moutdwm(ast, 0x1E6E0018, data);
1497                 data = data | 0x200;
1498                 ast_moutdwm(ast, 0x1E6E0018, data);
1499                 do {
1500                         data = ast_mindwm(ast, 0x1E6E001C);
1501                 } while (!(data & 0x08000000));
1502
1503                 data = ast_mindwm(ast, 0x1E6E001C);
1504                 data = (data >> 8) & 0xff;
1505         }
1506         ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1507         data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1508         ast_moutdwm(ast, 0x1E6E0018, data);
1509
1510         ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1511         ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1512         udelay(50);
1513         /* Mode Register Setting */
1514         ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1515         ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1516         ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1517         ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1518         ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1519         ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1520
1521         ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1522         ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1523         ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1524         ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1525         ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1526         ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1527         ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1528
1529         ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1530         data = 0;
1531         if (param->wodt) {
1532                 data = 0x500;
1533         }
1534         if (param->rodt) {
1535                 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1536         }
1537         ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1538         ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1539
1540         /* Calibrate the DQSI delay */
1541         if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1542                 goto ddr2_init_start;
1543
1544         /* ECC Memory Initialization */
1545 #ifdef ECC
1546         ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1547         ast_moutdwm(ast, 0x1E6E0070, 0x221);
1548         do {
1549                 data = ast_mindwm(ast, 0x1E6E0070);
1550         } while (!(data & 0x00001000));
1551         ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1552         ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1553         ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1554 #endif
1555
1556 }
1557
1558 static void ast_post_chip_2300(struct drm_device *dev)
1559 {
1560         struct ast_device *ast = to_ast_device(dev);
1561         struct ast2300_dram_param param;
1562         u32 temp;
1563         u8 reg;
1564
1565         reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1566         if ((reg & 0x80) == 0) {/* vga only */
1567                 ast_write32(ast, 0xf004, 0x1e6e0000);
1568                 ast_write32(ast, 0xf000, 0x1);
1569                 ast_write32(ast, 0x12000, 0x1688a8a8);
1570                 do {
1571                         ;
1572                 } while (ast_read32(ast, 0x12000) != 0x1);
1573
1574                 ast_write32(ast, 0x10000, 0xfc600309);
1575                 do {
1576                         ;
1577                 } while (ast_read32(ast, 0x10000) != 0x1);
1578
1579                 /* Slow down CPU/AHB CLK in VGA only mode */
1580                 temp = ast_read32(ast, 0x12008);
1581                 temp |= 0x73;
1582                 ast_write32(ast, 0x12008, temp);
1583
1584                 param.dram_freq = 396;
1585                 param.dram_type = AST_DDR3;
1586                 temp = ast_mindwm(ast, 0x1e6e2070);
1587                 if (temp & 0x01000000)
1588                         param.dram_type = AST_DDR2;
1589                 switch (temp & 0x18000000) {
1590                 case 0:
1591                         param.dram_chipid = AST_DRAM_512Mx16;
1592                         break;
1593                 default:
1594                 case 0x08000000:
1595                         param.dram_chipid = AST_DRAM_1Gx16;
1596                         break;
1597                 case 0x10000000:
1598                         param.dram_chipid = AST_DRAM_2Gx16;
1599                         break;
1600                 case 0x18000000:
1601                         param.dram_chipid = AST_DRAM_4Gx16;
1602                         break;
1603                 }
1604                 switch (temp & 0x0c) {
1605                 default:
1606                 case 0x00:
1607                         param.vram_size = AST_VIDMEM_SIZE_8M;
1608                         break;
1609
1610                 case 0x04:
1611                         param.vram_size = AST_VIDMEM_SIZE_16M;
1612                         break;
1613
1614                 case 0x08:
1615                         param.vram_size = AST_VIDMEM_SIZE_32M;
1616                         break;
1617
1618                 case 0x0c:
1619                         param.vram_size = AST_VIDMEM_SIZE_64M;
1620                         break;
1621                 }
1622
1623                 if (param.dram_type == AST_DDR3) {
1624                         get_ddr3_info(ast, &param);
1625                         ddr3_init(ast, &param);
1626                 } else {
1627                         get_ddr2_info(ast, &param);
1628                         ddr2_init(ast, &param);
1629                 }
1630
1631                 temp = ast_mindwm(ast, 0x1e6e2040);
1632                 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1633         }
1634
1635         /* wait ready */
1636         do {
1637                 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1638         } while ((reg & 0x40) == 0);
1639 }
1640
1641 static bool cbr_test_2500(struct ast_device *ast)
1642 {
1643         ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1644         ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1645         if (!mmc_test_burst(ast, 0))
1646                 return false;
1647         if (!mmc_test_single_2500(ast, 0))
1648                 return false;
1649         return true;
1650 }
1651
1652 static bool ddr_test_2500(struct ast_device *ast)
1653 {
1654         ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1655         ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1656         if (!mmc_test_burst(ast, 0))
1657                 return false;
1658         if (!mmc_test_burst(ast, 1))
1659                 return false;
1660         if (!mmc_test_burst(ast, 2))
1661                 return false;
1662         if (!mmc_test_burst(ast, 3))
1663                 return false;
1664         if (!mmc_test_single_2500(ast, 0))
1665                 return false;
1666         return true;
1667 }
1668
1669 static void ddr_init_common_2500(struct ast_device *ast)
1670 {
1671         ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1672         ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1673         ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1674         ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1675         ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1676         ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1677         ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1678         ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1679         ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1680         ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1681         ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1682         ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1683         ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1684         ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1685         ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1686         ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1687         ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1688         ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1689         ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1690 }
1691
1692 static void ddr_phy_init_2500(struct ast_device *ast)
1693 {
1694         u32 data, pass, timecnt;
1695
1696         pass = 0;
1697         ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1698         while (!pass) {
1699                 for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
1700                         data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1701                         if (!data)
1702                                 break;
1703                 }
1704                 if (timecnt != TIMEOUT) {
1705                         data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1706                         if (!data)
1707                                 pass = 1;
1708                 }
1709                 if (!pass) {
1710                         ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1711                         udelay(10); /* delay 10 us */
1712                         ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1713                 }
1714         }
1715
1716         ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1717 }
1718
1719 /*
1720  * Check DRAM Size
1721  * 1Gb : 0x80000000 ~ 0x87FFFFFF
1722  * 2Gb : 0x80000000 ~ 0x8FFFFFFF
1723  * 4Gb : 0x80000000 ~ 0x9FFFFFFF
1724  * 8Gb : 0x80000000 ~ 0xBFFFFFFF
1725  */
1726 static void check_dram_size_2500(struct ast_device *ast, u32 tRFC)
1727 {
1728         u32 reg_04, reg_14;
1729
1730         reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1731         reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1732
1733         ast_moutdwm(ast, 0xA0100000, 0x41424344);
1734         ast_moutdwm(ast, 0x90100000, 0x35363738);
1735         ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1736         ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1737
1738         /* Check 8Gbit */
1739         if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1740                 reg_04 |= 0x03;
1741                 reg_14 |= (tRFC >> 24) & 0xFF;
1742                 /* Check 4Gbit */
1743         } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1744                 reg_04 |= 0x02;
1745                 reg_14 |= (tRFC >> 16) & 0xFF;
1746                 /* Check 2Gbit */
1747         } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1748                 reg_04 |= 0x01;
1749                 reg_14 |= (tRFC >> 8) & 0xFF;
1750         } else {
1751                 reg_14 |= tRFC & 0xFF;
1752         }
1753         ast_moutdwm(ast, 0x1E6E0004, reg_04);
1754         ast_moutdwm(ast, 0x1E6E0014, reg_14);
1755 }
1756
1757 static void enable_cache_2500(struct ast_device *ast)
1758 {
1759         u32 reg_04, data;
1760
1761         reg_04 = ast_mindwm(ast, 0x1E6E0004);
1762         ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1763
1764         do
1765                 data = ast_mindwm(ast, 0x1E6E0004);
1766         while (!(data & 0x80000));
1767         ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1768 }
1769
1770 static void set_mpll_2500(struct ast_device *ast)
1771 {
1772         u32 addr, data, param;
1773
1774         /* Reset MMC */
1775         ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1776         ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1777         for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
1778                 ast_moutdwm(ast, addr, 0x0);
1779                 addr += 4;
1780         }
1781         ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1782
1783         ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1784         data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1785         if (data) {
1786                 /* CLKIN = 25MHz */
1787                 param = 0x930023E0;
1788                 ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1789         } else {
1790                 /* CLKIN = 24MHz */
1791                 param = 0x93002400;
1792         }
1793         ast_moutdwm(ast, 0x1E6E2020, param);
1794         udelay(100);
1795 }
1796
1797 static void reset_mmc_2500(struct ast_device *ast)
1798 {
1799         ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1800         ast_moutdwm(ast, 0x1E785044, 0x00000001);
1801         ast_moutdwm(ast, 0x1E785048, 0x00004755);
1802         ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1803         mdelay(100);
1804         ast_moutdwm(ast, 0x1E785054, 0x00000077);
1805         ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1806 }
1807
1808 static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table)
1809 {
1810
1811         ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1812         ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1813         ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1814         ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1815         ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);         /* MODEREG4/6 */
1816         ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);         /* MODEREG5 */
1817         ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1818         ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);         /* MODEREG1/3 */
1819
1820         /* DDR PHY Setting */
1821         ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1822         ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1823         ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1824         ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1825         ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1826         ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1827         ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1828         ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1829         ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1830         ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1831         ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1832         ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1833         ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1834         ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1835
1836         /* Controller Setting */
1837         ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1838
1839         /* Wait DDR PHY init done */
1840         ddr_phy_init_2500(ast);
1841
1842         ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1843         ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1844         ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1845
1846         check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1847         enable_cache_2500(ast);
1848         ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1849         ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1850 }
1851
1852 static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table)
1853 {
1854         u32 data, data2, pass, retrycnt;
1855         u32 ddr_vref, phy_vref;
1856         u32 min_ddr_vref = 0, min_phy_vref = 0;
1857         u32 max_ddr_vref = 0, max_phy_vref = 0;
1858
1859         ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1860         ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1861         ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1862         ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1863         ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);         /* MODEREG4/6 */
1864         ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);         /* MODEREG5 */
1865         ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1866         ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);         /* MODEREG1/3 */
1867
1868         /* DDR PHY Setting */
1869         ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1870         ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1871         ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1872         ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1873         ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1874         ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1875         ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1876         ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1877         ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1878         ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1879         ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1880         ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1881         ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1882         ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1883         ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1884
1885         /* Controller Setting */
1886         ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1887
1888         /* Train PHY Vref first */
1889         pass = 0;
1890
1891         for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1892                 max_phy_vref = 0x0;
1893                 pass = 0;
1894                 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1895                 for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
1896                         ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1897                         ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1898                         ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1899                         /* Fire DFI Init */
1900                         ddr_phy_init_2500(ast);
1901                         ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1902                         if (cbr_test_2500(ast)) {
1903                                 pass++;
1904                                 data = ast_mindwm(ast, 0x1E6E03D0);
1905                                 data2 = data >> 8;
1906                                 data  = data & 0xff;
1907                                 if (data > data2)
1908                                         data = data2;
1909                                 if (max_phy_vref < data) {
1910                                         max_phy_vref = data;
1911                                         min_phy_vref = phy_vref;
1912                                 }
1913                         } else if (pass > 0)
1914                                 break;
1915                 }
1916         }
1917         ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1918
1919         /* Train DDR Vref next */
1920         pass = 0;
1921
1922         for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1923                 min_ddr_vref = 0xFF;
1924                 max_ddr_vref = 0x0;
1925                 pass = 0;
1926                 for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
1927                         ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1928                         ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1929                         ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1930                         /* Fire DFI Init */
1931                         ddr_phy_init_2500(ast);
1932                         ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1933                         if (cbr_test_2500(ast)) {
1934                                 pass++;
1935                                 if (min_ddr_vref > ddr_vref)
1936                                         min_ddr_vref = ddr_vref;
1937                                 if (max_ddr_vref < ddr_vref)
1938                                         max_ddr_vref = ddr_vref;
1939                         } else if (pass != 0)
1940                                 break;
1941                 }
1942         }
1943
1944         ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1945         ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1946         ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
1947         ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1948
1949         /* Wait DDR PHY init done */
1950         ddr_phy_init_2500(ast);
1951
1952         ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1953         ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1954         ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1955
1956         check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1957         enable_cache_2500(ast);
1958         ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1959         ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1960 }
1961
1962 static bool ast_dram_init_2500(struct ast_device *ast)
1963 {
1964         u32 data;
1965         u32 max_tries = 5;
1966
1967         do {
1968                 if (max_tries-- == 0)
1969                         return false;
1970                 set_mpll_2500(ast);
1971                 reset_mmc_2500(ast);
1972                 ddr_init_common_2500(ast);
1973
1974                 data = ast_mindwm(ast, 0x1E6E2070);
1975                 if (data & 0x01000000)
1976                         ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
1977                 else
1978                         ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
1979         } while (!ddr_test_2500(ast));
1980
1981         ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
1982
1983         /* Patch code */
1984         data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
1985         ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
1986
1987         return true;
1988 }
1989
1990 void ast_patch_ahb_2500(struct ast_device *ast)
1991 {
1992         u32     data;
1993
1994         /* Clear bus lock condition */
1995         ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
1996         ast_moutdwm(ast, 0x1e600084, 0x00010000);
1997         ast_moutdwm(ast, 0x1e600088, 0x00000000);
1998         ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
1999         data = ast_mindwm(ast, 0x1e6e2070);
2000         if (data & 0x08000000) {                                        /* check fast reset */
2001                 /*
2002                  * If "Fast restet" is enabled for ARM-ICE debugger,
2003                  * then WDT needs to enable, that
2004                  * WDT04 is WDT#1 Reload reg.
2005                  * WDT08 is WDT#1 counter restart reg to avoid system deadlock
2006                  * WDT0C is WDT#1 control reg
2007                  *      [6:5]:= 01:Full chip
2008                  *      [4]:= 1:1MHz clock source
2009                  *      [1]:= 1:WDT will be cleeared and disabled after timeout occurs
2010                  *      [0]:= 1:WDT enable
2011                  */
2012                 ast_moutdwm(ast, 0x1E785004, 0x00000010);
2013                 ast_moutdwm(ast, 0x1E785008, 0x00004755);
2014                 ast_moutdwm(ast, 0x1E78500c, 0x00000033);
2015                 udelay(1000);
2016         }
2017         do {
2018                 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
2019                 data = ast_mindwm(ast, 0x1e6e2000);
2020         }       while (data != 1);
2021         ast_moutdwm(ast, 0x1e6e207c, 0x08000000);       /* clear fast reset */
2022 }
2023
2024 void ast_post_chip_2500(struct drm_device *dev)
2025 {
2026         struct ast_device *ast = to_ast_device(dev);
2027         u32 temp;
2028         u8 reg;
2029
2030         reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
2031         if ((reg & AST_VRAM_INIT_STATUS_MASK) == 0) {/* vga only */
2032                 /* Clear bus lock condition */
2033                 ast_patch_ahb_2500(ast);
2034
2035                 /* Disable watchdog */
2036                 ast_moutdwm(ast, 0x1E78502C, 0x00000000);
2037                 ast_moutdwm(ast, 0x1E78504C, 0x00000000);
2038
2039                 /*
2040                  * Reset USB port to patch USB unknown device issue
2041                  * SCU90 is Multi-function Pin Control #5
2042                  *      [29]:= 1:Enable USB2.0 Host port#1 (that the mutually shared USB2.0 Hub
2043                  *                              port).
2044                  * SCU94 is Multi-function Pin Control #6
2045                  *      [14:13]:= 1x:USB2.0 Host2 controller
2046                  * SCU70 is Hardware Strap reg
2047                  *      [23]:= 1:CLKIN is 25MHz and USBCK1 = 24/48 MHz (determined by
2048                  *                              [18]: 0(24)/1(48) MHz)
2049                  * SCU7C is Write clear reg to SCU70
2050                  *      [23]:= write 1 and then SCU70[23] will be clear as 0b.
2051                  */
2052                 ast_moutdwm(ast, 0x1E6E2090, 0x20000000);
2053                 ast_moutdwm(ast, 0x1E6E2094, 0x00004000);
2054                 if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) {
2055                         ast_moutdwm(ast, 0x1E6E207C, 0x00800000);
2056                         mdelay(100);
2057                         ast_moutdwm(ast, 0x1E6E2070, 0x00800000);
2058                 }
2059                 /* Modify eSPI reset pin */
2060                 temp = ast_mindwm(ast, 0x1E6E2070);
2061                 if (temp & 0x02000000)
2062                         ast_moutdwm(ast, 0x1E6E207C, 0x00004000);
2063
2064                 /* Slow down CPU/AHB CLK in VGA only mode */
2065                 temp = ast_read32(ast, 0x12008);
2066                 temp |= 0x73;
2067                 ast_write32(ast, 0x12008, temp);
2068
2069                 if (!ast_dram_init_2500(ast))
2070                         drm_err(dev, "DRAM init failed !\n");
2071
2072                 temp = ast_mindwm(ast, 0x1e6e2040);
2073                 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
2074         }
2075
2076         /* wait ready */
2077         do {
2078                 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
2079         } while ((reg & 0x40) == 0);
2080 }