drivers/gpu/drm/ast/ast_post.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  16  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  17  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  18  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * The above copyright notice and this permission notice (including the
  21  * next paragraph) shall be included in all copies or substantial portions
  22  * of the Software.
  23  *
  24  */
  25 /*
  26  * Authors: Dave Airlie <[email protected]>
  27  */
  28
  29 #include <linux/delay.h>
  30 #include <linux/pci.h>
  31
  32 #include <drm/drm_print.h>
  33
  34 #include "ast_dram_tables.h"
  35 #include "ast_drv.h"
  36
  37 static void ast_post_chip_2300(struct ast_device *ast);
  38 static void ast_post_chip_2500(struct ast_device *ast);
  39
  40 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
  41 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
  42
  43 static void ast_set_def_ext_reg(struct ast_device *ast)
  44 {
  45         u8 i, index, reg;
  46         const u8 *ext_reg_info;
  47
  48         /* reset scratch */
  49         for (i = 0x81; i <= 0x9f; i++)
  50                 ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
  51
  52         if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
  53                 ext_reg_info = extreginfo_ast2300;
  54         else
  55                 ext_reg_info = extreginfo;
  56
  57         index = 0xa0;
  58         while (*ext_reg_info != 0xff) {
  59                 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
  60                 index++;
  61                 ext_reg_info++;
  62         }
  63
  64         /* disable standard IO/MEM decode if secondary */
  65         /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
  66
  67         /* Set Ext. Default */
  68         ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
  69         ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
  70
  71         /* Enable RAMDAC for A1 */
  72         reg = 0x04;
  73         if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
  74                 reg |= 0x20;
  75         ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
  76 }
  77
  78 static u32 __ast_mindwm(void __iomem *regs, u32 r)
  79 {
  80         u32 data;
  81
  82         __ast_write32(regs, 0xf004, r & 0xffff0000);
  83         __ast_write32(regs, 0xf000, 0x1);
  84
  85         do {
  86                 data = __ast_read32(regs, 0xf004) & 0xffff0000;
  87         } while (data != (r & 0xffff0000));
  88
  89         return __ast_read32(regs, 0x10000 + (r & 0x0000ffff));
  90 }
  91
  92 static void __ast_moutdwm(void __iomem *regs, u32 r, u32 v)
  93 {
  94         u32 data;
  95
  96         __ast_write32(regs, 0xf004, r & 0xffff0000);
  97         __ast_write32(regs, 0xf000, 0x1);
  98
  99         do {
 100                 data = __ast_read32(regs, 0xf004) & 0xffff0000;
 101         } while (data != (r & 0xffff0000));
 102
 103         __ast_write32(regs, 0x10000 + (r & 0x0000ffff), v);
 104 }
 105
 106 u32 ast_mindwm(struct ast_device *ast, u32 r)
 107 {
 108         return __ast_mindwm(ast->regs, r);
 109 }
 110
 111 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v)
 112 {
 113         __ast_moutdwm(ast->regs, r, v);
 114 }
 115
 116 /*
 117  * AST2100/2150 DLL CBR Setting
 118  */
 119 #define CBR_SIZE_AST2150             ((16 << 10) - 1)
 120 #define CBR_PASSNUM_AST2150          5
 121 #define CBR_THRESHOLD_AST2150        10
 122 #define CBR_THRESHOLD2_AST2150       10
 123 #define TIMEOUT_AST2150              5000000
 124
 125 #define CBR_PATNUM_AST2150           8
 126
 127 static const u32 pattern_AST2150[14] = {
 128         0xFF00FF00,
 129         0xCC33CC33,
 130         0xAA55AA55,
 131         0xFFFE0001,
 132         0x683501FE,
 133         0x0F1929B0,
 134         0x2D0B4346,
 135         0x60767F02,
 136         0x6FBE36A6,
 137         0x3A253035,
 138         0x3019686D,
 139         0x41C6167E,
 140         0x620152BF,
 141         0x20F050E0
 142 };
 143
 144 static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen)
 145 {
 146         u32 data, timeout;
 147
 148         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 149         ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
 150         timeout = 0;
 151         do {
 152                 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
 153                 if (++timeout > TIMEOUT_AST2150) {
 154                         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 155                         return 0xffffffff;
 156                 }
 157         } while (!data);
 158         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 159         ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
 160         timeout = 0;
 161         do {
 162                 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
 163                 if (++timeout > TIMEOUT_AST2150) {
 164                         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 165                         return 0xffffffff;
 166                 }
 167         } while (!data);
 168         data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
 169         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 170         return data;
 171 }
 172
 173 #if 0 /* unused in DDX driver - here for completeness */
 174 static u32 mmctestsingle2_ast2150(struct ast_device *ast, u32 datagen)
 175 {
 176         u32 data, timeout;
 177
 178         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 179         ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
 180         timeout = 0;
 181         do {
 182                 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
 183                 if (++timeout > TIMEOUT_AST2150) {
 184                         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 185                         return 0xffffffff;
 186                 }
 187         } while (!data);
 188         data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
 189         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 190         return data;
 191 }
 192 #endif
 193
 194 static int cbrtest_ast2150(struct ast_device *ast)
 195 {
 196         int i;
 197
 198         for (i = 0; i < 8; i++)
 199                 if (mmctestburst2_ast2150(ast, i))
 200                         return 0;
 201         return 1;
 202 }
 203
 204 static int cbrscan_ast2150(struct ast_device *ast, int busw)
 205 {
 206         u32 patcnt, loop;
 207
 208         for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
 209                 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
 210                 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
 211                         if (cbrtest_ast2150(ast))
 212                                 break;
 213                 }
 214                 if (loop == CBR_PASSNUM_AST2150)
 215                         return 0;
 216         }
 217         return 1;
 218 }
 219
 220
 221 static void cbrdlli_ast2150(struct ast_device *ast, int busw)
 222 {
 223         u32 dll_min[4], dll_max[4], dlli, data, passcnt;
 224
 225 cbr_start:
 226         dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff;
 227         dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0;
 228         passcnt = 0;
 229
 230         for (dlli = 0; dlli < 100; dlli++) {
 231                 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
 232                 data = cbrscan_ast2150(ast, busw);
 233                 if (data != 0) {
 234                         if (data & 0x1) {
 235                                 if (dll_min[0] > dlli)
 236                                         dll_min[0] = dlli;
 237                                 if (dll_max[0] < dlli)
 238                                         dll_max[0] = dlli;
 239                         }
 240                         passcnt++;
 241                 } else if (passcnt >= CBR_THRESHOLD_AST2150)
 242                         goto cbr_start;
 243         }
 244         if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
 245                 goto cbr_start;
 246
 247         dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
 248         ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
 249 }
 250
 251
 252
 253 static void ast_init_dram_reg(struct ast_device *ast)
 254 {
 255         u8 j;
 256         u32 data, temp, i;
 257         const struct ast_dramstruct *dram_reg_info;
 258
 259         j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
 260
 261         if ((j & 0x80) == 0) { /* VGA only */
 262                 if (IS_AST_GEN1(ast)) {
 263                         dram_reg_info = ast2000_dram_table_data;
 264                         ast_write32(ast, 0xf004, 0x1e6e0000);
 265                         ast_write32(ast, 0xf000, 0x1);
 266                         ast_write32(ast, 0x10100, 0xa8);
 267
 268                         do {
 269                                 ;
 270                         } while (ast_read32(ast, 0x10100) != 0xa8);
 271                 } else { /* GEN2/GEN3 */
 272                         if (ast->chip == AST2100 || ast->chip == AST2200)
 273                                 dram_reg_info = ast2100_dram_table_data;
 274                         else
 275                                 dram_reg_info = ast1100_dram_table_data;
 276
 277                         ast_write32(ast, 0xf004, 0x1e6e0000);
 278                         ast_write32(ast, 0xf000, 0x1);
 279                         ast_write32(ast, 0x12000, 0x1688A8A8);
 280                         do {
 281                                 ;
 282                         } while (ast_read32(ast, 0x12000) != 0x01);
 283
 284                         ast_write32(ast, 0x10000, 0xfc600309);
 285                         do {
 286                                 ;
 287                         } while (ast_read32(ast, 0x10000) != 0x01);
 288                 }
 289
 290                 while (dram_reg_info->index != 0xffff) {
 291                         if (dram_reg_info->index == 0xff00) {/* delay fn */
 292                                 for (i = 0; i < 15; i++)
 293                                         udelay(dram_reg_info->data);
 294                         } else if (dram_reg_info->index == 0x4 && !IS_AST_GEN1(ast)) {
 295                                 data = dram_reg_info->data;
 296                                 if (ast->dram_type == AST_DRAM_1Gx16)
 297                                         data = 0x00000d89;
 298                                 else if (ast->dram_type == AST_DRAM_1Gx32)
 299                                         data = 0x00000c8d;
 300
 301                                 temp = ast_read32(ast, 0x12070);
 302                                 temp &= 0xc;
 303                                 temp <<= 2;
 304                                 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
 305                         } else
 306                                 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
 307                         dram_reg_info++;
 308                 }
 309
 310                 /* AST 2100/2150 DRAM calibration */
 311                 data = ast_read32(ast, 0x10120);
 312                 if (data == 0x5061) { /* 266Mhz */
 313                         data = ast_read32(ast, 0x10004);
 314                         if (data & 0x40)
 315                                 cbrdlli_ast2150(ast, 16); /* 16 bits */
 316                         else
 317                                 cbrdlli_ast2150(ast, 32); /* 32 bits */
 318                 }
 319
 320                 switch (AST_GEN(ast)) {
 321                 case 1:
 322                         temp = ast_read32(ast, 0x10140);
 323                         ast_write32(ast, 0x10140, temp | 0x40);
 324                         break;
 325                 case 2:
 326                 case 3:
 327                         temp = ast_read32(ast, 0x1200c);
 328                         ast_write32(ast, 0x1200c, temp & 0xfffffffd);
 329                         temp = ast_read32(ast, 0x12040);
 330                         ast_write32(ast, 0x12040, temp | 0x40);
 331                         break;
 332                 default:
 333                         break;
 334                 }
 335         }
 336
 337         /* wait ready */
 338         do {
 339                 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
 340         } while ((j & 0x40) == 0);
 341 }
 342
 343 void ast_post_gpu(struct ast_device *ast)
 344 {
 345         ast_set_def_ext_reg(ast);
 346
 347         if (IS_AST_GEN7(ast)) {
 348                 if (ast->tx_chip == AST_TX_ASTDP)
 349                         ast_dp_launch(ast);
 350         } else if (ast->config_mode == ast_use_p2a) {
 351                 if (IS_AST_GEN6(ast))
 352                         ast_post_chip_2500(ast);
 353                 else if (IS_AST_GEN5(ast) || IS_AST_GEN4(ast))
 354                         ast_post_chip_2300(ast);
 355                 else
 356                         ast_init_dram_reg(ast);
 357
 358                 ast_init_3rdtx(ast);
 359         } else {
 360                 if (ast->tx_chip == AST_TX_SIL164)
 361                         ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);   /* Enable DVO */
 362         }
 363 }
 364
 365 /* AST 2300 DRAM settings */
 366 #define AST_DDR3 0
 367 #define AST_DDR2 1
 368
 369 struct ast2300_dram_param {
 370         u32 dram_type;
 371         u32 dram_chipid;
 372         u32 dram_freq;
 373         u32 vram_size;
 374         u32 odt;
 375         u32 wodt;
 376         u32 rodt;
 377         u32 dram_config;
 378         u32 reg_PERIOD;
 379         u32 reg_MADJ;
 380         u32 reg_SADJ;
 381         u32 reg_MRS;
 382         u32 reg_EMRS;
 383         u32 reg_AC1;
 384         u32 reg_AC2;
 385         u32 reg_DQSIC;
 386         u32 reg_DRV;
 387         u32 reg_IOZ;
 388         u32 reg_DQIDLY;
 389         u32 reg_FREQ;
 390         u32 madj_max;
 391         u32 dll2_finetune_step;
 392 };
 393
 394 /*
 395  * DQSI DLL CBR Setting
 396  */
 397 #define CBR_SIZE0            ((1  << 10) - 1)
 398 #define CBR_SIZE1            ((4  << 10) - 1)
 399 #define CBR_SIZE2            ((64 << 10) - 1)
 400 #define CBR_PASSNUM          5
 401 #define CBR_PASSNUM2         5
 402 #define CBR_THRESHOLD        10
 403 #define CBR_THRESHOLD2       10
 404 #define TIMEOUT              5000000
 405 #define CBR_PATNUM           8
 406
 407 static const u32 pattern[8] = {
 408         0xFF00FF00,
 409         0xCC33CC33,
 410         0xAA55AA55,
 411         0x88778877,
 412         0x92CC4D6E,
 413         0x543D3CDE,
 414         0xF1E843C7,
 415         0x7C61D253
 416 };
 417
 418 static bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl)
 419 {
 420         u32 data, timeout;
 421
 422         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 423         ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
 424         timeout = 0;
 425         do {
 426                 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
 427                 if (data & 0x2000)
 428                         return false;
 429                 if (++timeout > TIMEOUT) {
 430                         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 431                         return false;
 432                 }
 433         } while (!data);
 434         ast_moutdwm(ast, 0x1e6e0070, 0x0);
 435         return true;
 436 }
 437
 438 static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl)
 439 {
 440         u32 data, timeout;
 441
 442         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 443         ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
 444         timeout = 0;
 445         do {
 446                 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
 447                 if (++timeout > TIMEOUT) {
 448                         ast_moutdwm(ast, 0x1e6e0070, 0x0);
 449                         return 0xffffffff;
 450                 }
 451         } while (!data);
 452         data = ast_mindwm(ast, 0x1e6e0078);
 453         data = (data | (data >> 16)) & 0xffff;
 454         ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
 455         return data;
 456 }
 457
 458
 459 static bool mmc_test_burst(struct ast_device *ast, u32 datagen)
 460 {
 461         return mmc_test(ast, datagen, 0xc1);
 462 }
 463
 464 static u32 mmc_test_burst2(struct ast_device *ast, u32 datagen)
 465 {
 466         return mmc_test2(ast, datagen, 0x41);
 467 }
 468
 469 static bool mmc_test_single(struct ast_device *ast, u32 datagen)
 470 {
 471         return mmc_test(ast, datagen, 0xc5);
 472 }
 473
 474 static u32 mmc_test_single2(struct ast_device *ast, u32 datagen)
 475 {
 476         return mmc_test2(ast, datagen, 0x05);
 477 }
 478
 479 static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen)
 480 {
 481         return mmc_test(ast, datagen, 0x85);
 482 }
 483
 484 static int cbr_test(struct ast_device *ast)
 485 {
 486         u32 data;
 487         int i;
 488         data = mmc_test_single2(ast, 0);
 489         if ((data & 0xff) && (data & 0xff00))
 490                 return 0;
 491         for (i = 0; i < 8; i++) {
 492                 data = mmc_test_burst2(ast, i);
 493                 if ((data & 0xff) && (data & 0xff00))
 494                         return 0;
 495         }
 496         if (!data)
 497                 return 3;
 498         else if (data & 0xff)
 499                 return 2;
 500         return 1;
 501 }
 502
 503 static int cbr_scan(struct ast_device *ast)
 504 {
 505         u32 data, data2, patcnt, loop;
 506
 507         data2 = 3;
 508         for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
 509                 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
 510                 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
 511                         if ((data = cbr_test(ast)) != 0) {
 512                                 data2 &= data;
 513                                 if (!data2)
 514                                         return 0;
 515                                 break;
 516                         }
 517                 }
 518                 if (loop == CBR_PASSNUM2)
 519                         return 0;
 520         }
 521         return data2;
 522 }
 523
 524 static u32 cbr_test2(struct ast_device *ast)
 525 {
 526         u32 data;
 527
 528         data = mmc_test_burst2(ast, 0);
 529         if (data == 0xffff)
 530                 return 0;
 531         data |= mmc_test_single2(ast, 0);
 532         if (data == 0xffff)
 533                 return 0;
 534
 535         return ~data & 0xffff;
 536 }
 537
 538 static u32 cbr_scan2(struct ast_device *ast)
 539 {
 540         u32 data, data2, patcnt, loop;
 541
 542         data2 = 0xffff;
 543         for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
 544                 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
 545                 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
 546                         if ((data = cbr_test2(ast)) != 0) {
 547                                 data2 &= data;
 548                                 if (!data2)
 549                                         return 0;
 550                                 break;
 551                         }
 552                 }
 553                 if (loop == CBR_PASSNUM2)
 554                         return 0;
 555         }
 556         return data2;
 557 }
 558
 559 static bool cbr_test3(struct ast_device *ast)
 560 {
 561         if (!mmc_test_burst(ast, 0))
 562                 return false;
 563         if (!mmc_test_single(ast, 0))
 564                 return false;
 565         return true;
 566 }
 567
 568 static bool cbr_scan3(struct ast_device *ast)
 569 {
 570         u32 patcnt, loop;
 571
 572         for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
 573                 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
 574                 for (loop = 0; loop < 2; loop++) {
 575                         if (cbr_test3(ast))
 576                                 break;
 577                 }
 578                 if (loop == 2)
 579                         return false;
 580         }
 581         return true;
 582 }
 583
 584 static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param)
 585 {
 586         u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
 587         bool status = false;
 588 FINETUNE_START:
 589         for (cnt = 0; cnt < 16; cnt++) {
 590                 dllmin[cnt] = 0xff;
 591                 dllmax[cnt] = 0x0;
 592         }
 593         passcnt = 0;
 594         for (dlli = 0; dlli < 76; dlli++) {
 595                 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
 596                 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
 597                 data = cbr_scan2(ast);
 598                 if (data != 0) {
 599                         mask = 0x00010001;
 600                         for (cnt = 0; cnt < 16; cnt++) {
 601                                 if (data & mask) {
 602                                         if (dllmin[cnt] > dlli) {
 603                                                 dllmin[cnt] = dlli;
 604                                         }
 605                                         if (dllmax[cnt] < dlli) {
 606                                                 dllmax[cnt] = dlli;
 607                                         }
 608                                 }
 609                                 mask <<= 1;
 610                         }
 611                         passcnt++;
 612                 } else if (passcnt >= CBR_THRESHOLD2) {
 613                         break;
 614                 }
 615         }
 616         gold_sadj[0] = 0x0;
 617         passcnt = 0;
 618         for (cnt = 0; cnt < 16; cnt++) {
 619                 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
 620                         gold_sadj[0] += dllmin[cnt];
 621                         passcnt++;
 622                 }
 623         }
 624         if (retry++ > 10)
 625                 goto FINETUNE_DONE;
 626         if (passcnt != 16) {
 627                 goto FINETUNE_START;
 628         }
 629         status = true;
 630 FINETUNE_DONE:
 631         gold_sadj[0] = gold_sadj[0] >> 4;
 632         gold_sadj[1] = gold_sadj[0];
 633
 634         data = 0;
 635         for (cnt = 0; cnt < 8; cnt++) {
 636                 data >>= 3;
 637                 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
 638                         dlli = dllmin[cnt];
 639                         if (gold_sadj[0] >= dlli) {
 640                                 dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
 641                                 if (dlli > 3) {
 642                                         dlli = 3;
 643                                 }
 644                         } else {
 645                                 dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
 646                                 if (dlli > 4) {
 647                                         dlli = 4;
 648                                 }
 649                                 dlli = (8 - dlli) & 0x7;
 650                         }
 651                         data |= dlli << 21;
 652                 }
 653         }
 654         ast_moutdwm(ast, 0x1E6E0080, data);
 655
 656         data = 0;
 657         for (cnt = 8; cnt < 16; cnt++) {
 658                 data >>= 3;
 659                 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
 660                         dlli = dllmin[cnt];
 661                         if (gold_sadj[1] >= dlli) {
 662                                 dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
 663                                 if (dlli > 3) {
 664                                         dlli = 3;
 665                                 } else {
 666                                         dlli = (dlli - 1) & 0x7;
 667                                 }
 668                         } else {
 669                                 dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
 670                                 dlli += 1;
 671                                 if (dlli > 4) {
 672                                         dlli = 4;
 673                                 }
 674                                 dlli = (8 - dlli) & 0x7;
 675                         }
 676                         data |= dlli << 21;
 677                 }
 678         }
 679         ast_moutdwm(ast, 0x1E6E0084, data);
 680         return status;
 681 } /* finetuneDQI_L */
 682
 683 static void finetuneDQSI(struct ast_device *ast)
 684 {
 685         u32 dlli, dqsip, dqidly;
 686         u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
 687         u32 g_dqidly, g_dqsip, g_margin, g_side;
 688         u16 pass[32][2][2];
 689         char tag[2][76];
 690
 691         /* Disable DQI CBR */
 692         reg_mcr0c  = ast_mindwm(ast, 0x1E6E000C);
 693         reg_mcr18  = ast_mindwm(ast, 0x1E6E0018);
 694         reg_mcr18 &= 0x0000ffff;
 695         ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
 696
 697         for (dlli = 0; dlli < 76; dlli++) {
 698                 tag[0][dlli] = 0x0;
 699                 tag[1][dlli] = 0x0;
 700         }
 701         for (dqidly = 0; dqidly < 32; dqidly++) {
 702                 pass[dqidly][0][0] = 0xff;
 703                 pass[dqidly][0][1] = 0x0;
 704                 pass[dqidly][1][0] = 0xff;
 705                 pass[dqidly][1][1] = 0x0;
 706         }
 707         for (dqidly = 0; dqidly < 32; dqidly++) {
 708                 passcnt[0] = passcnt[1] = 0;
 709                 for (dqsip = 0; dqsip < 2; dqsip++) {
 710                         ast_moutdwm(ast, 0x1E6E000C, 0);
 711                         ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
 712                         ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
 713                         for (dlli = 0; dlli < 76; dlli++) {
 714                                 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
 715                                 ast_moutdwm(ast, 0x1E6E0070, 0);
 716                                 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
 717                                 if (cbr_scan3(ast)) {
 718                                         if (dlli == 0)
 719                                                 break;
 720                                         passcnt[dqsip]++;
 721                                         tag[dqsip][dlli] = 'P';
 722                                         if (dlli < pass[dqidly][dqsip][0])
 723                                                 pass[dqidly][dqsip][0] = (u16) dlli;
 724                                         if (dlli > pass[dqidly][dqsip][1])
 725                                                 pass[dqidly][dqsip][1] = (u16) dlli;
 726                                 } else if (passcnt[dqsip] >= 5)
 727                                         break;
 728                                 else {
 729                                         pass[dqidly][dqsip][0] = 0xff;
 730                                         pass[dqidly][dqsip][1] = 0x0;
 731                                 }
 732                         }
 733                 }
 734                 if (passcnt[0] == 0 && passcnt[1] == 0)
 735                         dqidly++;
 736         }
 737         /* Search margin */
 738         g_dqidly = g_dqsip = g_margin = g_side = 0;
 739
 740         for (dqidly = 0; dqidly < 32; dqidly++) {
 741                 for (dqsip = 0; dqsip < 2; dqsip++) {
 742                         if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
 743                                 continue;
 744                         diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
 745                         if ((diff+2) < g_margin)
 746                                 continue;
 747                         passcnt[0] = passcnt[1] = 0;
 748                         for (dlli = pass[dqidly][dqsip][0]; dlli > 0  && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
 749                         for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
 750                         if (passcnt[0] > passcnt[1])
 751                                 passcnt[0] = passcnt[1];
 752                         passcnt[1] = 0;
 753                         if (passcnt[0] > g_side)
 754                                 passcnt[1] = passcnt[0] - g_side;
 755                         if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
 756                                 g_margin = diff;
 757                                 g_dqidly = dqidly;
 758                                 g_dqsip  = dqsip;
 759                                 g_side   = passcnt[0];
 760                         } else if (passcnt[1] > 1 && g_side < 8) {
 761                                 if (diff > g_margin)
 762                                         g_margin = diff;
 763                                 g_dqidly = dqidly;
 764                                 g_dqsip  = dqsip;
 765                                 g_side   = passcnt[0];
 766                         }
 767                 }
 768         }
 769         reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
 770         ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
 771
 772 }
 773 static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param)
 774 {
 775         u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
 776         bool status = false;
 777
 778         finetuneDQSI(ast);
 779         if (finetuneDQI_L(ast, param) == false)
 780                 return status;
 781
 782 CBR_START2:
 783         dllmin[0] = dllmin[1] = 0xff;
 784         dllmax[0] = dllmax[1] = 0x0;
 785         passcnt = 0;
 786         for (dlli = 0; dlli < 76; dlli++) {
 787                 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
 788                 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
 789                 data = cbr_scan(ast);
 790                 if (data != 0) {
 791                         if (data & 0x1) {
 792                                 if (dllmin[0] > dlli) {
 793                                         dllmin[0] = dlli;
 794                                 }
 795                                 if (dllmax[0] < dlli) {
 796                                         dllmax[0] = dlli;
 797                                 }
 798                         }
 799                         if (data & 0x2) {
 800                                 if (dllmin[1] > dlli) {
 801                                         dllmin[1] = dlli;
 802                                 }
 803                                 if (dllmax[1] < dlli) {
 804                                         dllmax[1] = dlli;
 805                                 }
 806                         }
 807                         passcnt++;
 808                 } else if (passcnt >= CBR_THRESHOLD) {
 809                         break;
 810                 }
 811         }
 812         if (retry++ > 10)
 813                 goto CBR_DONE2;
 814         if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
 815                 goto CBR_START2;
 816         }
 817         if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
 818                 goto CBR_START2;
 819         }
 820         status = true;
 821 CBR_DONE2:
 822         dlli  = (dllmin[1] + dllmax[1]) >> 1;
 823         dlli <<= 8;
 824         dlli += (dllmin[0] + dllmax[0]) >> 1;
 825         ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
 826         return status;
 827 } /* CBRDLL2 */
 828
 829 static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param)
 830 {
 831         u32 trap, trap_AC2, trap_MRS;
 832
 833         ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
 834
 835         /* Ger trap info */
 836         trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
 837         trap_AC2  = 0x00020000 + (trap << 16);
 838         trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
 839         trap_MRS  = 0x00000010 + (trap << 4);
 840         trap_MRS |= ((trap & 0x2) << 18);
 841
 842         param->reg_MADJ       = 0x00034C4C;
 843         param->reg_SADJ       = 0x00001800;
 844         param->reg_DRV        = 0x000000F0;
 845         param->reg_PERIOD     = param->dram_freq;
 846         param->rodt           = 0;
 847
 848         switch (param->dram_freq) {
 849         case 336:
 850                 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
 851                 param->wodt          = 0;
 852                 param->reg_AC1       = 0x22202725;
 853                 param->reg_AC2       = 0xAA007613 | trap_AC2;
 854                 param->reg_DQSIC     = 0x000000BA;
 855                 param->reg_MRS       = 0x04001400 | trap_MRS;
 856                 param->reg_EMRS      = 0x00000000;
 857                 param->reg_IOZ       = 0x00000023;
 858                 param->reg_DQIDLY    = 0x00000074;
 859                 param->reg_FREQ      = 0x00004DC0;
 860                 param->madj_max      = 96;
 861                 param->dll2_finetune_step = 3;
 862                 switch (param->dram_chipid) {
 863                 default:
 864                 case AST_DRAM_512Mx16:
 865                 case AST_DRAM_1Gx16:
 866                         param->reg_AC2   = 0xAA007613 | trap_AC2;
 867                         break;
 868                 case AST_DRAM_2Gx16:
 869                         param->reg_AC2   = 0xAA00761C | trap_AC2;
 870                         break;
 871                 case AST_DRAM_4Gx16:
 872                         param->reg_AC2   = 0xAA007636 | trap_AC2;
 873                         break;
 874                 }
 875                 break;
 876         default:
 877         case 396:
 878                 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
 879                 param->wodt          = 1;
 880                 param->reg_AC1       = 0x33302825;
 881                 param->reg_AC2       = 0xCC009617 | trap_AC2;
 882                 param->reg_DQSIC     = 0x000000E2;
 883                 param->reg_MRS       = 0x04001600 | trap_MRS;
 884                 param->reg_EMRS      = 0x00000000;
 885                 param->reg_IOZ       = 0x00000034;
 886                 param->reg_DRV       = 0x000000FA;
 887                 param->reg_DQIDLY    = 0x00000089;
 888                 param->reg_FREQ      = 0x00005040;
 889                 param->madj_max      = 96;
 890                 param->dll2_finetune_step = 4;
 891
 892                 switch (param->dram_chipid) {
 893                 default:
 894                 case AST_DRAM_512Mx16:
 895                 case AST_DRAM_1Gx16:
 896                         param->reg_AC2   = 0xCC009617 | trap_AC2;
 897                         break;
 898                 case AST_DRAM_2Gx16:
 899                         param->reg_AC2   = 0xCC009622 | trap_AC2;
 900                         break;
 901                 case AST_DRAM_4Gx16:
 902                         param->reg_AC2   = 0xCC00963F | trap_AC2;
 903                         break;
 904                 }
 905                 break;
 906
 907         case 408:
 908                 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
 909                 param->wodt          = 1;
 910                 param->reg_AC1       = 0x33302825;
 911                 param->reg_AC2       = 0xCC009617 | trap_AC2;
 912                 param->reg_DQSIC     = 0x000000E2;
 913                 param->reg_MRS       = 0x04001600 | trap_MRS;
 914                 param->reg_EMRS      = 0x00000000;
 915                 param->reg_IOZ       = 0x00000023;
 916                 param->reg_DRV       = 0x000000FA;
 917                 param->reg_DQIDLY    = 0x00000089;
 918                 param->reg_FREQ      = 0x000050C0;
 919                 param->madj_max      = 96;
 920                 param->dll2_finetune_step = 4;
 921
 922                 switch (param->dram_chipid) {
 923                 default:
 924                 case AST_DRAM_512Mx16:
 925                 case AST_DRAM_1Gx16:
 926                         param->reg_AC2   = 0xCC009617 | trap_AC2;
 927                         break;
 928                 case AST_DRAM_2Gx16:
 929                         param->reg_AC2   = 0xCC009622 | trap_AC2;
 930                         break;
 931                 case AST_DRAM_4Gx16:
 932                         param->reg_AC2   = 0xCC00963F | trap_AC2;
 933                         break;
 934                 }
 935
 936                 break;
 937         case 456:
 938                 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
 939                 param->wodt          = 0;
 940                 param->reg_AC1       = 0x33302926;
 941                 param->reg_AC2       = 0xCD44961A;
 942                 param->reg_DQSIC     = 0x000000FC;
 943                 param->reg_MRS       = 0x00081830;
 944                 param->reg_EMRS      = 0x00000000;
 945                 param->reg_IOZ       = 0x00000045;
 946                 param->reg_DQIDLY    = 0x00000097;
 947                 param->reg_FREQ      = 0x000052C0;
 948                 param->madj_max      = 88;
 949                 param->dll2_finetune_step = 4;
 950                 break;
 951         case 504:
 952                 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
 953                 param->wodt          = 1;
 954                 param->reg_AC1       = 0x33302926;
 955                 param->reg_AC2       = 0xDE44A61D;
 956                 param->reg_DQSIC     = 0x00000117;
 957                 param->reg_MRS       = 0x00081A30;
 958                 param->reg_EMRS      = 0x00000000;
 959                 param->reg_IOZ       = 0x070000BB;
 960                 param->reg_DQIDLY    = 0x000000A0;
 961                 param->reg_FREQ      = 0x000054C0;
 962                 param->madj_max      = 79;
 963                 param->dll2_finetune_step = 4;
 964                 break;
 965         case 528:
 966                 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
 967                 param->wodt          = 1;
 968                 param->rodt          = 1;
 969                 param->reg_AC1       = 0x33302926;
 970                 param->reg_AC2       = 0xEF44B61E;
 971                 param->reg_DQSIC     = 0x00000125;
 972                 param->reg_MRS       = 0x00081A30;
 973                 param->reg_EMRS      = 0x00000040;
 974                 param->reg_DRV       = 0x000000F5;
 975                 param->reg_IOZ       = 0x00000023;
 976                 param->reg_DQIDLY    = 0x00000088;
 977                 param->reg_FREQ      = 0x000055C0;
 978                 param->madj_max      = 76;
 979                 param->dll2_finetune_step = 3;
 980                 break;
 981         case 576:
 982                 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
 983                 param->reg_MADJ      = 0x00136868;
 984                 param->reg_SADJ      = 0x00004534;
 985                 param->wodt          = 1;
 986                 param->rodt          = 1;
 987                 param->reg_AC1       = 0x33302A37;
 988                 param->reg_AC2       = 0xEF56B61E;
 989                 param->reg_DQSIC     = 0x0000013F;
 990                 param->reg_MRS       = 0x00101A50;
 991                 param->reg_EMRS      = 0x00000040;
 992                 param->reg_DRV       = 0x000000FA;
 993                 param->reg_IOZ       = 0x00000023;
 994                 param->reg_DQIDLY    = 0x00000078;
 995                 param->reg_FREQ      = 0x000057C0;
 996                 param->madj_max      = 136;
 997                 param->dll2_finetune_step = 3;
 998                 break;
 999         case 600:
1000                 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1001                 param->reg_MADJ      = 0x00136868;
1002                 param->reg_SADJ      = 0x00004534;
1003                 param->wodt          = 1;
1004                 param->rodt          = 1;
1005                 param->reg_AC1       = 0x32302A37;
1006                 param->reg_AC2       = 0xDF56B61F;
1007                 param->reg_DQSIC     = 0x0000014D;
1008                 param->reg_MRS       = 0x00101A50;
1009                 param->reg_EMRS      = 0x00000004;
1010                 param->reg_DRV       = 0x000000F5;
1011                 param->reg_IOZ       = 0x00000023;
1012                 param->reg_DQIDLY    = 0x00000078;
1013                 param->reg_FREQ      = 0x000058C0;
1014                 param->madj_max      = 132;
1015                 param->dll2_finetune_step = 3;
1016                 break;
1017         case 624:
1018                 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1019                 param->reg_MADJ      = 0x00136868;
1020                 param->reg_SADJ      = 0x00004534;
1021                 param->wodt          = 1;
1022                 param->rodt          = 1;
1023                 param->reg_AC1       = 0x32302A37;
1024                 param->reg_AC2       = 0xEF56B621;
1025                 param->reg_DQSIC     = 0x0000015A;
1026                 param->reg_MRS       = 0x02101A50;
1027                 param->reg_EMRS      = 0x00000004;
1028                 param->reg_DRV       = 0x000000F5;
1029                 param->reg_IOZ       = 0x00000034;
1030                 param->reg_DQIDLY    = 0x00000078;
1031                 param->reg_FREQ      = 0x000059C0;
1032                 param->madj_max      = 128;
1033                 param->dll2_finetune_step = 3;
1034                 break;
1035         } /* switch freq */
1036
1037         switch (param->dram_chipid) {
1038         case AST_DRAM_512Mx16:
1039                 param->dram_config = 0x130;
1040                 break;
1041         default:
1042         case AST_DRAM_1Gx16:
1043                 param->dram_config = 0x131;
1044                 break;
1045         case AST_DRAM_2Gx16:
1046                 param->dram_config = 0x132;
1047                 break;
1048         case AST_DRAM_4Gx16:
1049                 param->dram_config = 0x133;
1050                 break;
1051         } /* switch size */
1052
1053         switch (param->vram_size) {
1054         default:
1055         case AST_VIDMEM_SIZE_8M:
1056                 param->dram_config |= 0x00;
1057                 break;
1058         case AST_VIDMEM_SIZE_16M:
1059                 param->dram_config |= 0x04;
1060                 break;
1061         case AST_VIDMEM_SIZE_32M:
1062                 param->dram_config |= 0x08;
1063                 break;
1064         case AST_VIDMEM_SIZE_64M:
1065                 param->dram_config |= 0x0c;
1066                 break;
1067         }
1068
1069 }
1070
1071 static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param)
1072 {
1073         u32 data, data2, retry = 0;
1074
1075 ddr3_init_start:
1076         ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1077         ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1078         ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1079         ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1080         udelay(10);
1081         ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1082         ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1083         udelay(10);
1084         ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1085         udelay(10);
1086
1087         ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1088         ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1089         ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1090         ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1091         ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1092         ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1093         ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1094         ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1095         ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1096         ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1097         ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1098         ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1099         ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1100         ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1101         ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1102         ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1103         ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1104         ast_moutdwm(ast, 0x1E6E0054, 0);
1105         ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1106         ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1107         ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1108         ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1109         ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1110         ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1111         /* Wait MCLK2X lock to MCLK */
1112         do {
1113                 data = ast_mindwm(ast, 0x1E6E001C);
1114         } while (!(data & 0x08000000));
1115         data = ast_mindwm(ast, 0x1E6E001C);
1116         data = (data >> 8) & 0xff;
1117         while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1118                 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1119                 if ((data2 & 0xff) > param->madj_max) {
1120                         break;
1121                 }
1122                 ast_moutdwm(ast, 0x1E6E0064, data2);
1123                 if (data2 & 0x00100000) {
1124                         data2 = ((data2 & 0xff) >> 3) + 3;
1125                 } else {
1126                         data2 = ((data2 & 0xff) >> 2) + 5;
1127                 }
1128                 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1129                 data2 += data & 0xff;
1130                 data = data | (data2 << 8);
1131                 ast_moutdwm(ast, 0x1E6E0068, data);
1132                 udelay(10);
1133                 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1134                 udelay(10);
1135                 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1136                 ast_moutdwm(ast, 0x1E6E0018, data);
1137                 data = data | 0x200;
1138                 ast_moutdwm(ast, 0x1E6E0018, data);
1139                 do {
1140                         data = ast_mindwm(ast, 0x1E6E001C);
1141                 } while (!(data & 0x08000000));
1142
1143                 data = ast_mindwm(ast, 0x1E6E001C);
1144                 data = (data >> 8) & 0xff;
1145         }
1146         ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1147         data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1148         ast_moutdwm(ast, 0x1E6E0018, data);
1149
1150         ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1151         ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1152         udelay(50);
1153         /* Mode Register Setting */
1154         ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1155         ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1156         ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1157         ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1158         ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1159         ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1160         ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1161         ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1162         ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1163
1164         ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1165         data = 0;
1166         if (param->wodt) {
1167                 data = 0x300;
1168         }
1169         if (param->rodt) {
1170                 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1171         }
1172         ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1173
1174         /* Calibrate the DQSI delay */
1175         if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1176                 goto ddr3_init_start;
1177
1178         ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1179         /* ECC Memory Initialization */
1180 #ifdef ECC
1181         ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1182         ast_moutdwm(ast, 0x1E6E0070, 0x221);
1183         do {
1184                 data = ast_mindwm(ast, 0x1E6E0070);
1185         } while (!(data & 0x00001000));
1186         ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1187         ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1188         ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1189 #endif
1190
1191
1192 }
1193
1194 static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param)
1195 {
1196         u32 trap, trap_AC2, trap_MRS;
1197
1198         ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1199
1200         /* Ger trap info */
1201         trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1202         trap_AC2  = (trap << 20) | (trap << 16);
1203         trap_AC2 += 0x00110000;
1204         trap_MRS  = 0x00000040 | (trap << 4);
1205
1206
1207         param->reg_MADJ       = 0x00034C4C;
1208         param->reg_SADJ       = 0x00001800;
1209         param->reg_DRV        = 0x000000F0;
1210         param->reg_PERIOD     = param->dram_freq;
1211         param->rodt           = 0;
1212
1213         switch (param->dram_freq) {
1214         case 264:
1215                 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1216                 param->wodt          = 0;
1217                 param->reg_AC1       = 0x11101513;
1218                 param->reg_AC2       = 0x78117011;
1219                 param->reg_DQSIC     = 0x00000092;
1220                 param->reg_MRS       = 0x00000842;
1221                 param->reg_EMRS      = 0x00000000;
1222                 param->reg_DRV       = 0x000000F0;
1223                 param->reg_IOZ       = 0x00000034;
1224                 param->reg_DQIDLY    = 0x0000005A;
1225                 param->reg_FREQ      = 0x00004AC0;
1226                 param->madj_max      = 138;
1227                 param->dll2_finetune_step = 3;
1228                 break;
1229         case 336:
1230                 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1231                 param->wodt          = 1;
1232                 param->reg_AC1       = 0x22202613;
1233                 param->reg_AC2       = 0xAA009016 | trap_AC2;
1234                 param->reg_DQSIC     = 0x000000BA;
1235                 param->reg_MRS       = 0x00000A02 | trap_MRS;
1236                 param->reg_EMRS      = 0x00000040;
1237                 param->reg_DRV       = 0x000000FA;
1238                 param->reg_IOZ       = 0x00000034;
1239                 param->reg_DQIDLY    = 0x00000074;
1240                 param->reg_FREQ      = 0x00004DC0;
1241                 param->madj_max      = 96;
1242                 param->dll2_finetune_step = 3;
1243                 switch (param->dram_chipid) {
1244                 default:
1245                 case AST_DRAM_512Mx16:
1246                         param->reg_AC2   = 0xAA009012 | trap_AC2;
1247                         break;
1248                 case AST_DRAM_1Gx16:
1249                         param->reg_AC2   = 0xAA009016 | trap_AC2;
1250                         break;
1251                 case AST_DRAM_2Gx16:
1252                         param->reg_AC2   = 0xAA009023 | trap_AC2;
1253                         break;
1254                 case AST_DRAM_4Gx16:
1255                         param->reg_AC2   = 0xAA00903B | trap_AC2;
1256                         break;
1257                 }
1258                 break;
1259         default:
1260         case 396:
1261                 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1262                 param->wodt          = 1;
1263                 param->rodt          = 0;
1264                 param->reg_AC1       = 0x33302714;
1265                 param->reg_AC2       = 0xCC00B01B | trap_AC2;
1266                 param->reg_DQSIC     = 0x000000E2;
1267                 param->reg_MRS       = 0x00000C02 | trap_MRS;
1268                 param->reg_EMRS      = 0x00000040;
1269                 param->reg_DRV       = 0x000000FA;
1270                 param->reg_IOZ       = 0x00000034;
1271                 param->reg_DQIDLY    = 0x00000089;
1272                 param->reg_FREQ      = 0x00005040;
1273                 param->madj_max      = 96;
1274                 param->dll2_finetune_step = 4;
1275
1276                 switch (param->dram_chipid) {
1277                 case AST_DRAM_512Mx16:
1278                         param->reg_AC2   = 0xCC00B016 | trap_AC2;
1279                         break;
1280                 default:
1281                 case AST_DRAM_1Gx16:
1282                         param->reg_AC2   = 0xCC00B01B | trap_AC2;
1283                         break;
1284                 case AST_DRAM_2Gx16:
1285                         param->reg_AC2   = 0xCC00B02B | trap_AC2;
1286                         break;
1287                 case AST_DRAM_4Gx16:
1288                         param->reg_AC2   = 0xCC00B03F | trap_AC2;
1289                         break;
1290                 }
1291
1292                 break;
1293
1294         case 408:
1295                 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1296                 param->wodt          = 1;
1297                 param->rodt          = 0;
1298                 param->reg_AC1       = 0x33302714;
1299                 param->reg_AC2       = 0xCC00B01B | trap_AC2;
1300                 param->reg_DQSIC     = 0x000000E2;
1301                 param->reg_MRS       = 0x00000C02 | trap_MRS;
1302                 param->reg_EMRS      = 0x00000040;
1303                 param->reg_DRV       = 0x000000FA;
1304                 param->reg_IOZ       = 0x00000034;
1305                 param->reg_DQIDLY    = 0x00000089;
1306                 param->reg_FREQ      = 0x000050C0;
1307                 param->madj_max      = 96;
1308                 param->dll2_finetune_step = 4;
1309
1310                 switch (param->dram_chipid) {
1311                 case AST_DRAM_512Mx16:
1312                         param->reg_AC2   = 0xCC00B016 | trap_AC2;
1313                         break;
1314                 default:
1315                 case AST_DRAM_1Gx16:
1316                         param->reg_AC2   = 0xCC00B01B | trap_AC2;
1317                         break;
1318                 case AST_DRAM_2Gx16:
1319                         param->reg_AC2   = 0xCC00B02B | trap_AC2;
1320                         break;
1321                 case AST_DRAM_4Gx16:
1322                         param->reg_AC2   = 0xCC00B03F | trap_AC2;
1323                         break;
1324                 }
1325
1326                 break;
1327         case 456:
1328                 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1329                 param->wodt          = 0;
1330                 param->reg_AC1       = 0x33302815;
1331                 param->reg_AC2       = 0xCD44B01E;
1332                 param->reg_DQSIC     = 0x000000FC;
1333                 param->reg_MRS       = 0x00000E72;
1334                 param->reg_EMRS      = 0x00000000;
1335                 param->reg_DRV       = 0x00000000;
1336                 param->reg_IOZ       = 0x00000034;
1337                 param->reg_DQIDLY    = 0x00000097;
1338                 param->reg_FREQ      = 0x000052C0;
1339                 param->madj_max      = 88;
1340                 param->dll2_finetune_step = 3;
1341                 break;
1342         case 504:
1343                 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1344                 param->wodt          = 1;
1345                 param->rodt          = 1;
1346                 param->reg_AC1       = 0x33302815;
1347                 param->reg_AC2       = 0xDE44C022;
1348                 param->reg_DQSIC     = 0x00000117;
1349                 param->reg_MRS       = 0x00000E72;
1350                 param->reg_EMRS      = 0x00000040;
1351                 param->reg_DRV       = 0x0000000A;
1352                 param->reg_IOZ       = 0x00000045;
1353                 param->reg_DQIDLY    = 0x000000A0;
1354                 param->reg_FREQ      = 0x000054C0;
1355                 param->madj_max      = 79;
1356                 param->dll2_finetune_step = 3;
1357                 break;
1358         case 528:
1359                 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1360                 param->wodt          = 1;
1361                 param->rodt          = 1;
1362                 param->reg_AC1       = 0x33302815;
1363                 param->reg_AC2       = 0xEF44D024;
1364                 param->reg_DQSIC     = 0x00000125;
1365                 param->reg_MRS       = 0x00000E72;
1366                 param->reg_EMRS      = 0x00000004;
1367                 param->reg_DRV       = 0x000000F9;
1368                 param->reg_IOZ       = 0x00000045;
1369                 param->reg_DQIDLY    = 0x000000A7;
1370                 param->reg_FREQ      = 0x000055C0;
1371                 param->madj_max      = 76;
1372                 param->dll2_finetune_step = 3;
1373                 break;
1374         case 552:
1375                 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1376                 param->wodt          = 1;
1377                 param->rodt          = 1;
1378                 param->reg_AC1       = 0x43402915;
1379                 param->reg_AC2       = 0xFF44E025;
1380                 param->reg_DQSIC     = 0x00000132;
1381                 param->reg_MRS       = 0x00000E72;
1382                 param->reg_EMRS      = 0x00000040;
1383                 param->reg_DRV       = 0x0000000A;
1384                 param->reg_IOZ       = 0x00000045;
1385                 param->reg_DQIDLY    = 0x000000AD;
1386                 param->reg_FREQ      = 0x000056C0;
1387                 param->madj_max      = 76;
1388                 param->dll2_finetune_step = 3;
1389                 break;
1390         case 576:
1391                 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1392                 param->wodt          = 1;
1393                 param->rodt          = 1;
1394                 param->reg_AC1       = 0x43402915;
1395                 param->reg_AC2       = 0xFF44E027;
1396                 param->reg_DQSIC     = 0x0000013F;
1397                 param->reg_MRS       = 0x00000E72;
1398                 param->reg_EMRS      = 0x00000004;
1399                 param->reg_DRV       = 0x000000F5;
1400                 param->reg_IOZ       = 0x00000045;
1401                 param->reg_DQIDLY    = 0x000000B3;
1402                 param->reg_FREQ      = 0x000057C0;
1403                 param->madj_max      = 76;
1404                 param->dll2_finetune_step = 3;
1405                 break;
1406         }
1407
1408         switch (param->dram_chipid) {
1409         case AST_DRAM_512Mx16:
1410                 param->dram_config = 0x100;
1411                 break;
1412         default:
1413         case AST_DRAM_1Gx16:
1414                 param->dram_config = 0x121;
1415                 break;
1416         case AST_DRAM_2Gx16:
1417                 param->dram_config = 0x122;
1418                 break;
1419         case AST_DRAM_4Gx16:
1420                 param->dram_config = 0x123;
1421                 break;
1422         } /* switch size */
1423
1424         switch (param->vram_size) {
1425         default:
1426         case AST_VIDMEM_SIZE_8M:
1427                 param->dram_config |= 0x00;
1428                 break;
1429         case AST_VIDMEM_SIZE_16M:
1430                 param->dram_config |= 0x04;
1431                 break;
1432         case AST_VIDMEM_SIZE_32M:
1433                 param->dram_config |= 0x08;
1434                 break;
1435         case AST_VIDMEM_SIZE_64M:
1436                 param->dram_config |= 0x0c;
1437                 break;
1438         }
1439 }
1440
1441 static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param)
1442 {
1443         u32 data, data2, retry = 0;
1444
1445 ddr2_init_start:
1446         ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1447         ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1448         ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1449         ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1450         ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1451         udelay(10);
1452         ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1453         udelay(10);
1454
1455         ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1456         ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1457         ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1458         ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1459         ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1460         ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1461         ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1462         ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1463         ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1464         ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1465         ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1466         ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1467         ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1468         ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1469         ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1470         ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1471         ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1472         ast_moutdwm(ast, 0x1E6E0054, 0);
1473         ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1474         ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1475         ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1476         ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1477         ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1478         ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1479
1480         /* Wait MCLK2X lock to MCLK */
1481         do {
1482                 data = ast_mindwm(ast, 0x1E6E001C);
1483         } while (!(data & 0x08000000));
1484         data = ast_mindwm(ast, 0x1E6E001C);
1485         data = (data >> 8) & 0xff;
1486         while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1487                 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1488                 if ((data2 & 0xff) > param->madj_max) {
1489                         break;
1490                 }
1491                 ast_moutdwm(ast, 0x1E6E0064, data2);
1492                 if (data2 & 0x00100000) {
1493                         data2 = ((data2 & 0xff) >> 3) + 3;
1494                 } else {
1495                         data2 = ((data2 & 0xff) >> 2) + 5;
1496                 }
1497                 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1498                 data2 += data & 0xff;
1499                 data = data | (data2 << 8);
1500                 ast_moutdwm(ast, 0x1E6E0068, data);
1501                 udelay(10);
1502                 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1503                 udelay(10);
1504                 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1505                 ast_moutdwm(ast, 0x1E6E0018, data);
1506                 data = data | 0x200;
1507                 ast_moutdwm(ast, 0x1E6E0018, data);
1508                 do {
1509                         data = ast_mindwm(ast, 0x1E6E001C);
1510                 } while (!(data & 0x08000000));
1511
1512                 data = ast_mindwm(ast, 0x1E6E001C);
1513                 data = (data >> 8) & 0xff;
1514         }
1515         ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1516         data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1517         ast_moutdwm(ast, 0x1E6E0018, data);
1518
1519         ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1520         ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1521         udelay(50);
1522         /* Mode Register Setting */
1523         ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1524         ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1525         ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1526         ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1527         ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1528         ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1529
1530         ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1531         ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1532         ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1533         ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1534         ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1535         ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1536         ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1537
1538         ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1539         data = 0;
1540         if (param->wodt) {
1541                 data = 0x500;
1542         }
1543         if (param->rodt) {
1544                 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1545         }
1546         ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1547         ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1548
1549         /* Calibrate the DQSI delay */
1550         if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1551                 goto ddr2_init_start;
1552
1553         /* ECC Memory Initialization */
1554 #ifdef ECC
1555         ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1556         ast_moutdwm(ast, 0x1E6E0070, 0x221);
1557         do {
1558                 data = ast_mindwm(ast, 0x1E6E0070);
1559         } while (!(data & 0x00001000));
1560         ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1561         ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1562         ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1563 #endif
1564
1565 }
1566
1567 static void ast_post_chip_2300(struct ast_device *ast)
1568 {
1569         struct ast2300_dram_param param;
1570         u32 temp;
1571         u8 reg;
1572
1573         reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1574         if ((reg & 0x80) == 0) {/* vga only */
1575                 ast_write32(ast, 0xf004, 0x1e6e0000);
1576                 ast_write32(ast, 0xf000, 0x1);
1577                 ast_write32(ast, 0x12000, 0x1688a8a8);
1578                 do {
1579                         ;
1580                 } while (ast_read32(ast, 0x12000) != 0x1);
1581
1582                 ast_write32(ast, 0x10000, 0xfc600309);
1583                 do {
1584                         ;
1585                 } while (ast_read32(ast, 0x10000) != 0x1);
1586
1587                 /* Slow down CPU/AHB CLK in VGA only mode */
1588                 temp = ast_read32(ast, 0x12008);
1589                 temp |= 0x73;
1590                 ast_write32(ast, 0x12008, temp);
1591
1592                 param.dram_freq = 396;
1593                 param.dram_type = AST_DDR3;
1594                 temp = ast_mindwm(ast, 0x1e6e2070);
1595                 if (temp & 0x01000000)
1596                         param.dram_type = AST_DDR2;
1597                 switch (temp & 0x18000000) {
1598                 case 0:
1599                         param.dram_chipid = AST_DRAM_512Mx16;
1600                         break;
1601                 default:
1602                 case 0x08000000:
1603                         param.dram_chipid = AST_DRAM_1Gx16;
1604                         break;
1605                 case 0x10000000:
1606                         param.dram_chipid = AST_DRAM_2Gx16;
1607                         break;
1608                 case 0x18000000:
1609                         param.dram_chipid = AST_DRAM_4Gx16;
1610                         break;
1611                 }
1612                 switch (temp & 0x0c) {
1613                 default:
1614                 case 0x00:
1615                         param.vram_size = AST_VIDMEM_SIZE_8M;
1616                         break;
1617
1618                 case 0x04:
1619                         param.vram_size = AST_VIDMEM_SIZE_16M;
1620                         break;
1621
1622                 case 0x08:
1623                         param.vram_size = AST_VIDMEM_SIZE_32M;
1624                         break;
1625
1626                 case 0x0c:
1627                         param.vram_size = AST_VIDMEM_SIZE_64M;
1628                         break;
1629                 }
1630
1631                 if (param.dram_type == AST_DDR3) {
1632                         get_ddr3_info(ast, &param);
1633                         ddr3_init(ast, &param);
1634                 } else {
1635                         get_ddr2_info(ast, &param);
1636                         ddr2_init(ast, &param);
1637                 }
1638
1639                 temp = ast_mindwm(ast, 0x1e6e2040);
1640                 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1641         }
1642
1643         /* wait ready */
1644         do {
1645                 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1646         } while ((reg & 0x40) == 0);
1647 }
1648
1649 static bool cbr_test_2500(struct ast_device *ast)
1650 {
1651         ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1652         ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1653         if (!mmc_test_burst(ast, 0))
1654                 return false;
1655         if (!mmc_test_single_2500(ast, 0))
1656                 return false;
1657         return true;
1658 }
1659
1660 static bool ddr_test_2500(struct ast_device *ast)
1661 {
1662         ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1663         ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1664         if (!mmc_test_burst(ast, 0))
1665                 return false;
1666         if (!mmc_test_burst(ast, 1))
1667                 return false;
1668         if (!mmc_test_burst(ast, 2))
1669                 return false;
1670         if (!mmc_test_burst(ast, 3))
1671                 return false;
1672         if (!mmc_test_single_2500(ast, 0))
1673                 return false;
1674         return true;
1675 }
1676
1677 static void ddr_init_common_2500(struct ast_device *ast)
1678 {
1679         ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1680         ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1681         ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1682         ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1683         ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1684         ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1685         ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1686         ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1687         ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1688         ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1689         ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1690         ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1691         ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1692         ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1693         ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1694         ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1695         ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1696         ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1697         ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1698 }
1699
1700 static void ddr_phy_init_2500(struct ast_device *ast)
1701 {
1702         u32 data, pass, timecnt;
1703
1704         pass = 0;
1705         ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1706         while (!pass) {
1707                 for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
1708                         data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1709                         if (!data)
1710                                 break;
1711                 }
1712                 if (timecnt != TIMEOUT) {
1713                         data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1714                         if (!data)
1715                                 pass = 1;
1716                 }
1717                 if (!pass) {
1718                         ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1719                         udelay(10); /* delay 10 us */
1720                         ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1721                 }
1722         }
1723
1724         ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1725 }
1726
1727 /*
1728  * Check DRAM Size
1729  * 1Gb : 0x80000000 ~ 0x87FFFFFF
1730  * 2Gb : 0x80000000 ~ 0x8FFFFFFF
1731  * 4Gb : 0x80000000 ~ 0x9FFFFFFF
1732  * 8Gb : 0x80000000 ~ 0xBFFFFFFF
1733  */
1734 static void check_dram_size_2500(struct ast_device *ast, u32 tRFC)
1735 {
1736         u32 reg_04, reg_14;
1737
1738         reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1739         reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1740
1741         ast_moutdwm(ast, 0xA0100000, 0x41424344);
1742         ast_moutdwm(ast, 0x90100000, 0x35363738);
1743         ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1744         ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1745
1746         /* Check 8Gbit */
1747         if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1748                 reg_04 |= 0x03;
1749                 reg_14 |= (tRFC >> 24) & 0xFF;
1750                 /* Check 4Gbit */
1751         } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1752                 reg_04 |= 0x02;
1753                 reg_14 |= (tRFC >> 16) & 0xFF;
1754                 /* Check 2Gbit */
1755         } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1756                 reg_04 |= 0x01;
1757                 reg_14 |= (tRFC >> 8) & 0xFF;
1758         } else {
1759                 reg_14 |= tRFC & 0xFF;
1760         }
1761         ast_moutdwm(ast, 0x1E6E0004, reg_04);
1762         ast_moutdwm(ast, 0x1E6E0014, reg_14);
1763 }
1764
1765 static void enable_cache_2500(struct ast_device *ast)
1766 {
1767         u32 reg_04, data;
1768
1769         reg_04 = ast_mindwm(ast, 0x1E6E0004);
1770         ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1771
1772         do
1773                 data = ast_mindwm(ast, 0x1E6E0004);
1774         while (!(data & 0x80000));
1775         ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1776 }
1777
1778 static void set_mpll_2500(struct ast_device *ast)
1779 {
1780         u32 addr, data, param;
1781
1782         /* Reset MMC */
1783         ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1784         ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1785         for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
1786                 ast_moutdwm(ast, addr, 0x0);
1787                 addr += 4;
1788         }
1789         ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1790
1791         ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1792         data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1793         if (data) {
1794                 /* CLKIN = 25MHz */
1795                 param = 0x930023E0;
1796                 ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1797         } else {
1798                 /* CLKIN = 24MHz */
1799                 param = 0x93002400;
1800         }
1801         ast_moutdwm(ast, 0x1E6E2020, param);
1802         udelay(100);
1803 }
1804
1805 static void reset_mmc_2500(struct ast_device *ast)
1806 {
1807         ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1808         ast_moutdwm(ast, 0x1E785044, 0x00000001);
1809         ast_moutdwm(ast, 0x1E785048, 0x00004755);
1810         ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1811         mdelay(100);
1812         ast_moutdwm(ast, 0x1E785054, 0x00000077);
1813         ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1814 }
1815
1816 static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table)
1817 {
1818
1819         ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1820         ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1821         ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1822         ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1823         ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);         /* MODEREG4/6 */
1824         ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);         /* MODEREG5 */
1825         ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1826         ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);         /* MODEREG1/3 */
1827
1828         /* DDR PHY Setting */
1829         ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1830         ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1831         ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1832         ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1833         ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1834         ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1835         ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1836         ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1837         ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1838         ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1839         ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1840         ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1841         ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1842         ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1843
1844         /* Controller Setting */
1845         ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1846
1847         /* Wait DDR PHY init done */
1848         ddr_phy_init_2500(ast);
1849
1850         ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1851         ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1852         ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1853
1854         check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1855         enable_cache_2500(ast);
1856         ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1857         ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1858 }
1859
1860 static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table)
1861 {
1862         u32 data, data2, pass, retrycnt;
1863         u32 ddr_vref, phy_vref;
1864         u32 min_ddr_vref = 0, min_phy_vref = 0;
1865         u32 max_ddr_vref = 0, max_phy_vref = 0;
1866
1867         ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1868         ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1869         ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1870         ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1871         ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]);         /* MODEREG4/6 */
1872         ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]);         /* MODEREG5 */
1873         ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1874         ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]);         /* MODEREG1/3 */
1875
1876         /* DDR PHY Setting */
1877         ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1878         ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1879         ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1880         ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1881         ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1882         ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1883         ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1884         ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1885         ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1886         ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1887         ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1888         ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1889         ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1890         ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1891         ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1892
1893         /* Controller Setting */
1894         ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1895
1896         /* Train PHY Vref first */
1897         pass = 0;
1898
1899         for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1900                 max_phy_vref = 0x0;
1901                 pass = 0;
1902                 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1903                 for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
1904                         ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1905                         ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1906                         ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1907                         /* Fire DFI Init */
1908                         ddr_phy_init_2500(ast);
1909                         ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1910                         if (cbr_test_2500(ast)) {
1911                                 pass++;
1912                                 data = ast_mindwm(ast, 0x1E6E03D0);
1913                                 data2 = data >> 8;
1914                                 data  = data & 0xff;
1915                                 if (data > data2)
1916                                         data = data2;
1917                                 if (max_phy_vref < data) {
1918                                         max_phy_vref = data;
1919                                         min_phy_vref = phy_vref;
1920                                 }
1921                         } else if (pass > 0)
1922                                 break;
1923                 }
1924         }
1925         ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1926
1927         /* Train DDR Vref next */
1928         pass = 0;
1929
1930         for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1931                 min_ddr_vref = 0xFF;
1932                 max_ddr_vref = 0x0;
1933                 pass = 0;
1934                 for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
1935                         ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1936                         ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1937                         ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1938                         /* Fire DFI Init */
1939                         ddr_phy_init_2500(ast);
1940                         ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1941                         if (cbr_test_2500(ast)) {
1942                                 pass++;
1943                                 if (min_ddr_vref > ddr_vref)
1944                                         min_ddr_vref = ddr_vref;
1945                                 if (max_ddr_vref < ddr_vref)
1946                                         max_ddr_vref = ddr_vref;
1947                         } else if (pass != 0)
1948                                 break;
1949                 }
1950         }
1951
1952         ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1953         ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1954         ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
1955         ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1956
1957         /* Wait DDR PHY init done */
1958         ddr_phy_init_2500(ast);
1959
1960         ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1961         ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1962         ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1963
1964         check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1965         enable_cache_2500(ast);
1966         ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1967         ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1968 }
1969
1970 static bool ast_dram_init_2500(struct ast_device *ast)
1971 {
1972         u32 data;
1973         u32 max_tries = 5;
1974
1975         do {
1976                 if (max_tries-- == 0)
1977                         return false;
1978                 set_mpll_2500(ast);
1979                 reset_mmc_2500(ast);
1980                 ddr_init_common_2500(ast);
1981
1982                 data = ast_mindwm(ast, 0x1E6E2070);
1983                 if (data & 0x01000000)
1984                         ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
1985                 else
1986                         ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
1987         } while (!ddr_test_2500(ast));
1988
1989         ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
1990
1991         /* Patch code */
1992         data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
1993         ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
1994
1995         return true;
1996 }
1997
1998 void ast_patch_ahb_2500(void __iomem *regs)
1999 {
2000         u32 data;
2001
2002         /* Clear bus lock condition */
2003         __ast_moutdwm(regs, 0x1e600000, 0xAEED1A03);
2004         __ast_moutdwm(regs, 0x1e600084, 0x00010000);
2005         __ast_moutdwm(regs, 0x1e600088, 0x00000000);
2006         __ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
2007
2008         data = __ast_mindwm(regs, 0x1e6e2070);
2009         if (data & 0x08000000) { /* check fast reset */
2010                 /*
2011                  * If "Fast restet" is enabled for ARM-ICE debugger,
2012                  * then WDT needs to enable, that
2013                  * WDT04 is WDT#1 Reload reg.
2014                  * WDT08 is WDT#1 counter restart reg to avoid system deadlock
2015                  * WDT0C is WDT#1 control reg
2016                  *      [6:5]:= 01:Full chip
2017                  *      [4]:= 1:1MHz clock source
2018                  *      [1]:= 1:WDT will be cleeared and disabled after timeout occurs
2019                  *      [0]:= 1:WDT enable
2020                  */
2021                 __ast_moutdwm(regs, 0x1E785004, 0x00000010);
2022                 __ast_moutdwm(regs, 0x1E785008, 0x00004755);
2023                 __ast_moutdwm(regs, 0x1E78500c, 0x00000033);
2024                 udelay(1000);
2025         }
2026
2027         do {
2028                 __ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
2029                 data = __ast_mindwm(regs, 0x1e6e2000);
2030         } while (data != 1);
2031
2032         __ast_moutdwm(regs, 0x1e6e207c, 0x08000000); /* clear fast reset */
2033 }
2034
2035 void ast_post_chip_2500(struct ast_device *ast)
2036 {
2037         struct drm_device *dev = &ast->base;
2038         u32 temp;
2039         u8 reg;
2040
2041         reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
2042         if ((reg & AST_VRAM_INIT_STATUS_MASK) == 0) {/* vga only */
2043                 /* Clear bus lock condition */
2044                 ast_patch_ahb_2500(ast->regs);
2045
2046                 /* Disable watchdog */
2047                 ast_moutdwm(ast, 0x1E78502C, 0x00000000);
2048                 ast_moutdwm(ast, 0x1E78504C, 0x00000000);
2049
2050                 /*
2051                  * Reset USB port to patch USB unknown device issue
2052                  * SCU90 is Multi-function Pin Control #5
2053                  *      [29]:= 1:Enable USB2.0 Host port#1 (that the mutually shared USB2.0 Hub
2054                  *                              port).
2055                  * SCU94 is Multi-function Pin Control #6
2056                  *      [14:13]:= 1x:USB2.0 Host2 controller
2057                  * SCU70 is Hardware Strap reg
2058                  *      [23]:= 1:CLKIN is 25MHz and USBCK1 = 24/48 MHz (determined by
2059                  *                              [18]: 0(24)/1(48) MHz)
2060                  * SCU7C is Write clear reg to SCU70
2061                  *      [23]:= write 1 and then SCU70[23] will be clear as 0b.
2062                  */
2063                 ast_moutdwm(ast, 0x1E6E2090, 0x20000000);
2064                 ast_moutdwm(ast, 0x1E6E2094, 0x00004000);
2065                 if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) {
2066                         ast_moutdwm(ast, 0x1E6E207C, 0x00800000);
2067                         mdelay(100);
2068                         ast_moutdwm(ast, 0x1E6E2070, 0x00800000);
2069                 }
2070                 /* Modify eSPI reset pin */
2071                 temp = ast_mindwm(ast, 0x1E6E2070);
2072                 if (temp & 0x02000000)
2073                         ast_moutdwm(ast, 0x1E6E207C, 0x00004000);
2074
2075                 /* Slow down CPU/AHB CLK in VGA only mode */
2076                 temp = ast_read32(ast, 0x12008);
2077                 temp |= 0x73;
2078                 ast_write32(ast, 0x12008, temp);
2079
2080                 if (!ast_dram_init_2500(ast))
2081                         drm_err(dev, "DRAM init failed !\n");
2082
2083                 temp = ast_mindwm(ast, 0x1e6e2040);
2084                 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
2085         }
2086
2087         /* wait ready */
2088         do {
2089                 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
2090         } while ((reg & 0x40) == 0);
2091 }