drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33
  34 #include <linux/vga_switcheroo.h>
  35 #include <linux/slab.h>
  36 #include <linux/pm_runtime.h>
  37 #include "amdgpu_amdkfd.h"
  38
  39 /**
  40  * amdgpu_driver_unload_kms - Main unload function for KMS.
  41  *
  42  * @dev: drm dev pointer
  43  *
  44  * This is the main unload function for KMS (all asics).
  45  * Returns 0 on success.
  46  */
  47 void amdgpu_driver_unload_kms(struct drm_device *dev)
  48 {
  49         struct amdgpu_device *adev = dev->dev_private;
  50
  51         if (adev == NULL)
  52                 return;
  53
  54         if (adev->rmmio == NULL)
  55                 goto done_free;
  56
  57         if (amdgpu_sriov_vf(adev))
  58                 amdgpu_virt_request_full_gpu(adev, false);
  59
  60         if (amdgpu_device_is_px(dev)) {
  61                 pm_runtime_get_sync(dev->dev);
  62                 pm_runtime_forbid(dev->dev);
  63         }
  64
  65         amdgpu_amdkfd_device_fini(adev);
  66
  67         amdgpu_acpi_fini(adev);
  68
  69         amdgpu_device_fini(adev);
  70
  71 done_free:
  72         kfree(adev);
  73         dev->dev_private = NULL;
  74 }
  75
  76 /**
  77  * amdgpu_driver_load_kms - Main load function for KMS.
  78  *
  79  * @dev: drm dev pointer
  80  * @flags: device flags
  81  *
  82  * This is the main load function for KMS (all asics).
  83  * Returns 0 on success, error on failure.
  84  */
  85 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
  86 {
  87         struct amdgpu_device *adev;
  88         int r, acpi_status;
  89
  90 #ifdef CONFIG_DRM_AMDGPU_SI
  91         if (!amdgpu_si_support) {
  92                 switch (flags & AMD_ASIC_MASK) {
  93                 case CHIP_TAHITI:
  94                 case CHIP_PITCAIRN:
  95                 case CHIP_VERDE:
  96                 case CHIP_OLAND:
  97                 case CHIP_HAINAN:
  98                         dev_info(dev->dev,
  99                                  "SI support provided by radeon.\n");
 100                         dev_info(dev->dev,
 101                 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
 102                                 );
 103                         return -ENODEV;
 104                 }
 105         }
 106 #endif
 107 #ifdef CONFIG_DRM_AMDGPU_CIK
 108         if (!amdgpu_cik_support) {
 109                 switch (flags & AMD_ASIC_MASK) {
 110                 case CHIP_KAVERI:
 111                 case CHIP_BONAIRE:
 112                 case CHIP_HAWAII:
 113                 case CHIP_KABINI:
 114                 case CHIP_MULLINS:
 115                         dev_info(dev->dev,
 116                                  "CIK support disabled by module param\n");
 117                         return -ENODEV;
 118                 }
 119         }
 120 #endif
 121
 122         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 123         if (adev == NULL) {
 124                 return -ENOMEM;
 125         }
 126         dev->dev_private = (void *)adev;
 127
 128         if ((amdgpu_runtime_pm != 0) &&
 129             amdgpu_has_atpx() &&
 130             (amdgpu_is_atpx_hybrid() ||
 131              amdgpu_has_atpx_dgpu_power_cntl()) &&
 132             ((flags & AMD_IS_APU) == 0) &&
 133             !pci_is_thunderbolt_attached(dev->pdev))
 134                 flags |= AMD_IS_PX;
 135
 136         /* amdgpu_device_init should report only fatal error
 137          * like memory allocation failure or iomapping failure,
 138          * or memory manager initialization failure, it must
 139          * properly initialize the GPU MC controller and permit
 140          * VRAM allocation
 141          */
 142         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 143         if (r) {
 144                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 145                 goto out;
 146         }
 147
 148         /* Call ACPI methods: require modeset init
 149          * but failure is not fatal
 150          */
 151         if (!r) {
 152                 acpi_status = amdgpu_acpi_init(adev);
 153                 if (acpi_status)
 154                 dev_dbg(&dev->pdev->dev,
 155                                 "Error during ACPI methods call\n");
 156         }
 157
 158         amdgpu_amdkfd_load_interface(adev);
 159         amdgpu_amdkfd_device_probe(adev);
 160         amdgpu_amdkfd_device_init(adev);
 161
 162         if (amdgpu_device_is_px(dev)) {
 163                 pm_runtime_use_autosuspend(dev->dev);
 164                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 165                 pm_runtime_set_active(dev->dev);
 166                 pm_runtime_allow(dev->dev);
 167                 pm_runtime_mark_last_busy(dev->dev);
 168                 pm_runtime_put_autosuspend(dev->dev);
 169         }
 170
 171         if (amdgpu_sriov_vf(adev))
 172                 amdgpu_virt_release_full_gpu(adev, true);
 173
 174 out:
 175         if (r) {
 176                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 177                 if (adev->rmmio && amdgpu_device_is_px(dev))
 178                         pm_runtime_put_noidle(dev->dev);
 179                 amdgpu_driver_unload_kms(dev);
 180         }
 181
 182         return r;
 183 }
 184
 185 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 186                                 struct drm_amdgpu_query_fw *query_fw,
 187                                 struct amdgpu_device *adev)
 188 {
 189         switch (query_fw->fw_type) {
 190         case AMDGPU_INFO_FW_VCE:
 191                 fw_info->ver = adev->vce.fw_version;
 192                 fw_info->feature = adev->vce.fb_version;
 193                 break;
 194         case AMDGPU_INFO_FW_UVD:
 195                 fw_info->ver = adev->uvd.fw_version;
 196                 fw_info->feature = 0;
 197                 break;
 198         case AMDGPU_INFO_FW_GMC:
 199                 fw_info->ver = adev->mc.fw_version;
 200                 fw_info->feature = 0;
 201                 break;
 202         case AMDGPU_INFO_FW_GFX_ME:
 203                 fw_info->ver = adev->gfx.me_fw_version;
 204                 fw_info->feature = adev->gfx.me_feature_version;
 205                 break;
 206         case AMDGPU_INFO_FW_GFX_PFP:
 207                 fw_info->ver = adev->gfx.pfp_fw_version;
 208                 fw_info->feature = adev->gfx.pfp_feature_version;
 209                 break;
 210         case AMDGPU_INFO_FW_GFX_CE:
 211                 fw_info->ver = adev->gfx.ce_fw_version;
 212                 fw_info->feature = adev->gfx.ce_feature_version;
 213                 break;
 214         case AMDGPU_INFO_FW_GFX_RLC:
 215                 fw_info->ver = adev->gfx.rlc_fw_version;
 216                 fw_info->feature = adev->gfx.rlc_feature_version;
 217                 break;
 218         case AMDGPU_INFO_FW_GFX_MEC:
 219                 if (query_fw->index == 0) {
 220                         fw_info->ver = adev->gfx.mec_fw_version;
 221                         fw_info->feature = adev->gfx.mec_feature_version;
 222                 } else if (query_fw->index == 1) {
 223                         fw_info->ver = adev->gfx.mec2_fw_version;
 224                         fw_info->feature = adev->gfx.mec2_feature_version;
 225                 } else
 226                         return -EINVAL;
 227                 break;
 228         case AMDGPU_INFO_FW_SMC:
 229                 fw_info->ver = adev->pm.fw_version;
 230                 fw_info->feature = 0;
 231                 break;
 232         case AMDGPU_INFO_FW_SDMA:
 233                 if (query_fw->index >= adev->sdma.num_instances)
 234                         return -EINVAL;
 235                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 236                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 237                 break;
 238         case AMDGPU_INFO_FW_SOS:
 239                 fw_info->ver = adev->psp.sos_fw_version;
 240                 fw_info->feature = adev->psp.sos_feature_version;
 241                 break;
 242         case AMDGPU_INFO_FW_ASD:
 243                 fw_info->ver = adev->psp.asd_fw_version;
 244                 fw_info->feature = adev->psp.asd_feature_version;
 245                 break;
 246         default:
 247                 return -EINVAL;
 248         }
 249         return 0;
 250 }
 251
 252 /*
 253  * Userspace get information ioctl
 254  */
 255 /**
 256  * amdgpu_info_ioctl - answer a device specific request.
 257  *
 258  * @adev: amdgpu device pointer
 259  * @data: request object
 260  * @filp: drm filp
 261  *
 262  * This function is used to pass device specific parameters to the userspace
 263  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 264  * etc. (all asics).
 265  * Returns 0 on success, -EINVAL on failure.
 266  */
 267 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 268 {
 269         struct amdgpu_device *adev = dev->dev_private;
 270         struct amdgpu_fpriv *fpriv = filp->driver_priv;
 271         struct drm_amdgpu_info *info = data;
 272         struct amdgpu_mode_info *minfo = &adev->mode_info;
 273         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 274         uint32_t size = info->return_size;
 275         struct drm_crtc *crtc;
 276         uint32_t ui32 = 0;
 277         uint64_t ui64 = 0;
 278         int i, found;
 279         int ui32_size = sizeof(ui32);
 280
 281         if (!info->return_size || !info->return_pointer)
 282                 return -EINVAL;
 283         if (amdgpu_kms_vram_lost(adev, fpriv))
 284                 return -ENODEV;
 285
 286         switch (info->query) {
 287         case AMDGPU_INFO_ACCEL_WORKING:
 288                 ui32 = adev->accel_working;
 289                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 290         case AMDGPU_INFO_CRTC_FROM_ID:
 291                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 292                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 293                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 294                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 295                                 ui32 = amdgpu_crtc->crtc_id;
 296                                 found = 1;
 297                                 break;
 298                         }
 299                 }
 300                 if (!found) {
 301                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 302                         return -EINVAL;
 303                 }
 304                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 305         case AMDGPU_INFO_HW_IP_INFO: {
 306                 struct drm_amdgpu_info_hw_ip ip = {};
 307                 enum amd_ip_block_type type;
 308                 uint32_t ring_mask = 0;
 309                 uint32_t ib_start_alignment = 0;
 310                 uint32_t ib_size_alignment = 0;
 311
 312                 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 313                         return -EINVAL;
 314
 315                 switch (info->query_hw_ip.type) {
 316                 case AMDGPU_HW_IP_GFX:
 317                         type = AMD_IP_BLOCK_TYPE_GFX;
 318                         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 319                                 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
 320                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 321                         ib_size_alignment = 8;
 322                         break;
 323                 case AMDGPU_HW_IP_COMPUTE:
 324                         type = AMD_IP_BLOCK_TYPE_GFX;
 325                         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 326                                 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
 327                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 328                         ib_size_alignment = 8;
 329                         break;
 330                 case AMDGPU_HW_IP_DMA:
 331                         type = AMD_IP_BLOCK_TYPE_SDMA;
 332                         for (i = 0; i < adev->sdma.num_instances; i++)
 333                                 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
 334                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 335                         ib_size_alignment = 1;
 336                         break;
 337                 case AMDGPU_HW_IP_UVD:
 338                         type = AMD_IP_BLOCK_TYPE_UVD;
 339                         ring_mask = adev->uvd.ring.ready ? 1 : 0;
 340                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 341                         ib_size_alignment = 16;
 342                         break;
 343                 case AMDGPU_HW_IP_VCE:
 344                         type = AMD_IP_BLOCK_TYPE_VCE;
 345                         for (i = 0; i < adev->vce.num_rings; i++)
 346                                 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
 347                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 348                         ib_size_alignment = 1;
 349                         break;
 350                 case AMDGPU_HW_IP_UVD_ENC:
 351                         type = AMD_IP_BLOCK_TYPE_UVD;
 352                         for (i = 0; i < adev->uvd.num_enc_rings; i++)
 353                                 ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i);
 354                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 355                         ib_size_alignment = 1;
 356                         break;
 357                 case AMDGPU_HW_IP_VCN_DEC:
 358                         type = AMD_IP_BLOCK_TYPE_VCN;
 359                         ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
 360                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 361                         ib_size_alignment = 16;
 362                         break;
 363                 case AMDGPU_HW_IP_VCN_ENC:
 364                         type = AMD_IP_BLOCK_TYPE_VCN;
 365                         for (i = 0; i < adev->vcn.num_enc_rings; i++)
 366                                 ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i);
 367                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
 368                         ib_size_alignment = 1;
 369                         break;
 370                 default:
 371                         return -EINVAL;
 372                 }
 373
 374                 for (i = 0; i < adev->num_ip_blocks; i++) {
 375                         if (adev->ip_blocks[i].version->type == type &&
 376                             adev->ip_blocks[i].status.valid) {
 377                                 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
 378                                 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 379                                 ip.capabilities_flags = 0;
 380                                 ip.available_rings = ring_mask;
 381                                 ip.ib_start_alignment = ib_start_alignment;
 382                                 ip.ib_size_alignment = ib_size_alignment;
 383                                 break;
 384                         }
 385                 }
 386                 return copy_to_user(out, &ip,
 387                                     min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
 388         }
 389         case AMDGPU_INFO_HW_IP_COUNT: {
 390                 enum amd_ip_block_type type;
 391                 uint32_t count = 0;
 392
 393                 switch (info->query_hw_ip.type) {
 394                 case AMDGPU_HW_IP_GFX:
 395                         type = AMD_IP_BLOCK_TYPE_GFX;
 396                         break;
 397                 case AMDGPU_HW_IP_COMPUTE:
 398                         type = AMD_IP_BLOCK_TYPE_GFX;
 399                         break;
 400                 case AMDGPU_HW_IP_DMA:
 401                         type = AMD_IP_BLOCK_TYPE_SDMA;
 402                         break;
 403                 case AMDGPU_HW_IP_UVD:
 404                         type = AMD_IP_BLOCK_TYPE_UVD;
 405                         break;
 406                 case AMDGPU_HW_IP_VCE:
 407                         type = AMD_IP_BLOCK_TYPE_VCE;
 408                         break;
 409                 case AMDGPU_HW_IP_UVD_ENC:
 410                         type = AMD_IP_BLOCK_TYPE_UVD;
 411                         break;
 412                 case AMDGPU_HW_IP_VCN_DEC:
 413                 case AMDGPU_HW_IP_VCN_ENC:
 414                         type = AMD_IP_BLOCK_TYPE_VCN;
 415                         break;
 416                 default:
 417                         return -EINVAL;
 418                 }
 419
 420                 for (i = 0; i < adev->num_ip_blocks; i++)
 421                         if (adev->ip_blocks[i].version->type == type &&
 422                             adev->ip_blocks[i].status.valid &&
 423                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 424                                 count++;
 425
 426                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 427         }
 428         case AMDGPU_INFO_TIMESTAMP:
 429                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 430                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 431         case AMDGPU_INFO_FW_VERSION: {
 432                 struct drm_amdgpu_info_firmware fw_info;
 433                 int ret;
 434
 435                 /* We only support one instance of each IP block right now. */
 436                 if (info->query_fw.ip_instance != 0)
 437                         return -EINVAL;
 438
 439                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 440                 if (ret)
 441                         return ret;
 442
 443                 return copy_to_user(out, &fw_info,
 444                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 445         }
 446         case AMDGPU_INFO_NUM_BYTES_MOVED:
 447                 ui64 = atomic64_read(&adev->num_bytes_moved);
 448                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 449         case AMDGPU_INFO_NUM_EVICTIONS:
 450                 ui64 = atomic64_read(&adev->num_evictions);
 451                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 452         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 453                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 454                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 455         case AMDGPU_INFO_VRAM_USAGE:
 456                 ui64 = atomic64_read(&adev->vram_usage);
 457                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 458         case AMDGPU_INFO_VIS_VRAM_USAGE:
 459                 ui64 = atomic64_read(&adev->vram_vis_usage);
 460                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 461         case AMDGPU_INFO_GTT_USAGE:
 462                 ui64 = atomic64_read(&adev->gtt_usage);
 463                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 464         case AMDGPU_INFO_GDS_CONFIG: {
 465                 struct drm_amdgpu_info_gds gds_info;
 466
 467                 memset(&gds_info, 0, sizeof(gds_info));
 468                 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
 469                 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
 470                 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
 471                 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
 472                 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
 473                 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
 474                 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
 475                 return copy_to_user(out, &gds_info,
 476                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 477         }
 478         case AMDGPU_INFO_VRAM_GTT: {
 479                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 480
 481                 vram_gtt.vram_size = adev->mc.real_vram_size;
 482                 vram_gtt.vram_size -= adev->vram_pin_size;
 483                 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
 484                 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
 485                 vram_gtt.gtt_size  = adev->mc.gtt_size;
 486                 vram_gtt.gtt_size -= adev->gart_pin_size;
 487                 return copy_to_user(out, &vram_gtt,
 488                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 489         }
 490         case AMDGPU_INFO_MEMORY: {
 491                 struct drm_amdgpu_memory_info mem;
 492
 493                 memset(&mem, 0, sizeof(mem));
 494                 mem.vram.total_heap_size = adev->mc.real_vram_size;
 495                 mem.vram.usable_heap_size =
 496                         adev->mc.real_vram_size - adev->vram_pin_size;
 497                 mem.vram.heap_usage = atomic64_read(&adev->vram_usage);
 498                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 499
 500                 mem.cpu_accessible_vram.total_heap_size =
 501                         adev->mc.visible_vram_size;
 502                 mem.cpu_accessible_vram.usable_heap_size =
 503                         adev->mc.visible_vram_size -
 504                         (adev->vram_pin_size - adev->invisible_pin_size);
 505                 mem.cpu_accessible_vram.heap_usage =
 506                         atomic64_read(&adev->vram_vis_usage);
 507                 mem.cpu_accessible_vram.max_allocation =
 508                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 509
 510                 mem.gtt.total_heap_size = adev->mc.gtt_size;
 511                 mem.gtt.usable_heap_size =
 512                         adev->mc.gtt_size - adev->gart_pin_size;
 513                 mem.gtt.heap_usage = atomic64_read(&adev->gtt_usage);
 514                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 515
 516                 return copy_to_user(out, &mem,
 517                                     min((size_t)size, sizeof(mem)))
 518                                     ? -EFAULT : 0;
 519         }
 520         case AMDGPU_INFO_READ_MMR_REG: {
 521                 unsigned n, alloc_size;
 522                 uint32_t *regs;
 523                 unsigned se_num = (info->read_mmr_reg.instance >>
 524                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 525                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 526                 unsigned sh_num = (info->read_mmr_reg.instance >>
 527                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 528                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 529
 530                 /* set full masks if the userspace set all bits
 531                  * in the bitfields */
 532                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 533                         se_num = 0xffffffff;
 534                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 535                         sh_num = 0xffffffff;
 536
 537                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 538                 if (!regs)
 539                         return -ENOMEM;
 540                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 541
 542                 for (i = 0; i < info->read_mmr_reg.count; i++)
 543                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 544                                                       info->read_mmr_reg.dword_offset + i,
 545                                                       &regs[i])) {
 546                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 547                                               info->read_mmr_reg.dword_offset + i);
 548                                 kfree(regs);
 549                                 return -EFAULT;
 550                         }
 551                 n = copy_to_user(out, regs, min(size, alloc_size));
 552                 kfree(regs);
 553                 return n ? -EFAULT : 0;
 554         }
 555         case AMDGPU_INFO_DEV_INFO: {
 556                 struct drm_amdgpu_info_device dev_info = {};
 557
 558                 dev_info.device_id = dev->pdev->device;
 559                 dev_info.chip_rev = adev->rev_id;
 560                 dev_info.external_rev = adev->external_rev_id;
 561                 dev_info.pci_rev = dev->pdev->revision;
 562                 dev_info.family = adev->family;
 563                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 564                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 565                 /* return all clocks in KHz */
 566                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 567                 if (adev->pm.dpm_enabled) {
 568                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 569                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 570                 } else {
 571                         dev_info.max_engine_clock = adev->pm.default_sclk * 10;
 572                         dev_info.max_memory_clock = adev->pm.default_mclk * 10;
 573                 }
 574                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 575                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 576                         adev->gfx.config.max_shader_engines;
 577                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 578                 dev_info._pad = 0;
 579                 dev_info.ids_flags = 0;
 580                 if (adev->flags & AMD_IS_APU)
 581                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 582                 if (amdgpu_sriov_vf(adev))
 583                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 584                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 585                 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 586                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 587                 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
 588                                              AMDGPU_GPU_PAGE_SIZE;
 589                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 590
 591                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 592                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 593                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 594                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 595                        sizeof(adev->gfx.cu_info.bitmap));
 596                 dev_info.vram_type = adev->mc.vram_type;
 597                 dev_info.vram_bit_width = adev->mc.vram_width;
 598                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 599                 dev_info.gc_double_offchip_lds_buf =
 600                         adev->gfx.config.double_offchip_lds_buf;
 601
 602                 if (amdgpu_ngg) {
 603                         dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
 604                         dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
 605                         dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
 606                         dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
 607                         dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
 608                         dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
 609                         dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
 610                         dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
 611                 }
 612                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
 613                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 614                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 615                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 616                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 617                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 618                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 619
 620                 return copy_to_user(out, &dev_info,
 621                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 622         }
 623         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 624                 unsigned i;
 625                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 626                 struct amd_vce_state *vce_state;
 627
 628                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 629                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 630                         if (vce_state) {
 631                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 632                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 633                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 634                                 vce_clk_table.num_valid_entries++;
 635                         }
 636                 }
 637
 638                 return copy_to_user(out, &vce_clk_table,
 639                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 640         }
 641         case AMDGPU_INFO_VBIOS: {
 642                 uint32_t bios_size = adev->bios_size;
 643
 644                 switch (info->vbios_info.type) {
 645                 case AMDGPU_INFO_VBIOS_SIZE:
 646                         return copy_to_user(out, &bios_size,
 647                                         min((size_t)size, sizeof(bios_size)))
 648                                         ? -EFAULT : 0;
 649                 case AMDGPU_INFO_VBIOS_IMAGE: {
 650                         uint8_t *bios;
 651                         uint32_t bios_offset = info->vbios_info.offset;
 652
 653                         if (bios_offset >= bios_size)
 654                                 return -EINVAL;
 655
 656                         bios = adev->bios + bios_offset;
 657                         return copy_to_user(out, bios,
 658                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 659                                         ? -EFAULT : 0;
 660                 }
 661                 default:
 662                         DRM_DEBUG_KMS("Invalid request %d\n",
 663                                         info->vbios_info.type);
 664                         return -EINVAL;
 665                 }
 666         }
 667         case AMDGPU_INFO_NUM_HANDLES: {
 668                 struct drm_amdgpu_info_num_handles handle;
 669
 670                 switch (info->query_hw_ip.type) {
 671                 case AMDGPU_HW_IP_UVD:
 672                         /* Starting Polaris, we support unlimited UVD handles */
 673                         if (adev->asic_type < CHIP_POLARIS10) {
 674                                 handle.uvd_max_handles = adev->uvd.max_handles;
 675                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 676
 677                                 return copy_to_user(out, &handle,
 678                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 679                         } else {
 680                                 return -ENODATA;
 681                         }
 682
 683                         break;
 684                 default:
 685                         return -EINVAL;
 686                 }
 687         }
 688         case AMDGPU_INFO_SENSOR: {
 689                 struct pp_gpu_power query = {0};
 690                 int query_size = sizeof(query);
 691
 692                 if (amdgpu_dpm == 0)
 693                         return -ENOENT;
 694
 695                 switch (info->sensor_info.type) {
 696                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 697                         /* get sclk in Mhz */
 698                         if (amdgpu_dpm_read_sensor(adev,
 699                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 700                                                    (void *)&ui32, &ui32_size)) {
 701                                 return -EINVAL;
 702                         }
 703                         ui32 /= 100;
 704                         break;
 705                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 706                         /* get mclk in Mhz */
 707                         if (amdgpu_dpm_read_sensor(adev,
 708                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 709                                                    (void *)&ui32, &ui32_size)) {
 710                                 return -EINVAL;
 711                         }
 712                         ui32 /= 100;
 713                         break;
 714                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 715                         /* get temperature in millidegrees C */
 716                         if (amdgpu_dpm_read_sensor(adev,
 717                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 718                                                    (void *)&ui32, &ui32_size)) {
 719                                 return -EINVAL;
 720                         }
 721                         break;
 722                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 723                         /* get GPU load */
 724                         if (amdgpu_dpm_read_sensor(adev,
 725                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 726                                                    (void *)&ui32, &ui32_size)) {
 727                                 return -EINVAL;
 728                         }
 729                         break;
 730                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 731                         /* get average GPU power */
 732                         if (amdgpu_dpm_read_sensor(adev,
 733                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 734                                                    (void *)&query, &query_size)) {
 735                                 return -EINVAL;
 736                         }
 737                         ui32 = query.average_gpu_power >> 8;
 738                         break;
 739                 case AMDGPU_INFO_SENSOR_VDDNB:
 740                         /* get VDDNB in millivolts */
 741                         if (amdgpu_dpm_read_sensor(adev,
 742                                                    AMDGPU_PP_SENSOR_VDDNB,
 743                                                    (void *)&ui32, &ui32_size)) {
 744                                 return -EINVAL;
 745                         }
 746                         break;
 747                 case AMDGPU_INFO_SENSOR_VDDGFX:
 748                         /* get VDDGFX in millivolts */
 749                         if (amdgpu_dpm_read_sensor(adev,
 750                                                    AMDGPU_PP_SENSOR_VDDGFX,
 751                                                    (void *)&ui32, &ui32_size)) {
 752                                 return -EINVAL;
 753                         }
 754                         break;
 755                 default:
 756                         DRM_DEBUG_KMS("Invalid request %d\n",
 757                                       info->sensor_info.type);
 758                         return -EINVAL;
 759                 }
 760                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 761         }
 762         default:
 763                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 764                 return -EINVAL;
 765         }
 766         return 0;
 767 }
 768
 769
 770 /*
 771  * Outdated mess for old drm with Xorg being in charge (void function now).
 772  */
 773 /**
 774  * amdgpu_driver_lastclose_kms - drm callback for last close
 775  *
 776  * @dev: drm dev pointer
 777  *
 778  * Switch vga_switcheroo state after last close (all asics).
 779  */
 780 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 781 {
 782         struct amdgpu_device *adev = dev->dev_private;
 783
 784         amdgpu_fbdev_restore_mode(adev);
 785         vga_switcheroo_process_delayed_switch();
 786 }
 787
 788 bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
 789                           struct amdgpu_fpriv *fpriv)
 790 {
 791         return fpriv->vram_lost_counter != atomic_read(&adev->vram_lost_counter);
 792 }
 793
 794 /**
 795  * amdgpu_driver_open_kms - drm callback for open
 796  *
 797  * @dev: drm dev pointer
 798  * @file_priv: drm file
 799  *
 800  * On device open, init vm on cayman+ (all asics).
 801  * Returns 0 on success, error on failure.
 802  */
 803 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 804 {
 805         struct amdgpu_device *adev = dev->dev_private;
 806         struct amdgpu_fpriv *fpriv;
 807         int r;
 808
 809         file_priv->driver_priv = NULL;
 810
 811         r = pm_runtime_get_sync(dev->dev);
 812         if (r < 0)
 813                 return r;
 814
 815         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 816         if (unlikely(!fpriv)) {
 817                 r = -ENOMEM;
 818                 goto out_suspend;
 819         }
 820
 821         r = amdgpu_vm_init(adev, &fpriv->vm);
 822         if (r) {
 823                 kfree(fpriv);
 824                 goto out_suspend;
 825         }
 826
 827         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
 828         if (!fpriv->prt_va) {
 829                 r = -ENOMEM;
 830                 amdgpu_vm_fini(adev, &fpriv->vm);
 831                 kfree(fpriv);
 832                 goto out_suspend;
 833         }
 834
 835         if (amdgpu_sriov_vf(adev)) {
 836                 r = amdgpu_map_static_csa(adev, &fpriv->vm);
 837                 if (r)
 838                         goto out_suspend;
 839         }
 840
 841         mutex_init(&fpriv->bo_list_lock);
 842         idr_init(&fpriv->bo_list_handles);
 843
 844         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
 845
 846         fpriv->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
 847         file_priv->driver_priv = fpriv;
 848
 849 out_suspend:
 850         pm_runtime_mark_last_busy(dev->dev);
 851         pm_runtime_put_autosuspend(dev->dev);
 852
 853         return r;
 854 }
 855
 856 /**
 857  * amdgpu_driver_postclose_kms - drm callback for post close
 858  *
 859  * @dev: drm dev pointer
 860  * @file_priv: drm file
 861  *
 862  * On device post close, tear down vm on cayman+ (all asics).
 863  */
 864 void amdgpu_driver_postclose_kms(struct drm_device *dev,
 865                                  struct drm_file *file_priv)
 866 {
 867         struct amdgpu_device *adev = dev->dev_private;
 868         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 869         struct amdgpu_bo_list *list;
 870         int handle;
 871
 872         if (!fpriv)
 873                 return;
 874
 875         pm_runtime_get_sync(dev->dev);
 876
 877         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
 878
 879         if (adev->asic_type != CHIP_RAVEN) {
 880                 amdgpu_uvd_free_handles(adev, file_priv);
 881                 amdgpu_vce_free_handles(adev, file_priv);
 882         }
 883
 884         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
 885
 886         if (amdgpu_sriov_vf(adev)) {
 887                 /* TODO: how to handle reserve failure */
 888                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
 889                 amdgpu_vm_bo_rmv(adev, fpriv->vm.csa_bo_va);
 890                 fpriv->vm.csa_bo_va = NULL;
 891                 amdgpu_bo_unreserve(adev->virt.csa_obj);
 892         }
 893
 894         amdgpu_vm_fini(adev, &fpriv->vm);
 895
 896         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
 897                 amdgpu_bo_list_free(list);
 898
 899         idr_destroy(&fpriv->bo_list_handles);
 900         mutex_destroy(&fpriv->bo_list_lock);
 901
 902         kfree(fpriv);
 903         file_priv->driver_priv = NULL;
 904
 905         pm_runtime_mark_last_busy(dev->dev);
 906         pm_runtime_put_autosuspend(dev->dev);
 907 }
 908
 909 /*
 910  * VBlank related functions.
 911  */
 912 /**
 913  * amdgpu_get_vblank_counter_kms - get frame count
 914  *
 915  * @dev: drm dev pointer
 916  * @pipe: crtc to get the frame count from
 917  *
 918  * Gets the frame count on the requested crtc (all asics).
 919  * Returns frame count on success, -EINVAL on failure.
 920  */
 921 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
 922 {
 923         struct amdgpu_device *adev = dev->dev_private;
 924         int vpos, hpos, stat;
 925         u32 count;
 926
 927         if (pipe >= adev->mode_info.num_crtc) {
 928                 DRM_ERROR("Invalid crtc %u\n", pipe);
 929                 return -EINVAL;
 930         }
 931
 932         /* The hw increments its frame counter at start of vsync, not at start
 933          * of vblank, as is required by DRM core vblank counter handling.
 934          * Cook the hw count here to make it appear to the caller as if it
 935          * incremented at start of vblank. We measure distance to start of
 936          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
 937          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
 938          * result by 1 to give the proper appearance to caller.
 939          */
 940         if (adev->mode_info.crtcs[pipe]) {
 941                 /* Repeat readout if needed to provide stable result if
 942                  * we cross start of vsync during the queries.
 943                  */
 944                 do {
 945                         count = amdgpu_display_vblank_get_counter(adev, pipe);
 946                         /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
 947                          * distance to start of vblank, instead of regular
 948                          * vertical scanout pos.
 949                          */
 950                         stat = amdgpu_get_crtc_scanoutpos(
 951                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
 952                                 &vpos, &hpos, NULL, NULL,
 953                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
 954                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
 955
 956                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
 957                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
 958                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
 959                 } else {
 960                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
 961                                       pipe, vpos);
 962
 963                         /* Bump counter if we are at >= leading edge of vblank,
 964                          * but before vsync where vpos would turn negative and
 965                          * the hw counter really increments.
 966                          */
 967                         if (vpos >= 0)
 968                                 count++;
 969                 }
 970         } else {
 971                 /* Fallback to use value as is. */
 972                 count = amdgpu_display_vblank_get_counter(adev, pipe);
 973                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
 974         }
 975
 976         return count;
 977 }
 978
 979 /**
 980  * amdgpu_enable_vblank_kms - enable vblank interrupt
 981  *
 982  * @dev: drm dev pointer
 983  * @pipe: crtc to enable vblank interrupt for
 984  *
 985  * Enable the interrupt on the requested crtc (all asics).
 986  * Returns 0 on success, -EINVAL on failure.
 987  */
 988 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
 989 {
 990         struct amdgpu_device *adev = dev->dev_private;
 991         int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
 992
 993         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
 994 }
 995
 996 /**
 997  * amdgpu_disable_vblank_kms - disable vblank interrupt
 998  *
 999  * @dev: drm dev pointer
1000  * @pipe: crtc to disable vblank interrupt for
1001  *
1002  * Disable the interrupt on the requested crtc (all asics).
1003  */
1004 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1005 {
1006         struct amdgpu_device *adev = dev->dev_private;
1007         int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
1008
1009         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1010 }
1011
1012 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1013         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1014         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1015         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1016         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1017         /* KMS */
1018         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1019         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1020         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1021         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1022         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1023         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1024         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1025         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1026         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1027         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1028 };
1029 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1030
1031 /*
1032  * Debugfs info
1033  */
1034 #if defined(CONFIG_DEBUG_FS)
1035
1036 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1037 {
1038         struct drm_info_node *node = (struct drm_info_node *) m->private;
1039         struct drm_device *dev = node->minor->dev;
1040         struct amdgpu_device *adev = dev->dev_private;
1041         struct drm_amdgpu_info_firmware fw_info;
1042         struct drm_amdgpu_query_fw query_fw;
1043         int ret, i;
1044
1045         /* VCE */
1046         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1047         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1048         if (ret)
1049                 return ret;
1050         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1051                    fw_info.feature, fw_info.ver);
1052
1053         /* UVD */
1054         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1055         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1056         if (ret)
1057                 return ret;
1058         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1059                    fw_info.feature, fw_info.ver);
1060
1061         /* GMC */
1062         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1063         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1064         if (ret)
1065                 return ret;
1066         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1067                    fw_info.feature, fw_info.ver);
1068
1069         /* ME */
1070         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1071         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1072         if (ret)
1073                 return ret;
1074         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1075                    fw_info.feature, fw_info.ver);
1076
1077         /* PFP */
1078         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1079         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1080         if (ret)
1081                 return ret;
1082         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1083                    fw_info.feature, fw_info.ver);
1084
1085         /* CE */
1086         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1087         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1088         if (ret)
1089                 return ret;
1090         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1091                    fw_info.feature, fw_info.ver);
1092
1093         /* RLC */
1094         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1095         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1096         if (ret)
1097                 return ret;
1098         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1099                    fw_info.feature, fw_info.ver);
1100
1101         /* MEC */
1102         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1103         query_fw.index = 0;
1104         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1105         if (ret)
1106                 return ret;
1107         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1108                    fw_info.feature, fw_info.ver);
1109
1110         /* MEC2 */
1111         if (adev->asic_type == CHIP_KAVERI ||
1112             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1113                 query_fw.index = 1;
1114                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1115                 if (ret)
1116                         return ret;
1117                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1118                            fw_info.feature, fw_info.ver);
1119         }
1120
1121         /* PSP SOS */
1122         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1123         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1124         if (ret)
1125                 return ret;
1126         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1127                    fw_info.feature, fw_info.ver);
1128
1129
1130         /* PSP ASD */
1131         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1132         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1133         if (ret)
1134                 return ret;
1135         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1136                    fw_info.feature, fw_info.ver);
1137
1138         /* SMC */
1139         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1140         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1141         if (ret)
1142                 return ret;
1143         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1144                    fw_info.feature, fw_info.ver);
1145
1146         /* SDMA */
1147         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1148         for (i = 0; i < adev->sdma.num_instances; i++) {
1149                 query_fw.index = i;
1150                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1151                 if (ret)
1152                         return ret;
1153                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1154                            i, fw_info.feature, fw_info.ver);
1155         }
1156
1157         return 0;
1158 }
1159
1160 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1161         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1162 };
1163 #endif
1164
1165 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1166 {
1167 #if defined(CONFIG_DEBUG_FS)
1168         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1169                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1170 #else
1171         return 0;
1172 #endif
1173 }