2 * Copyright (C) 2015 Red Hat, Inc.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
28 #include <linux/file.h>
29 #include <linux/sync_file.h>
31 #include <drm/drm_file.h>
32 #include <drm/virtgpu_drm.h>
34 #include "virtgpu_drv.h"
36 static void virtio_gpu_create_context(struct drm_device *dev,
37 struct drm_file *file)
39 struct virtio_gpu_device *vgdev = dev->dev_private;
40 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
41 char dbgname[TASK_COMM_LEN];
43 mutex_lock(&vfpriv->context_lock);
44 if (vfpriv->context_created)
47 get_task_comm(dbgname, current);
48 virtio_gpu_cmd_context_create(vgdev, vfpriv->ctx_id,
49 strlen(dbgname), dbgname);
50 virtio_gpu_notify(vgdev);
51 vfpriv->context_created = true;
54 mutex_unlock(&vfpriv->context_lock);
57 static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
58 struct drm_file *file)
60 struct virtio_gpu_device *vgdev = dev->dev_private;
61 struct drm_virtgpu_map *virtio_gpu_map = data;
63 return virtio_gpu_mode_dumb_mmap(file, vgdev->ddev,
64 virtio_gpu_map->handle,
65 &virtio_gpu_map->offset);
69 * Usage of execbuffer:
70 * Relocations need to take into account the full VIRTIO_GPUDrawable size.
71 * However, the command as passed from user space must *not* contain the initial
72 * VIRTIO_GPUReleaseInfo struct (first XXX bytes)
74 static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
75 struct drm_file *file)
77 struct drm_virtgpu_execbuffer *exbuf = data;
78 struct virtio_gpu_device *vgdev = dev->dev_private;
79 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
80 struct virtio_gpu_fence *out_fence;
82 uint32_t *bo_handles = NULL;
83 void __user *user_bo_handles = NULL;
84 struct virtio_gpu_object_array *buflist = NULL;
85 struct sync_file *sync_file;
86 int in_fence_fd = exbuf->fence_fd;
87 int out_fence_fd = -1;
90 if (vgdev->has_virgl_3d == false)
93 if ((exbuf->flags & ~VIRTGPU_EXECBUF_FLAGS))
98 virtio_gpu_create_context(dev, file);
99 if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_IN) {
100 struct dma_fence *in_fence;
102 in_fence = sync_file_get_fence(in_fence_fd);
108 * Wait if the fence is from a foreign context, or if the fence
109 * array contains any fence from a foreign context.
112 if (!dma_fence_match_context(in_fence, vgdev->fence_drv.context))
113 ret = dma_fence_wait(in_fence, true);
115 dma_fence_put(in_fence);
120 if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) {
121 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
122 if (out_fence_fd < 0)
126 if (exbuf->num_bo_handles) {
127 bo_handles = kvmalloc_array(exbuf->num_bo_handles,
128 sizeof(uint32_t), GFP_KERNEL);
134 user_bo_handles = u64_to_user_ptr(exbuf->bo_handles);
135 if (copy_from_user(bo_handles, user_bo_handles,
136 exbuf->num_bo_handles * sizeof(uint32_t))) {
141 buflist = virtio_gpu_array_from_handles(file, bo_handles,
142 exbuf->num_bo_handles);
151 buf = vmemdup_user(u64_to_user_ptr(exbuf->command), exbuf->size);
158 ret = virtio_gpu_array_lock_resv(buflist);
163 out_fence = virtio_gpu_fence_alloc(vgdev);
169 if (out_fence_fd >= 0) {
170 sync_file = sync_file_create(&out_fence->f);
172 dma_fence_put(&out_fence->f);
177 exbuf->fence_fd = out_fence_fd;
178 fd_install(out_fence_fd, sync_file->file);
181 virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
182 vfpriv->ctx_id, buflist, out_fence);
183 virtio_gpu_notify(vgdev);
188 virtio_gpu_array_unlock_resv(buflist);
194 virtio_gpu_array_put_free(buflist);
196 if (out_fence_fd >= 0)
197 put_unused_fd(out_fence_fd);
202 static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
203 struct drm_file *file)
205 struct virtio_gpu_device *vgdev = dev->dev_private;
206 struct drm_virtgpu_getparam *param = data;
209 switch (param->param) {
210 case VIRTGPU_PARAM_3D_FEATURES:
211 value = vgdev->has_virgl_3d == true ? 1 : 0;
213 case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
219 if (copy_to_user(u64_to_user_ptr(param->value), &value, sizeof(int)))
225 static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
226 struct drm_file *file)
228 struct virtio_gpu_device *vgdev = dev->dev_private;
229 struct drm_virtgpu_resource_create *rc = data;
230 struct virtio_gpu_fence *fence;
232 struct virtio_gpu_object *qobj;
233 struct drm_gem_object *obj;
235 struct virtio_gpu_object_params params = { 0 };
237 if (vgdev->has_virgl_3d) {
238 virtio_gpu_create_context(dev, file);
240 params.target = rc->target;
241 params.bind = rc->bind;
242 params.depth = rc->depth;
243 params.array_size = rc->array_size;
244 params.last_level = rc->last_level;
245 params.nr_samples = rc->nr_samples;
246 params.flags = rc->flags;
250 if (rc->nr_samples > 1)
252 if (rc->last_level > 1)
256 if (rc->array_size > 1)
260 params.format = rc->format;
261 params.width = rc->width;
262 params.height = rc->height;
263 params.size = rc->size;
264 /* allocate a single page size object */
265 if (params.size == 0)
266 params.size = PAGE_SIZE;
268 fence = virtio_gpu_fence_alloc(vgdev);
271 ret = virtio_gpu_object_create(vgdev, ¶ms, &qobj, fence);
272 dma_fence_put(&fence->f);
275 obj = &qobj->base.base;
277 ret = drm_gem_handle_create(file, obj, &handle);
279 drm_gem_object_release(obj);
282 drm_gem_object_put_unlocked(obj);
284 rc->res_handle = qobj->hw_res_handle; /* similiar to a VM address */
285 rc->bo_handle = handle;
289 static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
290 struct drm_file *file)
292 struct drm_virtgpu_resource_info *ri = data;
293 struct drm_gem_object *gobj = NULL;
294 struct virtio_gpu_object *qobj = NULL;
296 gobj = drm_gem_object_lookup(file, ri->bo_handle);
300 qobj = gem_to_virtio_gpu_obj(gobj);
302 ri->size = qobj->base.base.size;
303 ri->res_handle = qobj->hw_res_handle;
304 drm_gem_object_put_unlocked(gobj);
308 static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
310 struct drm_file *file)
312 struct virtio_gpu_device *vgdev = dev->dev_private;
313 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
314 struct drm_virtgpu_3d_transfer_from_host *args = data;
315 struct virtio_gpu_object_array *objs;
316 struct virtio_gpu_fence *fence;
318 u32 offset = args->offset;
320 if (vgdev->has_virgl_3d == false)
323 virtio_gpu_create_context(dev, file);
324 objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
328 ret = virtio_gpu_array_lock_resv(objs);
332 fence = virtio_gpu_fence_alloc(vgdev);
337 virtio_gpu_cmd_transfer_from_host_3d
338 (vgdev, vfpriv->ctx_id, offset, args->level,
339 &args->box, objs, fence);
340 dma_fence_put(&fence->f);
341 virtio_gpu_notify(vgdev);
345 virtio_gpu_array_unlock_resv(objs);
347 virtio_gpu_array_put_free(objs);
351 static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
352 struct drm_file *file)
354 struct virtio_gpu_device *vgdev = dev->dev_private;
355 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
356 struct drm_virtgpu_3d_transfer_to_host *args = data;
357 struct virtio_gpu_object_array *objs;
358 struct virtio_gpu_fence *fence;
360 u32 offset = args->offset;
362 objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
366 if (!vgdev->has_virgl_3d) {
367 virtio_gpu_cmd_transfer_to_host_2d
369 args->box.w, args->box.h, args->box.x, args->box.y,
372 virtio_gpu_create_context(dev, file);
373 ret = virtio_gpu_array_lock_resv(objs);
378 fence = virtio_gpu_fence_alloc(vgdev);
382 virtio_gpu_cmd_transfer_to_host_3d
384 vfpriv ? vfpriv->ctx_id : 0, offset,
385 args->level, &args->box, objs, fence);
386 dma_fence_put(&fence->f);
388 virtio_gpu_notify(vgdev);
392 virtio_gpu_array_unlock_resv(objs);
394 virtio_gpu_array_put_free(objs);
398 static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
399 struct drm_file *file)
401 struct drm_virtgpu_3d_wait *args = data;
402 struct drm_gem_object *obj;
403 long timeout = 15 * HZ;
406 obj = drm_gem_object_lookup(file, args->handle);
410 if (args->flags & VIRTGPU_WAIT_NOWAIT) {
411 ret = dma_resv_test_signaled_rcu(obj->resv, true);
413 ret = dma_resv_wait_timeout_rcu(obj->resv, true, true,
421 drm_gem_object_put_unlocked(obj);
425 static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
426 void *data, struct drm_file *file)
428 struct virtio_gpu_device *vgdev = dev->dev_private;
429 struct drm_virtgpu_get_caps *args = data;
430 unsigned size, host_caps_size;
432 int found_valid = -1;
434 struct virtio_gpu_drv_cap_cache *cache_ent;
437 if (vgdev->num_capsets == 0)
440 /* don't allow userspace to pass 0 */
444 spin_lock(&vgdev->display_info_lock);
445 for (i = 0; i < vgdev->num_capsets; i++) {
446 if (vgdev->capsets[i].id == args->cap_set_id) {
447 if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
454 if (found_valid == -1) {
455 spin_unlock(&vgdev->display_info_lock);
459 host_caps_size = vgdev->capsets[found_valid].max_size;
460 /* only copy to user the minimum of the host caps size or the guest caps size */
461 size = min(args->size, host_caps_size);
463 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
464 if (cache_ent->id == args->cap_set_id &&
465 cache_ent->version == args->cap_set_ver) {
466 spin_unlock(&vgdev->display_info_lock);
470 spin_unlock(&vgdev->display_info_lock);
472 /* not in cache - need to talk to hw */
473 virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
475 virtio_gpu_notify(vgdev);
478 ret = wait_event_timeout(vgdev->resp_wq,
479 atomic_read(&cache_ent->is_valid), 5 * HZ);
483 /* is_valid check must proceed before copy of the cache entry. */
486 ptr = cache_ent->caps_cache;
488 if (copy_to_user(u64_to_user_ptr(args->addr), ptr, size))
494 struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
495 DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
498 DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
501 DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
504 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
505 virtio_gpu_resource_create_ioctl,
508 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
511 /* make transfer async to the main ring? - no sure, can we
512 * thread these in the underlying GL
514 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
515 virtio_gpu_transfer_from_host_ioctl,
517 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
518 virtio_gpu_transfer_to_host_ioctl,
521 DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
524 DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,