drivers/gpu/drm/xlnx/zynqmp_dp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ZynqMP DisplayPort Driver
   4  *
   5  * Copyright (C) 2017 - 2020 Xilinx, Inc.
   6  *
   7  * Authors:
   8  * - Hyun Woo Kwon <[email protected]>
   9  * - Laurent Pinchart <[email protected]>
  10  */
  11
  12 #include <drm/display/drm_dp_helper.h>
  13 #include <drm/drm_atomic_helper.h>
  14 #include <drm/drm_crtc.h>
  15 #include <drm/drm_device.h>
  16 #include <drm/drm_edid.h>
  17 #include <drm/drm_fourcc.h>
  18 #include <drm/drm_modes.h>
  19 #include <drm/drm_of.h>
  20
  21 #include <linux/clk.h>
  22 #include <linux/delay.h>
  23 #include <linux/device.h>
  24 #include <linux/io.h>
  25 #include <linux/media-bus-format.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/phy/phy.h>
  30 #include <linux/reset.h>
  31 #include <linux/slab.h>
  32
  33 #include "zynqmp_disp.h"
  34 #include "zynqmp_dp.h"
  35 #include "zynqmp_dpsub.h"
  36 #include "zynqmp_kms.h"
  37
  38 static uint zynqmp_dp_aux_timeout_ms = 50;
  39 module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444);
  40 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
  41
  42 /*
  43  * Some sink requires a delay after power on request
  44  */
  45 static uint zynqmp_dp_power_on_delay_ms = 4;
  46 module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444);
  47 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
  48
  49 /* Link configuration registers */
  50 #define ZYNQMP_DP_LINK_BW_SET                           0x0
  51 #define ZYNQMP_DP_LANE_COUNT_SET                        0x4
  52 #define ZYNQMP_DP_ENHANCED_FRAME_EN                     0x8
  53 #define ZYNQMP_DP_TRAINING_PATTERN_SET                  0xc
  54 #define ZYNQMP_DP_SCRAMBLING_DISABLE                    0x14
  55 #define ZYNQMP_DP_DOWNSPREAD_CTL                        0x18
  56 #define ZYNQMP_DP_SOFTWARE_RESET                        0x1c
  57 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM1                BIT(0)
  58 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM2                BIT(1)
  59 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM3                BIT(2)
  60 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM4                BIT(3)
  61 #define ZYNQMP_DP_SOFTWARE_RESET_AUX                    BIT(7)
  62 #define ZYNQMP_DP_SOFTWARE_RESET_ALL                    (ZYNQMP_DP_SOFTWARE_RESET_STREAM1 | \
  63                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM2 | \
  64                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM3 | \
  65                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM4 | \
  66                                                          ZYNQMP_DP_SOFTWARE_RESET_AUX)
  67
  68 /* Core enable registers */
  69 #define ZYNQMP_DP_TRANSMITTER_ENABLE                    0x80
  70 #define ZYNQMP_DP_MAIN_STREAM_ENABLE                    0x84
  71 #define ZYNQMP_DP_FORCE_SCRAMBLER_RESET                 0xc0
  72 #define ZYNQMP_DP_VERSION                               0xf8
  73 #define ZYNQMP_DP_VERSION_MAJOR_MASK                    GENMASK(31, 24)
  74 #define ZYNQMP_DP_VERSION_MAJOR_SHIFT                   24
  75 #define ZYNQMP_DP_VERSION_MINOR_MASK                    GENMASK(23, 16)
  76 #define ZYNQMP_DP_VERSION_MINOR_SHIFT                   16
  77 #define ZYNQMP_DP_VERSION_REVISION_MASK                 GENMASK(15, 12)
  78 #define ZYNQMP_DP_VERSION_REVISION_SHIFT                12
  79 #define ZYNQMP_DP_VERSION_PATCH_MASK                    GENMASK(11, 8)
  80 #define ZYNQMP_DP_VERSION_PATCH_SHIFT                   8
  81 #define ZYNQMP_DP_VERSION_INTERNAL_MASK                 GENMASK(7, 0)
  82 #define ZYNQMP_DP_VERSION_INTERNAL_SHIFT                0
  83
  84 /* Core ID registers */
  85 #define ZYNQMP_DP_CORE_ID                               0xfc
  86 #define ZYNQMP_DP_CORE_ID_MAJOR_MASK                    GENMASK(31, 24)
  87 #define ZYNQMP_DP_CORE_ID_MAJOR_SHIFT                   24
  88 #define ZYNQMP_DP_CORE_ID_MINOR_MASK                    GENMASK(23, 16)
  89 #define ZYNQMP_DP_CORE_ID_MINOR_SHIFT                   16
  90 #define ZYNQMP_DP_CORE_ID_REVISION_MASK                 GENMASK(15, 8)
  91 #define ZYNQMP_DP_CORE_ID_REVISION_SHIFT                8
  92 #define ZYNQMP_DP_CORE_ID_DIRECTION                     GENMASK(1)
  93
  94 /* AUX channel interface registers */
  95 #define ZYNQMP_DP_AUX_COMMAND                           0x100
  96 #define ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT                 8
  97 #define ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY              BIT(12)
  98 #define ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT               0
  99 #define ZYNQMP_DP_AUX_WRITE_FIFO                        0x104
 100 #define ZYNQMP_DP_AUX_ADDRESS                           0x108
 101 #define ZYNQMP_DP_AUX_CLK_DIVIDER                       0x10c
 102 #define ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT      8
 103 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE                0x130
 104 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD            BIT(0)
 105 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST        BIT(1)
 106 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY          BIT(2)
 107 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT  BIT(3)
 108 #define ZYNQMP_DP_AUX_REPLY_DATA                        0x134
 109 #define ZYNQMP_DP_AUX_REPLY_CODE                        0x138
 110 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK                (0)
 111 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_NACK               BIT(0)
 112 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_DEFER              BIT(1)
 113 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK                (0)
 114 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_NACK               BIT(2)
 115 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_DEFER              BIT(3)
 116 #define ZYNQMP_DP_AUX_REPLY_COUNT                       0x13c
 117 #define ZYNQMP_DP_REPLY_DATA_COUNT                      0x148
 118 #define ZYNQMP_DP_REPLY_DATA_COUNT_MASK                 0xff
 119 #define ZYNQMP_DP_INT_STATUS                            0x3a0
 120 #define ZYNQMP_DP_INT_MASK                              0x3a4
 121 #define ZYNQMP_DP_INT_EN                                0x3a8
 122 #define ZYNQMP_DP_INT_DS                                0x3ac
 123 #define ZYNQMP_DP_INT_HPD_IRQ                           BIT(0)
 124 #define ZYNQMP_DP_INT_HPD_EVENT                         BIT(1)
 125 #define ZYNQMP_DP_INT_REPLY_RECEIVED                    BIT(2)
 126 #define ZYNQMP_DP_INT_REPLY_TIMEOUT                     BIT(3)
 127 #define ZYNQMP_DP_INT_HPD_PULSE_DET                     BIT(4)
 128 #define ZYNQMP_DP_INT_EXT_PKT_TXD                       BIT(5)
 129 #define ZYNQMP_DP_INT_LIV_ABUF_UNDRFLW                  BIT(12)
 130 #define ZYNQMP_DP_INT_VBLANK_START                      BIT(13)
 131 #define ZYNQMP_DP_INT_PIXEL1_MATCH                      BIT(14)
 132 #define ZYNQMP_DP_INT_PIXEL0_MATCH                      BIT(15)
 133 #define ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK               0x3f0000
 134 #define ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK                0xfc00000
 135 #define ZYNQMP_DP_INT_CUST_TS_2                         BIT(28)
 136 #define ZYNQMP_DP_INT_CUST_TS                           BIT(29)
 137 #define ZYNQMP_DP_INT_EXT_VSYNC_TS                      BIT(30)
 138 #define ZYNQMP_DP_INT_VSYNC_TS                          BIT(31)
 139 #define ZYNQMP_DP_INT_ALL                               (ZYNQMP_DP_INT_HPD_IRQ | \
 140                                                          ZYNQMP_DP_INT_HPD_EVENT | \
 141                                                          ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK | \
 142                                                          ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK)
 143
 144 /* Main stream attribute registers */
 145 #define ZYNQMP_DP_MAIN_STREAM_HTOTAL                    0x180
 146 #define ZYNQMP_DP_MAIN_STREAM_VTOTAL                    0x184
 147 #define ZYNQMP_DP_MAIN_STREAM_POLARITY                  0x188
 148 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT      0
 149 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT      1
 150 #define ZYNQMP_DP_MAIN_STREAM_HSWIDTH                   0x18c
 151 #define ZYNQMP_DP_MAIN_STREAM_VSWIDTH                   0x190
 152 #define ZYNQMP_DP_MAIN_STREAM_HRES                      0x194
 153 #define ZYNQMP_DP_MAIN_STREAM_VRES                      0x198
 154 #define ZYNQMP_DP_MAIN_STREAM_HSTART                    0x19c
 155 #define ZYNQMP_DP_MAIN_STREAM_VSTART                    0x1a0
 156 #define ZYNQMP_DP_MAIN_STREAM_MISC0                     0x1a4
 157 #define ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK           BIT(0)
 158 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB     (0 << 1)
 159 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422       (5 << 1)
 160 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444       (6 << 1)
 161 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK    (7 << 1)
 162 #define ZYNQMP_DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE       BIT(3)
 163 #define ZYNQMP_DP_MAIN_STREAM_MISC0_YCBCR_COLR          BIT(4)
 164 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6               (0 << 5)
 165 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8               (1 << 5)
 166 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10              (2 << 5)
 167 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12              (3 << 5)
 168 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16              (4 << 5)
 169 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK            (7 << 5)
 170 #define ZYNQMP_DP_MAIN_STREAM_MISC1                     0x1a8
 171 #define ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN           BIT(7)
 172 #define ZYNQMP_DP_MAIN_STREAM_M_VID                     0x1ac
 173 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE                0x1b0
 174 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF    64
 175 #define ZYNQMP_DP_MAIN_STREAM_N_VID                     0x1b4
 176 #define ZYNQMP_DP_USER_PIX_WIDTH                        0x1b8
 177 #define ZYNQMP_DP_USER_DATA_COUNT_PER_LANE              0x1bc
 178 #define ZYNQMP_DP_MIN_BYTES_PER_TU                      0x1c4
 179 #define ZYNQMP_DP_FRAC_BYTES_PER_TU                     0x1c8
 180 #define ZYNQMP_DP_INIT_WAIT                             0x1cc
 181
 182 /* PHY configuration and status registers */
 183 #define ZYNQMP_DP_PHY_RESET                             0x200
 184 #define ZYNQMP_DP_PHY_RESET_PHY_RESET                   BIT(0)
 185 #define ZYNQMP_DP_PHY_RESET_GTTX_RESET                  BIT(1)
 186 #define ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET               BIT(8)
 187 #define ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET               BIT(9)
 188 #define ZYNQMP_DP_PHY_RESET_ALL_RESET                   (ZYNQMP_DP_PHY_RESET_PHY_RESET | \
 189                                                          ZYNQMP_DP_PHY_RESET_GTTX_RESET | \
 190                                                          ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET | \
 191                                                          ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET)
 192 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_0                0x210
 193 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_1                0x214
 194 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_2                0x218
 195 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_3                0x21c
 196 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_0               0x220
 197 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_1               0x224
 198 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_2               0x228
 199 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_3               0x22c
 200 #define ZYNQMP_DP_PHY_CLOCK_SELECT                      0x234
 201 #define ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G                0x1
 202 #define ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G                0x3
 203 #define ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G                0x5
 204 #define ZYNQMP_DP_TX_PHY_POWER_DOWN                     0x238
 205 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_0              BIT(0)
 206 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_1              BIT(1)
 207 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_2              BIT(2)
 208 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_3              BIT(3)
 209 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL                 0xf
 210 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_0                  0x23c
 211 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_1                  0x240
 212 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_2                  0x244
 213 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_3                  0x248
 214 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_0                 0x24c
 215 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_1                 0x250
 216 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_2                 0x254
 217 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_3                 0x258
 218 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0           0x24c
 219 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_1           0x250
 220 #define ZYNQMP_DP_PHY_STATUS                            0x280
 221 #define ZYNQMP_DP_PHY_STATUS_PLL_LOCKED_SHIFT           4
 222 #define ZYNQMP_DP_PHY_STATUS_FPGA_PLL_LOCKED            BIT(6)
 223
 224 /* Audio registers */
 225 #define ZYNQMP_DP_TX_AUDIO_CONTROL                      0x300
 226 #define ZYNQMP_DP_TX_AUDIO_CHANNELS                     0x304
 227 #define ZYNQMP_DP_TX_AUDIO_INFO_DATA                    0x308
 228 #define ZYNQMP_DP_TX_M_AUD                              0x328
 229 #define ZYNQMP_DP_TX_N_AUD                              0x32c
 230 #define ZYNQMP_DP_TX_AUDIO_EXT_DATA                     0x330
 231
 232 #define ZYNQMP_DP_MAX_LANES                             2
 233 #define ZYNQMP_MAX_FREQ                                 3000000
 234
 235 #define DP_REDUCED_BIT_RATE                             162000
 236 #define DP_HIGH_BIT_RATE                                270000
 237 #define DP_HIGH_BIT_RATE2                               540000
 238 #define DP_MAX_TRAINING_TRIES                           5
 239 #define DP_V1_2                                         0x12
 240
 241 /**
 242  * struct zynqmp_dp_link_config - Common link config between source and sink
 243  * @max_rate: maximum link rate
 244  * @max_lanes: maximum number of lanes
 245  */
 246 struct zynqmp_dp_link_config {
 247         int max_rate;
 248         u8 max_lanes;
 249 };
 250
 251 /**
 252  * struct zynqmp_dp_mode - Configured mode of DisplayPort
 253  * @bw_code: code for bandwidth(link rate)
 254  * @lane_cnt: number of lanes
 255  * @pclock: pixel clock frequency of current mode
 256  * @fmt: format identifier string
 257  */
 258 struct zynqmp_dp_mode {
 259         const char *fmt;
 260         int pclock;
 261         u8 bw_code;
 262         u8 lane_cnt;
 263 };
 264
 265 /**
 266  * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
 267  * @misc0: misc0 configuration (per DP v1.2 spec)
 268  * @misc1: misc1 configuration (per DP v1.2 spec)
 269  * @bpp: bits per pixel
 270  */
 271 struct zynqmp_dp_config {
 272         u8 misc0;
 273         u8 misc1;
 274         u8 bpp;
 275 };
 276
 277 /**
 278  * struct zynqmp_dp - Xilinx DisplayPort core
 279  * @dev: device structure
 280  * @dpsub: Display subsystem
 281  * @iomem: device I/O memory for register access
 282  * @reset: reset controller
 283  * @irq: irq
 284  * @bridge: DRM bridge for the DP encoder
 285  * @next_bridge: The downstream bridge
 286  * @config: IP core configuration from DTS
 287  * @aux: aux channel
 288  * @phy: PHY handles for DP lanes
 289  * @num_lanes: number of enabled phy lanes
 290  * @hpd_work: hot plug detection worker
 291  * @status: connection status
 292  * @enabled: flag to indicate if the device is enabled
 293  * @dpcd: DP configuration data from currently connected sink device
 294  * @link_config: common link configuration between IP core and sink device
 295  * @mode: current mode between IP core and sink device
 296  * @train_set: set of training data
 297  */
 298 struct zynqmp_dp {
 299         struct drm_dp_aux aux;
 300         struct drm_bridge bridge;
 301         struct work_struct hpd_work;
 302
 303         struct drm_bridge *next_bridge;
 304         struct device *dev;
 305         struct zynqmp_dpsub *dpsub;
 306         void __iomem *iomem;
 307         struct reset_control *reset;
 308         struct phy *phy[ZYNQMP_DP_MAX_LANES];
 309
 310         enum drm_connector_status status;
 311         int irq;
 312         bool enabled;
 313
 314         struct zynqmp_dp_mode mode;
 315         struct zynqmp_dp_link_config link_config;
 316         struct zynqmp_dp_config config;
 317         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 318         u8 train_set[ZYNQMP_DP_MAX_LANES];
 319         u8 num_lanes;
 320 };
 321
 322 static inline struct zynqmp_dp *bridge_to_dp(struct drm_bridge *bridge)
 323 {
 324         return container_of(bridge, struct zynqmp_dp, bridge);
 325 }
 326
 327 static void zynqmp_dp_write(struct zynqmp_dp *dp, int offset, u32 val)
 328 {
 329         writel(val, dp->iomem + offset);
 330 }
 331
 332 static u32 zynqmp_dp_read(struct zynqmp_dp *dp, int offset)
 333 {
 334         return readl(dp->iomem + offset);
 335 }
 336
 337 static void zynqmp_dp_clr(struct zynqmp_dp *dp, int offset, u32 clr)
 338 {
 339         zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) & ~clr);
 340 }
 341
 342 static void zynqmp_dp_set(struct zynqmp_dp *dp, int offset, u32 set)
 343 {
 344         zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) | set);
 345 }
 346
 347 /* -----------------------------------------------------------------------------
 348  * PHY Handling
 349  */
 350
 351 #define RST_TIMEOUT_MS                  1000
 352
 353 static int zynqmp_dp_reset(struct zynqmp_dp *dp, bool assert)
 354 {
 355         unsigned long timeout;
 356
 357         if (assert)
 358                 reset_control_assert(dp->reset);
 359         else
 360                 reset_control_deassert(dp->reset);
 361
 362         /* Wait for the (de)assert to complete. */
 363         timeout = jiffies + msecs_to_jiffies(RST_TIMEOUT_MS);
 364         while (!time_after_eq(jiffies, timeout)) {
 365                 bool status = !!reset_control_status(dp->reset);
 366
 367                 if (assert == status)
 368                         return 0;
 369
 370                 cpu_relax();
 371         }
 372
 373         dev_err(dp->dev, "reset %s timeout\n", assert ? "assert" : "deassert");
 374         return -ETIMEDOUT;
 375 }
 376
 377 /**
 378  * zynqmp_dp_phy_init - Initialize the phy
 379  * @dp: DisplayPort IP core structure
 380  *
 381  * Initialize the phy.
 382  *
 383  * Return: 0 if the phy instances are initialized correctly, or the error code
 384  * returned from the callee functions.
 385  */
 386 static int zynqmp_dp_phy_init(struct zynqmp_dp *dp)
 387 {
 388         int ret;
 389         int i;
 390
 391         for (i = 0; i < dp->num_lanes; i++) {
 392                 ret = phy_init(dp->phy[i]);
 393                 if (ret) {
 394                         dev_err(dp->dev, "failed to init phy lane %d\n", i);
 395                         return ret;
 396                 }
 397         }
 398
 399         zynqmp_dp_clr(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET);
 400
 401         /*
 402          * Power on lanes in reverse order as only lane 0 waits for the PLL to
 403          * lock.
 404          */
 405         for (i = dp->num_lanes - 1; i >= 0; i--) {
 406                 ret = phy_power_on(dp->phy[i]);
 407                 if (ret) {
 408                         dev_err(dp->dev, "failed to power on phy lane %d\n", i);
 409                         return ret;
 410                 }
 411         }
 412
 413         return 0;
 414 }
 415
 416 /**
 417  * zynqmp_dp_phy_exit - Exit the phy
 418  * @dp: DisplayPort IP core structure
 419  *
 420  * Exit the phy.
 421  */
 422 static void zynqmp_dp_phy_exit(struct zynqmp_dp *dp)
 423 {
 424         unsigned int i;
 425         int ret;
 426
 427         for (i = 0; i < dp->num_lanes; i++) {
 428                 ret = phy_power_off(dp->phy[i]);
 429                 if (ret)
 430                         dev_err(dp->dev, "failed to power off phy(%d) %d\n", i,
 431                                 ret);
 432         }
 433
 434         for (i = 0; i < dp->num_lanes; i++) {
 435                 ret = phy_exit(dp->phy[i]);
 436                 if (ret)
 437                         dev_err(dp->dev, "failed to exit phy(%d) %d\n", i, ret);
 438         }
 439 }
 440
 441 /**
 442  * zynqmp_dp_phy_probe - Probe the PHYs
 443  * @dp: DisplayPort IP core structure
 444  *
 445  * Probe PHYs for all lanes. Less PHYs may be available than the number of
 446  * lanes, which is not considered an error as long as at least one PHY is
 447  * found. The caller can check dp->num_lanes to check how many PHYs were found.
 448  *
 449  * Return:
 450  * * 0                          - Success
 451  * * -ENXIO                     - No PHY found
 452  * * -EPROBE_DEFER              - Probe deferral requested
 453  * * Other negative value       - PHY retrieval failure
 454  */
 455 static int zynqmp_dp_phy_probe(struct zynqmp_dp *dp)
 456 {
 457         unsigned int i;
 458
 459         for (i = 0; i < ZYNQMP_DP_MAX_LANES; i++) {
 460                 char phy_name[16];
 461                 struct phy *phy;
 462
 463                 snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i);
 464                 phy = devm_phy_get(dp->dev, phy_name);
 465
 466                 if (IS_ERR(phy)) {
 467                         switch (PTR_ERR(phy)) {
 468                         case -ENODEV:
 469                                 if (dp->num_lanes)
 470                                         return 0;
 471
 472                                 dev_err(dp->dev, "no PHY found\n");
 473                                 return -ENXIO;
 474
 475                         case -EPROBE_DEFER:
 476                                 return -EPROBE_DEFER;
 477
 478                         default:
 479                                 dev_err(dp->dev, "failed to get PHY lane %u\n",
 480                                         i);
 481                                 return PTR_ERR(phy);
 482                         }
 483                 }
 484
 485                 dp->phy[i] = phy;
 486                 dp->num_lanes++;
 487         }
 488
 489         return 0;
 490 }
 491
 492 /**
 493  * zynqmp_dp_phy_ready - Check if PHY is ready
 494  * @dp: DisplayPort IP core structure
 495  *
 496  * Check if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times.
 497  * This amount of delay was suggested by IP designer.
 498  *
 499  * Return: 0 if PHY is ready, or -ENODEV if PHY is not ready.
 500  */
 501 static int zynqmp_dp_phy_ready(struct zynqmp_dp *dp)
 502 {
 503         u32 i, reg, ready;
 504
 505         ready = (1 << dp->num_lanes) - 1;
 506
 507         /* Wait for 100 * 1ms. This should be enough time for PHY to be ready */
 508         for (i = 0; ; i++) {
 509                 reg = zynqmp_dp_read(dp, ZYNQMP_DP_PHY_STATUS);
 510                 if ((reg & ready) == ready)
 511                         return 0;
 512
 513                 if (i == 100) {
 514                         dev_err(dp->dev, "PHY isn't ready\n");
 515                         return -ENODEV;
 516                 }
 517
 518                 usleep_range(1000, 1100);
 519         }
 520
 521         return 0;
 522 }
 523
 524 /* -----------------------------------------------------------------------------
 525  * DisplayPort Link Training
 526  */
 527
 528 /**
 529  * zynqmp_dp_max_rate - Calculate and return available max pixel clock
 530  * @link_rate: link rate (Kilo-bytes / sec)
 531  * @lane_num: number of lanes
 532  * @bpp: bits per pixel
 533  *
 534  * Return: max pixel clock (KHz) supported by current link config.
 535  */
 536 static inline int zynqmp_dp_max_rate(int link_rate, u8 lane_num, u8 bpp)
 537 {
 538         return link_rate * lane_num * 8 / bpp;
 539 }
 540
 541 /**
 542  * zynqmp_dp_mode_configure - Configure the link values
 543  * @dp: DisplayPort IP core structure
 544  * @pclock: pixel clock for requested display mode
 545  * @current_bw: current link rate
 546  *
 547  * Find the link configuration values, rate and lane count for requested pixel
 548  * clock @pclock. The @pclock is stored in the mode to be used in other
 549  * functions later. The returned rate is downshifted from the current rate
 550  * @current_bw.
 551  *
 552  * Return: Current link rate code, or -EINVAL.
 553  */
 554 static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock,
 555                                     u8 current_bw)
 556 {
 557         int max_rate = dp->link_config.max_rate;
 558         u8 bw_code;
 559         u8 max_lanes = dp->link_config.max_lanes;
 560         u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
 561         u8 bpp = dp->config.bpp;
 562         u8 lane_cnt;
 563
 564         /* Downshift from current bandwidth */
 565         switch (current_bw) {
 566         case DP_LINK_BW_5_4:
 567                 bw_code = DP_LINK_BW_2_7;
 568                 break;
 569         case DP_LINK_BW_2_7:
 570                 bw_code = DP_LINK_BW_1_62;
 571                 break;
 572         case DP_LINK_BW_1_62:
 573                 dev_err(dp->dev, "can't downshift. already lowest link rate\n");
 574                 return -EINVAL;
 575         default:
 576                 /* If not given, start with max supported */
 577                 bw_code = max_link_rate_code;
 578                 break;
 579         }
 580
 581         for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
 582                 int bw;
 583                 u32 rate;
 584
 585                 bw = drm_dp_bw_code_to_link_rate(bw_code);
 586                 rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp);
 587                 if (pclock <= rate) {
 588                         dp->mode.bw_code = bw_code;
 589                         dp->mode.lane_cnt = lane_cnt;
 590                         dp->mode.pclock = pclock;
 591                         return dp->mode.bw_code;
 592                 }
 593         }
 594
 595         dev_err(dp->dev, "failed to configure link values\n");
 596
 597         return -EINVAL;
 598 }
 599
 600 /**
 601  * zynqmp_dp_adjust_train - Adjust train values
 602  * @dp: DisplayPort IP core structure
 603  * @link_status: link status from sink which contains requested training values
 604  */
 605 static void zynqmp_dp_adjust_train(struct zynqmp_dp *dp,
 606                                    u8 link_status[DP_LINK_STATUS_SIZE])
 607 {
 608         u8 *train_set = dp->train_set;
 609         u8 i;
 610
 611         for (i = 0; i < dp->mode.lane_cnt; i++) {
 612                 u8 voltage = drm_dp_get_adjust_request_voltage(link_status, i);
 613                 u8 preemphasis =
 614                         drm_dp_get_adjust_request_pre_emphasis(link_status, i);
 615
 616                 if (voltage >= DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
 617                         voltage |= DP_TRAIN_MAX_SWING_REACHED;
 618
 619                 if (preemphasis >= DP_TRAIN_PRE_EMPH_LEVEL_2)
 620                         preemphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 621
 622                 train_set[i] = voltage | preemphasis;
 623         }
 624 }
 625
 626 /**
 627  * zynqmp_dp_update_vs_emph - Update the training values
 628  * @dp: DisplayPort IP core structure
 629  *
 630  * Update the training values based on the request from sink. The mapped values
 631  * are predefined, and values(vs, pe, pc) are from the device manual.
 632  *
 633  * Return: 0 if vs and emph are updated successfully, or the error code returned
 634  * by drm_dp_dpcd_write().
 635  */
 636 static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp)
 637 {
 638         unsigned int i;
 639         int ret;
 640
 641         ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set,
 642                                 dp->mode.lane_cnt);
 643         if (ret < 0)
 644                 return ret;
 645
 646         for (i = 0; i < dp->mode.lane_cnt; i++) {
 647                 u32 reg = ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 + i * 4;
 648                 union phy_configure_opts opts = { 0 };
 649                 u8 train = dp->train_set[i];
 650
 651                 opts.dp.voltage[0] = (train & DP_TRAIN_VOLTAGE_SWING_MASK)
 652                                    >> DP_TRAIN_VOLTAGE_SWING_SHIFT;
 653                 opts.dp.pre[0] = (train & DP_TRAIN_PRE_EMPHASIS_MASK)
 654                                >> DP_TRAIN_PRE_EMPHASIS_SHIFT;
 655
 656                 phy_configure(dp->phy[i], &opts);
 657
 658                 zynqmp_dp_write(dp, reg, 0x2);
 659         }
 660
 661         return 0;
 662 }
 663
 664 /**
 665  * zynqmp_dp_link_train_cr - Train clock recovery
 666  * @dp: DisplayPort IP core structure
 667  *
 668  * Return: 0 if clock recovery train is done successfully, or corresponding
 669  * error code.
 670  */
 671 static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp)
 672 {
 673         u8 link_status[DP_LINK_STATUS_SIZE];
 674         u8 lane_cnt = dp->mode.lane_cnt;
 675         u8 vs = 0, tries = 0;
 676         u16 max_tries, i;
 677         bool cr_done;
 678         int ret;
 679
 680         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET,
 681                         DP_TRAINING_PATTERN_1);
 682         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 683                                  DP_TRAINING_PATTERN_1 |
 684                                  DP_LINK_SCRAMBLING_DISABLE);
 685         if (ret < 0)
 686                 return ret;
 687
 688         /*
 689          * 256 loops should be maximum iterations for 4 lanes and 4 values.
 690          * So, This loop should exit before 512 iterations
 691          */
 692         for (max_tries = 0; max_tries < 512; max_tries++) {
 693                 ret = zynqmp_dp_update_vs_emph(dp);
 694                 if (ret)
 695                         return ret;
 696
 697                 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd);
 698                 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
 699                 if (ret < 0)
 700                         return ret;
 701
 702                 cr_done = drm_dp_clock_recovery_ok(link_status, lane_cnt);
 703                 if (cr_done)
 704                         break;
 705
 706                 for (i = 0; i < lane_cnt; i++)
 707                         if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED))
 708                                 break;
 709                 if (i == lane_cnt)
 710                         break;
 711
 712                 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs)
 713                         tries++;
 714                 else
 715                         tries = 0;
 716
 717                 if (tries == DP_MAX_TRAINING_TRIES)
 718                         break;
 719
 720                 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 721                 zynqmp_dp_adjust_train(dp, link_status);
 722         }
 723
 724         if (!cr_done)
 725                 return -EIO;
 726
 727         return 0;
 728 }
 729
 730 /**
 731  * zynqmp_dp_link_train_ce - Train channel equalization
 732  * @dp: DisplayPort IP core structure
 733  *
 734  * Return: 0 if channel equalization train is done successfully, or
 735  * corresponding error code.
 736  */
 737 static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp)
 738 {
 739         u8 link_status[DP_LINK_STATUS_SIZE];
 740         u8 lane_cnt = dp->mode.lane_cnt;
 741         u32 pat, tries;
 742         int ret;
 743         bool ce_done;
 744
 745         if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 &&
 746             dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED)
 747                 pat = DP_TRAINING_PATTERN_3;
 748         else
 749                 pat = DP_TRAINING_PATTERN_2;
 750
 751         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, pat);
 752         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 753                                  pat | DP_LINK_SCRAMBLING_DISABLE);
 754         if (ret < 0)
 755                 return ret;
 756
 757         for (tries = 0; tries < DP_MAX_TRAINING_TRIES; tries++) {
 758                 ret = zynqmp_dp_update_vs_emph(dp);
 759                 if (ret)
 760                         return ret;
 761
 762                 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd);
 763                 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
 764                 if (ret < 0)
 765                         return ret;
 766
 767                 ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt);
 768                 if (ce_done)
 769                         break;
 770
 771                 zynqmp_dp_adjust_train(dp, link_status);
 772         }
 773
 774         if (!ce_done)
 775                 return -EIO;
 776
 777         return 0;
 778 }
 779
 780 /**
 781  * zynqmp_dp_train - Train the link
 782  * @dp: DisplayPort IP core structure
 783  *
 784  * Return: 0 if all trains are done successfully, or corresponding error code.
 785  */
 786 static int zynqmp_dp_train(struct zynqmp_dp *dp)
 787 {
 788         u32 reg;
 789         u8 bw_code = dp->mode.bw_code;
 790         u8 lane_cnt = dp->mode.lane_cnt;
 791         u8 aux_lane_cnt = lane_cnt;
 792         bool enhanced;
 793         int ret;
 794
 795         zynqmp_dp_write(dp, ZYNQMP_DP_LANE_COUNT_SET, lane_cnt);
 796         enhanced = drm_dp_enhanced_frame_cap(dp->dpcd);
 797         if (enhanced) {
 798                 zynqmp_dp_write(dp, ZYNQMP_DP_ENHANCED_FRAME_EN, 1);
 799                 aux_lane_cnt |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 800         }
 801
 802         if (dp->dpcd[3] & 0x1) {
 803                 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 1);
 804                 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL,
 805                                    DP_SPREAD_AMP_0_5);
 806         } else {
 807                 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 0);
 808                 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0);
 809         }
 810
 811         ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt);
 812         if (ret < 0) {
 813                 dev_err(dp->dev, "failed to set lane count\n");
 814                 return ret;
 815         }
 816
 817         ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
 818                                  DP_SET_ANSI_8B10B);
 819         if (ret < 0) {
 820                 dev_err(dp->dev, "failed to set ANSI 8B/10B encoding\n");
 821                 return ret;
 822         }
 823
 824         ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code);
 825         if (ret < 0) {
 826                 dev_err(dp->dev, "failed to set DP bandwidth\n");
 827                 return ret;
 828         }
 829
 830         zynqmp_dp_write(dp, ZYNQMP_DP_LINK_BW_SET, bw_code);
 831         switch (bw_code) {
 832         case DP_LINK_BW_1_62:
 833                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G;
 834                 break;
 835         case DP_LINK_BW_2_7:
 836                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G;
 837                 break;
 838         case DP_LINK_BW_5_4:
 839         default:
 840                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G;
 841                 break;
 842         }
 843
 844         zynqmp_dp_write(dp, ZYNQMP_DP_PHY_CLOCK_SELECT, reg);
 845         ret = zynqmp_dp_phy_ready(dp);
 846         if (ret < 0)
 847                 return ret;
 848
 849         zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 1);
 850         memset(dp->train_set, 0, sizeof(dp->train_set));
 851         ret = zynqmp_dp_link_train_cr(dp);
 852         if (ret)
 853                 return ret;
 854
 855         ret = zynqmp_dp_link_train_ce(dp);
 856         if (ret)
 857                 return ret;
 858
 859         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 860                                  DP_TRAINING_PATTERN_DISABLE);
 861         if (ret < 0) {
 862                 dev_err(dp->dev, "failed to disable training pattern\n");
 863                 return ret;
 864         }
 865         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET,
 866                         DP_TRAINING_PATTERN_DISABLE);
 867
 868         zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 0);
 869
 870         return 0;
 871 }
 872
 873 /**
 874  * zynqmp_dp_train_loop - Downshift the link rate during training
 875  * @dp: DisplayPort IP core structure
 876  *
 877  * Train the link by downshifting the link rate if training is not successful.
 878  */
 879 static void zynqmp_dp_train_loop(struct zynqmp_dp *dp)
 880 {
 881         struct zynqmp_dp_mode *mode = &dp->mode;
 882         u8 bw = mode->bw_code;
 883         int ret;
 884
 885         do {
 886                 if (dp->status == connector_status_disconnected ||
 887                     !dp->enabled)
 888                         return;
 889
 890                 ret = zynqmp_dp_train(dp);
 891                 if (!ret)
 892                         return;
 893
 894                 ret = zynqmp_dp_mode_configure(dp, mode->pclock, bw);
 895                 if (ret < 0)
 896                         goto err_out;
 897
 898                 bw = ret;
 899         } while (bw >= DP_LINK_BW_1_62);
 900
 901 err_out:
 902         dev_err(dp->dev, "failed to train the DP link\n");
 903 }
 904
 905 /* -----------------------------------------------------------------------------
 906  * DisplayPort AUX
 907  */
 908
 909 #define AUX_READ_BIT    0x1
 910
 911 /**
 912  * zynqmp_dp_aux_cmd_submit - Submit aux command
 913  * @dp: DisplayPort IP core structure
 914  * @cmd: aux command
 915  * @addr: aux address
 916  * @buf: buffer for command data
 917  * @bytes: number of bytes for @buf
 918  * @reply: reply code to be returned
 919  *
 920  * Submit an aux command. All aux related commands, native or i2c aux
 921  * read/write, are submitted through this function. The function is mapped to
 922  * the transfer function of struct drm_dp_aux. This function involves in
 923  * multiple register reads/writes, thus synchronization is needed, and it is
 924  * done by drm_dp_helper using @hw_mutex. The calling thread goes into sleep
 925  * if there's no immediate reply to the command submission. The reply code is
 926  * returned at @reply if @reply != NULL.
 927  *
 928  * Return: 0 if the command is submitted properly, or corresponding error code:
 929  * -EBUSY when there is any request already being processed
 930  * -ETIMEDOUT when receiving reply is timed out
 931  * -EIO when received bytes are less than requested
 932  */
 933 static int zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr,
 934                                     u8 *buf, u8 bytes, u8 *reply)
 935 {
 936         bool is_read = (cmd & AUX_READ_BIT) ? true : false;
 937         u32 reg, i;
 938
 939         reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
 940         if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST)
 941                 return -EBUSY;
 942
 943         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_ADDRESS, addr);
 944         if (!is_read)
 945                 for (i = 0; i < bytes; i++)
 946                         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_WRITE_FIFO,
 947                                         buf[i]);
 948
 949         reg = cmd << ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT;
 950         if (!buf || !bytes)
 951                 reg |= ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY;
 952         else
 953                 reg |= (bytes - 1) << ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT;
 954         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_COMMAND, reg);
 955
 956         /* Wait for reply to be delivered upto 2ms */
 957         for (i = 0; ; i++) {
 958                 reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
 959                 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY)
 960                         break;
 961
 962                 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT ||
 963                     i == 2)
 964                         return -ETIMEDOUT;
 965
 966                 usleep_range(1000, 1100);
 967         }
 968
 969         reg = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_CODE);
 970         if (reply)
 971                 *reply = reg;
 972
 973         if (is_read &&
 974             (reg == ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK ||
 975              reg == ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK)) {
 976                 reg = zynqmp_dp_read(dp, ZYNQMP_DP_REPLY_DATA_COUNT);
 977                 if ((reg & ZYNQMP_DP_REPLY_DATA_COUNT_MASK) != bytes)
 978                         return -EIO;
 979
 980                 for (i = 0; i < bytes; i++)
 981                         buf[i] = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_DATA);
 982         }
 983
 984         return 0;
 985 }
 986
 987 static ssize_t
 988 zynqmp_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 989 {
 990         struct zynqmp_dp *dp = container_of(aux, struct zynqmp_dp, aux);
 991         int ret;
 992         unsigned int i, iter;
 993
 994         /* Number of loops = timeout in msec / aux delay (400 usec) */
 995         iter = zynqmp_dp_aux_timeout_ms * 1000 / 400;
 996         iter = iter ? iter : 1;
 997
 998         for (i = 0; i < iter; i++) {
 999                 ret = zynqmp_dp_aux_cmd_submit(dp, msg->request, msg->address,
1000                                                msg->buffer, msg->size,
1001                                                &msg->reply);
1002                 if (!ret) {
1003                         dev_vdbg(dp->dev, "aux %d retries\n", i);
1004                         return msg->size;
1005                 }
1006
1007                 if (dp->status == connector_status_disconnected) {
1008                         dev_dbg(dp->dev, "no connected aux device\n");
1009                         return -ENODEV;
1010                 }
1011
1012                 usleep_range(400, 500);
1013         }
1014
1015         dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret);
1016
1017         return ret;
1018 }
1019
1020 /**
1021  * zynqmp_dp_aux_init - Initialize and register the DP AUX
1022  * @dp: DisplayPort IP core structure
1023  *
1024  * Program the AUX clock divider and filter and register the DP AUX adapter.
1025  *
1026  * Return: 0 on success, error value otherwise
1027  */
1028 static int zynqmp_dp_aux_init(struct zynqmp_dp *dp)
1029 {
1030         unsigned long rate;
1031         unsigned int w;
1032
1033         /*
1034          * The AUX_SIGNAL_WIDTH_FILTER is the number of APB clock cycles
1035          * corresponding to the AUX pulse. Allowable values are 8, 16, 24, 32,
1036          * 40 and 48. The AUX pulse width must be between 0.4µs and 0.6µs,
1037          * compute the w / 8 value corresponding to 0.4µs rounded up, and make
1038          * sure it stays below 0.6µs and within the allowable values.
1039          */
1040         rate = clk_get_rate(dp->dpsub->apb_clk);
1041         w = DIV_ROUND_UP(4 * rate, 1000 * 1000 * 10 * 8) * 8;
1042         if (w > 6 * rate / (1000 * 1000 * 10) || w > 48) {
1043                 dev_err(dp->dev, "aclk frequency too high\n");
1044                 return -EINVAL;
1045         }
1046
1047         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_CLK_DIVIDER,
1048                         (w << ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT) |
1049                         (rate / (1000 * 1000)));
1050
1051         dp->aux.name = "ZynqMP DP AUX";
1052         dp->aux.dev = dp->dev;
1053         dp->aux.drm_dev = dp->bridge.dev;
1054         dp->aux.transfer = zynqmp_dp_aux_transfer;
1055
1056         return drm_dp_aux_register(&dp->aux);
1057 }
1058
1059 /**
1060  * zynqmp_dp_aux_cleanup - Cleanup the DP AUX
1061  * @dp: DisplayPort IP core structure
1062  *
1063  * Unregister the DP AUX adapter.
1064  */
1065 static void zynqmp_dp_aux_cleanup(struct zynqmp_dp *dp)
1066 {
1067         drm_dp_aux_unregister(&dp->aux);
1068 }
1069
1070 /* -----------------------------------------------------------------------------
1071  * DisplayPort Generic Support
1072  */
1073
1074 /**
1075  * zynqmp_dp_update_misc - Write the misc registers
1076  * @dp: DisplayPort IP core structure
1077  *
1078  * The misc register values are stored in the structure, and this
1079  * function applies the values into the registers.
1080  */
1081 static void zynqmp_dp_update_misc(struct zynqmp_dp *dp)
1082 {
1083         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC0, dp->config.misc0);
1084         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC1, dp->config.misc1);
1085 }
1086
1087 /**
1088  * zynqmp_dp_set_format - Set the input format
1089  * @dp: DisplayPort IP core structure
1090  * @info: Display info
1091  * @format: input format
1092  * @bpc: bits per component
1093  *
1094  * Update misc register values based on input @format and @bpc.
1095  *
1096  * Return: 0 on success, or -EINVAL.
1097  */
1098 static int zynqmp_dp_set_format(struct zynqmp_dp *dp,
1099                                 const struct drm_display_info *info,
1100                                 enum zynqmp_dpsub_format format,
1101                                 unsigned int bpc)
1102 {
1103         struct zynqmp_dp_config *config = &dp->config;
1104         unsigned int num_colors;
1105
1106         config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK;
1107         config->misc1 &= ~ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1108
1109         switch (format) {
1110         case ZYNQMP_DPSUB_FORMAT_RGB:
1111                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB;
1112                 num_colors = 3;
1113                 break;
1114
1115         case ZYNQMP_DPSUB_FORMAT_YCRCB444:
1116                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444;
1117                 num_colors = 3;
1118                 break;
1119
1120         case ZYNQMP_DPSUB_FORMAT_YCRCB422:
1121                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422;
1122                 num_colors = 2;
1123                 break;
1124
1125         case ZYNQMP_DPSUB_FORMAT_YONLY:
1126                 config->misc1 |= ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1127                 num_colors = 1;
1128                 break;
1129
1130         default:
1131                 dev_err(dp->dev, "Invalid colormetry in DT\n");
1132                 return -EINVAL;
1133         }
1134
1135         if (info && info->bpc && bpc > info->bpc) {
1136                 dev_warn(dp->dev,
1137                          "downgrading requested %ubpc to display limit %ubpc\n",
1138                          bpc, info->bpc);
1139                 bpc = info->bpc;
1140         }
1141
1142         config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK;
1143
1144         switch (bpc) {
1145         case 6:
1146                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6;
1147                 break;
1148         case 8:
1149                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1150                 break;
1151         case 10:
1152                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10;
1153                 break;
1154         case 12:
1155                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12;
1156                 break;
1157         case 16:
1158                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16;
1159                 break;
1160         default:
1161                 dev_warn(dp->dev, "Not supported bpc (%u). fall back to 8bpc\n",
1162                          bpc);
1163                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1164                 bpc = 8;
1165                 break;
1166         }
1167
1168         /* Update the current bpp based on the format. */
1169         config->bpp = bpc * num_colors;
1170
1171         return 0;
1172 }
1173
1174 /**
1175  * zynqmp_dp_encoder_mode_set_transfer_unit - Set the transfer unit values
1176  * @dp: DisplayPort IP core structure
1177  * @mode: requested display mode
1178  *
1179  * Set the transfer unit, and calculate all transfer unit size related values.
1180  * Calculation is based on DP and IP core specification.
1181  */
1182 static void
1183 zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp,
1184                                          const struct drm_display_mode *mode)
1185 {
1186         u32 tu = ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF;
1187         u32 bw, vid_kbytes, avg_bytes_per_tu, init_wait;
1188
1189         /* Use the max transfer unit size (default) */
1190         zynqmp_dp_write(dp, ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE, tu);
1191
1192         vid_kbytes = mode->clock * (dp->config.bpp / 8);
1193         bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1194         avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000);
1195         zynqmp_dp_write(dp, ZYNQMP_DP_MIN_BYTES_PER_TU,
1196                         avg_bytes_per_tu / 1000);
1197         zynqmp_dp_write(dp, ZYNQMP_DP_FRAC_BYTES_PER_TU,
1198                         avg_bytes_per_tu % 1000);
1199
1200         /* Configure the initial wait cycle based on transfer unit size */
1201         if (tu < (avg_bytes_per_tu / 1000))
1202                 init_wait = 0;
1203         else if ((avg_bytes_per_tu / 1000) <= 4)
1204                 init_wait = tu;
1205         else
1206                 init_wait = tu - avg_bytes_per_tu / 1000;
1207
1208         zynqmp_dp_write(dp, ZYNQMP_DP_INIT_WAIT, init_wait);
1209 }
1210
1211 /**
1212  * zynqmp_dp_encoder_mode_set_stream - Configure the main stream
1213  * @dp: DisplayPort IP core structure
1214  * @mode: requested display mode
1215  *
1216  * Configure the main stream based on the requested mode @mode. Calculation is
1217  * based on IP core specification.
1218  */
1219 static void zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp,
1220                                               const struct drm_display_mode *mode)
1221 {
1222         u8 lane_cnt = dp->mode.lane_cnt;
1223         u32 reg, wpl;
1224         unsigned int rate;
1225
1226         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HTOTAL, mode->htotal);
1227         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VTOTAL, mode->vtotal);
1228         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_POLARITY,
1229                         (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) <<
1230                          ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT) |
1231                         (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) <<
1232                          ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT));
1233         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSWIDTH,
1234                         mode->hsync_end - mode->hsync_start);
1235         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSWIDTH,
1236                         mode->vsync_end - mode->vsync_start);
1237         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HRES, mode->hdisplay);
1238         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VRES, mode->vdisplay);
1239         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSTART,
1240                         mode->htotal - mode->hsync_start);
1241         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSTART,
1242                         mode->vtotal - mode->vsync_start);
1243
1244         /* In synchronous mode, set the dividers */
1245         if (dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK) {
1246                 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1247                 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_N_VID, reg);
1248                 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_M_VID, mode->clock);
1249                 rate = zynqmp_dpsub_get_audio_clk_rate(dp->dpsub);
1250                 if (rate) {
1251                         dev_dbg(dp->dev, "Audio rate: %d\n", rate / 512);
1252                         zynqmp_dp_write(dp, ZYNQMP_DP_TX_N_AUD, reg);
1253                         zynqmp_dp_write(dp, ZYNQMP_DP_TX_M_AUD, rate / 1000);
1254                 }
1255         }
1256
1257         /* Only 2 channel audio is supported now */
1258         if (zynqmp_dpsub_audio_enabled(dp->dpsub))
1259                 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CHANNELS, 1);
1260
1261         zynqmp_dp_write(dp, ZYNQMP_DP_USER_PIX_WIDTH, 1);
1262
1263         /* Translate to the native 16 bit datapath based on IP core spec */
1264         wpl = (mode->hdisplay * dp->config.bpp + 15) / 16;
1265         reg = wpl + wpl % lane_cnt - lane_cnt;
1266         zynqmp_dp_write(dp, ZYNQMP_DP_USER_DATA_COUNT_PER_LANE, reg);
1267 }
1268
1269 /* -----------------------------------------------------------------------------
1270  * DISP Configuration
1271  */
1272
1273 /**
1274  * zynqmp_dp_disp_connected_live_layer - Return the first connected live layer
1275  * @dp: DisplayPort IP core structure
1276  *
1277  * Return: The first connected live display layer or NULL if none of the live
1278  * layers are connected.
1279  */
1280 static struct zynqmp_disp_layer *
1281 zynqmp_dp_disp_connected_live_layer(struct zynqmp_dp *dp)
1282 {
1283         if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_VIDEO))
1284                 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_VID];
1285         else if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_GFX))
1286                 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX];
1287         else
1288                 return NULL;
1289 }
1290
1291 static void zynqmp_dp_disp_enable(struct zynqmp_dp *dp,
1292                                   struct drm_bridge_state *old_bridge_state)
1293 {
1294         struct zynqmp_disp_layer *layer;
1295         struct drm_bridge_state *bridge_state;
1296         u32 bus_fmt;
1297
1298         layer = zynqmp_dp_disp_connected_live_layer(dp);
1299         if (!layer)
1300                 return;
1301
1302         bridge_state = drm_atomic_get_new_bridge_state(old_bridge_state->base.state,
1303                                                        old_bridge_state->bridge);
1304         if (WARN_ON(!bridge_state))
1305                 return;
1306
1307         bus_fmt = bridge_state->input_bus_cfg.format;
1308         zynqmp_disp_layer_set_live_format(layer, bus_fmt);
1309         zynqmp_disp_layer_enable(layer);
1310
1311         if (layer == dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX])
1312                 zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, true, 255);
1313         else
1314                 zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, false, 0);
1315
1316         zynqmp_disp_enable(dp->dpsub->disp);
1317 }
1318
1319 static void zynqmp_dp_disp_disable(struct zynqmp_dp *dp,
1320                                    struct drm_bridge_state *old_bridge_state)
1321 {
1322         struct zynqmp_disp_layer *layer;
1323
1324         layer = zynqmp_dp_disp_connected_live_layer(dp);
1325         if (!layer)
1326                 return;
1327
1328         zynqmp_disp_disable(dp->dpsub->disp);
1329         zynqmp_disp_layer_disable(layer);
1330 }
1331
1332 /* -----------------------------------------------------------------------------
1333  * DRM Bridge
1334  */
1335
1336 static int zynqmp_dp_bridge_attach(struct drm_bridge *bridge,
1337                                    enum drm_bridge_attach_flags flags)
1338 {
1339         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1340         int ret;
1341
1342         /* Initialize and register the AUX adapter. */
1343         ret = zynqmp_dp_aux_init(dp);
1344         if (ret) {
1345                 dev_err(dp->dev, "failed to initialize DP aux\n");
1346                 return ret;
1347         }
1348
1349         if (dp->next_bridge) {
1350                 ret = drm_bridge_attach(bridge->encoder, dp->next_bridge,
1351                                         bridge, flags);
1352                 if (ret < 0)
1353                         goto error;
1354         }
1355
1356         /* Now that initialisation is complete, enable interrupts. */
1357         zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_ALL);
1358
1359         return 0;
1360
1361 error:
1362         zynqmp_dp_aux_cleanup(dp);
1363         return ret;
1364 }
1365
1366 static void zynqmp_dp_bridge_detach(struct drm_bridge *bridge)
1367 {
1368         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1369
1370         zynqmp_dp_aux_cleanup(dp);
1371 }
1372
1373 static enum drm_mode_status
1374 zynqmp_dp_bridge_mode_valid(struct drm_bridge *bridge,
1375                             const struct drm_display_info *info,
1376                             const struct drm_display_mode *mode)
1377 {
1378         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1379         int rate;
1380
1381         if (mode->clock > ZYNQMP_MAX_FREQ) {
1382                 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n",
1383                         mode->name);
1384                 drm_mode_debug_printmodeline(mode);
1385                 return MODE_CLOCK_HIGH;
1386         }
1387
1388         /* Check with link rate and lane count */
1389         rate = zynqmp_dp_max_rate(dp->link_config.max_rate,
1390                                   dp->link_config.max_lanes, dp->config.bpp);
1391         if (mode->clock > rate) {
1392                 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n",
1393                         mode->name);
1394                 drm_mode_debug_printmodeline(mode);
1395                 return MODE_CLOCK_HIGH;
1396         }
1397
1398         return MODE_OK;
1399 }
1400
1401 static void zynqmp_dp_bridge_atomic_enable(struct drm_bridge *bridge,
1402                                            struct drm_bridge_state *old_bridge_state)
1403 {
1404         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1405         struct drm_atomic_state *state = old_bridge_state->base.state;
1406         const struct drm_crtc_state *crtc_state;
1407         const struct drm_display_mode *adjusted_mode;
1408         const struct drm_display_mode *mode;
1409         struct drm_connector *connector;
1410         struct drm_crtc *crtc;
1411         unsigned int i;
1412         int rate;
1413         int ret;
1414
1415         pm_runtime_get_sync(dp->dev);
1416
1417         zynqmp_dp_disp_enable(dp, old_bridge_state);
1418
1419         /*
1420          * Retrieve the CRTC mode and adjusted mode. This requires a little
1421          * dance to go from the bridge to the encoder, to the connector and to
1422          * the CRTC.
1423          */
1424         connector = drm_atomic_get_new_connector_for_encoder(state,
1425                                                              bridge->encoder);
1426         crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
1427         crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1428         adjusted_mode = &crtc_state->adjusted_mode;
1429         mode = &crtc_state->mode;
1430
1431         zynqmp_dp_set_format(dp, &connector->display_info,
1432                              ZYNQMP_DPSUB_FORMAT_RGB, 8);
1433
1434         /* Check again as bpp or format might have been changed */
1435         rate = zynqmp_dp_max_rate(dp->link_config.max_rate,
1436                                   dp->link_config.max_lanes, dp->config.bpp);
1437         if (mode->clock > rate) {
1438                 dev_err(dp->dev, "mode %s has too high pixel rate\n",
1439                         mode->name);
1440                 drm_mode_debug_printmodeline(mode);
1441         }
1442
1443         /* Configure the mode */
1444         ret = zynqmp_dp_mode_configure(dp, adjusted_mode->clock, 0);
1445         if (ret < 0) {
1446                 pm_runtime_put_sync(dp->dev);
1447                 return;
1448         }
1449
1450         zynqmp_dp_encoder_mode_set_transfer_unit(dp, adjusted_mode);
1451         zynqmp_dp_encoder_mode_set_stream(dp, adjusted_mode);
1452
1453         /* Enable the encoder */
1454         dp->enabled = true;
1455         zynqmp_dp_update_misc(dp);
1456         if (zynqmp_dpsub_audio_enabled(dp->dpsub))
1457                 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 1);
1458         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 0);
1459         if (dp->status == connector_status_connected) {
1460                 for (i = 0; i < 3; i++) {
1461                         ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER,
1462                                                  DP_SET_POWER_D0);
1463                         if (ret == 1)
1464                                 break;
1465                         usleep_range(300, 500);
1466                 }
1467                 /* Some monitors take time to wake up properly */
1468                 msleep(zynqmp_dp_power_on_delay_ms);
1469         }
1470         if (ret != 1)
1471                 dev_dbg(dp->dev, "DP aux failed\n");
1472         else
1473                 zynqmp_dp_train_loop(dp);
1474         zynqmp_dp_write(dp, ZYNQMP_DP_SOFTWARE_RESET,
1475                         ZYNQMP_DP_SOFTWARE_RESET_ALL);
1476         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 1);
1477 }
1478
1479 static void zynqmp_dp_bridge_atomic_disable(struct drm_bridge *bridge,
1480                                             struct drm_bridge_state *old_bridge_state)
1481 {
1482         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1483
1484         dp->enabled = false;
1485         cancel_work(&dp->hpd_work);
1486         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 0);
1487         drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3);
1488         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN,
1489                         ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
1490         if (zynqmp_dpsub_audio_enabled(dp->dpsub))
1491                 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 0);
1492
1493         zynqmp_dp_disp_disable(dp, old_bridge_state);
1494
1495         pm_runtime_put_sync(dp->dev);
1496 }
1497
1498 #define ZYNQMP_DP_MIN_H_BACKPORCH       20
1499
1500 static int zynqmp_dp_bridge_atomic_check(struct drm_bridge *bridge,
1501                                          struct drm_bridge_state *bridge_state,
1502                                          struct drm_crtc_state *crtc_state,
1503                                          struct drm_connector_state *conn_state)
1504 {
1505         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1506         struct drm_display_mode *mode = &crtc_state->mode;
1507         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1508         int diff = mode->htotal - mode->hsync_end;
1509
1510         /*
1511          * ZynqMP DP requires horizontal backporch to be greater than 12.
1512          * This limitation may not be compatible with the sink device.
1513          */
1514         if (diff < ZYNQMP_DP_MIN_H_BACKPORCH) {
1515                 int vrefresh = (adjusted_mode->clock * 1000) /
1516                                (adjusted_mode->vtotal * adjusted_mode->htotal);
1517
1518                 dev_dbg(dp->dev, "hbackporch adjusted: %d to %d",
1519                         diff, ZYNQMP_DP_MIN_H_BACKPORCH - diff);
1520                 diff = ZYNQMP_DP_MIN_H_BACKPORCH - diff;
1521                 adjusted_mode->htotal += diff;
1522                 adjusted_mode->clock = adjusted_mode->vtotal *
1523                                        adjusted_mode->htotal * vrefresh / 1000;
1524         }
1525
1526         return 0;
1527 }
1528
1529 static enum drm_connector_status zynqmp_dp_bridge_detect(struct drm_bridge *bridge)
1530 {
1531         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1532         struct zynqmp_dp_link_config *link_config = &dp->link_config;
1533         u32 state, i;
1534         int ret;
1535
1536         /*
1537          * This is from heuristic. It takes some delay (ex, 100 ~ 500 msec) to
1538          * get the HPD signal with some monitors.
1539          */
1540         for (i = 0; i < 10; i++) {
1541                 state = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
1542                 if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD)
1543                         break;
1544                 msleep(100);
1545         }
1546
1547         if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD) {
1548                 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd,
1549                                        sizeof(dp->dpcd));
1550                 if (ret < 0) {
1551                         dev_dbg(dp->dev, "DPCD read failed");
1552                         goto disconnected;
1553                 }
1554
1555                 link_config->max_rate = min_t(int,
1556                                               drm_dp_max_link_rate(dp->dpcd),
1557                                               DP_HIGH_BIT_RATE2);
1558                 link_config->max_lanes = min_t(u8,
1559                                                drm_dp_max_lane_count(dp->dpcd),
1560                                                dp->num_lanes);
1561
1562                 dp->status = connector_status_connected;
1563                 return connector_status_connected;
1564         }
1565
1566 disconnected:
1567         dp->status = connector_status_disconnected;
1568         return connector_status_disconnected;
1569 }
1570
1571 static const struct drm_edid *zynqmp_dp_bridge_edid_read(struct drm_bridge *bridge,
1572                                                          struct drm_connector *connector)
1573 {
1574         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1575
1576         return drm_edid_read_ddc(connector, &dp->aux.ddc);
1577 }
1578
1579 static u32 *zynqmp_dp_bridge_default_bus_fmts(unsigned int *num_input_fmts)
1580 {
1581         u32 *formats = kzalloc(sizeof(*formats), GFP_KERNEL);
1582
1583         if (formats)
1584                 *formats = MEDIA_BUS_FMT_FIXED;
1585         *num_input_fmts = !!formats;
1586
1587         return formats;
1588 }
1589
1590 static u32 *
1591 zynqmp_dp_bridge_get_input_bus_fmts(struct drm_bridge *bridge,
1592                                     struct drm_bridge_state *bridge_state,
1593                                     struct drm_crtc_state *crtc_state,
1594                                     struct drm_connector_state *conn_state,
1595                                     u32 output_fmt,
1596                                     unsigned int *num_input_fmts)
1597 {
1598         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1599         struct zynqmp_disp_layer *layer;
1600
1601         layer = zynqmp_dp_disp_connected_live_layer(dp);
1602         if (layer)
1603                 return zynqmp_disp_live_layer_formats(layer, num_input_fmts);
1604         else
1605                 return zynqmp_dp_bridge_default_bus_fmts(num_input_fmts);
1606 }
1607
1608 static const struct drm_bridge_funcs zynqmp_dp_bridge_funcs = {
1609         .attach = zynqmp_dp_bridge_attach,
1610         .detach = zynqmp_dp_bridge_detach,
1611         .mode_valid = zynqmp_dp_bridge_mode_valid,
1612         .atomic_enable = zynqmp_dp_bridge_atomic_enable,
1613         .atomic_disable = zynqmp_dp_bridge_atomic_disable,
1614         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1615         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1616         .atomic_reset = drm_atomic_helper_bridge_reset,
1617         .atomic_check = zynqmp_dp_bridge_atomic_check,
1618         .detect = zynqmp_dp_bridge_detect,
1619         .edid_read = zynqmp_dp_bridge_edid_read,
1620         .atomic_get_input_bus_fmts = zynqmp_dp_bridge_get_input_bus_fmts,
1621 };
1622
1623 /* -----------------------------------------------------------------------------
1624  * Interrupt Handling
1625  */
1626
1627 /**
1628  * zynqmp_dp_enable_vblank - Enable vblank
1629  * @dp: DisplayPort IP core structure
1630  *
1631  * Enable vblank interrupt
1632  */
1633 void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp)
1634 {
1635         zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_VBLANK_START);
1636 }
1637
1638 /**
1639  * zynqmp_dp_disable_vblank - Disable vblank
1640  * @dp: DisplayPort IP core structure
1641  *
1642  * Disable vblank interrupt
1643  */
1644 void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp)
1645 {
1646         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_VBLANK_START);
1647 }
1648
1649 static void zynqmp_dp_hpd_work_func(struct work_struct *work)
1650 {
1651         struct zynqmp_dp *dp = container_of(work, struct zynqmp_dp, hpd_work);
1652         enum drm_connector_status status;
1653
1654         status = zynqmp_dp_bridge_detect(&dp->bridge);
1655         drm_bridge_hpd_notify(&dp->bridge, status);
1656 }
1657
1658 static irqreturn_t zynqmp_dp_irq_handler(int irq, void *data)
1659 {
1660         struct zynqmp_dp *dp = (struct zynqmp_dp *)data;
1661         u32 status, mask;
1662
1663         status = zynqmp_dp_read(dp, ZYNQMP_DP_INT_STATUS);
1664         /* clear status register as soon as we read it */
1665         zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status);
1666         mask = zynqmp_dp_read(dp, ZYNQMP_DP_INT_MASK);
1667
1668         /*
1669          * Status register may report some events, which corresponding interrupts
1670          * have been disabled. Filter out those events against interrupts' mask.
1671          */
1672         status &= ~mask;
1673
1674         if (!status)
1675                 return IRQ_NONE;
1676
1677         /* dbg for diagnostic, but not much that the driver can do */
1678         if (status & ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK)
1679                 dev_dbg_ratelimited(dp->dev, "underflow interrupt\n");
1680         if (status & ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK)
1681                 dev_dbg_ratelimited(dp->dev, "overflow interrupt\n");
1682
1683         if (status & ZYNQMP_DP_INT_VBLANK_START)
1684                 zynqmp_dpsub_drm_handle_vblank(dp->dpsub);
1685
1686         if (status & ZYNQMP_DP_INT_HPD_EVENT)
1687                 schedule_work(&dp->hpd_work);
1688
1689         if (status & ZYNQMP_DP_INT_HPD_IRQ) {
1690                 int ret;
1691                 u8 status[DP_LINK_STATUS_SIZE + 2];
1692
1693                 ret = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status,
1694                                        DP_LINK_STATUS_SIZE + 2);
1695                 if (ret < 0)
1696                         goto handled;
1697
1698                 if (status[4] & DP_LINK_STATUS_UPDATED ||
1699                     !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) ||
1700                     !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) {
1701                         zynqmp_dp_train_loop(dp);
1702                 }
1703         }
1704
1705 handled:
1706         return IRQ_HANDLED;
1707 }
1708
1709 /* -----------------------------------------------------------------------------
1710  * Initialization & Cleanup
1711  */
1712
1713 int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub)
1714 {
1715         struct platform_device *pdev = to_platform_device(dpsub->dev);
1716         struct drm_bridge *bridge;
1717         struct zynqmp_dp *dp;
1718         struct resource *res;
1719         int ret;
1720
1721         dp = kzalloc(sizeof(*dp), GFP_KERNEL);
1722         if (!dp)
1723                 return -ENOMEM;
1724
1725         dp->dev = &pdev->dev;
1726         dp->dpsub = dpsub;
1727         dp->status = connector_status_disconnected;
1728
1729         INIT_WORK(&dp->hpd_work, zynqmp_dp_hpd_work_func);
1730
1731         /* Acquire all resources (IOMEM, IRQ and PHYs). */
1732         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dp");
1733         dp->iomem = devm_ioremap_resource(dp->dev, res);
1734         if (IS_ERR(dp->iomem)) {
1735                 ret = PTR_ERR(dp->iomem);
1736                 goto err_free;
1737         }
1738
1739         dp->irq = platform_get_irq(pdev, 0);
1740         if (dp->irq < 0) {
1741                 ret = dp->irq;
1742                 goto err_free;
1743         }
1744
1745         dp->reset = devm_reset_control_get(dp->dev, NULL);
1746         if (IS_ERR(dp->reset)) {
1747                 if (PTR_ERR(dp->reset) != -EPROBE_DEFER)
1748                         dev_err(dp->dev, "failed to get reset: %ld\n",
1749                                 PTR_ERR(dp->reset));
1750                 ret = PTR_ERR(dp->reset);
1751                 goto err_free;
1752         }
1753
1754         ret = zynqmp_dp_reset(dp, true);
1755         if (ret < 0)
1756                 goto err_free;
1757
1758         ret = zynqmp_dp_reset(dp, false);
1759         if (ret < 0)
1760                 goto err_free;
1761
1762         ret = zynqmp_dp_phy_probe(dp);
1763         if (ret)
1764                 goto err_reset;
1765
1766         /* Initialize the bridge. */
1767         bridge = &dp->bridge;
1768         bridge->funcs = &zynqmp_dp_bridge_funcs;
1769         bridge->ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
1770                     | DRM_BRIDGE_OP_HPD;
1771         bridge->type = DRM_MODE_CONNECTOR_DisplayPort;
1772         bridge->of_node = dp->dev->of_node;
1773         dpsub->bridge = bridge;
1774
1775         /*
1776          * Acquire the next bridge in the chain. Ignore errors caused by port@5
1777          * not being connected for backward-compatibility with older DTs.
1778          */
1779         ret = drm_of_find_panel_or_bridge(dp->dev->of_node, 5, 0, NULL,
1780                                           &dp->next_bridge);
1781         if (ret < 0 && ret != -ENODEV)
1782                 goto err_reset;
1783
1784         /* Initialize the hardware. */
1785         dp->config.misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK;
1786         zynqmp_dp_set_format(dp, NULL, ZYNQMP_DPSUB_FORMAT_RGB, 8);
1787
1788         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN,
1789                         ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
1790         zynqmp_dp_set(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET);
1791         zynqmp_dp_write(dp, ZYNQMP_DP_FORCE_SCRAMBLER_RESET, 1);
1792         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0);
1793         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff);
1794
1795         ret = zynqmp_dp_phy_init(dp);
1796         if (ret)
1797                 goto err_reset;
1798
1799         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 1);
1800
1801         /*
1802          * Now that the hardware is initialized and won't generate spurious
1803          * interrupts, request the IRQ.
1804          */
1805         ret = devm_request_threaded_irq(dp->dev, dp->irq, NULL,
1806                                         zynqmp_dp_irq_handler, IRQF_ONESHOT,
1807                                         dev_name(dp->dev), dp);
1808         if (ret < 0)
1809                 goto err_phy_exit;
1810
1811         dpsub->dp = dp;
1812
1813         dev_dbg(dp->dev, "ZynqMP DisplayPort Tx probed with %u lanes\n",
1814                 dp->num_lanes);
1815
1816         return 0;
1817
1818 err_phy_exit:
1819         zynqmp_dp_phy_exit(dp);
1820 err_reset:
1821         zynqmp_dp_reset(dp, true);
1822 err_free:
1823         kfree(dp);
1824         return ret;
1825 }
1826
1827 void zynqmp_dp_remove(struct zynqmp_dpsub *dpsub)
1828 {
1829         struct zynqmp_dp *dp = dpsub->dp;
1830
1831         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_ALL);
1832         disable_irq(dp->irq);
1833
1834         cancel_work_sync(&dp->hpd_work);
1835
1836         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0);
1837         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff);
1838
1839         zynqmp_dp_phy_exit(dp);
1840         zynqmp_dp_reset(dp, true);
1841 }