drivers/gpu/drm/xlnx/zynqmp_dp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ZynqMP DisplayPort Driver
   4  *
   5  * Copyright (C) 2017 - 2020 Xilinx, Inc.
   6  *
   7  * Authors:
   8  * - Hyun Woo Kwon <[email protected]>
   9  * - Laurent Pinchart <[email protected]>
  10  */
  11
  12 #include <drm/display/drm_dp_helper.h>
  13 #include <drm/drm_atomic_helper.h>
  14 #include <drm/drm_crtc.h>
  15 #include <drm/drm_device.h>
  16 #include <drm/drm_edid.h>
  17 #include <drm/drm_fourcc.h>
  18 #include <drm/drm_modes.h>
  19 #include <drm/drm_of.h>
  20
  21 #include <linux/bitfield.h>
  22 #include <linux/clk.h>
  23 #include <linux/debugfs.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/io.h>
  27 #include <linux/media-bus-format.h>
  28 #include <linux/module.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/phy/phy.h>
  32 #include <linux/reset.h>
  33 #include <linux/slab.h>
  34
  35 #include "zynqmp_disp.h"
  36 #include "zynqmp_dp.h"
  37 #include "zynqmp_dpsub.h"
  38 #include "zynqmp_kms.h"
  39
  40 static uint zynqmp_dp_aux_timeout_ms = 50;
  41 module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444);
  42 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
  43
  44 /*
  45  * Some sink requires a delay after power on request
  46  */
  47 static uint zynqmp_dp_power_on_delay_ms = 4;
  48 module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444);
  49 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
  50
  51 /* Link configuration registers */
  52 #define ZYNQMP_DP_LINK_BW_SET                           0x0
  53 #define ZYNQMP_DP_LANE_COUNT_SET                        0x4
  54 #define ZYNQMP_DP_ENHANCED_FRAME_EN                     0x8
  55 #define ZYNQMP_DP_TRAINING_PATTERN_SET                  0xc
  56 #define ZYNQMP_DP_LINK_QUAL_PATTERN_SET                 0x10
  57 #define ZYNQMP_DP_SCRAMBLING_DISABLE                    0x14
  58 #define ZYNQMP_DP_DOWNSPREAD_CTL                        0x18
  59 #define ZYNQMP_DP_SOFTWARE_RESET                        0x1c
  60 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM1                BIT(0)
  61 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM2                BIT(1)
  62 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM3                BIT(2)
  63 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM4                BIT(3)
  64 #define ZYNQMP_DP_SOFTWARE_RESET_AUX                    BIT(7)
  65 #define ZYNQMP_DP_SOFTWARE_RESET_ALL                    (ZYNQMP_DP_SOFTWARE_RESET_STREAM1 | \
  66                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM2 | \
  67                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM3 | \
  68                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM4 | \
  69                                                          ZYNQMP_DP_SOFTWARE_RESET_AUX)
  70 #define ZYNQMP_DP_COMP_PATTERN_80BIT_1                  0x20
  71 #define ZYNQMP_DP_COMP_PATTERN_80BIT_2                  0x24
  72 #define ZYNQMP_DP_COMP_PATTERN_80BIT_3                  0x28
  73
  74 /* Core enable registers */
  75 #define ZYNQMP_DP_TRANSMITTER_ENABLE                    0x80
  76 #define ZYNQMP_DP_MAIN_STREAM_ENABLE                    0x84
  77 #define ZYNQMP_DP_FORCE_SCRAMBLER_RESET                 0xc0
  78 #define ZYNQMP_DP_VERSION                               0xf8
  79 #define ZYNQMP_DP_VERSION_MAJOR_MASK                    GENMASK(31, 24)
  80 #define ZYNQMP_DP_VERSION_MAJOR_SHIFT                   24
  81 #define ZYNQMP_DP_VERSION_MINOR_MASK                    GENMASK(23, 16)
  82 #define ZYNQMP_DP_VERSION_MINOR_SHIFT                   16
  83 #define ZYNQMP_DP_VERSION_REVISION_MASK                 GENMASK(15, 12)
  84 #define ZYNQMP_DP_VERSION_REVISION_SHIFT                12
  85 #define ZYNQMP_DP_VERSION_PATCH_MASK                    GENMASK(11, 8)
  86 #define ZYNQMP_DP_VERSION_PATCH_SHIFT                   8
  87 #define ZYNQMP_DP_VERSION_INTERNAL_MASK                 GENMASK(7, 0)
  88 #define ZYNQMP_DP_VERSION_INTERNAL_SHIFT                0
  89
  90 /* Core ID registers */
  91 #define ZYNQMP_DP_CORE_ID                               0xfc
  92 #define ZYNQMP_DP_CORE_ID_MAJOR_MASK                    GENMASK(31, 24)
  93 #define ZYNQMP_DP_CORE_ID_MAJOR_SHIFT                   24
  94 #define ZYNQMP_DP_CORE_ID_MINOR_MASK                    GENMASK(23, 16)
  95 #define ZYNQMP_DP_CORE_ID_MINOR_SHIFT                   16
  96 #define ZYNQMP_DP_CORE_ID_REVISION_MASK                 GENMASK(15, 8)
  97 #define ZYNQMP_DP_CORE_ID_REVISION_SHIFT                8
  98 #define ZYNQMP_DP_CORE_ID_DIRECTION                     GENMASK(1)
  99
 100 /* AUX channel interface registers */
 101 #define ZYNQMP_DP_AUX_COMMAND                           0x100
 102 #define ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT                 8
 103 #define ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY              BIT(12)
 104 #define ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT               0
 105 #define ZYNQMP_DP_AUX_WRITE_FIFO                        0x104
 106 #define ZYNQMP_DP_AUX_ADDRESS                           0x108
 107 #define ZYNQMP_DP_AUX_CLK_DIVIDER                       0x10c
 108 #define ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT      8
 109 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE                0x130
 110 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD            BIT(0)
 111 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST        BIT(1)
 112 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY          BIT(2)
 113 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT  BIT(3)
 114 #define ZYNQMP_DP_AUX_REPLY_DATA                        0x134
 115 #define ZYNQMP_DP_AUX_REPLY_CODE                        0x138
 116 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK                (0)
 117 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_NACK               BIT(0)
 118 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_DEFER              BIT(1)
 119 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK                (0)
 120 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_NACK               BIT(2)
 121 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_DEFER              BIT(3)
 122 #define ZYNQMP_DP_AUX_REPLY_COUNT                       0x13c
 123 #define ZYNQMP_DP_REPLY_DATA_COUNT                      0x148
 124 #define ZYNQMP_DP_REPLY_DATA_COUNT_MASK                 0xff
 125 #define ZYNQMP_DP_INT_STATUS                            0x3a0
 126 #define ZYNQMP_DP_INT_MASK                              0x3a4
 127 #define ZYNQMP_DP_INT_EN                                0x3a8
 128 #define ZYNQMP_DP_INT_DS                                0x3ac
 129 #define ZYNQMP_DP_INT_HPD_IRQ                           BIT(0)
 130 #define ZYNQMP_DP_INT_HPD_EVENT                         BIT(1)
 131 #define ZYNQMP_DP_INT_REPLY_RECEIVED                    BIT(2)
 132 #define ZYNQMP_DP_INT_REPLY_TIMEOUT                     BIT(3)
 133 #define ZYNQMP_DP_INT_HPD_PULSE_DET                     BIT(4)
 134 #define ZYNQMP_DP_INT_EXT_PKT_TXD                       BIT(5)
 135 #define ZYNQMP_DP_INT_LIV_ABUF_UNDRFLW                  BIT(12)
 136 #define ZYNQMP_DP_INT_VBLANK_START                      BIT(13)
 137 #define ZYNQMP_DP_INT_PIXEL1_MATCH                      BIT(14)
 138 #define ZYNQMP_DP_INT_PIXEL0_MATCH                      BIT(15)
 139 #define ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK               0x3f0000
 140 #define ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK                0xfc00000
 141 #define ZYNQMP_DP_INT_CUST_TS_2                         BIT(28)
 142 #define ZYNQMP_DP_INT_CUST_TS                           BIT(29)
 143 #define ZYNQMP_DP_INT_EXT_VSYNC_TS                      BIT(30)
 144 #define ZYNQMP_DP_INT_VSYNC_TS                          BIT(31)
 145 #define ZYNQMP_DP_INT_ALL                               (ZYNQMP_DP_INT_HPD_IRQ | \
 146                                                          ZYNQMP_DP_INT_HPD_EVENT | \
 147                                                          ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK | \
 148                                                          ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK)
 149
 150 /* Main stream attribute registers */
 151 #define ZYNQMP_DP_MAIN_STREAM_HTOTAL                    0x180
 152 #define ZYNQMP_DP_MAIN_STREAM_VTOTAL                    0x184
 153 #define ZYNQMP_DP_MAIN_STREAM_POLARITY                  0x188
 154 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT      0
 155 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT      1
 156 #define ZYNQMP_DP_MAIN_STREAM_HSWIDTH                   0x18c
 157 #define ZYNQMP_DP_MAIN_STREAM_VSWIDTH                   0x190
 158 #define ZYNQMP_DP_MAIN_STREAM_HRES                      0x194
 159 #define ZYNQMP_DP_MAIN_STREAM_VRES                      0x198
 160 #define ZYNQMP_DP_MAIN_STREAM_HSTART                    0x19c
 161 #define ZYNQMP_DP_MAIN_STREAM_VSTART                    0x1a0
 162 #define ZYNQMP_DP_MAIN_STREAM_MISC0                     0x1a4
 163 #define ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK           BIT(0)
 164 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB     (0 << 1)
 165 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422       (5 << 1)
 166 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444       (6 << 1)
 167 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK    (7 << 1)
 168 #define ZYNQMP_DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE       BIT(3)
 169 #define ZYNQMP_DP_MAIN_STREAM_MISC0_YCBCR_COLR          BIT(4)
 170 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6               (0 << 5)
 171 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8               (1 << 5)
 172 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10              (2 << 5)
 173 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12              (3 << 5)
 174 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16              (4 << 5)
 175 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK            (7 << 5)
 176 #define ZYNQMP_DP_MAIN_STREAM_MISC1                     0x1a8
 177 #define ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN           BIT(7)
 178 #define ZYNQMP_DP_MAIN_STREAM_M_VID                     0x1ac
 179 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE                0x1b0
 180 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF    64
 181 #define ZYNQMP_DP_MAIN_STREAM_N_VID                     0x1b4
 182 #define ZYNQMP_DP_USER_PIX_WIDTH                        0x1b8
 183 #define ZYNQMP_DP_USER_DATA_COUNT_PER_LANE              0x1bc
 184 #define ZYNQMP_DP_MIN_BYTES_PER_TU                      0x1c4
 185 #define ZYNQMP_DP_FRAC_BYTES_PER_TU                     0x1c8
 186 #define ZYNQMP_DP_INIT_WAIT                             0x1cc
 187
 188 /* PHY configuration and status registers */
 189 #define ZYNQMP_DP_PHY_RESET                             0x200
 190 #define ZYNQMP_DP_PHY_RESET_PHY_RESET                   BIT(0)
 191 #define ZYNQMP_DP_PHY_RESET_GTTX_RESET                  BIT(1)
 192 #define ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET               BIT(8)
 193 #define ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET               BIT(9)
 194 #define ZYNQMP_DP_PHY_RESET_ALL_RESET                   (ZYNQMP_DP_PHY_RESET_PHY_RESET | \
 195                                                          ZYNQMP_DP_PHY_RESET_GTTX_RESET | \
 196                                                          ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET | \
 197                                                          ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET)
 198 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_0                0x210
 199 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_1                0x214
 200 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_2                0x218
 201 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_3                0x21c
 202 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_0               0x220
 203 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_1               0x224
 204 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_2               0x228
 205 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_3               0x22c
 206 #define ZYNQMP_DP_PHY_CLOCK_SELECT                      0x234
 207 #define ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G                0x1
 208 #define ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G                0x3
 209 #define ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G                0x5
 210 #define ZYNQMP_DP_TX_PHY_POWER_DOWN                     0x238
 211 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_0              BIT(0)
 212 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_1              BIT(1)
 213 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_2              BIT(2)
 214 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_3              BIT(3)
 215 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL                 0xf
 216 #define ZYNQMP_DP_TRANSMIT_PRBS7                        0x230
 217 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_0                  0x23c
 218 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_1                  0x240
 219 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_2                  0x244
 220 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_3                  0x248
 221 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_0                 0x24c
 222 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_1                 0x250
 223 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_2                 0x254
 224 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_3                 0x258
 225 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0           0x24c
 226 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_1           0x250
 227 #define ZYNQMP_DP_PHY_STATUS                            0x280
 228 #define ZYNQMP_DP_PHY_STATUS_PLL_LOCKED_SHIFT           4
 229 #define ZYNQMP_DP_PHY_STATUS_FPGA_PLL_LOCKED            BIT(6)
 230
 231 /* Audio registers */
 232 #define ZYNQMP_DP_TX_AUDIO_CONTROL                      0x300
 233 #define ZYNQMP_DP_TX_AUDIO_CHANNELS                     0x304
 234 #define ZYNQMP_DP_TX_AUDIO_INFO_DATA                    0x308
 235 #define ZYNQMP_DP_TX_M_AUD                              0x328
 236 #define ZYNQMP_DP_TX_N_AUD                              0x32c
 237 #define ZYNQMP_DP_TX_AUDIO_EXT_DATA                     0x330
 238
 239 #define ZYNQMP_DP_MAX_LANES                             2
 240 #define ZYNQMP_MAX_FREQ                                 3000000
 241
 242 #define DP_REDUCED_BIT_RATE                             162000
 243 #define DP_HIGH_BIT_RATE                                270000
 244 #define DP_HIGH_BIT_RATE2                               540000
 245 #define DP_MAX_TRAINING_TRIES                           5
 246 #define DP_V1_2                                         0x12
 247
 248 /**
 249  * struct zynqmp_dp_link_config - Common link config between source and sink
 250  * @max_rate: maximum link rate
 251  * @max_lanes: maximum number of lanes
 252  */
 253 struct zynqmp_dp_link_config {
 254         int max_rate;
 255         u8 max_lanes;
 256 };
 257
 258 /**
 259  * struct zynqmp_dp_mode - Configured mode of DisplayPort
 260  * @bw_code: code for bandwidth(link rate)
 261  * @lane_cnt: number of lanes
 262  * @pclock: pixel clock frequency of current mode
 263  * @fmt: format identifier string
 264  */
 265 struct zynqmp_dp_mode {
 266         const char *fmt;
 267         int pclock;
 268         u8 bw_code;
 269         u8 lane_cnt;
 270 };
 271
 272 /**
 273  * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
 274  * @misc0: misc0 configuration (per DP v1.2 spec)
 275  * @misc1: misc1 configuration (per DP v1.2 spec)
 276  * @bpp: bits per pixel
 277  */
 278 struct zynqmp_dp_config {
 279         u8 misc0;
 280         u8 misc1;
 281         u8 bpp;
 282 };
 283
 284 /**
 285  * enum test_pattern - Test patterns for test testing
 286  * @TEST_VIDEO: Use regular video input
 287  * @TEST_SYMBOL_ERROR: Symbol error measurement pattern
 288  * @TEST_PRBS7: Output of the PRBS7 (x^7 + x^6 + 1) polynomial
 289  * @TEST_80BIT_CUSTOM: A custom 80-bit pattern
 290  * @TEST_CP2520: HBR2 compliance eye pattern
 291  * @TEST_TPS1: Link training symbol pattern TPS1 (/D10.2/)
 292  * @TEST_TPS2: Link training symbol pattern TPS2
 293  * @TEST_TPS3: Link training symbol pattern TPS3 (for HBR2)
 294  */
 295 enum test_pattern {
 296         TEST_VIDEO,
 297         TEST_TPS1,
 298         TEST_TPS2,
 299         TEST_TPS3,
 300         TEST_SYMBOL_ERROR,
 301         TEST_PRBS7,
 302         TEST_80BIT_CUSTOM,
 303         TEST_CP2520,
 304 };
 305
 306 static const char *const test_pattern_str[] = {
 307         [TEST_VIDEO] = "video",
 308         [TEST_TPS1] = "tps1",
 309         [TEST_TPS2] = "tps2",
 310         [TEST_TPS3] = "tps3",
 311         [TEST_SYMBOL_ERROR] = "symbol-error",
 312         [TEST_PRBS7] = "prbs7",
 313         [TEST_80BIT_CUSTOM] = "80bit-custom",
 314         [TEST_CP2520] = "cp2520",
 315 };
 316
 317 /**
 318  * struct zynqmp_dp_test - Configuration for test mode
 319  * @pattern: The test pattern
 320  * @enhanced: Use enhanced framing
 321  * @downspread: Use SSC
 322  * @active: Whether test mode is active
 323  * @custom: Custom pattern for %TEST_80BIT_CUSTOM
 324  * @train_set: Voltage/preemphasis settings
 325  * @bw_code: Bandwidth code for the link
 326  * @link_cnt: Number of lanes
 327  */
 328 struct zynqmp_dp_test {
 329         enum test_pattern pattern;
 330         bool enhanced, downspread, active;
 331         u8 custom[10];
 332         u8 train_set[ZYNQMP_DP_MAX_LANES];
 333         u8 bw_code;
 334         u8 link_cnt;
 335 };
 336
 337 /**
 338  * struct zynqmp_dp_train_set_priv - Private data for train_set debugfs files
 339  * @dp: DisplayPort IP core structure
 340  * @lane: The lane for this file
 341  */
 342 struct zynqmp_dp_train_set_priv {
 343         struct zynqmp_dp *dp;
 344         int lane;
 345 };
 346
 347 /**
 348  * struct zynqmp_dp - Xilinx DisplayPort core
 349  * @dev: device structure
 350  * @dpsub: Display subsystem
 351  * @iomem: device I/O memory for register access
 352  * @reset: reset controller
 353  * @lock: Mutex protecting this struct and register access (but not AUX)
 354  * @irq: irq
 355  * @bridge: DRM bridge for the DP encoder
 356  * @next_bridge: The downstream bridge
 357  * @test: Configuration for test mode
 358  * @config: IP core configuration from DTS
 359  * @aux: aux channel
 360  * @aux_done: Completed when we get an AUX reply or timeout
 361  * @ignore_aux_errors: If set, AUX errors are suppressed
 362  * @phy: PHY handles for DP lanes
 363  * @num_lanes: number of enabled phy lanes
 364  * @hpd_work: hot plug detection worker
 365  * @hpd_irq_work: hot plug detection IRQ worker
 366  * @ignore_hpd: If set, HPD events and IRQs are ignored
 367  * @status: connection status
 368  * @enabled: flag to indicate if the device is enabled
 369  * @dpcd: DP configuration data from currently connected sink device
 370  * @link_config: common link configuration between IP core and sink device
 371  * @mode: current mode between IP core and sink device
 372  * @train_set: set of training data
 373  * @debugfs_train_set: Debugfs private data for @train_set
 374  *
 375  * @lock covers the link configuration in this struct and the device's
 376  * registers. It does not cover @aux or @ignore_aux_errors. It is not strictly
 377  * required for any of the members which are only modified at probe/remove time
 378  * (e.g. @dev).
 379  */
 380 struct zynqmp_dp {
 381         struct drm_dp_aux aux;
 382         struct drm_bridge bridge;
 383         struct work_struct hpd_work;
 384         struct work_struct hpd_irq_work;
 385         struct completion aux_done;
 386         struct mutex lock;
 387
 388         struct drm_bridge *next_bridge;
 389         struct device *dev;
 390         struct zynqmp_dpsub *dpsub;
 391         void __iomem *iomem;
 392         struct reset_control *reset;
 393         struct phy *phy[ZYNQMP_DP_MAX_LANES];
 394
 395         enum drm_connector_status status;
 396         int irq;
 397         bool enabled;
 398         bool ignore_aux_errors;
 399         bool ignore_hpd;
 400
 401         struct zynqmp_dp_train_set_priv debugfs_train_set[ZYNQMP_DP_MAX_LANES];
 402         struct zynqmp_dp_mode mode;
 403         struct zynqmp_dp_link_config link_config;
 404         struct zynqmp_dp_test test;
 405         struct zynqmp_dp_config config;
 406         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 407         u8 train_set[ZYNQMP_DP_MAX_LANES];
 408         u8 num_lanes;
 409 };
 410
 411 static inline struct zynqmp_dp *bridge_to_dp(struct drm_bridge *bridge)
 412 {
 413         return container_of(bridge, struct zynqmp_dp, bridge);
 414 }
 415
 416 static void zynqmp_dp_write(struct zynqmp_dp *dp, int offset, u32 val)
 417 {
 418         writel(val, dp->iomem + offset);
 419 }
 420
 421 static u32 zynqmp_dp_read(struct zynqmp_dp *dp, int offset)
 422 {
 423         return readl(dp->iomem + offset);
 424 }
 425
 426 static void zynqmp_dp_clr(struct zynqmp_dp *dp, int offset, u32 clr)
 427 {
 428         zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) & ~clr);
 429 }
 430
 431 static void zynqmp_dp_set(struct zynqmp_dp *dp, int offset, u32 set)
 432 {
 433         zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) | set);
 434 }
 435
 436 /* -----------------------------------------------------------------------------
 437  * PHY Handling
 438  */
 439
 440 #define RST_TIMEOUT_MS                  1000
 441
 442 static int zynqmp_dp_reset(struct zynqmp_dp *dp, bool assert)
 443 {
 444         unsigned long timeout;
 445
 446         if (assert)
 447                 reset_control_assert(dp->reset);
 448         else
 449                 reset_control_deassert(dp->reset);
 450
 451         /* Wait for the (de)assert to complete. */
 452         timeout = jiffies + msecs_to_jiffies(RST_TIMEOUT_MS);
 453         while (!time_after_eq(jiffies, timeout)) {
 454                 bool status = !!reset_control_status(dp->reset);
 455
 456                 if (assert == status)
 457                         return 0;
 458
 459                 cpu_relax();
 460         }
 461
 462         dev_err(dp->dev, "reset %s timeout\n", assert ? "assert" : "deassert");
 463         return -ETIMEDOUT;
 464 }
 465
 466 /**
 467  * zynqmp_dp_phy_init - Initialize the phy
 468  * @dp: DisplayPort IP core structure
 469  *
 470  * Initialize the phy.
 471  *
 472  * Return: 0 if the phy instances are initialized correctly, or the error code
 473  * returned from the callee functions.
 474  */
 475 static int zynqmp_dp_phy_init(struct zynqmp_dp *dp)
 476 {
 477         int ret;
 478         int i;
 479
 480         for (i = 0; i < dp->num_lanes; i++) {
 481                 ret = phy_init(dp->phy[i]);
 482                 if (ret) {
 483                         dev_err(dp->dev, "failed to init phy lane %d\n", i);
 484                         return ret;
 485                 }
 486         }
 487
 488         zynqmp_dp_clr(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET);
 489
 490         /*
 491          * Power on lanes in reverse order as only lane 0 waits for the PLL to
 492          * lock.
 493          */
 494         for (i = dp->num_lanes - 1; i >= 0; i--) {
 495                 ret = phy_power_on(dp->phy[i]);
 496                 if (ret) {
 497                         dev_err(dp->dev, "failed to power on phy lane %d\n", i);
 498                         return ret;
 499                 }
 500         }
 501
 502         return 0;
 503 }
 504
 505 /**
 506  * zynqmp_dp_phy_exit - Exit the phy
 507  * @dp: DisplayPort IP core structure
 508  *
 509  * Exit the phy.
 510  */
 511 static void zynqmp_dp_phy_exit(struct zynqmp_dp *dp)
 512 {
 513         unsigned int i;
 514         int ret;
 515
 516         for (i = 0; i < dp->num_lanes; i++) {
 517                 ret = phy_power_off(dp->phy[i]);
 518                 if (ret)
 519                         dev_err(dp->dev, "failed to power off phy(%d) %d\n", i,
 520                                 ret);
 521         }
 522
 523         for (i = 0; i < dp->num_lanes; i++) {
 524                 ret = phy_exit(dp->phy[i]);
 525                 if (ret)
 526                         dev_err(dp->dev, "failed to exit phy(%d) %d\n", i, ret);
 527         }
 528 }
 529
 530 /**
 531  * zynqmp_dp_phy_probe - Probe the PHYs
 532  * @dp: DisplayPort IP core structure
 533  *
 534  * Probe PHYs for all lanes. Less PHYs may be available than the number of
 535  * lanes, which is not considered an error as long as at least one PHY is
 536  * found. The caller can check dp->num_lanes to check how many PHYs were found.
 537  *
 538  * Return:
 539  * * 0                          - Success
 540  * * -ENXIO                     - No PHY found
 541  * * -EPROBE_DEFER              - Probe deferral requested
 542  * * Other negative value       - PHY retrieval failure
 543  */
 544 static int zynqmp_dp_phy_probe(struct zynqmp_dp *dp)
 545 {
 546         unsigned int i;
 547
 548         for (i = 0; i < ZYNQMP_DP_MAX_LANES; i++) {
 549                 char phy_name[16];
 550                 struct phy *phy;
 551
 552                 snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i);
 553                 phy = devm_phy_get(dp->dev, phy_name);
 554
 555                 if (IS_ERR(phy)) {
 556                         switch (PTR_ERR(phy)) {
 557                         case -ENODEV:
 558                                 if (dp->num_lanes)
 559                                         return 0;
 560
 561                                 dev_err(dp->dev, "no PHY found\n");
 562                                 return -ENXIO;
 563
 564                         case -EPROBE_DEFER:
 565                                 return -EPROBE_DEFER;
 566
 567                         default:
 568                                 dev_err(dp->dev, "failed to get PHY lane %u\n",
 569                                         i);
 570                                 return PTR_ERR(phy);
 571                         }
 572                 }
 573
 574                 dp->phy[i] = phy;
 575                 dp->num_lanes++;
 576         }
 577
 578         return 0;
 579 }
 580
 581 /**
 582  * zynqmp_dp_phy_ready - Check if PHY is ready
 583  * @dp: DisplayPort IP core structure
 584  *
 585  * Check if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times.
 586  * This amount of delay was suggested by IP designer.
 587  *
 588  * Return: 0 if PHY is ready, or -ENODEV if PHY is not ready.
 589  */
 590 static int zynqmp_dp_phy_ready(struct zynqmp_dp *dp)
 591 {
 592         u32 i, reg, ready;
 593
 594         ready = (1 << dp->num_lanes) - 1;
 595
 596         /* Wait for 100 * 1ms. This should be enough time for PHY to be ready */
 597         for (i = 0; ; i++) {
 598                 reg = zynqmp_dp_read(dp, ZYNQMP_DP_PHY_STATUS);
 599                 if ((reg & ready) == ready)
 600                         return 0;
 601
 602                 if (i == 100) {
 603                         dev_err(dp->dev, "PHY isn't ready\n");
 604                         return -ENODEV;
 605                 }
 606
 607                 usleep_range(1000, 1100);
 608         }
 609
 610         return 0;
 611 }
 612
 613 /* -----------------------------------------------------------------------------
 614  * DisplayPort Link Training
 615  */
 616
 617 /**
 618  * zynqmp_dp_max_rate - Calculate and return available max pixel clock
 619  * @link_rate: link rate (Kilo-bytes / sec)
 620  * @lane_num: number of lanes
 621  * @bpp: bits per pixel
 622  *
 623  * Return: max pixel clock (KHz) supported by current link config.
 624  */
 625 static inline int zynqmp_dp_max_rate(int link_rate, u8 lane_num, u8 bpp)
 626 {
 627         return link_rate * lane_num * 8 / bpp;
 628 }
 629
 630 /**
 631  * zynqmp_dp_mode_configure - Configure the link values
 632  * @dp: DisplayPort IP core structure
 633  * @pclock: pixel clock for requested display mode
 634  * @current_bw: current link rate
 635  *
 636  * Find the link configuration values, rate and lane count for requested pixel
 637  * clock @pclock. The @pclock is stored in the mode to be used in other
 638  * functions later. The returned rate is downshifted from the current rate
 639  * @current_bw.
 640  *
 641  * Return: Current link rate code, or -EINVAL.
 642  */
 643 static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock,
 644                                     u8 current_bw)
 645 {
 646         int max_rate = dp->link_config.max_rate;
 647         u8 bw_code;
 648         u8 max_lanes = dp->link_config.max_lanes;
 649         u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
 650         u8 bpp = dp->config.bpp;
 651         u8 lane_cnt;
 652
 653         /* Downshift from current bandwidth */
 654         switch (current_bw) {
 655         case DP_LINK_BW_5_4:
 656                 bw_code = DP_LINK_BW_2_7;
 657                 break;
 658         case DP_LINK_BW_2_7:
 659                 bw_code = DP_LINK_BW_1_62;
 660                 break;
 661         case DP_LINK_BW_1_62:
 662                 dev_err(dp->dev, "can't downshift. already lowest link rate\n");
 663                 return -EINVAL;
 664         default:
 665                 /* If not given, start with max supported */
 666                 bw_code = max_link_rate_code;
 667                 break;
 668         }
 669
 670         for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
 671                 int bw;
 672                 u32 rate;
 673
 674                 bw = drm_dp_bw_code_to_link_rate(bw_code);
 675                 rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp);
 676                 if (pclock <= rate) {
 677                         dp->mode.bw_code = bw_code;
 678                         dp->mode.lane_cnt = lane_cnt;
 679                         dp->mode.pclock = pclock;
 680                         return dp->mode.bw_code;
 681                 }
 682         }
 683
 684         dev_err(dp->dev, "failed to configure link values\n");
 685
 686         return -EINVAL;
 687 }
 688
 689 /**
 690  * zynqmp_dp_adjust_train - Adjust train values
 691  * @dp: DisplayPort IP core structure
 692  * @link_status: link status from sink which contains requested training values
 693  */
 694 static void zynqmp_dp_adjust_train(struct zynqmp_dp *dp,
 695                                    u8 link_status[DP_LINK_STATUS_SIZE])
 696 {
 697         u8 *train_set = dp->train_set;
 698         u8 i;
 699
 700         for (i = 0; i < dp->mode.lane_cnt; i++) {
 701                 u8 voltage = drm_dp_get_adjust_request_voltage(link_status, i);
 702                 u8 preemphasis =
 703                         drm_dp_get_adjust_request_pre_emphasis(link_status, i);
 704
 705                 if (voltage >= DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
 706                         voltage |= DP_TRAIN_MAX_SWING_REACHED;
 707
 708                 if (preemphasis >= DP_TRAIN_PRE_EMPH_LEVEL_2)
 709                         preemphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 710
 711                 train_set[i] = voltage | preemphasis;
 712         }
 713 }
 714
 715 /**
 716  * zynqmp_dp_update_vs_emph - Update the training values
 717  * @dp: DisplayPort IP core structure
 718  * @train_set: A set of training values
 719  *
 720  * Update the training values based on the request from sink. The mapped values
 721  * are predefined, and values(vs, pe, pc) are from the device manual.
 722  *
 723  * Return: 0 if vs and emph are updated successfully, or the error code returned
 724  * by drm_dp_dpcd_write().
 725  */
 726 static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp, u8 *train_set)
 727 {
 728         unsigned int i;
 729         int ret;
 730
 731         ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set,
 732                                 dp->mode.lane_cnt);
 733         if (ret < 0)
 734                 return ret;
 735
 736         for (i = 0; i < dp->mode.lane_cnt; i++) {
 737                 u32 reg = ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 + i * 4;
 738                 union phy_configure_opts opts = { 0 };
 739                 u8 train = train_set[i];
 740
 741                 opts.dp.voltage[0] = (train & DP_TRAIN_VOLTAGE_SWING_MASK)
 742                                    >> DP_TRAIN_VOLTAGE_SWING_SHIFT;
 743                 opts.dp.pre[0] = (train & DP_TRAIN_PRE_EMPHASIS_MASK)
 744                                >> DP_TRAIN_PRE_EMPHASIS_SHIFT;
 745
 746                 phy_configure(dp->phy[i], &opts);
 747
 748                 zynqmp_dp_write(dp, reg, 0x2);
 749         }
 750
 751         return 0;
 752 }
 753
 754 /**
 755  * zynqmp_dp_link_train_cr - Train clock recovery
 756  * @dp: DisplayPort IP core structure
 757  *
 758  * Return: 0 if clock recovery train is done successfully, or corresponding
 759  * error code.
 760  */
 761 static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp)
 762 {
 763         u8 link_status[DP_LINK_STATUS_SIZE];
 764         u8 lane_cnt = dp->mode.lane_cnt;
 765         u8 vs = 0, tries = 0;
 766         u16 max_tries, i;
 767         bool cr_done;
 768         int ret;
 769
 770         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET,
 771                         DP_TRAINING_PATTERN_1);
 772         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 773                                  DP_TRAINING_PATTERN_1 |
 774                                  DP_LINK_SCRAMBLING_DISABLE);
 775         if (ret < 0)
 776                 return ret;
 777
 778         /*
 779          * 256 loops should be maximum iterations for 4 lanes and 4 values.
 780          * So, This loop should exit before 512 iterations
 781          */
 782         for (max_tries = 0; max_tries < 512; max_tries++) {
 783                 ret = zynqmp_dp_update_vs_emph(dp, dp->train_set);
 784                 if (ret)
 785                         return ret;
 786
 787                 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd);
 788                 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
 789                 if (ret < 0)
 790                         return ret;
 791
 792                 cr_done = drm_dp_clock_recovery_ok(link_status, lane_cnt);
 793                 if (cr_done)
 794                         break;
 795
 796                 for (i = 0; i < lane_cnt; i++)
 797                         if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED))
 798                                 break;
 799                 if (i == lane_cnt)
 800                         break;
 801
 802                 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs)
 803                         tries++;
 804                 else
 805                         tries = 0;
 806
 807                 if (tries == DP_MAX_TRAINING_TRIES)
 808                         break;
 809
 810                 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 811                 zynqmp_dp_adjust_train(dp, link_status);
 812         }
 813
 814         if (!cr_done)
 815                 return -EIO;
 816
 817         return 0;
 818 }
 819
 820 /**
 821  * zynqmp_dp_link_train_ce - Train channel equalization
 822  * @dp: DisplayPort IP core structure
 823  *
 824  * Return: 0 if channel equalization train is done successfully, or
 825  * corresponding error code.
 826  */
 827 static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp)
 828 {
 829         u8 link_status[DP_LINK_STATUS_SIZE];
 830         u8 lane_cnt = dp->mode.lane_cnt;
 831         u32 pat, tries;
 832         int ret;
 833         bool ce_done;
 834
 835         if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 &&
 836             dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED)
 837                 pat = DP_TRAINING_PATTERN_3;
 838         else
 839                 pat = DP_TRAINING_PATTERN_2;
 840
 841         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, pat);
 842         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 843                                  pat | DP_LINK_SCRAMBLING_DISABLE);
 844         if (ret < 0)
 845                 return ret;
 846
 847         for (tries = 0; tries < DP_MAX_TRAINING_TRIES; tries++) {
 848                 ret = zynqmp_dp_update_vs_emph(dp, dp->train_set);
 849                 if (ret)
 850                         return ret;
 851
 852                 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd);
 853                 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
 854                 if (ret < 0)
 855                         return ret;
 856
 857                 ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt);
 858                 if (ce_done)
 859                         break;
 860
 861                 zynqmp_dp_adjust_train(dp, link_status);
 862         }
 863
 864         if (!ce_done)
 865                 return -EIO;
 866
 867         return 0;
 868 }
 869
 870 /**
 871  * zynqmp_dp_setup() - Set up major link parameters
 872  * @dp: DisplayPort IP core structure
 873  * @bw_code: The link bandwidth as a multiple of 270 MHz
 874  * @lane_cnt: The number of lanes to use
 875  * @enhanced: Use enhanced framing
 876  * @downspread: Enable spread-spectrum clocking
 877  *
 878  * Return: 0 on success, or -errno on failure
 879  */
 880 static int zynqmp_dp_setup(struct zynqmp_dp *dp, u8 bw_code, u8 lane_cnt,
 881                            bool enhanced, bool downspread)
 882 {
 883         u32 reg;
 884         u8 aux_lane_cnt = lane_cnt;
 885         int ret;
 886
 887         zynqmp_dp_write(dp, ZYNQMP_DP_LANE_COUNT_SET, lane_cnt);
 888         if (enhanced) {
 889                 zynqmp_dp_write(dp, ZYNQMP_DP_ENHANCED_FRAME_EN, 1);
 890                 aux_lane_cnt |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 891         }
 892
 893         if (downspread) {
 894                 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 1);
 895                 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL,
 896                                    DP_SPREAD_AMP_0_5);
 897         } else {
 898                 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 0);
 899                 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0);
 900         }
 901
 902         ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt);
 903         if (ret < 0) {
 904                 dev_err(dp->dev, "failed to set lane count\n");
 905                 return ret;
 906         }
 907
 908         ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
 909                                  DP_SET_ANSI_8B10B);
 910         if (ret < 0) {
 911                 dev_err(dp->dev, "failed to set ANSI 8B/10B encoding\n");
 912                 return ret;
 913         }
 914
 915         ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code);
 916         if (ret < 0) {
 917                 dev_err(dp->dev, "failed to set DP bandwidth\n");
 918                 return ret;
 919         }
 920
 921         zynqmp_dp_write(dp, ZYNQMP_DP_LINK_BW_SET, bw_code);
 922         switch (bw_code) {
 923         case DP_LINK_BW_1_62:
 924                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G;
 925                 break;
 926         case DP_LINK_BW_2_7:
 927                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G;
 928                 break;
 929         case DP_LINK_BW_5_4:
 930         default:
 931                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G;
 932                 break;
 933         }
 934
 935         zynqmp_dp_write(dp, ZYNQMP_DP_PHY_CLOCK_SELECT, reg);
 936         return zynqmp_dp_phy_ready(dp);
 937 }
 938
 939 /**
 940  * zynqmp_dp_train - Train the link
 941  * @dp: DisplayPort IP core structure
 942  *
 943  * Return: 0 if all trains are done successfully, or corresponding error code.
 944  */
 945 static int zynqmp_dp_train(struct zynqmp_dp *dp)
 946 {
 947         int ret;
 948
 949         ret = zynqmp_dp_setup(dp, dp->mode.bw_code, dp->mode.lane_cnt,
 950                               drm_dp_enhanced_frame_cap(dp->dpcd),
 951                               dp->dpcd[DP_MAX_DOWNSPREAD] &
 952                               DP_MAX_DOWNSPREAD_0_5);
 953         if (ret)
 954                 return ret;
 955
 956         zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 1);
 957         memset(dp->train_set, 0, sizeof(dp->train_set));
 958         ret = zynqmp_dp_link_train_cr(dp);
 959         if (ret)
 960                 return ret;
 961
 962         ret = zynqmp_dp_link_train_ce(dp);
 963         if (ret)
 964                 return ret;
 965
 966         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 967                                  DP_TRAINING_PATTERN_DISABLE);
 968         if (ret < 0) {
 969                 dev_err(dp->dev, "failed to disable training pattern\n");
 970                 return ret;
 971         }
 972         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET,
 973                         DP_TRAINING_PATTERN_DISABLE);
 974
 975         zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 0);
 976
 977         return 0;
 978 }
 979
 980 /**
 981  * zynqmp_dp_train_loop - Downshift the link rate during training
 982  * @dp: DisplayPort IP core structure
 983  *
 984  * Train the link by downshifting the link rate if training is not successful.
 985  */
 986 static void zynqmp_dp_train_loop(struct zynqmp_dp *dp)
 987 {
 988         struct zynqmp_dp_mode *mode = &dp->mode;
 989         u8 bw = mode->bw_code;
 990         int ret;
 991
 992         do {
 993                 if (dp->status == connector_status_disconnected ||
 994                     !dp->enabled)
 995                         return;
 996
 997                 ret = zynqmp_dp_train(dp);
 998                 if (!ret)
 999                         return;
1000
1001                 ret = zynqmp_dp_mode_configure(dp, mode->pclock, bw);
1002                 if (ret < 0)
1003                         goto err_out;
1004
1005                 bw = ret;
1006         } while (bw >= DP_LINK_BW_1_62);
1007
1008 err_out:
1009         dev_err(dp->dev, "failed to train the DP link\n");
1010 }
1011
1012 /* -----------------------------------------------------------------------------
1013  * DisplayPort AUX
1014  */
1015
1016 #define AUX_READ_BIT    0x1
1017
1018 /**
1019  * zynqmp_dp_aux_cmd_submit - Submit aux command
1020  * @dp: DisplayPort IP core structure
1021  * @cmd: aux command
1022  * @addr: aux address
1023  * @buf: buffer for command data
1024  * @bytes: number of bytes for @buf
1025  * @reply: reply code to be returned
1026  *
1027  * Submit an aux command. All aux related commands, native or i2c aux
1028  * read/write, are submitted through this function. The function is mapped to
1029  * the transfer function of struct drm_dp_aux. This function involves in
1030  * multiple register reads/writes, thus synchronization is needed, and it is
1031  * done by drm_dp_helper using @hw_mutex. The calling thread goes into sleep
1032  * if there's no immediate reply to the command submission. The reply code is
1033  * returned at @reply if @reply != NULL.
1034  *
1035  * Return: 0 if the command is submitted properly, or corresponding error code:
1036  * -EBUSY when there is any request already being processed
1037  * -ETIMEDOUT when receiving reply is timed out
1038  * -EIO when received bytes are less than requested
1039  */
1040 static int zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr,
1041                                     u8 *buf, u8 bytes, u8 *reply)
1042 {
1043         bool is_read = (cmd & AUX_READ_BIT) ? true : false;
1044         unsigned long time_left;
1045         u32 reg, i;
1046
1047         reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
1048         if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST)
1049                 return -EBUSY;
1050
1051         reinit_completion(&dp->aux_done);
1052
1053         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_ADDRESS, addr);
1054         if (!is_read)
1055                 for (i = 0; i < bytes; i++)
1056                         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_WRITE_FIFO,
1057                                         buf[i]);
1058
1059         reg = cmd << ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT;
1060         if (!buf || !bytes)
1061                 reg |= ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY;
1062         else
1063                 reg |= (bytes - 1) << ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT;
1064         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_COMMAND, reg);
1065
1066         /* Wait for reply to be delivered upto 2ms */
1067         time_left = wait_for_completion_timeout(&dp->aux_done,
1068                                                 msecs_to_jiffies(2));
1069         if (!time_left)
1070                 return -ETIMEDOUT;
1071
1072         reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
1073         if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT)
1074                 return -ETIMEDOUT;
1075
1076         reg = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_CODE);
1077         if (reply)
1078                 *reply = reg;
1079
1080         if (is_read &&
1081             (reg == ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK ||
1082              reg == ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK)) {
1083                 reg = zynqmp_dp_read(dp, ZYNQMP_DP_REPLY_DATA_COUNT);
1084                 if ((reg & ZYNQMP_DP_REPLY_DATA_COUNT_MASK) != bytes)
1085                         return -EIO;
1086
1087                 for (i = 0; i < bytes; i++)
1088                         buf[i] = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_DATA);
1089         }
1090
1091         return 0;
1092 }
1093
1094 static ssize_t
1095 zynqmp_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1096 {
1097         struct zynqmp_dp *dp = container_of(aux, struct zynqmp_dp, aux);
1098         int ret;
1099         unsigned int i, iter;
1100
1101         /* Number of loops = timeout in msec / aux delay (400 usec) */
1102         iter = zynqmp_dp_aux_timeout_ms * 1000 / 400;
1103         iter = iter ? iter : 1;
1104
1105         for (i = 0; i < iter; i++) {
1106                 ret = zynqmp_dp_aux_cmd_submit(dp, msg->request, msg->address,
1107                                                msg->buffer, msg->size,
1108                                                &msg->reply);
1109                 if (!ret) {
1110                         dev_vdbg(dp->dev, "aux %d retries\n", i);
1111                         return msg->size;
1112                 }
1113
1114                 if (dp->status == connector_status_disconnected) {
1115                         dev_dbg(dp->dev, "no connected aux device\n");
1116                         if (dp->ignore_aux_errors)
1117                                 goto fake_response;
1118                         return -ENODEV;
1119                 }
1120
1121                 usleep_range(400, 500);
1122         }
1123
1124         dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret);
1125
1126         if (!dp->ignore_aux_errors)
1127                 return ret;
1128
1129 fake_response:
1130         msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1131         memset(msg->buffer, 0, msg->size);
1132         return msg->size;
1133 }
1134
1135 /**
1136  * zynqmp_dp_aux_init - Initialize and register the DP AUX
1137  * @dp: DisplayPort IP core structure
1138  *
1139  * Program the AUX clock divider and filter and register the DP AUX adapter.
1140  *
1141  * Return: 0 on success, error value otherwise
1142  */
1143 static int zynqmp_dp_aux_init(struct zynqmp_dp *dp)
1144 {
1145         unsigned long rate;
1146         unsigned int w;
1147
1148         /*
1149          * The AUX_SIGNAL_WIDTH_FILTER is the number of APB clock cycles
1150          * corresponding to the AUX pulse. Allowable values are 8, 16, 24, 32,
1151          * 40 and 48. The AUX pulse width must be between 0.4µs and 0.6µs,
1152          * compute the w / 8 value corresponding to 0.4µs rounded up, and make
1153          * sure it stays below 0.6µs and within the allowable values.
1154          */
1155         rate = clk_get_rate(dp->dpsub->apb_clk);
1156         w = DIV_ROUND_UP(4 * rate, 1000 * 1000 * 10 * 8) * 8;
1157         if (w > 6 * rate / (1000 * 1000 * 10) || w > 48) {
1158                 dev_err(dp->dev, "aclk frequency too high\n");
1159                 return -EINVAL;
1160         }
1161
1162         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_CLK_DIVIDER,
1163                         (w << ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT) |
1164                         (rate / (1000 * 1000)));
1165
1166         zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_REPLY_RECEIVED |
1167                                               ZYNQMP_DP_INT_REPLY_TIMEOUT);
1168
1169         dp->aux.name = "ZynqMP DP AUX";
1170         dp->aux.dev = dp->dev;
1171         dp->aux.drm_dev = dp->bridge.dev;
1172         dp->aux.transfer = zynqmp_dp_aux_transfer;
1173
1174         return drm_dp_aux_register(&dp->aux);
1175 }
1176
1177 /**
1178  * zynqmp_dp_aux_cleanup - Cleanup the DP AUX
1179  * @dp: DisplayPort IP core structure
1180  *
1181  * Unregister the DP AUX adapter.
1182  */
1183 static void zynqmp_dp_aux_cleanup(struct zynqmp_dp *dp)
1184 {
1185         drm_dp_aux_unregister(&dp->aux);
1186
1187         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_REPLY_RECEIVED |
1188                                               ZYNQMP_DP_INT_REPLY_TIMEOUT);
1189 }
1190
1191 /* -----------------------------------------------------------------------------
1192  * DisplayPort Generic Support
1193  */
1194
1195 /**
1196  * zynqmp_dp_update_misc - Write the misc registers
1197  * @dp: DisplayPort IP core structure
1198  *
1199  * The misc register values are stored in the structure, and this
1200  * function applies the values into the registers.
1201  */
1202 static void zynqmp_dp_update_misc(struct zynqmp_dp *dp)
1203 {
1204         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC0, dp->config.misc0);
1205         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC1, dp->config.misc1);
1206 }
1207
1208 /**
1209  * zynqmp_dp_set_format - Set the input format
1210  * @dp: DisplayPort IP core structure
1211  * @info: Display info
1212  * @format: input format
1213  * @bpc: bits per component
1214  *
1215  * Update misc register values based on input @format and @bpc.
1216  *
1217  * Return: 0 on success, or -EINVAL.
1218  */
1219 static int zynqmp_dp_set_format(struct zynqmp_dp *dp,
1220                                 const struct drm_display_info *info,
1221                                 enum zynqmp_dpsub_format format,
1222                                 unsigned int bpc)
1223 {
1224         struct zynqmp_dp_config *config = &dp->config;
1225         unsigned int num_colors;
1226
1227         config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK;
1228         config->misc1 &= ~ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1229
1230         switch (format) {
1231         case ZYNQMP_DPSUB_FORMAT_RGB:
1232                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB;
1233                 num_colors = 3;
1234                 break;
1235
1236         case ZYNQMP_DPSUB_FORMAT_YCRCB444:
1237                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444;
1238                 num_colors = 3;
1239                 break;
1240
1241         case ZYNQMP_DPSUB_FORMAT_YCRCB422:
1242                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422;
1243                 num_colors = 2;
1244                 break;
1245
1246         case ZYNQMP_DPSUB_FORMAT_YONLY:
1247                 config->misc1 |= ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1248                 num_colors = 1;
1249                 break;
1250
1251         default:
1252                 dev_err(dp->dev, "Invalid colormetry in DT\n");
1253                 return -EINVAL;
1254         }
1255
1256         if (info && info->bpc && bpc > info->bpc) {
1257                 dev_warn(dp->dev,
1258                          "downgrading requested %ubpc to display limit %ubpc\n",
1259                          bpc, info->bpc);
1260                 bpc = info->bpc;
1261         }
1262
1263         config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK;
1264
1265         switch (bpc) {
1266         case 6:
1267                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6;
1268                 break;
1269         case 8:
1270                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1271                 break;
1272         case 10:
1273                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10;
1274                 break;
1275         case 12:
1276                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12;
1277                 break;
1278         case 16:
1279                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16;
1280                 break;
1281         default:
1282                 dev_warn(dp->dev, "Not supported bpc (%u). fall back to 8bpc\n",
1283                          bpc);
1284                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1285                 bpc = 8;
1286                 break;
1287         }
1288
1289         /* Update the current bpp based on the format. */
1290         config->bpp = bpc * num_colors;
1291
1292         return 0;
1293 }
1294
1295 /**
1296  * zynqmp_dp_encoder_mode_set_transfer_unit - Set the transfer unit values
1297  * @dp: DisplayPort IP core structure
1298  * @mode: requested display mode
1299  *
1300  * Set the transfer unit, and calculate all transfer unit size related values.
1301  * Calculation is based on DP and IP core specification.
1302  */
1303 static void
1304 zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp,
1305                                          const struct drm_display_mode *mode)
1306 {
1307         u32 tu = ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF;
1308         u32 bw, vid_kbytes, avg_bytes_per_tu, init_wait;
1309
1310         /* Use the max transfer unit size (default) */
1311         zynqmp_dp_write(dp, ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE, tu);
1312
1313         vid_kbytes = mode->clock * (dp->config.bpp / 8);
1314         bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1315         avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000);
1316         zynqmp_dp_write(dp, ZYNQMP_DP_MIN_BYTES_PER_TU,
1317                         avg_bytes_per_tu / 1000);
1318         zynqmp_dp_write(dp, ZYNQMP_DP_FRAC_BYTES_PER_TU,
1319                         avg_bytes_per_tu % 1000);
1320
1321         /* Configure the initial wait cycle based on transfer unit size */
1322         if (tu < (avg_bytes_per_tu / 1000))
1323                 init_wait = 0;
1324         else if ((avg_bytes_per_tu / 1000) <= 4)
1325                 init_wait = tu;
1326         else
1327                 init_wait = tu - avg_bytes_per_tu / 1000;
1328
1329         zynqmp_dp_write(dp, ZYNQMP_DP_INIT_WAIT, init_wait);
1330 }
1331
1332 /**
1333  * zynqmp_dp_encoder_mode_set_stream - Configure the main stream
1334  * @dp: DisplayPort IP core structure
1335  * @mode: requested display mode
1336  *
1337  * Configure the main stream based on the requested mode @mode. Calculation is
1338  * based on IP core specification.
1339  */
1340 static void zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp,
1341                                               const struct drm_display_mode *mode)
1342 {
1343         u8 lane_cnt = dp->mode.lane_cnt;
1344         u32 reg, wpl;
1345
1346         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HTOTAL, mode->htotal);
1347         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VTOTAL, mode->vtotal);
1348         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_POLARITY,
1349                         (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) <<
1350                          ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT) |
1351                         (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) <<
1352                          ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT));
1353         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSWIDTH,
1354                         mode->hsync_end - mode->hsync_start);
1355         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSWIDTH,
1356                         mode->vsync_end - mode->vsync_start);
1357         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HRES, mode->hdisplay);
1358         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VRES, mode->vdisplay);
1359         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSTART,
1360                         mode->htotal - mode->hsync_start);
1361         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSTART,
1362                         mode->vtotal - mode->vsync_start);
1363
1364         /* In synchronous mode, set the dividers */
1365         if (dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK) {
1366                 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1367                 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_N_VID, reg);
1368                 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_M_VID, mode->clock);
1369         }
1370
1371         zynqmp_dp_write(dp, ZYNQMP_DP_USER_PIX_WIDTH, 1);
1372
1373         /* Translate to the native 16 bit datapath based on IP core spec */
1374         wpl = (mode->hdisplay * dp->config.bpp + 15) / 16;
1375         reg = wpl + wpl % lane_cnt - lane_cnt;
1376         zynqmp_dp_write(dp, ZYNQMP_DP_USER_DATA_COUNT_PER_LANE, reg);
1377 }
1378
1379 /* -----------------------------------------------------------------------------
1380  * Audio
1381  */
1382
1383 void zynqmp_dp_audio_set_channels(struct zynqmp_dp *dp,
1384                                   unsigned int num_channels)
1385 {
1386         zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CHANNELS, num_channels - 1);
1387 }
1388
1389 void zynqmp_dp_audio_enable(struct zynqmp_dp *dp)
1390 {
1391         zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 1);
1392 }
1393
1394 void zynqmp_dp_audio_disable(struct zynqmp_dp *dp)
1395 {
1396         zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 0);
1397 }
1398
1399 void zynqmp_dp_audio_write_n_m(struct zynqmp_dp *dp)
1400 {
1401         unsigned int rate;
1402         u32 link_rate;
1403
1404         if (!(dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK))
1405                 return;
1406
1407         link_rate = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1408
1409         rate = clk_get_rate(dp->dpsub->aud_clk);
1410
1411         dev_dbg(dp->dev, "Audio rate: %d\n", rate / 512);
1412
1413         zynqmp_dp_write(dp, ZYNQMP_DP_TX_N_AUD, link_rate);
1414         zynqmp_dp_write(dp, ZYNQMP_DP_TX_M_AUD, rate / 1000);
1415 }
1416
1417 /* -----------------------------------------------------------------------------
1418  * DISP Configuration
1419  */
1420
1421 /**
1422  * zynqmp_dp_disp_connected_live_layer - Return the first connected live layer
1423  * @dp: DisplayPort IP core structure
1424  *
1425  * Return: The first connected live display layer or NULL if none of the live
1426  * layers are connected.
1427  */
1428 static struct zynqmp_disp_layer *
1429 zynqmp_dp_disp_connected_live_layer(struct zynqmp_dp *dp)
1430 {
1431         if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_VIDEO))
1432                 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_VID];
1433         else if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_GFX))
1434                 return dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX];
1435         else
1436                 return NULL;
1437 }
1438
1439 static void zynqmp_dp_disp_enable(struct zynqmp_dp *dp,
1440                                   struct drm_bridge_state *old_bridge_state)
1441 {
1442         struct zynqmp_disp_layer *layer;
1443         struct drm_bridge_state *bridge_state;
1444         u32 bus_fmt;
1445
1446         layer = zynqmp_dp_disp_connected_live_layer(dp);
1447         if (!layer)
1448                 return;
1449
1450         bridge_state = drm_atomic_get_new_bridge_state(old_bridge_state->base.state,
1451                                                        old_bridge_state->bridge);
1452         if (WARN_ON(!bridge_state))
1453                 return;
1454
1455         bus_fmt = bridge_state->input_bus_cfg.format;
1456         zynqmp_disp_layer_set_live_format(layer, bus_fmt);
1457         zynqmp_disp_layer_enable(layer);
1458
1459         if (layer == dp->dpsub->layers[ZYNQMP_DPSUB_LAYER_GFX])
1460                 zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, true, 255);
1461         else
1462                 zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, false, 0);
1463
1464         zynqmp_disp_enable(dp->dpsub->disp);
1465 }
1466
1467 static void zynqmp_dp_disp_disable(struct zynqmp_dp *dp,
1468                                    struct drm_bridge_state *old_bridge_state)
1469 {
1470         struct zynqmp_disp_layer *layer;
1471
1472         layer = zynqmp_dp_disp_connected_live_layer(dp);
1473         if (!layer)
1474                 return;
1475
1476         zynqmp_disp_disable(dp->dpsub->disp);
1477         zynqmp_disp_layer_disable(layer);
1478 }
1479
1480 /* -----------------------------------------------------------------------------
1481  * DRM Bridge
1482  */
1483
1484 static int zynqmp_dp_bridge_attach(struct drm_bridge *bridge,
1485                                    enum drm_bridge_attach_flags flags)
1486 {
1487         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1488         int ret;
1489
1490         /* Initialize and register the AUX adapter. */
1491         ret = zynqmp_dp_aux_init(dp);
1492         if (ret) {
1493                 dev_err(dp->dev, "failed to initialize DP aux\n");
1494                 return ret;
1495         }
1496
1497         if (dp->next_bridge) {
1498                 ret = drm_bridge_attach(bridge->encoder, dp->next_bridge,
1499                                         bridge, flags);
1500                 if (ret < 0)
1501                         goto error;
1502         }
1503
1504         /* Now that initialisation is complete, enable interrupts. */
1505         zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_ALL);
1506
1507         return 0;
1508
1509 error:
1510         zynqmp_dp_aux_cleanup(dp);
1511         return ret;
1512 }
1513
1514 static void zynqmp_dp_bridge_detach(struct drm_bridge *bridge)
1515 {
1516         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1517
1518         zynqmp_dp_aux_cleanup(dp);
1519 }
1520
1521 static enum drm_mode_status
1522 zynqmp_dp_bridge_mode_valid(struct drm_bridge *bridge,
1523                             const struct drm_display_info *info,
1524                             const struct drm_display_mode *mode)
1525 {
1526         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1527         int rate;
1528
1529         if (mode->clock > ZYNQMP_MAX_FREQ) {
1530                 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n",
1531                         mode->name);
1532                 drm_mode_debug_printmodeline(mode);
1533                 return MODE_CLOCK_HIGH;
1534         }
1535
1536         /* Check with link rate and lane count */
1537         mutex_lock(&dp->lock);
1538         rate = zynqmp_dp_max_rate(dp->link_config.max_rate,
1539                                   dp->link_config.max_lanes, dp->config.bpp);
1540         mutex_unlock(&dp->lock);
1541         if (mode->clock > rate) {
1542                 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n",
1543                         mode->name);
1544                 drm_mode_debug_printmodeline(mode);
1545                 return MODE_CLOCK_HIGH;
1546         }
1547
1548         return MODE_OK;
1549 }
1550
1551 static void zynqmp_dp_bridge_atomic_enable(struct drm_bridge *bridge,
1552                                            struct drm_bridge_state *old_bridge_state)
1553 {
1554         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1555         struct drm_atomic_state *state = old_bridge_state->base.state;
1556         const struct drm_crtc_state *crtc_state;
1557         const struct drm_display_mode *adjusted_mode;
1558         const struct drm_display_mode *mode;
1559         struct drm_connector *connector;
1560         struct drm_crtc *crtc;
1561         unsigned int i;
1562         int rate;
1563         int ret;
1564
1565         pm_runtime_get_sync(dp->dev);
1566
1567         guard(mutex)(&dp->lock);
1568         zynqmp_dp_disp_enable(dp, old_bridge_state);
1569
1570         /*
1571          * Retrieve the CRTC mode and adjusted mode. This requires a little
1572          * dance to go from the bridge to the encoder, to the connector and to
1573          * the CRTC.
1574          */
1575         connector = drm_atomic_get_new_connector_for_encoder(state,
1576                                                              bridge->encoder);
1577         crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
1578         crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1579         adjusted_mode = &crtc_state->adjusted_mode;
1580         mode = &crtc_state->mode;
1581
1582         zynqmp_dp_set_format(dp, &connector->display_info,
1583                              ZYNQMP_DPSUB_FORMAT_RGB, 8);
1584
1585         /* Check again as bpp or format might have been changed */
1586         rate = zynqmp_dp_max_rate(dp->link_config.max_rate,
1587                                   dp->link_config.max_lanes, dp->config.bpp);
1588         if (mode->clock > rate) {
1589                 dev_err(dp->dev, "mode %s has too high pixel rate\n",
1590                         mode->name);
1591                 drm_mode_debug_printmodeline(mode);
1592         }
1593
1594         /* Configure the mode */
1595         ret = zynqmp_dp_mode_configure(dp, adjusted_mode->clock, 0);
1596         if (ret < 0) {
1597                 pm_runtime_put_sync(dp->dev);
1598                 return;
1599         }
1600
1601         zynqmp_dp_encoder_mode_set_transfer_unit(dp, adjusted_mode);
1602         zynqmp_dp_encoder_mode_set_stream(dp, adjusted_mode);
1603
1604         /* Enable the encoder */
1605         dp->enabled = true;
1606         zynqmp_dp_update_misc(dp);
1607
1608         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 0);
1609         if (dp->status == connector_status_connected) {
1610                 for (i = 0; i < 3; i++) {
1611                         ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER,
1612                                                  DP_SET_POWER_D0);
1613                         if (ret == 1)
1614                                 break;
1615                         usleep_range(300, 500);
1616                 }
1617                 /* Some monitors take time to wake up properly */
1618                 msleep(zynqmp_dp_power_on_delay_ms);
1619         }
1620         if (ret != 1)
1621                 dev_dbg(dp->dev, "DP aux failed\n");
1622         else
1623                 zynqmp_dp_train_loop(dp);
1624         zynqmp_dp_write(dp, ZYNQMP_DP_SOFTWARE_RESET,
1625                         ZYNQMP_DP_SOFTWARE_RESET_ALL);
1626         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 1);
1627 }
1628
1629 static void zynqmp_dp_bridge_atomic_disable(struct drm_bridge *bridge,
1630                                             struct drm_bridge_state *old_bridge_state)
1631 {
1632         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1633
1634         mutex_lock(&dp->lock);
1635         dp->enabled = false;
1636         cancel_work(&dp->hpd_work);
1637         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 0);
1638         drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3);
1639         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN,
1640                         ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
1641
1642         zynqmp_dp_disp_disable(dp, old_bridge_state);
1643         mutex_unlock(&dp->lock);
1644
1645         pm_runtime_put_sync(dp->dev);
1646 }
1647
1648 #define ZYNQMP_DP_MIN_H_BACKPORCH       20
1649
1650 static int zynqmp_dp_bridge_atomic_check(struct drm_bridge *bridge,
1651                                          struct drm_bridge_state *bridge_state,
1652                                          struct drm_crtc_state *crtc_state,
1653                                          struct drm_connector_state *conn_state)
1654 {
1655         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1656         struct drm_display_mode *mode = &crtc_state->mode;
1657         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1658         int diff = mode->htotal - mode->hsync_end;
1659
1660         /*
1661          * ZynqMP DP requires horizontal backporch to be greater than 12.
1662          * This limitation may not be compatible with the sink device.
1663          */
1664         if (diff < ZYNQMP_DP_MIN_H_BACKPORCH) {
1665                 int vrefresh = (adjusted_mode->clock * 1000) /
1666                                (adjusted_mode->vtotal * adjusted_mode->htotal);
1667
1668                 dev_dbg(dp->dev, "hbackporch adjusted: %d to %d",
1669                         diff, ZYNQMP_DP_MIN_H_BACKPORCH - diff);
1670                 diff = ZYNQMP_DP_MIN_H_BACKPORCH - diff;
1671                 adjusted_mode->htotal += diff;
1672                 adjusted_mode->clock = adjusted_mode->vtotal *
1673                                        adjusted_mode->htotal * vrefresh / 1000;
1674         }
1675
1676         return 0;
1677 }
1678
1679 static enum drm_connector_status __zynqmp_dp_bridge_detect(struct zynqmp_dp *dp)
1680 {
1681         struct zynqmp_dp_link_config *link_config = &dp->link_config;
1682         u32 state, i;
1683         int ret;
1684
1685         lockdep_assert_held(&dp->lock);
1686
1687         /*
1688          * This is from heuristic. It takes some delay (ex, 100 ~ 500 msec) to
1689          * get the HPD signal with some monitors.
1690          */
1691         for (i = 0; i < 10; i++) {
1692                 state = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
1693                 if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD)
1694                         break;
1695                 msleep(100);
1696         }
1697
1698         if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD) {
1699                 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd,
1700                                        sizeof(dp->dpcd));
1701                 if (ret < 0) {
1702                         dev_dbg(dp->dev, "DPCD read failed");
1703                         goto disconnected;
1704                 }
1705
1706                 link_config->max_rate = min_t(int,
1707                                               drm_dp_max_link_rate(dp->dpcd),
1708                                               DP_HIGH_BIT_RATE2);
1709                 link_config->max_lanes = min_t(u8,
1710                                                drm_dp_max_lane_count(dp->dpcd),
1711                                                dp->num_lanes);
1712
1713                 dp->status = connector_status_connected;
1714                 return connector_status_connected;
1715         }
1716
1717 disconnected:
1718         dp->status = connector_status_disconnected;
1719         return connector_status_disconnected;
1720 }
1721
1722 static enum drm_connector_status zynqmp_dp_bridge_detect(struct drm_bridge *bridge)
1723 {
1724         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1725         enum drm_connector_status ret;
1726
1727         mutex_lock(&dp->lock);
1728         ret = __zynqmp_dp_bridge_detect(dp);
1729         mutex_unlock(&dp->lock);
1730
1731         return ret;
1732 }
1733
1734 static const struct drm_edid *zynqmp_dp_bridge_edid_read(struct drm_bridge *bridge,
1735                                                          struct drm_connector *connector)
1736 {
1737         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1738
1739         return drm_edid_read_ddc(connector, &dp->aux.ddc);
1740 }
1741
1742 static u32 *zynqmp_dp_bridge_default_bus_fmts(unsigned int *num_input_fmts)
1743 {
1744         u32 *formats = kzalloc(sizeof(*formats), GFP_KERNEL);
1745
1746         if (formats)
1747                 *formats = MEDIA_BUS_FMT_FIXED;
1748         *num_input_fmts = !!formats;
1749
1750         return formats;
1751 }
1752
1753 static u32 *
1754 zynqmp_dp_bridge_get_input_bus_fmts(struct drm_bridge *bridge,
1755                                     struct drm_bridge_state *bridge_state,
1756                                     struct drm_crtc_state *crtc_state,
1757                                     struct drm_connector_state *conn_state,
1758                                     u32 output_fmt,
1759                                     unsigned int *num_input_fmts)
1760 {
1761         struct zynqmp_dp *dp = bridge_to_dp(bridge);
1762         struct zynqmp_disp_layer *layer;
1763
1764         layer = zynqmp_dp_disp_connected_live_layer(dp);
1765         if (layer)
1766                 return zynqmp_disp_live_layer_formats(layer, num_input_fmts);
1767         else
1768                 return zynqmp_dp_bridge_default_bus_fmts(num_input_fmts);
1769 }
1770
1771 /* -----------------------------------------------------------------------------
1772  * debugfs
1773  */
1774
1775 /**
1776  * zynqmp_dp_set_test_pattern() - Configure the link for a test pattern
1777  * @dp: DisplayPort IP core structure
1778  * @pattern: The test pattern to configure
1779  * @custom: The custom pattern to use if @pattern is %TEST_80BIT_CUSTOM
1780  *
1781  * Return: 0 on success, or negative errno on (DPCD) failure
1782  */
1783 static int zynqmp_dp_set_test_pattern(struct zynqmp_dp *dp,
1784                                       enum test_pattern pattern,
1785                                       u8 *const custom)
1786 {
1787         bool scramble = false;
1788         u32 train_pattern = 0;
1789         u32 link_pattern = 0;
1790         u8 dpcd_train = 0;
1791         u8 dpcd_link = 0;
1792         int ret;
1793
1794         switch (pattern) {
1795         case TEST_TPS1:
1796                 train_pattern = 1;
1797                 break;
1798         case TEST_TPS2:
1799                 train_pattern = 2;
1800                 break;
1801         case TEST_TPS3:
1802                 train_pattern = 3;
1803                 break;
1804         case TEST_SYMBOL_ERROR:
1805                 scramble = true;
1806                 link_pattern = DP_PHY_TEST_PATTERN_ERROR_COUNT;
1807                 break;
1808         case TEST_PRBS7:
1809                 /* We use a dedicated register to enable PRBS7 */
1810                 dpcd_link = DP_LINK_QUAL_PATTERN_ERROR_RATE;
1811                 break;
1812         case TEST_80BIT_CUSTOM: {
1813                 const u8 *p = custom;
1814
1815                 link_pattern = DP_LINK_QUAL_PATTERN_80BIT_CUSTOM;
1816
1817                 zynqmp_dp_write(dp, ZYNQMP_DP_COMP_PATTERN_80BIT_1,
1818                                 (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]);
1819                 zynqmp_dp_write(dp, ZYNQMP_DP_COMP_PATTERN_80BIT_2,
1820                                 (p[7] << 24) | (p[6] << 16) | (p[5] << 8) | p[4]);
1821                 zynqmp_dp_write(dp, ZYNQMP_DP_COMP_PATTERN_80BIT_3,
1822                                 (p[9] << 8) | p[8]);
1823                 break;
1824         }
1825         case TEST_CP2520:
1826                 link_pattern = DP_LINK_QUAL_PATTERN_CP2520_PAT_1;
1827                 break;
1828         default:
1829                 WARN_ON_ONCE(1);
1830                 fallthrough;
1831         case TEST_VIDEO:
1832                 scramble = true;
1833         }
1834
1835         zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, !scramble);
1836         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, train_pattern);
1837         zynqmp_dp_write(dp, ZYNQMP_DP_LINK_QUAL_PATTERN_SET, link_pattern);
1838         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMIT_PRBS7, pattern == TEST_PRBS7);
1839
1840         dpcd_link = dpcd_link ?: link_pattern;
1841         dpcd_train = train_pattern;
1842         if (!scramble)
1843                 dpcd_train |= DP_LINK_SCRAMBLING_DISABLE;
1844
1845         if (dp->dpcd[DP_DPCD_REV] < 0x12) {
1846                 if (pattern == TEST_CP2520)
1847                         dev_warn(dp->dev,
1848                                 "can't set sink link quality pattern to CP2520 for DPCD < r1.2; error counters will be invalid\n");
1849                 else
1850                         dpcd_train |= FIELD_PREP(DP_LINK_QUAL_PATTERN_11_MASK,
1851                                                  dpcd_link);
1852         } else {
1853                 u8 dpcd_link_lane[ZYNQMP_DP_MAX_LANES];
1854
1855                 memset(dpcd_link_lane, dpcd_link, ZYNQMP_DP_MAX_LANES);
1856                 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_QUAL_LANE0_SET,
1857                                         dpcd_link_lane, ZYNQMP_DP_MAX_LANES);
1858                 if (ret < 0)
1859                         return ret;
1860         }
1861
1862         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, dpcd_train);
1863         return ret < 0 ? ret : 0;
1864 }
1865
1866 static int zynqmp_dp_test_setup(struct zynqmp_dp *dp)
1867 {
1868         return zynqmp_dp_setup(dp, dp->test.bw_code, dp->test.link_cnt,
1869                                dp->test.enhanced, dp->test.downspread);
1870 }
1871
1872 static ssize_t zynqmp_dp_pattern_read(struct file *file, char __user *user_buf,
1873                                       size_t count, loff_t *ppos)
1874 {
1875         struct dentry *dentry = file->f_path.dentry;
1876         struct zynqmp_dp *dp = file->private_data;
1877         char buf[16];
1878         ssize_t ret;
1879
1880         ret = debugfs_file_get(dentry);
1881         if (unlikely(ret))
1882                 return ret;
1883
1884         mutex_lock(&dp->lock);
1885         ret = snprintf(buf, sizeof(buf), "%s\n",
1886                        test_pattern_str[dp->test.pattern]);
1887         mutex_unlock(&dp->lock);
1888
1889         debugfs_file_put(dentry);
1890         return simple_read_from_buffer(user_buf, count, ppos, buf, ret);
1891 }
1892
1893 static ssize_t zynqmp_dp_pattern_write(struct file *file,
1894                                        const char __user *user_buf,
1895                                        size_t count, loff_t *ppos)
1896 {
1897         struct dentry *dentry = file->f_path.dentry;
1898         struct zynqmp_dp *dp = file->private_data;
1899         char buf[16];
1900         ssize_t ret;
1901         int pattern;
1902
1903         ret = debugfs_file_get(dentry);
1904         if (unlikely(ret))
1905                 return ret;
1906
1907         ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf,
1908                                      count);
1909         if (ret < 0)
1910                 goto out;
1911         buf[ret] = '\0';
1912
1913         pattern = sysfs_match_string(test_pattern_str, buf);
1914         if (pattern < 0) {
1915                 ret = -EINVAL;
1916                 goto out;
1917         }
1918
1919         mutex_lock(&dp->lock);
1920         dp->test.pattern = pattern;
1921         if (dp->test.active)
1922                 ret = zynqmp_dp_set_test_pattern(dp, dp->test.pattern,
1923                                                  dp->test.custom) ?: ret;
1924         mutex_unlock(&dp->lock);
1925
1926 out:
1927         debugfs_file_put(dentry);
1928         return ret;
1929 }
1930
1931 static const struct file_operations fops_zynqmp_dp_pattern = {
1932         .read = zynqmp_dp_pattern_read,
1933         .write = zynqmp_dp_pattern_write,
1934         .open = simple_open,
1935         .llseek = noop_llseek,
1936 };
1937
1938 static int zynqmp_dp_enhanced_get(void *data, u64 *val)
1939 {
1940         struct zynqmp_dp *dp = data;
1941
1942         mutex_lock(&dp->lock);
1943         *val = dp->test.enhanced;
1944         mutex_unlock(&dp->lock);
1945         return 0;
1946 }
1947
1948 static int zynqmp_dp_enhanced_set(void *data, u64 val)
1949 {
1950         struct zynqmp_dp *dp = data;
1951         int ret = 0;
1952
1953         mutex_lock(&dp->lock);
1954         dp->test.enhanced = val;
1955         if (dp->test.active)
1956                 ret = zynqmp_dp_test_setup(dp);
1957         mutex_unlock(&dp->lock);
1958
1959         return ret;
1960 }
1961
1962 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_enhanced, zynqmp_dp_enhanced_get,
1963                          zynqmp_dp_enhanced_set, "%llu\n");
1964
1965 static int zynqmp_dp_downspread_get(void *data, u64 *val)
1966 {
1967         struct zynqmp_dp *dp = data;
1968
1969         mutex_lock(&dp->lock);
1970         *val = dp->test.downspread;
1971         mutex_unlock(&dp->lock);
1972         return 0;
1973 }
1974
1975 static int zynqmp_dp_downspread_set(void *data, u64 val)
1976 {
1977         struct zynqmp_dp *dp = data;
1978         int ret = 0;
1979
1980         mutex_lock(&dp->lock);
1981         dp->test.downspread = val;
1982         if (dp->test.active)
1983                 ret = zynqmp_dp_test_setup(dp);
1984         mutex_unlock(&dp->lock);
1985
1986         return ret;
1987 }
1988
1989 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_downspread, zynqmp_dp_downspread_get,
1990                          zynqmp_dp_downspread_set, "%llu\n");
1991
1992 static int zynqmp_dp_active_get(void *data, u64 *val)
1993 {
1994         struct zynqmp_dp *dp = data;
1995
1996         mutex_lock(&dp->lock);
1997         *val = dp->test.active;
1998         mutex_unlock(&dp->lock);
1999         return 0;
2000 }
2001
2002 static int zynqmp_dp_active_set(void *data, u64 val)
2003 {
2004         struct zynqmp_dp *dp = data;
2005         int ret = 0;
2006
2007         mutex_lock(&dp->lock);
2008         if (val) {
2009                 if (val < 2) {
2010                         ret = zynqmp_dp_test_setup(dp);
2011                         if (ret)
2012                                 goto out;
2013                 }
2014
2015                 ret = zynqmp_dp_set_test_pattern(dp, dp->test.pattern,
2016                                                  dp->test.custom);
2017                 if (ret)
2018                         goto out;
2019
2020                 ret = zynqmp_dp_update_vs_emph(dp, dp->test.train_set);
2021                 if (ret)
2022                         goto out;
2023
2024                 dp->test.active = true;
2025         } else {
2026                 int err;
2027
2028                 dp->test.active = false;
2029                 err = zynqmp_dp_set_test_pattern(dp, TEST_VIDEO, NULL);
2030                 if (err)
2031                         dev_warn(dp->dev, "could not clear test pattern: %d\n",
2032                                  err);
2033                 zynqmp_dp_train_loop(dp);
2034         }
2035 out:
2036         mutex_unlock(&dp->lock);
2037
2038         return ret;
2039 }
2040
2041 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_active, zynqmp_dp_active_get,
2042                          zynqmp_dp_active_set, "%llu\n");
2043
2044 static ssize_t zynqmp_dp_custom_read(struct file *file, char __user *user_buf,
2045                                      size_t count, loff_t *ppos)
2046 {
2047         struct dentry *dentry = file->f_path.dentry;
2048         struct zynqmp_dp *dp = file->private_data;
2049         ssize_t ret;
2050
2051         ret = debugfs_file_get(dentry);
2052         if (unlikely(ret))
2053                 return ret;
2054
2055         mutex_lock(&dp->lock);
2056         ret = simple_read_from_buffer(user_buf, count, ppos, &dp->test.custom,
2057                                       sizeof(dp->test.custom));
2058         mutex_unlock(&dp->lock);
2059
2060         debugfs_file_put(dentry);
2061         return ret;
2062 }
2063
2064 static ssize_t zynqmp_dp_custom_write(struct file *file,
2065                                       const char __user *user_buf,
2066                                       size_t count, loff_t *ppos)
2067 {
2068         struct dentry *dentry = file->f_path.dentry;
2069         struct zynqmp_dp *dp = file->private_data;
2070         ssize_t ret;
2071         char buf[sizeof(dp->test.custom)];
2072
2073         ret = debugfs_file_get(dentry);
2074         if (unlikely(ret))
2075                 return ret;
2076
2077         ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
2078         if (ret < 0)
2079                 goto out;
2080
2081         mutex_lock(&dp->lock);
2082         memcpy(dp->test.custom, buf, ret);
2083         if (dp->test.active)
2084                 ret = zynqmp_dp_set_test_pattern(dp, dp->test.pattern,
2085                                                  dp->test.custom) ?: ret;
2086         mutex_unlock(&dp->lock);
2087
2088 out:
2089         debugfs_file_put(dentry);
2090         return ret;
2091 }
2092
2093 static const struct file_operations fops_zynqmp_dp_custom = {
2094         .read = zynqmp_dp_custom_read,
2095         .write = zynqmp_dp_custom_write,
2096         .open = simple_open,
2097         .llseek = noop_llseek,
2098 };
2099
2100 static int zynqmp_dp_swing_get(void *data, u64 *val)
2101 {
2102         struct zynqmp_dp_train_set_priv *priv = data;
2103         struct zynqmp_dp *dp = priv->dp;
2104
2105         mutex_lock(&dp->lock);
2106         *val = dp->test.train_set[priv->lane] & DP_TRAIN_VOLTAGE_SWING_MASK;
2107         mutex_unlock(&dp->lock);
2108         return 0;
2109 }
2110
2111 static int zynqmp_dp_swing_set(void *data, u64 val)
2112 {
2113         struct zynqmp_dp_train_set_priv *priv = data;
2114         struct zynqmp_dp *dp = priv->dp;
2115         u8 *train_set = &dp->test.train_set[priv->lane];
2116         int ret = 0;
2117
2118         if (val > 3)
2119                 return -EINVAL;
2120
2121         mutex_lock(&dp->lock);
2122         *train_set &= ~(DP_TRAIN_MAX_SWING_REACHED |
2123                         DP_TRAIN_VOLTAGE_SWING_MASK);
2124         *train_set |= val;
2125         if (val == 3)
2126                 *train_set |= DP_TRAIN_MAX_SWING_REACHED;
2127
2128         if (dp->test.active)
2129                 ret = zynqmp_dp_update_vs_emph(dp, dp->test.train_set);
2130         mutex_unlock(&dp->lock);
2131
2132         return ret;
2133 }
2134
2135 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_swing, zynqmp_dp_swing_get,
2136                          zynqmp_dp_swing_set, "%llu\n");
2137
2138 static int zynqmp_dp_preemphasis_get(void *data, u64 *val)
2139 {
2140         struct zynqmp_dp_train_set_priv *priv = data;
2141         struct zynqmp_dp *dp = priv->dp;
2142
2143         mutex_lock(&dp->lock);
2144         *val = FIELD_GET(DP_TRAIN_PRE_EMPHASIS_MASK,
2145                          dp->test.train_set[priv->lane]);
2146         mutex_unlock(&dp->lock);
2147         return 0;
2148 }
2149
2150 static int zynqmp_dp_preemphasis_set(void *data, u64 val)
2151 {
2152         struct zynqmp_dp_train_set_priv *priv = data;
2153         struct zynqmp_dp *dp = priv->dp;
2154         u8 *train_set = &dp->test.train_set[priv->lane];
2155         int ret = 0;
2156
2157         if (val > 2)
2158                 return -EINVAL;
2159
2160         mutex_lock(&dp->lock);
2161         *train_set &= ~(DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
2162                         DP_TRAIN_PRE_EMPHASIS_MASK);
2163         *train_set |= val;
2164         if (val == 2)
2165                 *train_set |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2166
2167         if (dp->test.active)
2168                 ret = zynqmp_dp_update_vs_emph(dp, dp->test.train_set);
2169         mutex_unlock(&dp->lock);
2170
2171         return ret;
2172 }
2173
2174 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_preemphasis, zynqmp_dp_preemphasis_get,
2175                          zynqmp_dp_preemphasis_set, "%llu\n");
2176
2177 static int zynqmp_dp_lanes_get(void *data, u64 *val)
2178 {
2179         struct zynqmp_dp *dp = data;
2180
2181         mutex_lock(&dp->lock);
2182         *val = dp->test.link_cnt;
2183         mutex_unlock(&dp->lock);
2184         return 0;
2185 }
2186
2187 static int zynqmp_dp_lanes_set(void *data, u64 val)
2188 {
2189         struct zynqmp_dp *dp = data;
2190         int ret = 0;
2191
2192         if (val > ZYNQMP_DP_MAX_LANES)
2193                 return -EINVAL;
2194
2195         mutex_lock(&dp->lock);
2196         if (val > dp->num_lanes) {
2197                 ret = -EINVAL;
2198         } else {
2199                 dp->test.link_cnt = val;
2200                 if (dp->test.active)
2201                         ret = zynqmp_dp_test_setup(dp);
2202         }
2203         mutex_unlock(&dp->lock);
2204
2205         return ret;
2206 }
2207
2208 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_lanes, zynqmp_dp_lanes_get,
2209                          zynqmp_dp_lanes_set, "%llu\n");
2210
2211 static int zynqmp_dp_rate_get(void *data, u64 *val)
2212 {
2213         struct zynqmp_dp *dp = data;
2214
2215         mutex_lock(&dp->lock);
2216         *val = drm_dp_bw_code_to_link_rate(dp->test.bw_code) * 10000ULL;
2217         mutex_unlock(&dp->lock);
2218         return 0;
2219 }
2220
2221 static int zynqmp_dp_rate_set(void *data, u64 val)
2222 {
2223         struct zynqmp_dp *dp = data;
2224         int link_rate;
2225         int ret = 0;
2226         u8 bw_code;
2227
2228         if (do_div(val, 10000))
2229                 return -EINVAL;
2230
2231         bw_code = drm_dp_link_rate_to_bw_code(val);
2232         link_rate = drm_dp_bw_code_to_link_rate(bw_code);
2233         if (val != link_rate)
2234                 return -EINVAL;
2235
2236         if (bw_code != DP_LINK_BW_1_62 && bw_code != DP_LINK_BW_2_7 &&
2237             bw_code != DP_LINK_BW_5_4)
2238                 return -EINVAL;
2239
2240         mutex_lock(&dp->lock);
2241         dp->test.bw_code = bw_code;
2242         if (dp->test.active)
2243                 ret = zynqmp_dp_test_setup(dp);
2244         mutex_unlock(&dp->lock);
2245
2246         return ret;
2247 }
2248
2249 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_rate, zynqmp_dp_rate_get,
2250                          zynqmp_dp_rate_set, "%llu\n");
2251
2252 static int zynqmp_dp_ignore_aux_errors_get(void *data, u64 *val)
2253 {
2254         struct zynqmp_dp *dp = data;
2255
2256         mutex_lock(&dp->aux.hw_mutex);
2257         *val = dp->ignore_aux_errors;
2258         mutex_unlock(&dp->aux.hw_mutex);
2259         return 0;
2260 }
2261
2262 static int zynqmp_dp_ignore_aux_errors_set(void *data, u64 val)
2263 {
2264         struct zynqmp_dp *dp = data;
2265
2266         if (val != !!val)
2267                 return -EINVAL;
2268
2269         mutex_lock(&dp->aux.hw_mutex);
2270         dp->ignore_aux_errors = val;
2271         mutex_unlock(&dp->aux.hw_mutex);
2272         return 0;
2273 }
2274
2275 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_ignore_aux_errors,
2276                          zynqmp_dp_ignore_aux_errors_get,
2277                          zynqmp_dp_ignore_aux_errors_set, "%llu\n");
2278
2279 static int zynqmp_dp_ignore_hpd_get(void *data, u64 *val)
2280 {
2281         struct zynqmp_dp *dp = data;
2282
2283         mutex_lock(&dp->lock);
2284         *val = dp->ignore_hpd;
2285         mutex_unlock(&dp->lock);
2286         return 0;
2287 }
2288
2289 static int zynqmp_dp_ignore_hpd_set(void *data, u64 val)
2290 {
2291         struct zynqmp_dp *dp = data;
2292
2293         if (val != !!val)
2294                 return -EINVAL;
2295
2296         mutex_lock(&dp->lock);
2297         dp->ignore_hpd = val;
2298         mutex_lock(&dp->lock);
2299         return 0;
2300 }
2301
2302 DEFINE_DEBUGFS_ATTRIBUTE(fops_zynqmp_dp_ignore_hpd, zynqmp_dp_ignore_hpd_get,
2303                          zynqmp_dp_ignore_hpd_set, "%llu\n");
2304
2305 static void zynqmp_dp_bridge_debugfs_init(struct drm_bridge *bridge,
2306                                           struct dentry *root)
2307 {
2308         struct zynqmp_dp *dp = bridge_to_dp(bridge);
2309         struct dentry *test;
2310         int i;
2311
2312         dp->test.bw_code = DP_LINK_BW_5_4;
2313         dp->test.link_cnt = dp->num_lanes;
2314
2315         test = debugfs_create_dir("test", root);
2316 #define CREATE_FILE(name) \
2317         debugfs_create_file(#name, 0600, test, dp, &fops_zynqmp_dp_##name)
2318         CREATE_FILE(pattern);
2319         CREATE_FILE(enhanced);
2320         CREATE_FILE(downspread);
2321         CREATE_FILE(active);
2322         CREATE_FILE(custom);
2323         CREATE_FILE(rate);
2324         CREATE_FILE(lanes);
2325         CREATE_FILE(ignore_aux_errors);
2326         CREATE_FILE(ignore_hpd);
2327
2328         for (i = 0; i < dp->num_lanes; i++) {
2329                 static const char fmt[] = "lane%d_preemphasis";
2330                 char name[sizeof(fmt)];
2331
2332                 dp->debugfs_train_set[i].dp = dp;
2333                 dp->debugfs_train_set[i].lane = i;
2334
2335                 snprintf(name, sizeof(name), fmt, i);
2336                 debugfs_create_file(name, 0600, test,
2337                                     &dp->debugfs_train_set[i],
2338                                     &fops_zynqmp_dp_preemphasis);
2339
2340                 snprintf(name, sizeof(name), "lane%d_swing", i);
2341                 debugfs_create_file(name, 0600, test,
2342                                     &dp->debugfs_train_set[i],
2343                                     &fops_zynqmp_dp_swing);
2344         }
2345 }
2346
2347 static const struct drm_bridge_funcs zynqmp_dp_bridge_funcs = {
2348         .attach = zynqmp_dp_bridge_attach,
2349         .detach = zynqmp_dp_bridge_detach,
2350         .mode_valid = zynqmp_dp_bridge_mode_valid,
2351         .atomic_enable = zynqmp_dp_bridge_atomic_enable,
2352         .atomic_disable = zynqmp_dp_bridge_atomic_disable,
2353         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2354         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2355         .atomic_reset = drm_atomic_helper_bridge_reset,
2356         .atomic_check = zynqmp_dp_bridge_atomic_check,
2357         .detect = zynqmp_dp_bridge_detect,
2358         .edid_read = zynqmp_dp_bridge_edid_read,
2359         .atomic_get_input_bus_fmts = zynqmp_dp_bridge_get_input_bus_fmts,
2360         .debugfs_init = zynqmp_dp_bridge_debugfs_init,
2361 };
2362
2363 /* -----------------------------------------------------------------------------
2364  * Interrupt Handling
2365  */
2366
2367 /**
2368  * zynqmp_dp_enable_vblank - Enable vblank
2369  * @dp: DisplayPort IP core structure
2370  *
2371  * Enable vblank interrupt
2372  */
2373 void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp)
2374 {
2375         zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_VBLANK_START);
2376 }
2377
2378 /**
2379  * zynqmp_dp_disable_vblank - Disable vblank
2380  * @dp: DisplayPort IP core structure
2381  *
2382  * Disable vblank interrupt
2383  */
2384 void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp)
2385 {
2386         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_VBLANK_START);
2387 }
2388
2389 static void zynqmp_dp_hpd_work_func(struct work_struct *work)
2390 {
2391         struct zynqmp_dp *dp = container_of(work, struct zynqmp_dp, hpd_work);
2392         enum drm_connector_status status;
2393
2394         mutex_lock(&dp->lock);
2395         if (dp->ignore_hpd) {
2396                 mutex_unlock(&dp->lock);
2397                 return;
2398         }
2399
2400         status = __zynqmp_dp_bridge_detect(dp);
2401         mutex_unlock(&dp->lock);
2402
2403         drm_bridge_hpd_notify(&dp->bridge, status);
2404 }
2405
2406 static void zynqmp_dp_hpd_irq_work_func(struct work_struct *work)
2407 {
2408         struct zynqmp_dp *dp = container_of(work, struct zynqmp_dp,
2409                                             hpd_irq_work);
2410         u8 status[DP_LINK_STATUS_SIZE + 2];
2411         int err;
2412
2413         mutex_lock(&dp->lock);
2414         if (dp->ignore_hpd) {
2415                 mutex_unlock(&dp->lock);
2416                 return;
2417         }
2418
2419         err = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status,
2420                                DP_LINK_STATUS_SIZE + 2);
2421         if (err < 0) {
2422                 dev_dbg_ratelimited(dp->dev,
2423                                     "could not read sink status: %d\n", err);
2424         } else {
2425                 if (status[4] & DP_LINK_STATUS_UPDATED ||
2426                     !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) ||
2427                     !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) {
2428                         zynqmp_dp_train_loop(dp);
2429                 }
2430         }
2431         mutex_unlock(&dp->lock);
2432 }
2433
2434 static irqreturn_t zynqmp_dp_irq_handler(int irq, void *data)
2435 {
2436         struct zynqmp_dp *dp = (struct zynqmp_dp *)data;
2437         u32 status, mask;
2438
2439         status = zynqmp_dp_read(dp, ZYNQMP_DP_INT_STATUS);
2440         /* clear status register as soon as we read it */
2441         zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status);
2442         mask = zynqmp_dp_read(dp, ZYNQMP_DP_INT_MASK);
2443
2444         /*
2445          * Status register may report some events, which corresponding interrupts
2446          * have been disabled. Filter out those events against interrupts' mask.
2447          */
2448         status &= ~mask;
2449
2450         if (!status)
2451                 return IRQ_NONE;
2452
2453         /* dbg for diagnostic, but not much that the driver can do */
2454         if (status & ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK)
2455                 dev_dbg_ratelimited(dp->dev, "underflow interrupt\n");
2456         if (status & ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK)
2457                 dev_dbg_ratelimited(dp->dev, "overflow interrupt\n");
2458
2459         if (status & ZYNQMP_DP_INT_VBLANK_START)
2460                 zynqmp_dpsub_drm_handle_vblank(dp->dpsub);
2461
2462         if (status & ZYNQMP_DP_INT_HPD_EVENT)
2463                 schedule_work(&dp->hpd_work);
2464
2465         if (status & ZYNQMP_DP_INT_HPD_IRQ)
2466                 schedule_work(&dp->hpd_irq_work);
2467
2468         if (status & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY)
2469                 complete(&dp->aux_done);
2470
2471         if (status & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT)
2472                 complete(&dp->aux_done);
2473
2474         return IRQ_HANDLED;
2475 }
2476
2477 /* -----------------------------------------------------------------------------
2478  * Initialization & Cleanup
2479  */
2480
2481 int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub)
2482 {
2483         struct platform_device *pdev = to_platform_device(dpsub->dev);
2484         struct drm_bridge *bridge;
2485         struct zynqmp_dp *dp;
2486         struct resource *res;
2487         int ret;
2488
2489         dp = kzalloc(sizeof(*dp), GFP_KERNEL);
2490         if (!dp)
2491                 return -ENOMEM;
2492
2493         dp->dev = &pdev->dev;
2494         dp->dpsub = dpsub;
2495         dp->status = connector_status_disconnected;
2496         mutex_init(&dp->lock);
2497         init_completion(&dp->aux_done);
2498
2499         INIT_WORK(&dp->hpd_work, zynqmp_dp_hpd_work_func);
2500         INIT_WORK(&dp->hpd_irq_work, zynqmp_dp_hpd_irq_work_func);
2501
2502         /* Acquire all resources (IOMEM, IRQ and PHYs). */
2503         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dp");
2504         dp->iomem = devm_ioremap_resource(dp->dev, res);
2505         if (IS_ERR(dp->iomem)) {
2506                 ret = PTR_ERR(dp->iomem);
2507                 goto err_free;
2508         }
2509
2510         dp->irq = platform_get_irq(pdev, 0);
2511         if (dp->irq < 0) {
2512                 ret = dp->irq;
2513                 goto err_free;
2514         }
2515
2516         dp->reset = devm_reset_control_get(dp->dev, NULL);
2517         if (IS_ERR(dp->reset)) {
2518                 if (PTR_ERR(dp->reset) != -EPROBE_DEFER)
2519                         dev_err(dp->dev, "failed to get reset: %ld\n",
2520                                 PTR_ERR(dp->reset));
2521                 ret = PTR_ERR(dp->reset);
2522                 goto err_free;
2523         }
2524
2525         ret = zynqmp_dp_reset(dp, true);
2526         if (ret < 0)
2527                 goto err_free;
2528
2529         ret = zynqmp_dp_reset(dp, false);
2530         if (ret < 0)
2531                 goto err_free;
2532
2533         ret = zynqmp_dp_phy_probe(dp);
2534         if (ret)
2535                 goto err_reset;
2536
2537         /* Initialize the bridge. */
2538         bridge = &dp->bridge;
2539         bridge->funcs = &zynqmp_dp_bridge_funcs;
2540         bridge->ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
2541                     | DRM_BRIDGE_OP_HPD;
2542         bridge->type = DRM_MODE_CONNECTOR_DisplayPort;
2543         bridge->of_node = dp->dev->of_node;
2544         dpsub->bridge = bridge;
2545
2546         /*
2547          * Acquire the next bridge in the chain. Ignore errors caused by port@5
2548          * not being connected for backward-compatibility with older DTs.
2549          */
2550         ret = drm_of_find_panel_or_bridge(dp->dev->of_node, 5, 0, NULL,
2551                                           &dp->next_bridge);
2552         if (ret < 0 && ret != -ENODEV)
2553                 goto err_reset;
2554
2555         /* Initialize the hardware. */
2556         dp->config.misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK;
2557         zynqmp_dp_set_format(dp, NULL, ZYNQMP_DPSUB_FORMAT_RGB, 8);
2558
2559         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN,
2560                         ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
2561         zynqmp_dp_set(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET);
2562         zynqmp_dp_write(dp, ZYNQMP_DP_FORCE_SCRAMBLER_RESET, 1);
2563         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0);
2564         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff);
2565
2566         ret = zynqmp_dp_phy_init(dp);
2567         if (ret)
2568                 goto err_reset;
2569
2570         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 1);
2571
2572         /*
2573          * Now that the hardware is initialized and won't generate spurious
2574          * interrupts, request the IRQ.
2575          */
2576         ret = devm_request_irq(dp->dev, dp->irq, zynqmp_dp_irq_handler,
2577                                IRQF_SHARED, dev_name(dp->dev), dp);
2578         if (ret < 0)
2579                 goto err_phy_exit;
2580
2581         dpsub->dp = dp;
2582
2583         dev_dbg(dp->dev, "ZynqMP DisplayPort Tx probed with %u lanes\n",
2584                 dp->num_lanes);
2585
2586         return 0;
2587
2588 err_phy_exit:
2589         zynqmp_dp_phy_exit(dp);
2590 err_reset:
2591         zynqmp_dp_reset(dp, true);
2592 err_free:
2593         kfree(dp);
2594         return ret;
2595 }
2596
2597 void zynqmp_dp_remove(struct zynqmp_dpsub *dpsub)
2598 {
2599         struct zynqmp_dp *dp = dpsub->dp;
2600
2601         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_ALL);
2602         devm_free_irq(dp->dev, dp->irq, dp);
2603
2604         cancel_work_sync(&dp->hpd_irq_work);
2605         cancel_work_sync(&dp->hpd_work);
2606
2607         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0);
2608         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff);
2609
2610         zynqmp_dp_phy_exit(dp);
2611         zynqmp_dp_reset(dp, true);
2612         mutex_destroy(&dp->lock);
2613 }