drivers/media/dvb-frontends/cxd2841er.c

   1 /*
   2  * cxd2841er.c
   3  *
   4  * Sony digital demodulator driver for
   5  *      CXD2841ER - DVB-S/S2/T/T2/C/C2
   6  *      CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
   7  *
   8  * Copyright 2012 Sony Corporation
   9  * Copyright (C) 2014 NetUP Inc.
  10  * Copyright (C) 2014 Sergey Kozlov <[email protected]>
  11  * Copyright (C) 2014 Abylay Ospan <[email protected]>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22   */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/string.h>
  27 #include <linux/slab.h>
  28 #include <linux/bitops.h>
  29 #include <linux/math64.h>
  30 #include <linux/log2.h>
  31 #include <linux/dynamic_debug.h>
  32
  33 #include "dvb_math.h"
  34 #include "dvb_frontend.h"
  35 #include "cxd2841er.h"
  36 #include "cxd2841er_priv.h"
  37
  38 #define MAX_WRITE_REGSIZE       16
  39
  40 enum cxd2841er_state {
  41         STATE_SHUTDOWN = 0,
  42         STATE_SLEEP_S,
  43         STATE_ACTIVE_S,
  44         STATE_SLEEP_TC,
  45         STATE_ACTIVE_TC
  46 };
  47
  48 struct cxd2841er_priv {
  49         struct dvb_frontend             frontend;
  50         struct i2c_adapter              *i2c;
  51         u8                              i2c_addr_slvx;
  52         u8                              i2c_addr_slvt;
  53         const struct cxd2841er_config   *config;
  54         enum cxd2841er_state            state;
  55         u8                              system;
  56         enum cxd2841er_xtal             xtal;
  57         enum fe_caps caps;
  58 };
  59
  60 static const struct cxd2841er_cnr_data s_cn_data[] = {
  61         { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
  62         { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
  63         { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
  64         { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
  65         { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
  66         { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
  67         { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
  68         { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
  69         { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
  70         { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
  71         { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
  72         { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
  73         { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
  74         { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
  75         { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
  76         { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
  77         { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
  78         { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
  79         { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
  80         { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
  81         { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
  82         { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
  83         { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
  84         { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
  85         { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
  86         { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
  87         { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
  88         { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
  89         { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
  90         { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
  91         { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
  92         { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
  93         { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
  94         { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
  95         { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
  96         { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
  97         { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
  98         { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
  99         { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
 100         { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
 101         { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
 102         { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
 103         { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
 104         { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
 105         { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
 106         { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
 107         { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
 108         { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 109         { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 110         { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
 111         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 112         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 113         { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
 114         { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
 115         { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
 116         { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
 117         { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
 118         { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
 119         { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
 120         { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
 121         { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
 122         { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
 123         { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
 124         { 0x0015, 19900 }, { 0x0014, 20000 },
 125 };
 126
 127 static const struct cxd2841er_cnr_data s2_cn_data[] = {
 128         { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
 129         { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
 130         { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
 131         { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
 132         { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
 133         { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
 134         { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
 135         { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
 136         { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
 137         { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
 138         { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
 139         { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
 140         { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
 141         { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
 142         { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
 143         { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
 144         { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
 145         { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
 146         { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
 147         { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
 148         { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
 149         { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
 150         { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
 151         { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
 152         { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
 153         { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
 154         { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
 155         { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
 156         { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
 157         { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
 158         { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
 159         { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
 160         { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
 161         { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
 162         { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
 163         { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
 164         { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
 165         { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
 166         { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
 167         { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
 168         { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
 169         { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
 170         { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
 171         { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
 172         { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
 173         { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
 174         { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
 175         { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 176         { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 177         { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
 178         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 179         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 180         { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
 181         { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
 182         { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
 183         { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
 184         { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
 185         { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
 186         { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
 187         { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
 188         { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
 189         { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
 190         { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
 191         { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
 192 };
 193
 194 #define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
 195 #define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
 196                 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
 197                 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
 198
 199 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
 200                                 u8 addr, u8 reg, u8 write,
 201                                 const u8 *data, u32 len)
 202 {
 203         dev_dbg(&priv->i2c->dev,
 204                 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
 205                 (write == 0 ? "read" : "write"), addr, reg, len);
 206         print_hex_dump_bytes("cxd2841er: I2C data: ",
 207                 DUMP_PREFIX_OFFSET, data, len);
 208 }
 209
 210 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
 211                                 u8 addr, u8 reg, const u8 *data, u32 len)
 212 {
 213         int ret;
 214         u8 buf[MAX_WRITE_REGSIZE + 1];
 215         u8 i2c_addr = (addr == I2C_SLVX ?
 216                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 217         struct i2c_msg msg[1] = {
 218                 {
 219                         .addr = i2c_addr,
 220                         .flags = 0,
 221                         .len = len + 1,
 222                         .buf = buf,
 223                 }
 224         };
 225
 226         if (len + 1 >= sizeof(buf)) {
 227                 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
 228                          reg, len + 1);
 229                 return -E2BIG;
 230         }
 231
 232         cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
 233         buf[0] = reg;
 234         memcpy(&buf[1], data, len);
 235
 236         ret = i2c_transfer(priv->i2c, msg, 1);
 237         if (ret >= 0 && ret != 1)
 238                 ret = -EIO;
 239         if (ret < 0) {
 240                 dev_warn(&priv->i2c->dev,
 241                         "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
 242                         KBUILD_MODNAME, ret, i2c_addr, reg, len);
 243                 return ret;
 244         }
 245         return 0;
 246 }
 247
 248 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
 249                                u8 addr, u8 reg, u8 val)
 250 {
 251         return cxd2841er_write_regs(priv, addr, reg, &val, 1);
 252 }
 253
 254 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
 255                                u8 addr, u8 reg, u8 *val, u32 len)
 256 {
 257         int ret;
 258         u8 i2c_addr = (addr == I2C_SLVX ?
 259                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 260         struct i2c_msg msg[2] = {
 261                 {
 262                         .addr = i2c_addr,
 263                         .flags = 0,
 264                         .len = 1,
 265                         .buf = &reg,
 266                 }, {
 267                         .addr = i2c_addr,
 268                         .flags = I2C_M_RD,
 269                         .len = len,
 270                         .buf = val,
 271                 }
 272         };
 273
 274         ret = i2c_transfer(priv->i2c, &msg[0], 1);
 275         if (ret >= 0 && ret != 1)
 276                 ret = -EIO;
 277         if (ret < 0) {
 278                 dev_warn(&priv->i2c->dev,
 279                         "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
 280                         KBUILD_MODNAME, ret, i2c_addr, reg);
 281                 return ret;
 282         }
 283         ret = i2c_transfer(priv->i2c, &msg[1], 1);
 284         if (ret >= 0 && ret != 1)
 285                 ret = -EIO;
 286         if (ret < 0) {
 287                 dev_warn(&priv->i2c->dev,
 288                         "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
 289                         KBUILD_MODNAME, ret, i2c_addr, reg);
 290                 return ret;
 291         }
 292         cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
 293         return 0;
 294 }
 295
 296 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
 297                               u8 addr, u8 reg, u8 *val)
 298 {
 299         return cxd2841er_read_regs(priv, addr, reg, val, 1);
 300 }
 301
 302 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
 303                                   u8 addr, u8 reg, u8 data, u8 mask)
 304 {
 305         int res;
 306         u8 rdata;
 307
 308         if (mask != 0xff) {
 309                 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
 310                 if (res)
 311                         return res;
 312                 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
 313         }
 314         return cxd2841er_write_reg(priv, addr, reg, data);
 315 }
 316
 317 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
 318                                            u32 symbol_rate)
 319 {
 320         u32 reg_value = 0;
 321         u8 data[3] = {0, 0, 0};
 322
 323         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 324         /*
 325          * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
 326          *          = ((symbolRateKSps * 2^14) + 500) / 1000
 327          *          = ((symbolRateKSps * 16384) + 500) / 1000
 328          */
 329         reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
 330         if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
 331                 dev_err(&priv->i2c->dev,
 332                         "%s(): reg_value is out of range\n", __func__);
 333                 return -EINVAL;
 334         }
 335         data[0] = (u8)((reg_value >> 16) & 0x0F);
 336         data[1] = (u8)((reg_value >>  8) & 0xFF);
 337         data[2] = (u8)(reg_value & 0xFF);
 338         /* Set SLV-T Bank : 0xAE */
 339         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 340         cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
 341         return 0;
 342 }
 343
 344 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 345                                         u8 system);
 346
 347 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
 348                                          u8 system, u32 symbol_rate)
 349 {
 350         int ret;
 351         u8 data[4] = { 0, 0, 0, 0 };
 352
 353         if (priv->state != STATE_SLEEP_S) {
 354                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 355                         __func__, (int)priv->state);
 356                 return -EINVAL;
 357         }
 358         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 359         cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
 360         /* Set demod mode */
 361         if (system == SYS_DVBS) {
 362                 data[0] = 0x0A;
 363         } else if (system == SYS_DVBS2) {
 364                 data[0] = 0x0B;
 365         } else {
 366                 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
 367                         __func__, system);
 368                 return -EINVAL;
 369         }
 370         /* Set SLV-X Bank : 0x00 */
 371         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 372         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
 373         /* DVB-S/S2 */
 374         data[0] = 0x00;
 375         /* Set SLV-T Bank : 0x00 */
 376         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 377         /* Enable S/S2 auto detection 1 */
 378         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
 379         /* Set SLV-T Bank : 0xAE */
 380         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 381         /* Enable S/S2 auto detection 2 */
 382         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
 383         /* Set SLV-T Bank : 0x00 */
 384         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 385         /* Enable demod clock */
 386         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
 387         /* Enable ADC clock */
 388         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
 389         /* Enable ADC 1 */
 390         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 391         /* Enable ADC 2 */
 392         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
 393         /* Set SLV-X Bank : 0x00 */
 394         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 395         /* Enable ADC 3 */
 396         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
 397         /* Set SLV-T Bank : 0xA3 */
 398         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
 399         cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
 400         data[0] = 0x07;
 401         data[1] = 0x3B;
 402         data[2] = 0x08;
 403         data[3] = 0xC5;
 404         /* Set SLV-T Bank : 0xAB */
 405         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
 406         cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
 407         data[0] = 0x05;
 408         data[1] = 0x80;
 409         data[2] = 0x0A;
 410         data[3] = 0x80;
 411         cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
 412         data[0] = 0x0C;
 413         data[1] = 0xCC;
 414         cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
 415         /* Set demod parameter */
 416         ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
 417         if (ret != 0)
 418                 return ret;
 419         /* Set SLV-T Bank : 0x00 */
 420         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 421         /* disable Hi-Z setting 1 */
 422         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
 423         /* disable Hi-Z setting 2 */
 424         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
 425         priv->state = STATE_ACTIVE_S;
 426         return 0;
 427 }
 428
 429 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
 430                                                u32 bandwidth);
 431
 432 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
 433                                                 u32 bandwidth);
 434
 435 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
 436                                                u32 bandwidth);
 437
 438 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
 439                 u32 bandwidth);
 440
 441 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
 442
 443 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
 444
 445 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
 446
 447 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
 448                                    struct dtv_frontend_properties *p)
 449 {
 450         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 451         if (priv->state != STATE_ACTIVE_S &&
 452                         priv->state != STATE_ACTIVE_TC) {
 453                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
 454                         __func__, priv->state);
 455                 return -EINVAL;
 456         }
 457         /* Set SLV-T Bank : 0x00 */
 458         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 459         /* disable TS output */
 460         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 461         if (priv->state == STATE_ACTIVE_S)
 462                 return cxd2841er_dvbs2_set_symbol_rate(
 463                                 priv, p->symbol_rate / 1000);
 464         else if (priv->state == STATE_ACTIVE_TC) {
 465                 switch (priv->system) {
 466                 case SYS_DVBT:
 467                         return cxd2841er_sleep_tc_to_active_t_band(
 468                                         priv, p->bandwidth_hz);
 469                 case SYS_DVBT2:
 470                         return cxd2841er_sleep_tc_to_active_t2_band(
 471                                         priv, p->bandwidth_hz);
 472                 case SYS_DVBC_ANNEX_A:
 473                         return cxd2841er_sleep_tc_to_active_c_band(
 474                                         priv, p->bandwidth_hz);
 475                 case SYS_ISDBT:
 476                         cxd2841er_active_i_to_sleep_tc(priv);
 477                         cxd2841er_sleep_tc_to_shutdown(priv);
 478                         cxd2841er_shutdown_to_sleep_tc(priv);
 479                         return cxd2841er_sleep_tc_to_active_i(
 480                                         priv, p->bandwidth_hz);
 481                 }
 482         }
 483         dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
 484                 __func__, priv->system);
 485         return -EINVAL;
 486 }
 487
 488 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
 489 {
 490         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 491         if (priv->state != STATE_ACTIVE_S) {
 492                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 493                         __func__, priv->state);
 494                 return -EINVAL;
 495         }
 496         /* Set SLV-T Bank : 0x00 */
 497         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 498         /* disable TS output */
 499         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 500         /* enable Hi-Z setting 1 */
 501         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
 502         /* enable Hi-Z setting 2 */
 503         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 504         /* Set SLV-X Bank : 0x00 */
 505         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 506         /* disable ADC 1 */
 507         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 508         /* Set SLV-T Bank : 0x00 */
 509         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 510         /* disable ADC clock */
 511         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
 512         /* disable ADC 2 */
 513         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 514         /* disable ADC 3 */
 515         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 516         /* SADC Bias ON */
 517         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 518         /* disable demod clock */
 519         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 520         /* Set SLV-T Bank : 0xAE */
 521         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 522         /* disable S/S2 auto detection1 */
 523         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 524         /* Set SLV-T Bank : 0x00 */
 525         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 526         /* disable S/S2 auto detection2 */
 527         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
 528         priv->state = STATE_SLEEP_S;
 529         return 0;
 530 }
 531
 532 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
 533 {
 534         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 535         if (priv->state != STATE_SLEEP_S) {
 536                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 537                         __func__, priv->state);
 538                 return -EINVAL;
 539         }
 540         /* Set SLV-T Bank : 0x00 */
 541         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 542         /* Disable DSQOUT */
 543         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 544         /* Disable DSQIN */
 545         cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
 546         /* Set SLV-X Bank : 0x00 */
 547         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 548         /* Disable oscillator */
 549         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 550         /* Set demod mode */
 551         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 552         priv->state = STATE_SHUTDOWN;
 553         return 0;
 554 }
 555
 556 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
 557 {
 558         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 559         if (priv->state != STATE_SLEEP_TC) {
 560                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 561                         __func__, priv->state);
 562                 return -EINVAL;
 563         }
 564         /* Set SLV-X Bank : 0x00 */
 565         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 566         /* Disable oscillator */
 567         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 568         /* Set demod mode */
 569         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 570         priv->state = STATE_SHUTDOWN;
 571         return 0;
 572 }
 573
 574 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
 575 {
 576         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 577         if (priv->state != STATE_ACTIVE_TC) {
 578                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 579                         __func__, priv->state);
 580                 return -EINVAL;
 581         }
 582         /* Set SLV-T Bank : 0x00 */
 583         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 584         /* disable TS output */
 585         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 586         /* enable Hi-Z setting 1 */
 587         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 588         /* enable Hi-Z setting 2 */
 589         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 590         /* Set SLV-X Bank : 0x00 */
 591         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 592         /* disable ADC 1 */
 593         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 594         /* Set SLV-T Bank : 0x00 */
 595         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 596         /* Disable ADC 2 */
 597         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 598         /* Disable ADC 3 */
 599         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 600         /* Disable ADC clock */
 601         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 602         /* Disable RF level monitor */
 603         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 604         /* Disable demod clock */
 605         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 606         priv->state = STATE_SLEEP_TC;
 607         return 0;
 608 }
 609
 610 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
 611 {
 612         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 613         if (priv->state != STATE_ACTIVE_TC) {
 614                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 615                         __func__, priv->state);
 616                 return -EINVAL;
 617         }
 618         /* Set SLV-T Bank : 0x00 */
 619         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 620         /* disable TS output */
 621         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 622         /* enable Hi-Z setting 1 */
 623         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 624         /* enable Hi-Z setting 2 */
 625         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 626         /* Cancel DVB-T2 setting */
 627         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
 628         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
 629         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
 630         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
 631         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
 632         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
 633         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
 634         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
 635         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
 636         /* Set SLV-X Bank : 0x00 */
 637         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 638         /* disable ADC 1 */
 639         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 640         /* Set SLV-T Bank : 0x00 */
 641         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 642         /* Disable ADC 2 */
 643         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 644         /* Disable ADC 3 */
 645         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 646         /* Disable ADC clock */
 647         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 648         /* Disable RF level monitor */
 649         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 650         /* Disable demod clock */
 651         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 652         priv->state = STATE_SLEEP_TC;
 653         return 0;
 654 }
 655
 656 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
 657 {
 658         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 659         if (priv->state != STATE_ACTIVE_TC) {
 660                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 661                         __func__, priv->state);
 662                 return -EINVAL;
 663         }
 664         /* Set SLV-T Bank : 0x00 */
 665         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 666         /* disable TS output */
 667         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 668         /* enable Hi-Z setting 1 */
 669         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 670         /* enable Hi-Z setting 2 */
 671         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 672         /* Cancel DVB-C setting */
 673         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
 674         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
 675         /* Set SLV-X Bank : 0x00 */
 676         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 677         /* disable ADC 1 */
 678         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 679         /* Set SLV-T Bank : 0x00 */
 680         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 681         /* Disable ADC 2 */
 682         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 683         /* Disable ADC 3 */
 684         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 685         /* Disable ADC clock */
 686         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 687         /* Disable RF level monitor */
 688         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 689         /* Disable demod clock */
 690         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 691         priv->state = STATE_SLEEP_TC;
 692         return 0;
 693 }
 694
 695 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
 696 {
 697         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 698         if (priv->state != STATE_ACTIVE_TC) {
 699                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 700                                 __func__, priv->state);
 701                 return -EINVAL;
 702         }
 703         /* Set SLV-T Bank : 0x00 */
 704         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 705         /* disable TS output */
 706         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 707         /* enable Hi-Z setting 1 */
 708         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 709         /* enable Hi-Z setting 2 */
 710         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 711
 712         /* TODO: Cancel demod parameter */
 713
 714         /* Set SLV-X Bank : 0x00 */
 715         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 716         /* disable ADC 1 */
 717         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 718         /* Set SLV-T Bank : 0x00 */
 719         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 720         /* Disable ADC 2 */
 721         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 722         /* Disable ADC 3 */
 723         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 724         /* Disable ADC clock */
 725         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 726         /* Disable RF level monitor */
 727         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 728         /* Disable demod clock */
 729         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 730         priv->state = STATE_SLEEP_TC;
 731         return 0;
 732 }
 733
 734 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
 735 {
 736         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 737         if (priv->state != STATE_SHUTDOWN) {
 738                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 739                         __func__, priv->state);
 740                 return -EINVAL;
 741         }
 742         /* Set SLV-X Bank : 0x00 */
 743         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 744         /* Clear all demodulator registers */
 745         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 746         usleep_range(3000, 5000);
 747         /* Set SLV-X Bank : 0x00 */
 748         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 749         /* Set demod SW reset */
 750         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 751
 752         switch (priv->xtal) {
 753         case SONY_XTAL_20500:
 754                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
 755                 break;
 756         case SONY_XTAL_24000:
 757                 /* Select demod frequency */
 758                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 759                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
 760                 break;
 761         case SONY_XTAL_41000:
 762                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
 763                 break;
 764         default:
 765                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
 766                                 __func__, priv->xtal);
 767                 return -EINVAL;
 768         }
 769
 770         /* Set demod mode */
 771         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
 772         /* Clear demod SW reset */
 773         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 774         usleep_range(1000, 2000);
 775         /* Set SLV-T Bank : 0x00 */
 776         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 777         /* enable DSQOUT */
 778         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
 779         /* enable DSQIN */
 780         cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
 781         /* TADC Bias On */
 782         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 783         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 784         /* SADC Bias On */
 785         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 786         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 787         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 788         priv->state = STATE_SLEEP_S;
 789         return 0;
 790 }
 791
 792 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
 793 {
 794         u8 data = 0;
 795
 796         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 797         if (priv->state != STATE_SHUTDOWN) {
 798                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 799                         __func__, priv->state);
 800                 return -EINVAL;
 801         }
 802         /* Set SLV-X Bank : 0x00 */
 803         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 804         /* Clear all demodulator registers */
 805         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 806         usleep_range(3000, 5000);
 807         /* Set SLV-X Bank : 0x00 */
 808         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 809         /* Set demod SW reset */
 810         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 811   /* Select ADC clock mode */
 812         cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
 813
 814         switch (priv->xtal) {
 815         case SONY_XTAL_20500:
 816                 data = 0x0;
 817                 break;
 818         case SONY_XTAL_24000:
 819                 /* Select demod frequency */
 820                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 821                 data = 0x3;
 822                 break;
 823         case SONY_XTAL_41000:
 824                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 825                 data = 0x1;
 826                 break;
 827         }
 828         cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
 829         /* Clear demod SW reset */
 830         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 831         usleep_range(1000, 2000);
 832         /* Set SLV-T Bank : 0x00 */
 833         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 834         /* TADC Bias On */
 835         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 836         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 837         /* SADC Bias On */
 838         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 839         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 840         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 841         priv->state = STATE_SLEEP_TC;
 842         return 0;
 843 }
 844
 845 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
 846 {
 847         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 848         /* Set SLV-T Bank : 0x00 */
 849         cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
 850         /* SW Reset */
 851         cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
 852         /* Enable TS output */
 853         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
 854         return 0;
 855 }
 856
 857 /* Set TS parallel mode */
 858 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 859                                         u8 system)
 860 {
 861         u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
 862
 863         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 864         /* Set SLV-T Bank : 0x00 */
 865         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 866         cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
 867         cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
 868         cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
 869         dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
 870                 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
 871
 872         /*
 873          * slave    Bank    Addr    Bit    default    Name
 874          * <SLV-T>  00h     D9h     [7:0]  8'h08      OTSCKPERIOD
 875          */
 876         cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
 877         /*
 878          * Disable TS IF Clock
 879          * slave    Bank    Addr    Bit    default    Name
 880          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 881          */
 882         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
 883         /*
 884          * slave    Bank    Addr    Bit    default    Name
 885          * <SLV-T>  00h     33h     [1:0]  2'b01      OREG_CKSEL_TSIF
 886          */
 887         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
 888         /*
 889          * Enable TS IF Clock
 890          * slave    Bank    Addr    Bit    default    Name
 891          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 892          */
 893         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
 894
 895         if (system == SYS_DVBT) {
 896                 /* Enable parity period for DVB-T */
 897                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 898                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 899         } else if (system == SYS_DVBC_ANNEX_A) {
 900                 /* Enable parity period for DVB-C */
 901                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 902                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 903         }
 904 }
 905
 906 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
 907 {
 908         u8 chip_id = 0;
 909
 910         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 911         if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
 912                 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
 913         else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
 914                 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
 915
 916         return chip_id;
 917 }
 918
 919 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
 920                                    enum fe_status *status)
 921 {
 922         u8 reg = 0;
 923         struct cxd2841er_priv *priv = fe->demodulator_priv;
 924
 925         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 926         *status = 0;
 927         if (priv->state != STATE_ACTIVE_S) {
 928                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 929                         __func__, priv->state);
 930                 return -EINVAL;
 931         }
 932         /* Set SLV-T Bank : 0xA0 */
 933         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
 934         /*
 935          *  slave     Bank      Addr      Bit      Signal name
 936          * <SLV-T>    A0h       11h       [2]      ITSLOCK
 937          */
 938         cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
 939         if (reg & 0x04) {
 940                 *status = FE_HAS_SIGNAL
 941                         | FE_HAS_CARRIER
 942                         | FE_HAS_VITERBI
 943                         | FE_HAS_SYNC
 944                         | FE_HAS_LOCK;
 945         }
 946         dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
 947         return 0;
 948 }
 949
 950 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
 951                                       u8 *sync, u8 *tslock, u8 *unlock)
 952 {
 953         u8 data = 0;
 954
 955         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 956         if (priv->state != STATE_ACTIVE_TC)
 957                 return -EINVAL;
 958         if (priv->system == SYS_DVBT) {
 959                 /* Set SLV-T Bank : 0x10 */
 960                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 961         } else {
 962                 /* Set SLV-T Bank : 0x20 */
 963                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
 964         }
 965         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
 966         if ((data & 0x07) == 0x07) {
 967                 dev_dbg(&priv->i2c->dev,
 968                         "%s(): invalid hardware state detected\n", __func__);
 969                 *sync = 0;
 970                 *tslock = 0;
 971                 *unlock = 0;
 972         } else {
 973                 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
 974                 *tslock = ((data & 0x20) ? 1 : 0);
 975                 *unlock = ((data & 0x10) ? 1 : 0);
 976         }
 977         return 0;
 978 }
 979
 980 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
 981 {
 982         u8 data;
 983
 984         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 985         if (priv->state != STATE_ACTIVE_TC)
 986                 return -EINVAL;
 987         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 988         cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
 989         if ((data & 0x01) == 0) {
 990                 *tslock = 0;
 991         } else {
 992                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
 993                 *tslock = ((data & 0x20) ? 1 : 0);
 994         }
 995         return 0;
 996 }
 997
 998 static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
 999                 u8 *sync, u8 *tslock, u8 *unlock)
1000 {
1001         u8 data = 0;
1002
1003         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1004         if (priv->state != STATE_ACTIVE_TC)
1005                 return -EINVAL;
1006         /* Set SLV-T Bank : 0x60 */
1007         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1008         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1009         dev_dbg(&priv->i2c->dev,
1010                         "%s(): lock=0x%x\n", __func__, data);
1011         *sync = ((data & 0x02) ? 1 : 0);
1012         *tslock = ((data & 0x01) ? 1 : 0);
1013         *unlock = ((data & 0x10) ? 1 : 0);
1014         return 0;
1015 }
1016
1017 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1018                                     enum fe_status *status)
1019 {
1020         int ret = 0;
1021         u8 sync = 0;
1022         u8 tslock = 0;
1023         u8 unlock = 0;
1024         struct cxd2841er_priv *priv = fe->demodulator_priv;
1025
1026         *status = 0;
1027         if (priv->state == STATE_ACTIVE_TC) {
1028                 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1029                         ret = cxd2841er_read_status_t_t2(
1030                                 priv, &sync, &tslock, &unlock);
1031                         if (ret)
1032                                 goto done;
1033                         if (unlock)
1034                                 goto done;
1035                         if (sync)
1036                                 *status = FE_HAS_SIGNAL |
1037                                         FE_HAS_CARRIER |
1038                                         FE_HAS_VITERBI |
1039                                         FE_HAS_SYNC;
1040                         if (tslock)
1041                                 *status |= FE_HAS_LOCK;
1042                 } else if (priv->system == SYS_ISDBT) {
1043                         ret = cxd2841er_read_status_i(
1044                                         priv, &sync, &tslock, &unlock);
1045                         if (ret)
1046                                 goto done;
1047                         if (unlock)
1048                                 goto done;
1049                         if (sync)
1050                                 *status = FE_HAS_SIGNAL |
1051                                         FE_HAS_CARRIER |
1052                                         FE_HAS_VITERBI |
1053                                         FE_HAS_SYNC;
1054                         if (tslock)
1055                                 *status |= FE_HAS_LOCK;
1056                 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1057                         ret = cxd2841er_read_status_c(priv, &tslock);
1058                         if (ret)
1059                                 goto done;
1060                         if (tslock)
1061                                 *status = FE_HAS_SIGNAL |
1062                                         FE_HAS_CARRIER |
1063                                         FE_HAS_VITERBI |
1064                                         FE_HAS_SYNC |
1065                                         FE_HAS_LOCK;
1066                 }
1067         }
1068 done:
1069         dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1070         return ret;
1071 }
1072
1073 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1074                                              int *offset)
1075 {
1076         u8 data[3];
1077         u8 is_hs_mode;
1078         s32 cfrl_ctrlval;
1079         s32 temp_div, temp_q, temp_r;
1080
1081         if (priv->state != STATE_ACTIVE_S) {
1082                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1083                         __func__, priv->state);
1084                 return -EINVAL;
1085         }
1086         /*
1087          * Get High Sampling Rate mode
1088          *  slave     Bank      Addr      Bit      Signal name
1089          * <SLV-T>    A0h       10h       [0]      ITRL_LOCK
1090          */
1091         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1092         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1093         if (data[0] & 0x01) {
1094                 /*
1095                  *  slave     Bank      Addr      Bit      Signal name
1096                  * <SLV-T>    A0h       50h       [4]      IHSMODE
1097                  */
1098                 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1099                 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1100         } else {
1101                 dev_dbg(&priv->i2c->dev,
1102                         "%s(): unable to detect sampling rate mode\n",
1103                         __func__);
1104                 return -EINVAL;
1105         }
1106         /*
1107          *  slave     Bank      Addr      Bit      Signal name
1108          * <SLV-T>    A0h       45h       [4:0]    ICFRL_CTRLVAL[20:16]
1109          * <SLV-T>    A0h       46h       [7:0]    ICFRL_CTRLVAL[15:8]
1110          * <SLV-T>    A0h       47h       [7:0]    ICFRL_CTRLVAL[7:0]
1111          */
1112         cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1113         cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1114                                 (((u32)data[1] & 0xFF) <<  8) |
1115                                 ((u32)data[2] & 0xFF), 20);
1116         temp_div = (is_hs_mode ? 1048576 : 1572864);
1117         if (cfrl_ctrlval > 0) {
1118                 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1119                         temp_div, &temp_r);
1120         } else {
1121                 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1122                         temp_div, &temp_r);
1123         }
1124         if (temp_r >= temp_div / 2)
1125                 temp_q++;
1126         if (cfrl_ctrlval > 0)
1127                 temp_q *= -1;
1128         *offset = temp_q;
1129         return 0;
1130 }
1131
1132 static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1133                                            u32 bandwidth, int *offset)
1134 {
1135         u8 data[4];
1136
1137         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1138         if (priv->state != STATE_ACTIVE_TC) {
1139                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1140                         __func__, priv->state);
1141                 return -EINVAL;
1142         }
1143         if (priv->system != SYS_ISDBT) {
1144                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1145                         __func__, priv->system);
1146                 return -EINVAL;
1147         }
1148         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1149         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1150         *offset = -1 * sign_extend32(
1151                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1152                 ((u32)data[2] << 8) | (u32)data[3], 29);
1153
1154         switch (bandwidth) {
1155         case 6000000:
1156                 *offset = -1 * ((*offset) * 8/264);
1157                 break;
1158         case 7000000:
1159                 *offset = -1 * ((*offset) * 8/231);
1160                 break;
1161         case 8000000:
1162                 *offset = -1 * ((*offset) * 8/198);
1163                 break;
1164         default:
1165                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1166                                 __func__, bandwidth);
1167                 return -EINVAL;
1168         }
1169
1170         dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1171                         __func__, bandwidth, *offset);
1172
1173         return 0;
1174 }
1175
1176 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1177                                            u32 bandwidth, int *offset)
1178 {
1179         u8 data[4];
1180
1181         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1182         if (priv->state != STATE_ACTIVE_TC) {
1183                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1184                         __func__, priv->state);
1185                 return -EINVAL;
1186         }
1187         if (priv->system != SYS_DVBT) {
1188                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1189                         __func__, priv->system);
1190                 return -EINVAL;
1191         }
1192         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1193         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1194         *offset = -1 * sign_extend32(
1195                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1196                 ((u32)data[2] << 8) | (u32)data[3], 29);
1197         *offset *= (bandwidth / 1000000);
1198         *offset /= 235;
1199         return 0;
1200 }
1201
1202 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1203                                            u32 bandwidth, int *offset)
1204 {
1205         u8 data[4];
1206
1207         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1208         if (priv->state != STATE_ACTIVE_TC) {
1209                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1210                         __func__, priv->state);
1211                 return -EINVAL;
1212         }
1213         if (priv->system != SYS_DVBT2) {
1214                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1215                         __func__, priv->system);
1216                 return -EINVAL;
1217         }
1218         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1219         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1220         *offset = -1 * sign_extend32(
1221                 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1222                 ((u32)data[2] << 8) | (u32)data[3], 27);
1223         switch (bandwidth) {
1224         case 1712000:
1225                 *offset /= 582;
1226                 break;
1227         case 5000000:
1228         case 6000000:
1229         case 7000000:
1230         case 8000000:
1231                 *offset *= (bandwidth / 1000000);
1232                 *offset /= 940;
1233                 break;
1234         default:
1235                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1236                         __func__, bandwidth);
1237                 return -EINVAL;
1238         }
1239         return 0;
1240 }
1241
1242 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1243                                           int *offset)
1244 {
1245         u8 data[2];
1246
1247         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1248         if (priv->state != STATE_ACTIVE_TC) {
1249                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1250                         __func__, priv->state);
1251                 return -EINVAL;
1252         }
1253         if (priv->system != SYS_DVBC_ANNEX_A) {
1254                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1255                         __func__, priv->system);
1256                 return -EINVAL;
1257         }
1258         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1259         cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1260         *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1261                                                 | (u32)data[1], 13), 16384);
1262         return 0;
1263 }
1264
1265 static int cxd2841er_read_packet_errors_t(
1266                 struct cxd2841er_priv *priv, u32 *penum)
1267 {
1268         u8 data[3];
1269
1270         *penum = 0;
1271         if (priv->state != STATE_ACTIVE_TC) {
1272                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1273                         __func__, priv->state);
1274                 return -EINVAL;
1275         }
1276         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1277         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1278         if (data[2] & 0x01)
1279                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1280         return 0;
1281 }
1282
1283 static int cxd2841er_read_packet_errors_t2(
1284                 struct cxd2841er_priv *priv, u32 *penum)
1285 {
1286         u8 data[3];
1287
1288         *penum = 0;
1289         if (priv->state != STATE_ACTIVE_TC) {
1290                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1291                         __func__, priv->state);
1292                 return -EINVAL;
1293         }
1294         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1295         cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1296         if (data[0] & 0x01)
1297                 *penum = ((u32)data[1] << 8) | (u32)data[2];
1298         return 0;
1299 }
1300
1301 static int cxd2841er_read_packet_errors_i(
1302                 struct cxd2841er_priv *priv, u32 *penum)
1303 {
1304         u8 data[2];
1305
1306         *penum = 0;
1307         if (priv->state != STATE_ACTIVE_TC) {
1308                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1309                                 __func__, priv->state);
1310                 return -EINVAL;
1311         }
1312         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1313         cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1314
1315         if (!(data[0] & 0x01))
1316                 return 0;
1317
1318         /* Layer A */
1319         cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1320         *penum = ((u32)data[0] << 8) | (u32)data[1];
1321
1322         /* Layer B */
1323         cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1324         *penum += ((u32)data[0] << 8) | (u32)data[1];
1325
1326         /* Layer C */
1327         cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1328         *penum += ((u32)data[0] << 8) | (u32)data[1];
1329
1330         return 0;
1331 }
1332
1333 static u32 cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv)
1334 {
1335         u8 data[11];
1336         u32 bit_error, bit_count;
1337         u32 temp_q, temp_r;
1338
1339         /* Set SLV-T Bank : 0xA0 */
1340         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1341         /*
1342          *  slave     Bank      Addr      Bit      Signal name
1343          * <SLV-T>    A0h       35h       [0]      IFVBER_VALID
1344          * <SLV-T>    A0h       36h       [5:0]    IFVBER_BITERR[21:16]
1345          * <SLV-T>    A0h       37h       [7:0]    IFVBER_BITERR[15:8]
1346          * <SLV-T>    A0h       38h       [7:0]    IFVBER_BITERR[7:0]
1347          * <SLV-T>    A0h       3Dh       [5:0]    IFVBER_BITNUM[21:16]
1348          * <SLV-T>    A0h       3Eh       [7:0]    IFVBER_BITNUM[15:8]
1349          * <SLV-T>    A0h       3Fh       [7:0]    IFVBER_BITNUM[7:0]
1350          */
1351         cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1352         if (data[0] & 0x01) {
1353                 bit_error = ((u32)(data[1]  & 0x3F) << 16) |
1354                         ((u32)(data[2]  & 0xFF) <<  8) |
1355                         (u32)(data[3]  & 0xFF);
1356                 bit_count = ((u32)(data[8]  & 0x3F) << 16) |
1357                         ((u32)(data[9]  & 0xFF) <<  8) |
1358                         (u32)(data[10] & 0xFF);
1359                 /*
1360                  *      BER = bitError / bitCount
1361                  *      = (bitError * 10^7) / bitCount
1362                  *      = ((bitError * 625 * 125 * 128) / bitCount
1363                  */
1364                 if ((bit_count == 0) || (bit_error > bit_count)) {
1365                         dev_dbg(&priv->i2c->dev,
1366                                 "%s(): invalid bit_error %d, bit_count %d\n",
1367                                 __func__, bit_error, bit_count);
1368                         return 0;
1369                 }
1370                 temp_q = div_u64_rem(10000000ULL * bit_error,
1371                                                 bit_count, &temp_r);
1372                 if (bit_count != 1 && temp_r >= bit_count / 2)
1373                         temp_q++;
1374                 return temp_q;
1375         }
1376         dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1377         return 0;
1378 }
1379
1380
1381 static u32 cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv)
1382 {
1383         u8 data[5];
1384         u32 bit_error, period;
1385         u32 temp_q, temp_r;
1386         u32 result = 0;
1387
1388         /* Set SLV-T Bank : 0xB2 */
1389         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1390         /*
1391          *  slave     Bank      Addr      Bit      Signal name
1392          * <SLV-T>    B2h       30h       [0]      IFLBER_VALID
1393          * <SLV-T>    B2h       31h       [3:0]    IFLBER_BITERR[27:24]
1394          * <SLV-T>    B2h       32h       [7:0]    IFLBER_BITERR[23:16]
1395          * <SLV-T>    B2h       33h       [7:0]    IFLBER_BITERR[15:8]
1396          * <SLV-T>    B2h       34h       [7:0]    IFLBER_BITERR[7:0]
1397          */
1398         cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1399         if (data[0] & 0x01) {
1400                 /* Bit error count */
1401                 bit_error = ((u32)(data[1] & 0x0F) << 24) |
1402                         ((u32)(data[2] & 0xFF) << 16) |
1403                         ((u32)(data[3] & 0xFF) <<  8) |
1404                         (u32)(data[4] & 0xFF);
1405
1406                 /* Set SLV-T Bank : 0xA0 */
1407                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1408                 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1409                 /* Measurement period */
1410                 period = (u32)(1 << (data[0] & 0x0F));
1411                 if (period == 0) {
1412                         dev_dbg(&priv->i2c->dev,
1413                                 "%s(): period is 0\n", __func__);
1414                         return 0;
1415                 }
1416                 if (bit_error > (period * 64800)) {
1417                         dev_dbg(&priv->i2c->dev,
1418                                 "%s(): invalid bit_err 0x%x period 0x%x\n",
1419                                 __func__, bit_error, period);
1420                         return 0;
1421                 }
1422                 /*
1423                  * BER = bitError / (period * 64800)
1424                  *      = (bitError * 10^7) / (period * 64800)
1425                  *      = (bitError * 10^5) / (period * 648)
1426                  *      = (bitError * 12500) / (period * 81)
1427                  *      = (bitError * 10) * 1250 / (period * 81)
1428                  */
1429                 temp_q = div_u64_rem(12500ULL * bit_error,
1430                                         period * 81, &temp_r);
1431                 if (temp_r >= period * 40)
1432                         temp_q++;
1433                 result = temp_q;
1434         } else {
1435                 dev_dbg(&priv->i2c->dev,
1436                         "%s(): no data available\n", __func__);
1437         }
1438         return result;
1439 }
1440
1441 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv, u32 *ber)
1442 {
1443         u8 data[4];
1444         u32 div, q, r;
1445         u32 bit_err, period_exp, n_ldpc;
1446
1447         *ber = 0;
1448         if (priv->state != STATE_ACTIVE_TC) {
1449                 dev_dbg(&priv->i2c->dev,
1450                         "%s(): invalid state %d\n", __func__, priv->state);
1451                 return -EINVAL;
1452         }
1453         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1454         cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1455         if (!(data[0] & 0x10)) {
1456                 dev_dbg(&priv->i2c->dev,
1457                         "%s(): no valid BER data\n", __func__);
1458                 return 0;
1459         }
1460         bit_err = ((u32)(data[0] & 0x0f) << 24) |
1461                 ((u32)data[1] << 16) |
1462                 ((u32)data[2] << 8) |
1463                 (u32)data[3];
1464         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1465         period_exp = data[0] & 0x0f;
1466         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1467         cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1468         n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1469         if (bit_err > ((1U << period_exp) * n_ldpc)) {
1470                 dev_dbg(&priv->i2c->dev,
1471                         "%s(): invalid BER value\n", __func__);
1472                 return -EINVAL;
1473         }
1474         if (period_exp >= 4) {
1475                 div = (1U << (period_exp - 4)) * (n_ldpc / 200);
1476                 q = div_u64_rem(3125ULL * bit_err, div, &r);
1477         } else {
1478                 div = (1U << period_exp) * (n_ldpc / 200);
1479                 q = div_u64_rem(50000ULL * bit_err, div, &r);
1480         }
1481         *ber = (r >= div / 2) ? q + 1 : q;
1482         return 0;
1483 }
1484
1485 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv, u32 *ber)
1486 {
1487         u8 data[2];
1488         u32 div, q, r;
1489         u32 bit_err, period;
1490
1491         *ber = 0;
1492         if (priv->state != STATE_ACTIVE_TC) {
1493                 dev_dbg(&priv->i2c->dev,
1494                         "%s(): invalid state %d\n", __func__, priv->state);
1495                 return -EINVAL;
1496         }
1497         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1498         cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1499         if (!(data[0] & 0x01)) {
1500                 dev_dbg(&priv->i2c->dev,
1501                         "%s(): no valid BER data\n", __func__);
1502                 return 0;
1503         }
1504         cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1505         bit_err = ((u32)data[0] << 8) | (u32)data[1];
1506         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1507         period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1508         div = period / 128;
1509         q = div_u64_rem(78125ULL * bit_err, div, &r);
1510         *ber = (r >= div / 2) ? q + 1 : q;
1511         return 0;
1512 }
1513
1514 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys)
1515 {
1516         u8 data[3];
1517         u32 res = 0, value;
1518         int min_index, max_index, index;
1519         static const struct cxd2841er_cnr_data *cn_data;
1520
1521         /* Set SLV-T Bank : 0xA1 */
1522         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1523         /*
1524          *  slave     Bank      Addr      Bit     Signal name
1525          * <SLV-T>    A1h       10h       [0]     ICPM_QUICKRDY
1526          * <SLV-T>    A1h       11h       [4:0]   ICPM_QUICKCNDT[12:8]
1527          * <SLV-T>    A1h       12h       [7:0]   ICPM_QUICKCNDT[7:0]
1528          */
1529         cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1530         if (data[0] & 0x01) {
1531                 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1532                 min_index = 0;
1533                 if (delsys == SYS_DVBS) {
1534                         cn_data = s_cn_data;
1535                         max_index = sizeof(s_cn_data) /
1536                                 sizeof(s_cn_data[0]) - 1;
1537                 } else {
1538                         cn_data = s2_cn_data;
1539                         max_index = sizeof(s2_cn_data) /
1540                                 sizeof(s2_cn_data[0]) - 1;
1541                 }
1542                 if (value >= cn_data[min_index].value) {
1543                         res = cn_data[min_index].cnr_x1000;
1544                         goto done;
1545                 }
1546                 if (value <= cn_data[max_index].value) {
1547                         res = cn_data[max_index].cnr_x1000;
1548                         goto done;
1549                 }
1550                 while ((max_index - min_index) > 1) {
1551                         index = (max_index + min_index) / 2;
1552                         if (value == cn_data[index].value) {
1553                                 res = cn_data[index].cnr_x1000;
1554                                 goto done;
1555                         } else if (value > cn_data[index].value)
1556                                 max_index = index;
1557                         else
1558                                 min_index = index;
1559                         if ((max_index - min_index) <= 1) {
1560                                 if (value == cn_data[max_index].value) {
1561                                         res = cn_data[max_index].cnr_x1000;
1562                                         goto done;
1563                                 } else {
1564                                         res = cn_data[min_index].cnr_x1000;
1565                                         goto done;
1566                                 }
1567                         }
1568                 }
1569         } else {
1570                 dev_dbg(&priv->i2c->dev,
1571                         "%s(): no data available\n", __func__);
1572         }
1573 done:
1574         return res;
1575 }
1576
1577 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1578 {
1579         u32 reg;
1580         u8 data[2];
1581
1582         *snr = 0;
1583         if (priv->state != STATE_ACTIVE_TC) {
1584                 dev_dbg(&priv->i2c->dev,
1585                         "%s(): invalid state %d\n", __func__, priv->state);
1586                 return -EINVAL;
1587         }
1588         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1589         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1590         reg = ((u32)data[0] << 8) | (u32)data[1];
1591         if (reg == 0) {
1592                 dev_dbg(&priv->i2c->dev,
1593                         "%s(): reg value out of range\n", __func__);
1594                 return 0;
1595         }
1596         if (reg > 4996)
1597                 reg = 4996;
1598         *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1599         return 0;
1600 }
1601
1602 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1603 {
1604         u32 reg;
1605         u8 data[2];
1606
1607         *snr = 0;
1608         if (priv->state != STATE_ACTIVE_TC) {
1609                 dev_dbg(&priv->i2c->dev,
1610                         "%s(): invalid state %d\n", __func__, priv->state);
1611                 return -EINVAL;
1612         }
1613         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1614         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1615         reg = ((u32)data[0] << 8) | (u32)data[1];
1616         if (reg == 0) {
1617                 dev_dbg(&priv->i2c->dev,
1618                         "%s(): reg value out of range\n", __func__);
1619                 return 0;
1620         }
1621         if (reg > 10876)
1622                 reg = 10876;
1623         *snr = 10000 * ((intlog10(reg) -
1624                 intlog10(12600 - reg)) >> 24) + 32000;
1625         return 0;
1626 }
1627
1628 static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1629 {
1630         u32 reg;
1631         u8 data[2];
1632
1633         *snr = 0;
1634         if (priv->state != STATE_ACTIVE_TC) {
1635                 dev_dbg(&priv->i2c->dev,
1636                                 "%s(): invalid state %d\n", __func__,
1637                                 priv->state);
1638                 return -EINVAL;
1639         }
1640
1641         /* Freeze all registers */
1642         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1643
1644
1645         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1646         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1647         reg = ((u32)data[0] << 8) | (u32)data[1];
1648         if (reg == 0) {
1649                 dev_dbg(&priv->i2c->dev,
1650                                 "%s(): reg value out of range\n", __func__);
1651                 return 0;
1652         }
1653         if (reg > 4996)
1654                 reg = 4996;
1655         *snr = 100 * intlog10(reg) - 9031;
1656         return 0;
1657 }
1658
1659 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1660                                         u8 delsys)
1661 {
1662         u8 data[2];
1663
1664         cxd2841er_write_reg(
1665                 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1666         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1667         dev_dbg(&priv->i2c->dev,
1668                         "%s(): AGC value=%u\n",
1669                         __func__, (((u16)data[0] & 0x0F) << 8) |
1670                         (u16)(data[1] & 0xFF));
1671         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1672 }
1673
1674 static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1675                 u8 delsys)
1676 {
1677         u8 data[2];
1678
1679         cxd2841er_write_reg(
1680                         priv, I2C_SLVT, 0x00, 0x60);
1681         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1682
1683         dev_dbg(&priv->i2c->dev,
1684                         "%s(): AGC value=%u\n",
1685                         __func__, (((u16)data[0] & 0x0F) << 8) |
1686                         (u16)(data[1] & 0xFF));
1687         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1688 }
1689
1690 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1691 {
1692         u8 data[2];
1693
1694         /* Set SLV-T Bank : 0xA0 */
1695         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1696         /*
1697          *  slave     Bank      Addr      Bit       Signal name
1698          * <SLV-T>    A0h       1Fh       [4:0]     IRFAGC_GAIN[12:8]
1699          * <SLV-T>    A0h       20h       [7:0]     IRFAGC_GAIN[7:0]
1700          */
1701         cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1702         return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1703 }
1704
1705 static int cxd2841er_read_ber(struct dvb_frontend *fe, u32 *ber)
1706 {
1707         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1708         struct cxd2841er_priv *priv = fe->demodulator_priv;
1709
1710         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1711         *ber = 0;
1712         switch (p->delivery_system) {
1713         case SYS_DVBS:
1714                 *ber = cxd2841er_mon_read_ber_s(priv);
1715                 break;
1716         case SYS_DVBS2:
1717                 *ber = cxd2841er_mon_read_ber_s2(priv);
1718                 break;
1719         case SYS_DVBT:
1720                 return cxd2841er_read_ber_t(priv, ber);
1721         case SYS_DVBT2:
1722                 return cxd2841er_read_ber_t2(priv, ber);
1723         default:
1724                 *ber = 0;
1725                 break;
1726         }
1727         return 0;
1728 }
1729
1730 static int cxd2841er_read_signal_strength(struct dvb_frontend *fe,
1731                                           u16 *strength)
1732 {
1733         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1734         struct cxd2841er_priv *priv = fe->demodulator_priv;
1735
1736         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1737         switch (p->delivery_system) {
1738         case SYS_DVBT:
1739         case SYS_DVBT2:
1740                 *strength = 65535 - cxd2841er_read_agc_gain_t_t2(
1741                         priv, p->delivery_system);
1742                 break;
1743         case SYS_ISDBT:
1744                 *strength = 65535 - cxd2841er_read_agc_gain_i(
1745                                 priv, p->delivery_system);
1746                 break;
1747         case SYS_DVBS:
1748         case SYS_DVBS2:
1749                 *strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1750                 break;
1751         default:
1752                 *strength = 0;
1753                 break;
1754         }
1755         return 0;
1756 }
1757
1758 static int cxd2841er_read_snr(struct dvb_frontend *fe, u16 *snr)
1759 {
1760         u32 tmp = 0;
1761         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1762         struct cxd2841er_priv *priv = fe->demodulator_priv;
1763
1764         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1765         switch (p->delivery_system) {
1766         case SYS_DVBT:
1767                 cxd2841er_read_snr_t(priv, &tmp);
1768                 break;
1769         case SYS_DVBT2:
1770                 cxd2841er_read_snr_t2(priv, &tmp);
1771                 break;
1772         case SYS_ISDBT:
1773                 cxd2841er_read_snr_i(priv, &tmp);
1774                 break;
1775         case SYS_DVBS:
1776         case SYS_DVBS2:
1777                 tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system);
1778                 break;
1779         default:
1780                 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1781                         __func__, p->delivery_system);
1782                 break;
1783         }
1784         *snr = tmp & 0xffff;
1785         return 0;
1786 }
1787
1788 static int cxd2841er_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1789 {
1790         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1791         struct cxd2841er_priv *priv = fe->demodulator_priv;
1792
1793         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1794         switch (p->delivery_system) {
1795         case SYS_DVBT:
1796                 cxd2841er_read_packet_errors_t(priv, ucblocks);
1797                 break;
1798         case SYS_DVBT2:
1799                 cxd2841er_read_packet_errors_t2(priv, ucblocks);
1800                 break;
1801         case SYS_ISDBT:
1802                 cxd2841er_read_packet_errors_i(priv, ucblocks);
1803                 break;
1804         default:
1805                 *ucblocks = 0;
1806                 break;
1807         }
1808         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1809         return 0;
1810 }
1811
1812 static int cxd2841er_dvbt2_set_profile(
1813         struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
1814 {
1815         u8 tune_mode;
1816         u8 seq_not2d_time;
1817
1818         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1819         switch (profile) {
1820         case DVBT2_PROFILE_BASE:
1821                 tune_mode = 0x01;
1822                 /* Set early unlock time */
1823                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
1824                 break;
1825         case DVBT2_PROFILE_LITE:
1826                 tune_mode = 0x05;
1827                 /* Set early unlock time */
1828                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
1829                 break;
1830         case DVBT2_PROFILE_ANY:
1831                 tune_mode = 0x00;
1832                 /* Set early unlock time */
1833                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
1834                 break;
1835         default:
1836                 return -EINVAL;
1837         }
1838         /* Set SLV-T Bank : 0x2E */
1839         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
1840         /* Set profile and tune mode */
1841         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
1842         /* Set SLV-T Bank : 0x2B */
1843         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1844         /* Set early unlock detection time */
1845         cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
1846         return 0;
1847 }
1848
1849 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
1850                                           u8 is_auto, u8 plp_id)
1851 {
1852         if (is_auto) {
1853                 dev_dbg(&priv->i2c->dev,
1854                         "%s() using auto PLP selection\n", __func__);
1855         } else {
1856                 dev_dbg(&priv->i2c->dev,
1857                         "%s() using manual PLP selection, ID %d\n",
1858                         __func__, plp_id);
1859         }
1860         /* Set SLV-T Bank : 0x23 */
1861         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
1862         if (!is_auto) {
1863                 /* Manual PLP selection mode. Set the data PLP Id. */
1864                 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
1865         }
1866         /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1867         cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
1868         return 0;
1869 }
1870
1871 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
1872                                                 u32 bandwidth)
1873 {
1874         u32 iffreq;
1875         u8 data[MAX_WRITE_REGSIZE];
1876
1877         const uint8_t nominalRate8bw[3][5] = {
1878                 /* TRCG Nominal Rate [37:0] */
1879                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1880                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1881                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
1882         };
1883
1884         const uint8_t nominalRate7bw[3][5] = {
1885                 /* TRCG Nominal Rate [37:0] */
1886                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
1887                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1888                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
1889         };
1890
1891         const uint8_t nominalRate6bw[3][5] = {
1892                 /* TRCG Nominal Rate [37:0] */
1893                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
1894                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
1895                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
1896         };
1897
1898         const uint8_t nominalRate5bw[3][5] = {
1899                 /* TRCG Nominal Rate [37:0] */
1900                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
1901                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
1902                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
1903         };
1904
1905         const uint8_t nominalRate17bw[3][5] = {
1906                 /* TRCG Nominal Rate [37:0] */
1907                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
1908                 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
1909                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}  /* 41MHz XTal */
1910         };
1911
1912         const uint8_t itbCoef8bw[3][14] = {
1913                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
1914                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
1915                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
1916                         0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
1917                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
1918                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
1919         };
1920
1921         const uint8_t itbCoef7bw[3][14] = {
1922                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
1923                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
1924                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
1925                         0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
1926                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
1927                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
1928         };
1929
1930         const uint8_t itbCoef6bw[3][14] = {
1931                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1932                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1933                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
1934                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
1935                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1936                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
1937         };
1938
1939         const uint8_t itbCoef5bw[3][14] = {
1940                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1941                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
1942                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
1943                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
1944                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1945                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
1946         };
1947
1948         const uint8_t itbCoef17bw[3][14] = {
1949                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
1950                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
1951                 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
1952                         0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal   */
1953                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
1954                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}  /* 41MHz XTal   */
1955         };
1956
1957         /* Set SLV-T Bank : 0x20 */
1958         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1959
1960         switch (bandwidth) {
1961         case 8000000:
1962                 /* <Timing Recovery setting> */
1963                 cxd2841er_write_regs(priv, I2C_SLVT,
1964                                 0x9F, nominalRate8bw[priv->xtal], 5);
1965
1966                 /* Set SLV-T Bank : 0x27 */
1967                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
1968                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
1969                                 0x7a, 0x00, 0x0f);
1970
1971                 /* Set SLV-T Bank : 0x10 */
1972                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1973
1974                 /* Group delay equaliser settings for
1975                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
1976                  */
1977                 cxd2841er_write_regs(priv, I2C_SLVT,
1978                                 0xA6, itbCoef8bw[priv->xtal], 14);
1979                 /* <IF freq setting> */
1980                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
1981                 data[0] = (u8) ((iffreq >> 16) & 0xff);
1982                 data[1] = (u8)((iffreq >> 8) & 0xff);
1983                 data[2] = (u8)(iffreq & 0xff);
1984                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
1985                 /* System bandwidth setting */
1986                 cxd2841er_set_reg_bits(
1987                                 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
1988                 break;
1989         case 7000000:
1990                 /* <Timing Recovery setting> */
1991                 cxd2841er_write_regs(priv, I2C_SLVT,
1992                                 0x9F, nominalRate7bw[priv->xtal], 5);
1993
1994                 /* Set SLV-T Bank : 0x27 */
1995                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
1996                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
1997                                 0x7a, 0x00, 0x0f);
1998
1999                 /* Set SLV-T Bank : 0x10 */
2000                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2001
2002                 /* Group delay equaliser settings for
2003                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2004                  */
2005                 cxd2841er_write_regs(priv, I2C_SLVT,
2006                                 0xA6, itbCoef7bw[priv->xtal], 14);
2007                 /* <IF freq setting> */
2008                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2009                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2010                 data[1] = (u8)((iffreq >> 8) & 0xff);
2011                 data[2] = (u8)(iffreq & 0xff);
2012                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2013                 /* System bandwidth setting */
2014                 cxd2841er_set_reg_bits(
2015                                 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2016                 break;
2017         case 6000000:
2018                 /* <Timing Recovery setting> */
2019                 cxd2841er_write_regs(priv, I2C_SLVT,
2020                                 0x9F, nominalRate6bw[priv->xtal], 5);
2021
2022                 /* Set SLV-T Bank : 0x27 */
2023                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2024                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2025                                 0x7a, 0x00, 0x0f);
2026
2027                 /* Set SLV-T Bank : 0x10 */
2028                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2029
2030                 /* Group delay equaliser settings for
2031                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2032                  */
2033                 cxd2841er_write_regs(priv, I2C_SLVT,
2034                                 0xA6, itbCoef6bw[priv->xtal], 14);
2035                 /* <IF freq setting> */
2036                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2037                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2038                 data[1] = (u8)((iffreq >> 8) & 0xff);
2039                 data[2] = (u8)(iffreq & 0xff);
2040                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2041                 /* System bandwidth setting */
2042                 cxd2841er_set_reg_bits(
2043                                 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2044                 break;
2045         case 5000000:
2046                 /* <Timing Recovery setting> */
2047                 cxd2841er_write_regs(priv, I2C_SLVT,
2048                                 0x9F, nominalRate5bw[priv->xtal], 5);
2049
2050                 /* Set SLV-T Bank : 0x27 */
2051                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2052                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2053                                 0x7a, 0x00, 0x0f);
2054
2055                 /* Set SLV-T Bank : 0x10 */
2056                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2057
2058                 /* Group delay equaliser settings for
2059                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2060                  */
2061                 cxd2841er_write_regs(priv, I2C_SLVT,
2062                                 0xA6, itbCoef5bw[priv->xtal], 14);
2063                 /* <IF freq setting> */
2064                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2065                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2066                 data[1] = (u8)((iffreq >> 8) & 0xff);
2067                 data[2] = (u8)(iffreq & 0xff);
2068                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2069                 /* System bandwidth setting */
2070                 cxd2841er_set_reg_bits(
2071                                 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2072                 break;
2073         case 1712000:
2074                 /* <Timing Recovery setting> */
2075                 cxd2841er_write_regs(priv, I2C_SLVT,
2076                                 0x9F, nominalRate17bw[priv->xtal], 5);
2077
2078                 /* Set SLV-T Bank : 0x27 */
2079                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2080                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2081                                 0x7a, 0x03, 0x0f);
2082
2083                 /* Set SLV-T Bank : 0x10 */
2084                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2085
2086                 /* Group delay equaliser settings for
2087                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2088                  */
2089                 cxd2841er_write_regs(priv, I2C_SLVT,
2090                                 0xA6, itbCoef17bw[priv->xtal], 14);
2091                 /* <IF freq setting> */
2092                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.50);
2093                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2094                 data[1] = (u8)((iffreq >> 8) & 0xff);
2095                 data[2] = (u8)(iffreq & 0xff);
2096                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2097                 /* System bandwidth setting */
2098                 cxd2841er_set_reg_bits(
2099                                 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
2100                 break;
2101         default:
2102                 return -EINVAL;
2103         }
2104         return 0;
2105 }
2106
2107 static int cxd2841er_sleep_tc_to_active_t_band(
2108                 struct cxd2841er_priv *priv, u32 bandwidth)
2109 {
2110         u8 data[MAX_WRITE_REGSIZE];
2111         u32 iffreq;
2112         u8 nominalRate8bw[3][5] = {
2113                 /* TRCG Nominal Rate [37:0] */
2114                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2115                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2116                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2117         };
2118         u8 nominalRate7bw[3][5] = {
2119                 /* TRCG Nominal Rate [37:0] */
2120                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2121                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2122                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2123         };
2124         u8 nominalRate6bw[3][5] = {
2125                 /* TRCG Nominal Rate [37:0] */
2126                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2127                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2128                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2129         };
2130         u8 nominalRate5bw[3][5] = {
2131                 /* TRCG Nominal Rate [37:0] */
2132                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2133                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2134                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2135         };
2136
2137         u8 itbCoef8bw[3][14] = {
2138                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2139                         0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2140                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2141                         0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2142                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2143                         0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2144         };
2145         u8 itbCoef7bw[3][14] = {
2146                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2147                         0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2148                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2149                         0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2150                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2151                         0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2152         };
2153         u8 itbCoef6bw[3][14] = {
2154                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2155                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2156                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2157                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2158                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2159                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2160         };
2161         u8 itbCoef5bw[3][14] = {
2162                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2163                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2164                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2165                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2166                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2167                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2168         };
2169
2170         /* Set SLV-T Bank : 0x13 */
2171         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2172         /* Echo performance optimization setting */
2173         data[0] = 0x01;
2174         data[1] = 0x14;
2175         cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2176
2177         /* Set SLV-T Bank : 0x10 */
2178         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2179
2180         switch (bandwidth) {
2181         case 8000000:
2182                 /* <Timing Recovery setting> */
2183                 cxd2841er_write_regs(priv, I2C_SLVT,
2184                                 0x9F, nominalRate8bw[priv->xtal], 5);
2185                 /* Group delay equaliser settings for
2186                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2187                 */
2188                 cxd2841er_write_regs(priv, I2C_SLVT,
2189                                 0xA6, itbCoef8bw[priv->xtal], 14);
2190                 /* <IF freq setting> */
2191                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2192                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2193                 data[1] = (u8)((iffreq >> 8) & 0xff);
2194                 data[2] = (u8)(iffreq & 0xff);
2195                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2196                 /* System bandwidth setting */
2197                 cxd2841er_set_reg_bits(
2198                         priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2199
2200                 /* Demod core latency setting */
2201                 if (priv->xtal == SONY_XTAL_24000) {
2202                         data[0] = 0x15;
2203                         data[1] = 0x28;
2204                 } else {
2205                         data[0] = 0x01;
2206                         data[1] = 0xE0;
2207                 }
2208                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2209
2210                 /* Notch filter setting */
2211                 data[0] = 0x01;
2212                 data[1] = 0x02;
2213                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2214                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2215                 break;
2216         case 7000000:
2217                 /* <Timing Recovery setting> */
2218                 cxd2841er_write_regs(priv, I2C_SLVT,
2219                                 0x9F, nominalRate7bw[priv->xtal], 5);
2220                 /* Group delay equaliser settings for
2221                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2222                 */
2223                 cxd2841er_write_regs(priv, I2C_SLVT,
2224                                 0xA6, itbCoef7bw[priv->xtal], 14);
2225                 /* <IF freq setting> */
2226                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2227                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2228                 data[1] = (u8)((iffreq >> 8) & 0xff);
2229                 data[2] = (u8)(iffreq & 0xff);
2230                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2231                 /* System bandwidth setting */
2232                 cxd2841er_set_reg_bits(
2233                         priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2234
2235                 /* Demod core latency setting */
2236                 if (priv->xtal == SONY_XTAL_24000) {
2237                         data[0] = 0x1F;
2238                         data[1] = 0xF8;
2239                 } else {
2240                         data[0] = 0x12;
2241                         data[1] = 0xF8;
2242                 }
2243                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2244
2245                 /* Notch filter setting */
2246                 data[0] = 0x00;
2247                 data[1] = 0x03;
2248                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2249                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2250                 break;
2251         case 6000000:
2252                 /* <Timing Recovery setting> */
2253                 cxd2841er_write_regs(priv, I2C_SLVT,
2254                                 0x9F, nominalRate6bw[priv->xtal], 5);
2255                 /* Group delay equaliser settings for
2256                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2257                 */
2258                 cxd2841er_write_regs(priv, I2C_SLVT,
2259                                 0xA6, itbCoef6bw[priv->xtal], 14);
2260                 /* <IF freq setting> */
2261                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2262                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2263                 data[1] = (u8)((iffreq >> 8) & 0xff);
2264                 data[2] = (u8)(iffreq & 0xff);
2265                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2266                 /* System bandwidth setting */
2267                 cxd2841er_set_reg_bits(
2268                         priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2269
2270                 /* Demod core latency setting */
2271                 if (priv->xtal == SONY_XTAL_24000) {
2272                         data[0] = 0x25;
2273                         data[1] = 0x4C;
2274                 } else {
2275                         data[0] = 0x1F;
2276                         data[1] = 0xDC;
2277                 }
2278                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2279
2280                 /* Notch filter setting */
2281                 data[0] = 0x00;
2282                 data[1] = 0x03;
2283                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2284                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2285                 break;
2286         case 5000000:
2287                 /* <Timing Recovery setting> */
2288                 cxd2841er_write_regs(priv, I2C_SLVT,
2289                                 0x9F, nominalRate5bw[priv->xtal], 5);
2290                 /* Group delay equaliser settings for
2291                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2292                 */
2293                 cxd2841er_write_regs(priv, I2C_SLVT,
2294                                 0xA6, itbCoef5bw[priv->xtal], 14);
2295                 /* <IF freq setting> */
2296                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2297                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2298                 data[1] = (u8)((iffreq >> 8) & 0xff);
2299                 data[2] = (u8)(iffreq & 0xff);
2300                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2301                 /* System bandwidth setting */
2302                 cxd2841er_set_reg_bits(
2303                         priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2304
2305                 /* Demod core latency setting */
2306                 if (priv->xtal == SONY_XTAL_24000) {
2307                         data[0] = 0x2C;
2308                         data[1] = 0xC2;
2309                 } else {
2310                         data[0] = 0x26;
2311                         data[1] = 0x3C;
2312                 }
2313                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2314
2315                 /* Notch filter setting */
2316                 data[0] = 0x00;
2317                 data[1] = 0x03;
2318                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2319                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2320                 break;
2321         }
2322
2323         return 0;
2324 }
2325
2326 static int cxd2841er_sleep_tc_to_active_i_band(
2327                 struct cxd2841er_priv *priv, u32 bandwidth)
2328 {
2329         u32 iffreq;
2330         u8 data[3];
2331
2332         /* TRCG Nominal Rate */
2333         u8 nominalRate8bw[3][5] = {
2334                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2335                 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2336                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2337         };
2338
2339         u8 nominalRate7bw[3][5] = {
2340                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2341                 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2342                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2343         };
2344
2345         u8 nominalRate6bw[3][5] = {
2346                 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2347                 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2348                 {0x14, 0x2E, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2349         };
2350
2351         u8 itbCoef8bw[3][14] = {
2352                 {0x00}, /* 20.5MHz XTal */
2353                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2354                         0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2355                 {0x0}, /* 41MHz XTal   */
2356         };
2357
2358         u8 itbCoef7bw[3][14] = {
2359                 {0x00}, /* 20.5MHz XTal */
2360                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2361                         0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2362                 {0x00}, /* 41MHz XTal   */
2363         };
2364
2365         u8 itbCoef6bw[3][14] = {
2366                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2367                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2368                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2369                         0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal   */
2370                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2371                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal   */
2372         };
2373
2374         dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2375         /* Set SLV-T Bank : 0x10 */
2376         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2377
2378         /*  20.5/41MHz Xtal support is not available
2379          *  on ISDB-T 7MHzBW and 8MHzBW
2380         */
2381         if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2382                 dev_err(&priv->i2c->dev,
2383                         "%s(): bandwidth %d supported only for 24MHz xtal\n",
2384                         __func__, bandwidth);
2385                 return -EINVAL;
2386         }
2387
2388         switch (bandwidth) {
2389         case 8000000:
2390                 /* TRCG Nominal Rate */
2391                 cxd2841er_write_regs(priv, I2C_SLVT,
2392                                 0x9F, nominalRate8bw[priv->xtal], 5);
2393                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2394                 cxd2841er_write_regs(priv, I2C_SLVT,
2395                                 0xA6, itbCoef8bw[priv->xtal], 14);
2396
2397                 /* IF freq setting */
2398                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75);
2399                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2400                 data[1] = (u8)((iffreq >> 8) & 0xff);
2401                 data[2] = (u8)(iffreq & 0xff);
2402                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2403
2404                 /* System bandwidth setting */
2405                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2406
2407                 /* Demod core latency setting */
2408                 data[0] = 0x13;
2409                 data[1] = 0xFC;
2410                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2411
2412                 /* Acquisition optimization setting */
2413                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2414                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2415                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2416                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2417                 break;
2418         case 7000000:
2419                 /* TRCG Nominal Rate */
2420                 cxd2841er_write_regs(priv, I2C_SLVT,
2421                                 0x9F, nominalRate7bw[priv->xtal], 5);
2422                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2423                 cxd2841er_write_regs(priv, I2C_SLVT,
2424                                 0xA6, itbCoef7bw[priv->xtal], 14);
2425
2426                 /* IF freq setting */
2427                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15);
2428                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2429                 data[1] = (u8)((iffreq >> 8) & 0xff);
2430                 data[2] = (u8)(iffreq & 0xff);
2431                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2432
2433                 /* System bandwidth setting */
2434                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2435
2436                 /* Demod core latency setting */
2437                 data[0] = 0x1A;
2438                 data[1] = 0xFA;
2439                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2440
2441                 /* Acquisition optimization setting */
2442                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2443                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2444                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2445                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2446                 break;
2447         case 6000000:
2448                 /* TRCG Nominal Rate */
2449                 cxd2841er_write_regs(priv, I2C_SLVT,
2450                                 0x9F, nominalRate6bw[priv->xtal], 5);
2451                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2452                 cxd2841er_write_regs(priv, I2C_SLVT,
2453                                 0xA6, itbCoef6bw[priv->xtal], 14);
2454
2455                 /* IF freq setting */
2456                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55);
2457                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2458                 data[1] = (u8)((iffreq >> 8) & 0xff);
2459                 data[2] = (u8)(iffreq & 0xff);
2460                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2461
2462                 /* System bandwidth setting */
2463                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2464
2465                 /* Demod core latency setting */
2466                 if (priv->xtal == SONY_XTAL_24000) {
2467                         data[0] = 0x1F;
2468                         data[1] = 0x79;
2469                 } else {
2470                         data[0] = 0x1A;
2471                         data[1] = 0xE2;
2472                 }
2473                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2474
2475                 /* Acquisition optimization setting */
2476                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2477                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2478                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2479                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2480                 break;
2481         default:
2482                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2483                                 __func__, bandwidth);
2484                 return -EINVAL;
2485         }
2486         return 0;
2487 }
2488
2489 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2490                                                u32 bandwidth)
2491 {
2492         u8 bw7_8mhz_b10_a6[] = {
2493                 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2494                 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2495         u8 bw6mhz_b10_a6[] = {
2496                 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2497                 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2498         u8 b10_b6[3];
2499         u32 iffreq;
2500
2501         dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
2502         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2503         switch (bandwidth) {
2504         case 8000000:
2505         case 7000000:
2506                 cxd2841er_write_regs(
2507                         priv, I2C_SLVT, 0xa6,
2508                         bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2509                 iffreq = MAKE_IFFREQ_CONFIG(4.9);
2510                 break;
2511         case 6000000:
2512                 cxd2841er_write_regs(
2513                         priv, I2C_SLVT, 0xa6,
2514                         bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2515                 iffreq = MAKE_IFFREQ_CONFIG(3.7);
2516                 break;
2517         default:
2518                 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2519                         __func__, bandwidth);
2520                 return -EINVAL;
2521         }
2522         /* <IF freq setting> */
2523         b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2524         b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2525         b10_b6[2] = (u8)(iffreq & 0xff);
2526         cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2527         /* Set SLV-T Bank : 0x11 */
2528         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2529         switch (bandwidth) {
2530         case 8000000:
2531         case 7000000:
2532                 cxd2841er_set_reg_bits(
2533                         priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2534                 break;
2535         case 6000000:
2536                 cxd2841er_set_reg_bits(
2537                         priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2538                 break;
2539         }
2540         /* Set SLV-T Bank : 0x40 */
2541         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2542         switch (bandwidth) {
2543         case 8000000:
2544                 cxd2841er_set_reg_bits(
2545                         priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2546                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x3e);
2547                 break;
2548         case 7000000:
2549                 cxd2841er_set_reg_bits(
2550                         priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2551                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0xd6);
2552                 break;
2553         case 6000000:
2554                 cxd2841er_set_reg_bits(
2555                         priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2556                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x6e);
2557                 break;
2558         }
2559         return 0;
2560 }
2561
2562 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2563                                           u32 bandwidth)
2564 {
2565         u8 data[2] = { 0x09, 0x54 };
2566         u8 data24m[3] = {0xDC, 0x6C, 0x00};
2567
2568         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2569         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2570         /* Set SLV-X Bank : 0x00 */
2571         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2572         /* Set demod mode */
2573         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2574         /* Set SLV-T Bank : 0x00 */
2575         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2576         /* Enable demod clock */
2577         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2578         /* Disable RF level monitor */
2579         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2580         /* Enable ADC clock */
2581         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2582         /* Enable ADC 1 */
2583         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2584         /* Enable ADC 2 & 3 */
2585         if (priv->xtal == SONY_XTAL_41000) {
2586                 data[0] = 0x0A;
2587                 data[1] = 0xD4;
2588         }
2589         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2590         /* Enable ADC 4 */
2591         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2592         /* Set SLV-T Bank : 0x10 */
2593         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2594         /* IFAGC gain settings */
2595         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2596         /* Set SLV-T Bank : 0x11 */
2597         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2598         /* BBAGC TARGET level setting */
2599         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2600         /* Set SLV-T Bank : 0x10 */
2601         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2602         /* ASCOT setting ON */
2603         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2604         /* Set SLV-T Bank : 0x18 */
2605         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2606         /* Pre-RS BER moniter setting */
2607         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2608         /* FEC Auto Recovery setting */
2609         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2610         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2611         /* Set SLV-T Bank : 0x00 */
2612         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2613         /* TSIF setting */
2614         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2615         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2616
2617         if (priv->xtal == SONY_XTAL_24000) {
2618                 /* Set SLV-T Bank : 0x10 */
2619                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2620                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2621                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2622                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2623         }
2624
2625         cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2626         /* Set SLV-T Bank : 0x00 */
2627         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2628         /* Disable HiZ Setting 1 */
2629         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2630         /* Disable HiZ Setting 2 */
2631         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2632         priv->state = STATE_ACTIVE_TC;
2633         return 0;
2634 }
2635
2636 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2637                                            u32 bandwidth)
2638 {
2639         u8 data[MAX_WRITE_REGSIZE];
2640
2641         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2642         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2643         /* Set SLV-X Bank : 0x00 */
2644         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2645         /* Set demod mode */
2646         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2647         /* Set SLV-T Bank : 0x00 */
2648         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2649         /* Enable demod clock */
2650         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2651         /* Disable RF level monitor */
2652         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
2653         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2654         /* Enable ADC clock */
2655         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2656         /* Enable ADC 1 */
2657         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2658
2659         if (priv->xtal == SONY_XTAL_41000) {
2660                 data[0] = 0x0A;
2661                 data[1] = 0xD4;
2662         } else {
2663                 data[0] = 0x09;
2664                 data[1] = 0x54;
2665         }
2666
2667         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2668         /* Enable ADC 4 */
2669         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2670         /* Set SLV-T Bank : 0x10 */
2671         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2672         /* IFAGC gain settings */
2673         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2674         /* Set SLV-T Bank : 0x11 */
2675         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2676         /* BBAGC TARGET level setting */
2677         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2678         /* Set SLV-T Bank : 0x10 */
2679         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2680         /* ASCOT setting ON */
2681         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2682         /* Set SLV-T Bank : 0x20 */
2683         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2684         /* Acquisition optimization setting */
2685         cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2686         /* Set SLV-T Bank : 0x2b */
2687         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2688         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
2689         /* Set SLV-T Bank : 0x23 */
2690         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2691         /* L1 Control setting */
2692         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
2693         /* Set SLV-T Bank : 0x00 */
2694         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2695         /* TSIF setting */
2696         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2697         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2698         /* DVB-T2 initial setting */
2699         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2700         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2701         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2702         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2703         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2704         /* Set SLV-T Bank : 0x2a */
2705         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2706         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2707         /* Set SLV-T Bank : 0x2b */
2708         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2709         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2710
2711         /* 24MHz Xtal setting */
2712         if (priv->xtal == SONY_XTAL_24000) {
2713                 /* Set SLV-T Bank : 0x11 */
2714                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2715                 data[0] = 0xEB;
2716                 data[1] = 0x03;
2717                 data[2] = 0x3B;
2718                 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
2719
2720                 /* Set SLV-T Bank : 0x20 */
2721                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2722                 data[0] = 0x5E;
2723                 data[1] = 0x5E;
2724                 data[2] = 0x47;
2725                 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
2726
2727                 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
2728
2729                 data[0] = 0x3F;
2730                 data[1] = 0xFF;
2731                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2732
2733                 /* Set SLV-T Bank : 0x24 */
2734                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
2735                 data[0] = 0x0B;
2736                 data[1] = 0x72;
2737                 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
2738
2739                 data[0] = 0x93;
2740                 data[1] = 0xF3;
2741                 data[2] = 0x00;
2742                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
2743
2744                 data[0] = 0x05;
2745                 data[1] = 0xB8;
2746                 data[2] = 0xD8;
2747                 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
2748
2749                 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
2750
2751                 /* Set SLV-T Bank : 0x25 */
2752                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
2753                 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
2754
2755                 /* Set SLV-T Bank : 0x27 */
2756                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2757                 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
2758
2759                 /* Set SLV-T Bank : 0x2B */
2760                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
2761                 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
2762                 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
2763
2764                 /* Set SLV-T Bank : 0x2D */
2765                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
2766                 data[0] = 0x89;
2767                 data[1] = 0x89;
2768                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
2769
2770                 /* Set SLV-T Bank : 0x5E */
2771                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
2772                 data[0] = 0x24;
2773                 data[1] = 0x95;
2774                 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
2775         }
2776
2777         cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2778
2779         /* Set SLV-T Bank : 0x00 */
2780         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2781         /* Disable HiZ Setting 1 */
2782         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2783         /* Disable HiZ Setting 2 */
2784         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2785         priv->state = STATE_ACTIVE_TC;
2786         return 0;
2787 }
2788
2789 /* ISDB-Tb part */
2790 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
2791                 u32 bandwidth)
2792 {
2793         u8 data[2] = { 0x09, 0x54 };
2794         u8 data24m[2] = {0x60, 0x00};
2795         u8 data24m2[3] = {0xB7, 0x1B, 0x00};
2796
2797         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2798         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2799         /* Set SLV-X Bank : 0x00 */
2800         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2801         /* Set demod mode */
2802         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
2803         /* Set SLV-T Bank : 0x00 */
2804         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2805         /* Enable demod clock */
2806         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2807         /* Enable RF level monitor */
2808         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
2809         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
2810         /* Enable ADC clock */
2811         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2812         /* Enable ADC 1 */
2813         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2814         /* xtal freq 20.5MHz or 24M */
2815         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2816         /* Enable ADC 4 */
2817         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2818         /* ASCOT setting ON */
2819         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2820         /* FEC Auto Recovery setting */
2821         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2822         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
2823         /* ISDB-T initial setting */
2824         /* Set SLV-T Bank : 0x00 */
2825         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2826         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
2827         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
2828         /* Set SLV-T Bank : 0x10 */
2829         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2830         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
2831         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
2832         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
2833         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
2834         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
2835         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
2836         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
2837         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
2838         /* Set SLV-T Bank : 0x15 */
2839         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2840         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
2841         /* Set SLV-T Bank : 0x1E */
2842         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
2843         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
2844         /* Set SLV-T Bank : 0x63 */
2845         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
2846         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
2847
2848         /* for xtal 24MHz */
2849         /* Set SLV-T Bank : 0x10 */
2850         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2851         cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
2852         /* Set SLV-T Bank : 0x60 */
2853         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
2854         cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
2855
2856         cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
2857         /* Set SLV-T Bank : 0x00 */
2858         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2859         /* Disable HiZ Setting 1 */
2860         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2861         /* Disable HiZ Setting 2 */
2862         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2863         priv->state = STATE_ACTIVE_TC;
2864         return 0;
2865 }
2866
2867 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
2868                                           u32 bandwidth)
2869 {
2870         u8 data[2] = { 0x09, 0x54 };
2871
2872         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2873         cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
2874         /* Set SLV-X Bank : 0x00 */
2875         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2876         /* Set demod mode */
2877         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
2878         /* Set SLV-T Bank : 0x00 */
2879         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2880         /* Enable demod clock */
2881         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2882         /* Disable RF level monitor */
2883         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2884         /* Enable ADC clock */
2885         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2886         /* Enable ADC 1 */
2887         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2888         /* xtal freq 20.5MHz */
2889         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2890         /* Enable ADC 4 */
2891         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2892         /* Set SLV-T Bank : 0x10 */
2893         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2894         /* IFAGC gain settings */
2895         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
2896         /* Set SLV-T Bank : 0x11 */
2897         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2898         /* BBAGC TARGET level setting */
2899         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
2900         /* Set SLV-T Bank : 0x10 */
2901         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2902         /* ASCOT setting ON */
2903         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2904         /* Set SLV-T Bank : 0x40 */
2905         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2906         /* Demod setting */
2907         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
2908         /* Set SLV-T Bank : 0x00 */
2909         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2910         /* TSIF setting */
2911         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2912         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2913
2914         cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
2915         /* Set SLV-T Bank : 0x00 */
2916         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2917         /* Disable HiZ Setting 1 */
2918         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2919         /* Disable HiZ Setting 2 */
2920         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2921         priv->state = STATE_ACTIVE_TC;
2922         return 0;
2923 }
2924
2925 static int cxd2841er_get_frontend(struct dvb_frontend *fe,
2926                                   struct dtv_frontend_properties *p)
2927 {
2928         enum fe_status status = 0;
2929         u16 strength = 0, snr = 0;
2930         u32 errors = 0, ber = 0;
2931         struct cxd2841er_priv *priv = fe->demodulator_priv;
2932
2933         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2934         if (priv->state == STATE_ACTIVE_S)
2935                 cxd2841er_read_status_s(fe, &status);
2936         else if (priv->state == STATE_ACTIVE_TC)
2937                 cxd2841er_read_status_tc(fe, &status);
2938
2939         if (status & FE_HAS_LOCK) {
2940                 cxd2841er_read_signal_strength(fe, &strength);
2941                 p->strength.len = 1;
2942                 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2943                 p->strength.stat[0].uvalue = strength;
2944                 cxd2841er_read_snr(fe, &snr);
2945                 p->cnr.len = 1;
2946                 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2947                 p->cnr.stat[0].svalue = snr;
2948                 cxd2841er_read_ucblocks(fe, &errors);
2949                 p->block_error.len = 1;
2950                 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2951                 p->block_error.stat[0].uvalue = errors;
2952                 cxd2841er_read_ber(fe, &ber);
2953                 p->post_bit_error.len = 1;
2954                 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
2955                 p->post_bit_error.stat[0].uvalue = ber;
2956         } else {
2957                 p->strength.len = 1;
2958                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2959                 p->cnr.len = 1;
2960                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2961                 p->block_error.len = 1;
2962                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2963                 p->post_bit_error.len = 1;
2964                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2965         }
2966         return 0;
2967 }
2968
2969 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
2970 {
2971         int ret = 0, i, timeout, carr_offset;
2972         enum fe_status status;
2973         struct cxd2841er_priv *priv = fe->demodulator_priv;
2974         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2975         u32 symbol_rate = p->symbol_rate/1000;
2976
2977         dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
2978                 __func__,
2979                 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
2980                  p->frequency, symbol_rate, priv->xtal);
2981         switch (priv->state) {
2982         case STATE_SLEEP_S:
2983                 ret = cxd2841er_sleep_s_to_active_s(
2984                         priv, p->delivery_system, symbol_rate);
2985                 break;
2986         case STATE_ACTIVE_S:
2987                 ret = cxd2841er_retune_active(priv, p);
2988                 break;
2989         default:
2990                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2991                         __func__, priv->state);
2992                 ret = -EINVAL;
2993                 goto done;
2994         }
2995         if (ret) {
2996                 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
2997                 goto done;
2998         }
2999         if (fe->ops.i2c_gate_ctrl)
3000                 fe->ops.i2c_gate_ctrl(fe, 1);
3001         if (fe->ops.tuner_ops.set_params)
3002                 fe->ops.tuner_ops.set_params(fe);
3003         if (fe->ops.i2c_gate_ctrl)
3004                 fe->ops.i2c_gate_ctrl(fe, 0);
3005         cxd2841er_tune_done(priv);
3006         timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3007         for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
3008                 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3009                         (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3010                 cxd2841er_read_status_s(fe, &status);
3011                 if (status & FE_HAS_LOCK)
3012                         break;
3013         }
3014         if (status & FE_HAS_LOCK) {
3015                 if (cxd2841er_get_carrier_offset_s_s2(
3016                                 priv, &carr_offset)) {
3017                         ret = -EINVAL;
3018                         goto done;
3019                 }
3020                 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3021                         __func__, carr_offset);
3022         }
3023 done:
3024         return ret;
3025 }
3026
3027 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3028 {
3029         int ret = 0, timeout;
3030         enum fe_status status;
3031         struct cxd2841er_priv *priv = fe->demodulator_priv;
3032         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3033
3034         dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3035                  __func__, p->delivery_system, p->bandwidth_hz);
3036         if (p->delivery_system == SYS_DVBT) {
3037                 priv->system = SYS_DVBT;
3038                 switch (priv->state) {
3039                 case STATE_SLEEP_TC:
3040                         ret = cxd2841er_sleep_tc_to_active_t(
3041                                 priv, p->bandwidth_hz);
3042                         break;
3043                 case STATE_ACTIVE_TC:
3044                         ret = cxd2841er_retune_active(priv, p);
3045                         break;
3046                 default:
3047                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3048                                 __func__, priv->state);
3049                         ret = -EINVAL;
3050                 }
3051         } else if (p->delivery_system == SYS_DVBT2) {
3052                 priv->system = SYS_DVBT2;
3053                 cxd2841er_dvbt2_set_plp_config(priv,
3054                         (int)(p->stream_id > 255), p->stream_id);
3055                 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3056                 switch (priv->state) {
3057                 case STATE_SLEEP_TC:
3058                         ret = cxd2841er_sleep_tc_to_active_t2(priv,
3059                                 p->bandwidth_hz);
3060                         break;
3061                 case STATE_ACTIVE_TC:
3062                         ret = cxd2841er_retune_active(priv, p);
3063                         break;
3064                 default:
3065                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3066                                 __func__, priv->state);
3067                         ret = -EINVAL;
3068                 }
3069         } else if (p->delivery_system == SYS_ISDBT) {
3070                 priv->system = SYS_ISDBT;
3071                 switch (priv->state) {
3072                 case STATE_SLEEP_TC:
3073                         ret = cxd2841er_sleep_tc_to_active_i(
3074                                         priv, p->bandwidth_hz);
3075                         break;
3076                 case STATE_ACTIVE_TC:
3077                         ret = cxd2841er_retune_active(priv, p);
3078                         break;
3079                 default:
3080                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3081                                         __func__, priv->state);
3082                         ret = -EINVAL;
3083                 }
3084         } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3085                         p->delivery_system == SYS_DVBC_ANNEX_C) {
3086                 priv->system = SYS_DVBC_ANNEX_A;
3087                 /* correct bandwidth */
3088                 if (p->bandwidth_hz != 6000000 &&
3089                                 p->bandwidth_hz != 7000000 &&
3090                                 p->bandwidth_hz != 8000000) {
3091                         p->bandwidth_hz = 8000000;
3092                         dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3093                                         __func__, p->bandwidth_hz);
3094                 }
3095
3096                 switch (priv->state) {
3097                 case STATE_SLEEP_TC:
3098                         ret = cxd2841er_sleep_tc_to_active_c(
3099                                 priv, p->bandwidth_hz);
3100                         break;
3101                 case STATE_ACTIVE_TC:
3102                         ret = cxd2841er_retune_active(priv, p);
3103                         break;
3104                 default:
3105                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3106                                 __func__, priv->state);
3107                         ret = -EINVAL;
3108                 }
3109         } else {
3110                 dev_dbg(&priv->i2c->dev,
3111                         "%s(): invalid delivery system %d\n",
3112                         __func__, p->delivery_system);
3113                 ret = -EINVAL;
3114         }
3115         if (ret)
3116                 goto done;
3117         if (fe->ops.i2c_gate_ctrl)
3118                 fe->ops.i2c_gate_ctrl(fe, 1);
3119         if (fe->ops.tuner_ops.set_params)
3120                 fe->ops.tuner_ops.set_params(fe);
3121         if (fe->ops.i2c_gate_ctrl)
3122                 fe->ops.i2c_gate_ctrl(fe, 0);
3123         cxd2841er_tune_done(priv);
3124         timeout = 2500;
3125         while (timeout > 0) {
3126                 ret = cxd2841er_read_status_tc(fe, &status);
3127                 if (ret)
3128                         goto done;
3129                 if (status & FE_HAS_LOCK)
3130                         break;
3131                 msleep(20);
3132                 timeout -= 20;
3133         }
3134         if (timeout < 0)
3135                 dev_dbg(&priv->i2c->dev,
3136                         "%s(): LOCK wait timeout\n", __func__);
3137 done:
3138         return ret;
3139 }
3140
3141 static int cxd2841er_tune_s(struct dvb_frontend *fe,
3142                             bool re_tune,
3143                             unsigned int mode_flags,
3144                             unsigned int *delay,
3145                             enum fe_status *status)
3146 {
3147         int ret, carrier_offset;
3148         struct cxd2841er_priv *priv = fe->demodulator_priv;
3149         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3150
3151         dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3152         if (re_tune) {
3153                 ret = cxd2841er_set_frontend_s(fe);
3154                 if (ret)
3155                         return ret;
3156                 cxd2841er_read_status_s(fe, status);
3157                 if (*status & FE_HAS_LOCK) {
3158                         if (cxd2841er_get_carrier_offset_s_s2(
3159                                         priv, &carrier_offset))
3160                                 return -EINVAL;
3161                         p->frequency += carrier_offset;
3162                         ret = cxd2841er_set_frontend_s(fe);
3163                         if (ret)
3164                                 return ret;
3165                 }
3166         }
3167         *delay = HZ / 5;
3168         return cxd2841er_read_status_s(fe, status);
3169 }
3170
3171 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3172                              bool re_tune,
3173                              unsigned int mode_flags,
3174                              unsigned int *delay,
3175                              enum fe_status *status)
3176 {
3177         int ret, carrier_offset;
3178         struct cxd2841er_priv *priv = fe->demodulator_priv;
3179         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3180
3181         dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3182                         re_tune, p->bandwidth_hz);
3183         if (re_tune) {
3184                 ret = cxd2841er_set_frontend_tc(fe);
3185                 if (ret)
3186                         return ret;
3187                 cxd2841er_read_status_tc(fe, status);
3188                 if (*status & FE_HAS_LOCK) {
3189                         switch (priv->system) {
3190                         case SYS_ISDBT:
3191                                 ret = cxd2841er_get_carrier_offset_i(
3192                                                 priv, p->bandwidth_hz,
3193                                                 &carrier_offset);
3194                                 break;
3195                         case SYS_DVBT:
3196                                 ret = cxd2841er_get_carrier_offset_t(
3197                                         priv, p->bandwidth_hz,
3198                                         &carrier_offset);
3199                                 break;
3200                         case SYS_DVBT2:
3201                                 ret = cxd2841er_get_carrier_offset_t2(
3202                                         priv, p->bandwidth_hz,
3203                                         &carrier_offset);
3204                                 break;
3205                         case SYS_DVBC_ANNEX_A:
3206                                 ret = cxd2841er_get_carrier_offset_c(
3207                                         priv, &carrier_offset);
3208                                 break;
3209                         default:
3210                                 dev_dbg(&priv->i2c->dev,
3211                                         "%s(): invalid delivery system %d\n",
3212                                         __func__, priv->system);
3213                                 return -EINVAL;
3214                         }
3215                         if (ret)
3216                                 return ret;
3217                         dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3218                                 __func__, carrier_offset);
3219                         p->frequency += carrier_offset;
3220                         ret = cxd2841er_set_frontend_tc(fe);
3221                         if (ret)
3222                                 return ret;
3223                 }
3224         }
3225         *delay = HZ / 5;
3226         return cxd2841er_read_status_tc(fe, status);
3227 }
3228
3229 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3230 {
3231         struct cxd2841er_priv *priv = fe->demodulator_priv;
3232
3233         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3234         cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3235         cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3236         return 0;
3237 }
3238
3239 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3240 {
3241         struct cxd2841er_priv *priv = fe->demodulator_priv;
3242
3243         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3244         if (priv->state == STATE_ACTIVE_TC) {
3245                 switch (priv->system) {
3246                 case SYS_DVBT:
3247                         cxd2841er_active_t_to_sleep_tc(priv);
3248                         break;
3249                 case SYS_DVBT2:
3250                         cxd2841er_active_t2_to_sleep_tc(priv);
3251                         break;
3252                 case SYS_ISDBT:
3253                         cxd2841er_active_i_to_sleep_tc(priv);
3254                         break;
3255                 case SYS_DVBC_ANNEX_A:
3256                         cxd2841er_active_c_to_sleep_tc(priv);
3257                         break;
3258                 default:
3259                         dev_warn(&priv->i2c->dev,
3260                                 "%s(): unknown delivery system %d\n",
3261                                 __func__, priv->system);
3262                 }
3263         }
3264         if (priv->state != STATE_SLEEP_TC) {
3265                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3266                         __func__, priv->state);
3267                 return -EINVAL;
3268         }
3269         cxd2841er_sleep_tc_to_shutdown(priv);
3270         return 0;
3271 }
3272
3273 static int cxd2841er_send_burst(struct dvb_frontend *fe,
3274                                 enum fe_sec_mini_cmd burst)
3275 {
3276         u8 data;
3277         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3278
3279         dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3280                 (burst == SEC_MINI_A ? "A" : "B"));
3281         if (priv->state != STATE_SLEEP_S &&
3282                         priv->state != STATE_ACTIVE_S) {
3283                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3284                         __func__, priv->state);
3285                 return -EINVAL;
3286         }
3287         data = (burst == SEC_MINI_A ? 0 : 1);
3288         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3289         cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3290         cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3291         return 0;
3292 }
3293
3294 static int cxd2841er_set_tone(struct dvb_frontend *fe,
3295                               enum fe_sec_tone_mode tone)
3296 {
3297         u8 data;
3298         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3299
3300         dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3301                 (tone == SEC_TONE_ON ? "On" : "Off"));
3302         if (priv->state != STATE_SLEEP_S &&
3303                         priv->state != STATE_ACTIVE_S) {
3304                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3305                         __func__, priv->state);
3306                 return -EINVAL;
3307         }
3308         data = (tone == SEC_TONE_ON ? 1 : 0);
3309         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3310         cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3311         return 0;
3312 }
3313
3314 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3315                                      struct dvb_diseqc_master_cmd *cmd)
3316 {
3317         int i;
3318         u8 data[12];
3319         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3320
3321         if (priv->state != STATE_SLEEP_S &&
3322                         priv->state != STATE_ACTIVE_S) {
3323                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3324                         __func__, priv->state);
3325                 return -EINVAL;
3326         }
3327         dev_dbg(&priv->i2c->dev,
3328                 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3329         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3330         /* DiDEqC enable */
3331         cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3332         /* cmd1 length & data */
3333         cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3334         memset(data, 0, sizeof(data));
3335         for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3336                 data[i] = cmd->msg[i];
3337         cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3338         /* repeat count for cmd1 */
3339         cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3340         /* repeat count for cmd2: always 0 */
3341         cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3342         /* start transmit */
3343         cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3344         /* wait for 1 sec timeout */
3345         for (i = 0; i < 50; i++) {
3346                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3347                 if (!data[0]) {
3348                         dev_dbg(&priv->i2c->dev,
3349                                 "%s(): DiSEqC cmd has been sent\n", __func__);
3350                         return 0;
3351                 }
3352                 msleep(20);
3353         }
3354         dev_dbg(&priv->i2c->dev,
3355                 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3356         return -ETIMEDOUT;
3357 }
3358
3359 static void cxd2841er_release(struct dvb_frontend *fe)
3360 {
3361         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3362
3363         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3364         kfree(priv);
3365 }
3366
3367 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3368 {
3369         struct cxd2841er_priv *priv = fe->demodulator_priv;
3370
3371         dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3372         cxd2841er_set_reg_bits(
3373                 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3374         return 0;
3375 }
3376
3377 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3378 {
3379         struct cxd2841er_priv *priv = fe->demodulator_priv;
3380
3381         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3382         return DVBFE_ALGO_HW;
3383 }
3384
3385 static int cxd2841er_init_s(struct dvb_frontend *fe)
3386 {
3387         struct cxd2841er_priv *priv = fe->demodulator_priv;
3388
3389         /* sanity. force demod to SHUTDOWN state */
3390         if (priv->state == STATE_SLEEP_S) {
3391                 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3392                                 __func__);
3393                 cxd2841er_sleep_s_to_shutdown(priv);
3394         } else if (priv->state == STATE_ACTIVE_S) {
3395                 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3396                                 __func__);
3397                 cxd2841er_active_s_to_sleep_s(priv);
3398                 cxd2841er_sleep_s_to_shutdown(priv);
3399         }
3400
3401         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3402         cxd2841er_shutdown_to_sleep_s(priv);
3403         /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3404         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3405         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3406         return 0;
3407 }
3408
3409 static int cxd2841er_init_tc(struct dvb_frontend *fe)
3410 {
3411         struct cxd2841er_priv *priv = fe->demodulator_priv;
3412         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3413
3414         dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3415                         __func__, p->bandwidth_hz);
3416         cxd2841er_shutdown_to_sleep_tc(priv);
3417         /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3418         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3419         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3420         /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3421         cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3422         /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3423         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3424         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
3425         return 0;
3426 }
3427
3428 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3429 static struct dvb_frontend_ops cxd2841er_t_c_ops;
3430
3431 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3432                                              struct i2c_adapter *i2c,
3433                                              u8 system)
3434 {
3435         u8 chip_id = 0;
3436         const char *type;
3437         const char *name;
3438         struct cxd2841er_priv *priv = NULL;
3439
3440         /* allocate memory for the internal state */
3441         priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3442         if (!priv)
3443                 return NULL;
3444         priv->i2c = i2c;
3445         priv->config = cfg;
3446         priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3447         priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
3448         priv->xtal = cfg->xtal;
3449         priv->frontend.demodulator_priv = priv;
3450         dev_info(&priv->i2c->dev,
3451                 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3452                 __func__, priv->i2c,
3453                 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3454         chip_id = cxd2841er_chip_id(priv);
3455         switch (chip_id) {
3456         case CXD2841ER_CHIP_ID:
3457                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3458                                 "Sony CXD2841ER DVB-T/T2/C demodulator");
3459                 name = "CXD2841ER";
3460                 break;
3461         case CXD2854ER_CHIP_ID:
3462                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3463                                 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3464                 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3465                 name = "CXD2854ER";
3466                 break;
3467         default:
3468                 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3469                                 __func__, chip_id);
3470                 priv->frontend.demodulator_priv = NULL;
3471                 kfree(priv);
3472                 return NULL;
3473         }
3474
3475         /* create dvb_frontend */
3476         if (system == SYS_DVBS) {
3477                 memcpy(&priv->frontend.ops,
3478                         &cxd2841er_dvbs_s2_ops,
3479                         sizeof(struct dvb_frontend_ops));
3480                 type = "S/S2";
3481         } else {
3482                 memcpy(&priv->frontend.ops,
3483                         &cxd2841er_t_c_ops,
3484                         sizeof(struct dvb_frontend_ops));
3485                 type = "T/T2/C/ISDB-T";
3486         }
3487
3488         dev_info(&priv->i2c->dev,
3489                 "%s(): attaching %s DVB-%s frontend\n",
3490                 __func__, name, type);
3491         dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3492                 __func__, chip_id);
3493         return &priv->frontend;
3494 }
3495
3496 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3497                                         struct i2c_adapter *i2c)
3498 {
3499         return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3500 }
3501 EXPORT_SYMBOL(cxd2841er_attach_s);
3502
3503 struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
3504                                         struct i2c_adapter *i2c)
3505 {
3506         return cxd2841er_attach(cfg, i2c, 0);
3507 }
3508 EXPORT_SYMBOL(cxd2841er_attach_t_c);
3509
3510 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3511         .delsys = { SYS_DVBS, SYS_DVBS2 },
3512         .info = {
3513                 .name           = "Sony CXD2841ER DVB-S/S2 demodulator",
3514                 .frequency_min  = 500000,
3515                 .frequency_max  = 2500000,
3516                 .frequency_stepsize     = 0,
3517                 .symbol_rate_min = 1000000,
3518                 .symbol_rate_max = 45000000,
3519                 .symbol_rate_tolerance = 500,
3520                 .caps = FE_CAN_INVERSION_AUTO |
3521                         FE_CAN_FEC_AUTO |
3522                         FE_CAN_QPSK,
3523         },
3524         .init = cxd2841er_init_s,
3525         .sleep = cxd2841er_sleep_s,
3526         .release = cxd2841er_release,
3527         .set_frontend = cxd2841er_set_frontend_s,
3528         .get_frontend = cxd2841er_get_frontend,
3529         .read_status = cxd2841er_read_status_s,
3530         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3531         .get_frontend_algo = cxd2841er_get_algo,
3532         .set_tone = cxd2841er_set_tone,
3533         .diseqc_send_burst = cxd2841er_send_burst,
3534         .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3535         .tune = cxd2841er_tune_s
3536 };
3537
3538 static struct  dvb_frontend_ops cxd2841er_t_c_ops = {
3539         .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
3540         .info = {
3541                 .name   = "", /* will set in attach function */
3542                 .caps = FE_CAN_FEC_1_2 |
3543                         FE_CAN_FEC_2_3 |
3544                         FE_CAN_FEC_3_4 |
3545                         FE_CAN_FEC_5_6 |
3546                         FE_CAN_FEC_7_8 |
3547                         FE_CAN_FEC_AUTO |
3548                         FE_CAN_QPSK |
3549                         FE_CAN_QAM_16 |
3550                         FE_CAN_QAM_32 |
3551                         FE_CAN_QAM_64 |
3552                         FE_CAN_QAM_128 |
3553                         FE_CAN_QAM_256 |
3554                         FE_CAN_QAM_AUTO |
3555                         FE_CAN_TRANSMISSION_MODE_AUTO |
3556                         FE_CAN_GUARD_INTERVAL_AUTO |
3557                         FE_CAN_HIERARCHY_AUTO |
3558                         FE_CAN_MUTE_TS |
3559                         FE_CAN_2G_MODULATION,
3560                 .frequency_min = 42000000,
3561                 .frequency_max = 1002000000
3562         },
3563         .init = cxd2841er_init_tc,
3564         .sleep = cxd2841er_sleep_tc,
3565         .release = cxd2841er_release,
3566         .set_frontend = cxd2841er_set_frontend_tc,
3567         .get_frontend = cxd2841er_get_frontend,
3568         .read_status = cxd2841er_read_status_tc,
3569         .tune = cxd2841er_tune_tc,
3570         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3571         .get_frontend_algo = cxd2841er_get_algo
3572 };
3573
3574 MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3575 MODULE_AUTHOR("Sergey Kozlov <[email protected]>, Abylay Ospan <[email protected]>");
3576 MODULE_LICENSE("GPL");