drivers/media/dvb-frontends/cxd2841er.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * cxd2841er.c
   4  *
   5  * Sony digital demodulator driver for
   6  *      CXD2841ER - DVB-S/S2/T/T2/C/C2
   7  *      CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
   8  *
   9  * Copyright 2012 Sony Corporation
  10  * Copyright (C) 2014 NetUP Inc.
  11  * Copyright (C) 2014 Sergey Kozlov <[email protected]>
  12  * Copyright (C) 2014 Abylay Ospan <[email protected]>
  13   */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/string.h>
  18 #include <linux/slab.h>
  19 #include <linux/bitops.h>
  20 #include <linux/math64.h>
  21 #include <linux/log2.h>
  22 #include <linux/dynamic_debug.h>
  23 #include <linux/kernel.h>
  24
  25 #include <linux/int_log.h>
  26 #include <media/dvb_frontend.h>
  27 #include "cxd2841er.h"
  28 #include "cxd2841er_priv.h"
  29
  30 #define MAX_WRITE_REGSIZE       16
  31 #define LOG2_E_100X 144
  32
  33 #define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24))
  34
  35 /* DVB-C constellation */
  36 enum sony_dvbc_constellation_t {
  37         SONY_DVBC_CONSTELLATION_16QAM,
  38         SONY_DVBC_CONSTELLATION_32QAM,
  39         SONY_DVBC_CONSTELLATION_64QAM,
  40         SONY_DVBC_CONSTELLATION_128QAM,
  41         SONY_DVBC_CONSTELLATION_256QAM
  42 };
  43
  44 enum cxd2841er_state {
  45         STATE_SHUTDOWN = 0,
  46         STATE_SLEEP_S,
  47         STATE_ACTIVE_S,
  48         STATE_SLEEP_TC,
  49         STATE_ACTIVE_TC
  50 };
  51
  52 struct cxd2841er_priv {
  53         struct dvb_frontend             frontend;
  54         struct i2c_adapter              *i2c;
  55         u8                              i2c_addr_slvx;
  56         u8                              i2c_addr_slvt;
  57         const struct cxd2841er_config   *config;
  58         enum cxd2841er_state            state;
  59         u8                              system;
  60         enum cxd2841er_xtal             xtal;
  61         enum fe_caps caps;
  62         u32                             flags;
  63         unsigned long                   stats_time;
  64 };
  65
  66 static const struct cxd2841er_cnr_data s_cn_data[] = {
  67         { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
  68         { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
  69         { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
  70         { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
  71         { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
  72         { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
  73         { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
  74         { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
  75         { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
  76         { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
  77         { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
  78         { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
  79         { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
  80         { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
  81         { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
  82         { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
  83         { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
  84         { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
  85         { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
  86         { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
  87         { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
  88         { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
  89         { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
  90         { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
  91         { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
  92         { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
  93         { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
  94         { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
  95         { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
  96         { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
  97         { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
  98         { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
  99         { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
 100         { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
 101         { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
 102         { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
 103         { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
 104         { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
 105         { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
 106         { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
 107         { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
 108         { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
 109         { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
 110         { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
 111         { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
 112         { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
 113         { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
 114         { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 115         { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 116         { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
 117         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 118         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 119         { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
 120         { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
 121         { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
 122         { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
 123         { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
 124         { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
 125         { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
 126         { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
 127         { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
 128         { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
 129         { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
 130         { 0x0015, 19900 }, { 0x0014, 20000 },
 131 };
 132
 133 static const struct cxd2841er_cnr_data s2_cn_data[] = {
 134         { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
 135         { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
 136         { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
 137         { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
 138         { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
 139         { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
 140         { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
 141         { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
 142         { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
 143         { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
 144         { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
 145         { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
 146         { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
 147         { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
 148         { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
 149         { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
 150         { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
 151         { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
 152         { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
 153         { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
 154         { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
 155         { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
 156         { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
 157         { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
 158         { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
 159         { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
 160         { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
 161         { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
 162         { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
 163         { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
 164         { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
 165         { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
 166         { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
 167         { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
 168         { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
 169         { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
 170         { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
 171         { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
 172         { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
 173         { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
 174         { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
 175         { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
 176         { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
 177         { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
 178         { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
 179         { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
 180         { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
 181         { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 182         { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 183         { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
 184         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 185         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 186         { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
 187         { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
 188         { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
 189         { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
 190         { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
 191         { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
 192         { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
 193         { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
 194         { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
 195         { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
 196         { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
 197         { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
 198 };
 199
 200 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv);
 201 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv);
 202
 203 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
 204                                 u8 addr, u8 reg, u8 write,
 205                                 const u8 *data, u32 len)
 206 {
 207         dev_dbg(&priv->i2c->dev,
 208                 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d data %*ph\n",
 209                 (write == 0 ? "read" : "write"), addr, reg, len, len, data);
 210 }
 211
 212 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
 213                                 u8 addr, u8 reg, const u8 *data, u32 len)
 214 {
 215         int ret;
 216         u8 buf[MAX_WRITE_REGSIZE + 1];
 217         u8 i2c_addr = (addr == I2C_SLVX ?
 218                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 219         struct i2c_msg msg[1] = {
 220                 {
 221                         .addr = i2c_addr,
 222                         .flags = 0,
 223                         .len = len + 1,
 224                         .buf = buf,
 225                 }
 226         };
 227
 228         if (len + 1 >= sizeof(buf)) {
 229                 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
 230                          reg, len + 1);
 231                 return -E2BIG;
 232         }
 233
 234         cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
 235         buf[0] = reg;
 236         memcpy(&buf[1], data, len);
 237
 238         ret = i2c_transfer(priv->i2c, msg, 1);
 239         if (ret >= 0 && ret != 1)
 240                 ret = -EIO;
 241         if (ret < 0) {
 242                 dev_warn(&priv->i2c->dev,
 243                         "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
 244                         KBUILD_MODNAME, ret, i2c_addr, reg, len);
 245                 return ret;
 246         }
 247         return 0;
 248 }
 249
 250 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
 251                                u8 addr, u8 reg, u8 val)
 252 {
 253         u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
 254
 255         return cxd2841er_write_regs(priv, addr, reg, &tmp, 1);
 256 }
 257
 258 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
 259                                u8 addr, u8 reg, u8 *val, u32 len)
 260 {
 261         int ret;
 262         u8 i2c_addr = (addr == I2C_SLVX ?
 263                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 264         struct i2c_msg msg[2] = {
 265                 {
 266                         .addr = i2c_addr,
 267                         .flags = 0,
 268                         .len = 1,
 269                         .buf = &reg,
 270                 }, {
 271                         .addr = i2c_addr,
 272                         .flags = I2C_M_RD,
 273                         .len = len,
 274                         .buf = val,
 275                 }
 276         };
 277
 278         ret = i2c_transfer(priv->i2c, msg, 2);
 279         if (ret >= 0 && ret != 2)
 280                 ret = -EIO;
 281         if (ret < 0) {
 282                 dev_warn(&priv->i2c->dev,
 283                         "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
 284                         KBUILD_MODNAME, ret, i2c_addr, reg);
 285                 return ret;
 286         }
 287         cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
 288         return 0;
 289 }
 290
 291 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
 292                               u8 addr, u8 reg, u8 *val)
 293 {
 294         return cxd2841er_read_regs(priv, addr, reg, val, 1);
 295 }
 296
 297 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
 298                                   u8 addr, u8 reg, u8 data, u8 mask)
 299 {
 300         int res;
 301         u8 rdata;
 302
 303         if (mask != 0xff) {
 304                 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
 305                 if (res)
 306                         return res;
 307                 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
 308         }
 309         return cxd2841er_write_reg(priv, addr, reg, data);
 310 }
 311
 312 static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz)
 313 {
 314         return div_u64(ifhz * 16777216ull,
 315                        (xtal == SONY_XTAL_24000) ? 48000000 : 41000000);
 316 }
 317
 318 static u32 cxd2841er_calc_iffreq(u32 ifhz)
 319 {
 320         return cxd2841er_calc_iffreq_xtal(SONY_XTAL_20500, ifhz);
 321 }
 322
 323 static int cxd2841er_get_if_hz(struct cxd2841er_priv *priv, u32 def_hz)
 324 {
 325         u32 hz;
 326
 327         if (priv->frontend.ops.tuner_ops.get_if_frequency
 328                         && (priv->flags & CXD2841ER_AUTO_IFHZ))
 329                 priv->frontend.ops.tuner_ops.get_if_frequency(
 330                         &priv->frontend, &hz);
 331         else
 332                 hz = def_hz;
 333
 334         return hz;
 335 }
 336
 337 static int cxd2841er_tuner_set(struct dvb_frontend *fe)
 338 {
 339         struct cxd2841er_priv *priv = fe->demodulator_priv;
 340
 341         if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
 342                 fe->ops.i2c_gate_ctrl(fe, 1);
 343         if (fe->ops.tuner_ops.set_params)
 344                 fe->ops.tuner_ops.set_params(fe);
 345         if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
 346                 fe->ops.i2c_gate_ctrl(fe, 0);
 347
 348         return 0;
 349 }
 350
 351 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
 352                                            u32 symbol_rate)
 353 {
 354         u32 reg_value = 0;
 355         u8 data[3] = {0, 0, 0};
 356
 357         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 358         /*
 359          * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
 360          *          = ((symbolRateKSps * 2^14) + 500) / 1000
 361          *          = ((symbolRateKSps * 16384) + 500) / 1000
 362          */
 363         reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
 364         if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
 365                 dev_err(&priv->i2c->dev,
 366                         "%s(): reg_value is out of range\n", __func__);
 367                 return -EINVAL;
 368         }
 369         data[0] = (u8)((reg_value >> 16) & 0x0F);
 370         data[1] = (u8)((reg_value >>  8) & 0xFF);
 371         data[2] = (u8)(reg_value & 0xFF);
 372         /* Set SLV-T Bank : 0xAE */
 373         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 374         cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
 375         return 0;
 376 }
 377
 378 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 379                                         u8 system);
 380
 381 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
 382                                          u8 system, u32 symbol_rate)
 383 {
 384         int ret;
 385         u8 data[4] = { 0, 0, 0, 0 };
 386
 387         if (priv->state != STATE_SLEEP_S) {
 388                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 389                         __func__, (int)priv->state);
 390                 return -EINVAL;
 391         }
 392         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 393         cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
 394         /* Set demod mode */
 395         if (system == SYS_DVBS) {
 396                 data[0] = 0x0A;
 397         } else if (system == SYS_DVBS2) {
 398                 data[0] = 0x0B;
 399         } else {
 400                 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
 401                         __func__, system);
 402                 return -EINVAL;
 403         }
 404         /* Set SLV-X Bank : 0x00 */
 405         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 406         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
 407         /* DVB-S/S2 */
 408         data[0] = 0x00;
 409         /* Set SLV-T Bank : 0x00 */
 410         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 411         /* Enable S/S2 auto detection 1 */
 412         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
 413         /* Set SLV-T Bank : 0xAE */
 414         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 415         /* Enable S/S2 auto detection 2 */
 416         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
 417         /* Set SLV-T Bank : 0x00 */
 418         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 419         /* Enable demod clock */
 420         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
 421         /* Enable ADC clock */
 422         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
 423         /* Enable ADC 1 */
 424         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 425         /* Enable ADC 2 */
 426         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
 427         /* Set SLV-X Bank : 0x00 */
 428         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 429         /* Enable ADC 3 */
 430         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
 431         /* Set SLV-T Bank : 0xA3 */
 432         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
 433         cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
 434         data[0] = 0x07;
 435         data[1] = 0x3B;
 436         data[2] = 0x08;
 437         data[3] = 0xC5;
 438         /* Set SLV-T Bank : 0xAB */
 439         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
 440         cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
 441         data[0] = 0x05;
 442         data[1] = 0x80;
 443         data[2] = 0x0A;
 444         data[3] = 0x80;
 445         cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
 446         data[0] = 0x0C;
 447         data[1] = 0xCC;
 448         cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
 449         /* Set demod parameter */
 450         ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
 451         if (ret != 0)
 452                 return ret;
 453         /* Set SLV-T Bank : 0x00 */
 454         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 455         /* disable Hi-Z setting 1 */
 456         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
 457         /* disable Hi-Z setting 2 */
 458         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
 459         priv->state = STATE_ACTIVE_S;
 460         return 0;
 461 }
 462
 463 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
 464                                                u32 bandwidth);
 465
 466 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
 467                                                 u32 bandwidth);
 468
 469 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
 470                                                u32 bandwidth);
 471
 472 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
 473                 u32 bandwidth);
 474
 475 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
 476
 477 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
 478
 479 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
 480
 481 static int cxd2841er_sleep_tc(struct dvb_frontend *fe);
 482
 483 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
 484                                    struct dtv_frontend_properties *p)
 485 {
 486         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 487         if (priv->state != STATE_ACTIVE_S &&
 488                         priv->state != STATE_ACTIVE_TC) {
 489                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
 490                         __func__, priv->state);
 491                 return -EINVAL;
 492         }
 493         /* Set SLV-T Bank : 0x00 */
 494         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 495         /* disable TS output */
 496         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 497         if (priv->state == STATE_ACTIVE_S)
 498                 return cxd2841er_dvbs2_set_symbol_rate(
 499                                 priv, p->symbol_rate / 1000);
 500         else if (priv->state == STATE_ACTIVE_TC) {
 501                 switch (priv->system) {
 502                 case SYS_DVBT:
 503                         return cxd2841er_sleep_tc_to_active_t_band(
 504                                         priv, p->bandwidth_hz);
 505                 case SYS_DVBT2:
 506                         return cxd2841er_sleep_tc_to_active_t2_band(
 507                                         priv, p->bandwidth_hz);
 508                 case SYS_DVBC_ANNEX_A:
 509                         return cxd2841er_sleep_tc_to_active_c_band(
 510                                         priv, p->bandwidth_hz);
 511                 case SYS_ISDBT:
 512                         cxd2841er_active_i_to_sleep_tc(priv);
 513                         cxd2841er_sleep_tc_to_shutdown(priv);
 514                         cxd2841er_shutdown_to_sleep_tc(priv);
 515                         return cxd2841er_sleep_tc_to_active_i(
 516                                         priv, p->bandwidth_hz);
 517                 }
 518         }
 519         dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
 520                 __func__, priv->system);
 521         return -EINVAL;
 522 }
 523
 524 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
 525 {
 526         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 527         if (priv->state != STATE_ACTIVE_S) {
 528                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 529                         __func__, priv->state);
 530                 return -EINVAL;
 531         }
 532         /* Set SLV-T Bank : 0x00 */
 533         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 534         /* disable TS output */
 535         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 536         /* enable Hi-Z setting 1 */
 537         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
 538         /* enable Hi-Z setting 2 */
 539         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 540         /* Set SLV-X Bank : 0x00 */
 541         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 542         /* disable ADC 1 */
 543         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 544         /* Set SLV-T Bank : 0x00 */
 545         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 546         /* disable ADC clock */
 547         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
 548         /* disable ADC 2 */
 549         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 550         /* disable ADC 3 */
 551         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 552         /* SADC Bias ON */
 553         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 554         /* disable demod clock */
 555         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 556         /* Set SLV-T Bank : 0xAE */
 557         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 558         /* disable S/S2 auto detection1 */
 559         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 560         /* Set SLV-T Bank : 0x00 */
 561         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 562         /* disable S/S2 auto detection2 */
 563         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
 564         priv->state = STATE_SLEEP_S;
 565         return 0;
 566 }
 567
 568 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
 569 {
 570         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 571         if (priv->state != STATE_SLEEP_S) {
 572                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 573                         __func__, priv->state);
 574                 return -EINVAL;
 575         }
 576         /* Set SLV-T Bank : 0x00 */
 577         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 578         /* Disable DSQOUT */
 579         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 580         /* Disable DSQIN */
 581         cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
 582         /* Set SLV-X Bank : 0x00 */
 583         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 584         /* Disable oscillator */
 585         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 586         /* Set demod mode */
 587         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 588         priv->state = STATE_SHUTDOWN;
 589         return 0;
 590 }
 591
 592 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
 593 {
 594         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 595         if (priv->state != STATE_SLEEP_TC) {
 596                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 597                         __func__, priv->state);
 598                 return -EINVAL;
 599         }
 600         /* Set SLV-X Bank : 0x00 */
 601         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 602         /* Disable oscillator */
 603         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 604         /* Set demod mode */
 605         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 606         priv->state = STATE_SHUTDOWN;
 607         return 0;
 608 }
 609
 610 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
 611 {
 612         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 613         if (priv->state != STATE_ACTIVE_TC) {
 614                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 615                         __func__, priv->state);
 616                 return -EINVAL;
 617         }
 618         /* Set SLV-T Bank : 0x00 */
 619         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 620         /* disable TS output */
 621         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 622         /* enable Hi-Z setting 1 */
 623         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 624         /* enable Hi-Z setting 2 */
 625         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 626         /* Set SLV-X Bank : 0x00 */
 627         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 628         /* disable ADC 1 */
 629         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 630         /* Set SLV-T Bank : 0x00 */
 631         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 632         /* Disable ADC 2 */
 633         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 634         /* Disable ADC 3 */
 635         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 636         /* Disable ADC clock */
 637         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 638         /* Disable RF level monitor */
 639         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 640         /* Disable demod clock */
 641         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 642         priv->state = STATE_SLEEP_TC;
 643         return 0;
 644 }
 645
 646 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
 647 {
 648         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 649         if (priv->state != STATE_ACTIVE_TC) {
 650                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 651                         __func__, priv->state);
 652                 return -EINVAL;
 653         }
 654         /* Set SLV-T Bank : 0x00 */
 655         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 656         /* disable TS output */
 657         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 658         /* enable Hi-Z setting 1 */
 659         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 660         /* enable Hi-Z setting 2 */
 661         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 662         /* Cancel DVB-T2 setting */
 663         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
 664         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
 665         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
 666         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
 667         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
 668         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
 669         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
 670         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
 671         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
 672         /* Set SLV-X Bank : 0x00 */
 673         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 674         /* disable ADC 1 */
 675         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 676         /* Set SLV-T Bank : 0x00 */
 677         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 678         /* Disable ADC 2 */
 679         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 680         /* Disable ADC 3 */
 681         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 682         /* Disable ADC clock */
 683         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 684         /* Disable RF level monitor */
 685         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 686         /* Disable demod clock */
 687         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 688         priv->state = STATE_SLEEP_TC;
 689         return 0;
 690 }
 691
 692 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
 693 {
 694         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 695         if (priv->state != STATE_ACTIVE_TC) {
 696                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 697                         __func__, priv->state);
 698                 return -EINVAL;
 699         }
 700         /* Set SLV-T Bank : 0x00 */
 701         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 702         /* disable TS output */
 703         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 704         /* enable Hi-Z setting 1 */
 705         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 706         /* enable Hi-Z setting 2 */
 707         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 708         /* Cancel DVB-C setting */
 709         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
 710         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
 711         /* Set SLV-X Bank : 0x00 */
 712         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 713         /* disable ADC 1 */
 714         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 715         /* Set SLV-T Bank : 0x00 */
 716         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 717         /* Disable ADC 2 */
 718         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 719         /* Disable ADC 3 */
 720         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 721         /* Disable ADC clock */
 722         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 723         /* Disable RF level monitor */
 724         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 725         /* Disable demod clock */
 726         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 727         priv->state = STATE_SLEEP_TC;
 728         return 0;
 729 }
 730
 731 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
 732 {
 733         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 734         if (priv->state != STATE_ACTIVE_TC) {
 735                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 736                                 __func__, priv->state);
 737                 return -EINVAL;
 738         }
 739         /* Set SLV-T Bank : 0x00 */
 740         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 741         /* disable TS output */
 742         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 743         /* enable Hi-Z setting 1 */
 744         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 745         /* enable Hi-Z setting 2 */
 746         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 747
 748         /* TODO: Cancel demod parameter */
 749
 750         /* Set SLV-X Bank : 0x00 */
 751         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 752         /* disable ADC 1 */
 753         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 754         /* Set SLV-T Bank : 0x00 */
 755         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 756         /* Disable ADC 2 */
 757         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 758         /* Disable ADC 3 */
 759         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 760         /* Disable ADC clock */
 761         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 762         /* Disable RF level monitor */
 763         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 764         /* Disable demod clock */
 765         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 766         priv->state = STATE_SLEEP_TC;
 767         return 0;
 768 }
 769
 770 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
 771 {
 772         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 773         if (priv->state != STATE_SHUTDOWN) {
 774                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 775                         __func__, priv->state);
 776                 return -EINVAL;
 777         }
 778         /* Set SLV-X Bank : 0x00 */
 779         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 780         /* Clear all demodulator registers */
 781         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 782         usleep_range(3000, 5000);
 783         /* Set SLV-X Bank : 0x00 */
 784         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 785         /* Set demod SW reset */
 786         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 787
 788         switch (priv->xtal) {
 789         case SONY_XTAL_20500:
 790                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
 791                 break;
 792         case SONY_XTAL_24000:
 793                 /* Select demod frequency */
 794                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 795                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
 796                 break;
 797         case SONY_XTAL_41000:
 798                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
 799                 break;
 800         default:
 801                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
 802                                 __func__, priv->xtal);
 803                 return -EINVAL;
 804         }
 805
 806         /* Set demod mode */
 807         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
 808         /* Clear demod SW reset */
 809         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 810         usleep_range(1000, 2000);
 811         /* Set SLV-T Bank : 0x00 */
 812         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 813         /* enable DSQOUT */
 814         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
 815         /* enable DSQIN */
 816         cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
 817         /* TADC Bias On */
 818         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 819         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 820         /* SADC Bias On */
 821         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 822         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 823         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 824         priv->state = STATE_SLEEP_S;
 825         return 0;
 826 }
 827
 828 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
 829 {
 830         u8 data = 0;
 831
 832         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 833         if (priv->state != STATE_SHUTDOWN) {
 834                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 835                         __func__, priv->state);
 836                 return -EINVAL;
 837         }
 838         /* Set SLV-X Bank : 0x00 */
 839         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 840         /* Clear all demodulator registers */
 841         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 842         usleep_range(3000, 5000);
 843         /* Set SLV-X Bank : 0x00 */
 844         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 845         /* Set demod SW reset */
 846         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 847   /* Select ADC clock mode */
 848         cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
 849
 850         switch (priv->xtal) {
 851         case SONY_XTAL_20500:
 852                 data = 0x0;
 853                 break;
 854         case SONY_XTAL_24000:
 855                 /* Select demod frequency */
 856                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 857                 data = 0x3;
 858                 break;
 859         case SONY_XTAL_41000:
 860                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 861                 data = 0x1;
 862                 break;
 863         }
 864         cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
 865         /* Clear demod SW reset */
 866         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 867         usleep_range(1000, 2000);
 868         /* Set SLV-T Bank : 0x00 */
 869         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 870         /* TADC Bias On */
 871         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 872         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 873         /* SADC Bias On */
 874         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 875         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 876         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 877         priv->state = STATE_SLEEP_TC;
 878         return 0;
 879 }
 880
 881 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
 882 {
 883         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 884         /* Set SLV-T Bank : 0x00 */
 885         cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
 886         /* SW Reset */
 887         cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
 888         /* Enable TS output */
 889         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
 890         return 0;
 891 }
 892
 893 /* Set TS parallel mode */
 894 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 895                                         u8 system)
 896 {
 897         u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
 898
 899         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 900         /* Set SLV-T Bank : 0x00 */
 901         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 902         cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
 903         cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
 904         cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
 905         dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
 906                 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
 907
 908         /*
 909          * slave    Bank    Addr    Bit    default    Name
 910          * <SLV-T>  00h     C4h     [1:0]  2'b??      OSERCKMODE
 911          */
 912         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
 913                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
 914         /*
 915          * slave    Bank    Addr    Bit    default    Name
 916          * <SLV-T>  00h     D1h     [1:0]  2'b??      OSERDUTYMODE
 917          */
 918         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd1,
 919                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
 920         /*
 921          * slave    Bank    Addr    Bit    default    Name
 922          * <SLV-T>  00h     D9h     [7:0]  8'h08      OTSCKPERIOD
 923          */
 924         cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
 925         /*
 926          * Disable TS IF Clock
 927          * slave    Bank    Addr    Bit    default    Name
 928          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 929          */
 930         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
 931         /*
 932          * slave    Bank    Addr    Bit    default    Name
 933          * <SLV-T>  00h     33h     [1:0]  2'b01      OREG_CKSEL_TSIF
 934          */
 935         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33,
 936                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
 937         /*
 938          * Enable TS IF Clock
 939          * slave    Bank    Addr    Bit    default    Name
 940          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 941          */
 942         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
 943
 944         if (system == SYS_DVBT) {
 945                 /* Enable parity period for DVB-T */
 946                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 947                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 948         } else if (system == SYS_DVBC_ANNEX_A) {
 949                 /* Enable parity period for DVB-C */
 950                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 951                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 952         }
 953 }
 954
 955 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
 956 {
 957         u8 chip_id = 0;
 958
 959         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 960         if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
 961                 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
 962         else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
 963                 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
 964
 965         return chip_id;
 966 }
 967
 968 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
 969                                    enum fe_status *status)
 970 {
 971         u8 reg = 0;
 972         struct cxd2841er_priv *priv = fe->demodulator_priv;
 973
 974         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 975         *status = 0;
 976         if (priv->state != STATE_ACTIVE_S) {
 977                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 978                         __func__, priv->state);
 979                 return -EINVAL;
 980         }
 981         /* Set SLV-T Bank : 0xA0 */
 982         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
 983         /*
 984          *  slave     Bank      Addr      Bit      Signal name
 985          * <SLV-T>    A0h       11h       [2]      ITSLOCK
 986          */
 987         cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
 988         if (reg & 0x04) {
 989                 *status = FE_HAS_SIGNAL
 990                         | FE_HAS_CARRIER
 991                         | FE_HAS_VITERBI
 992                         | FE_HAS_SYNC
 993                         | FE_HAS_LOCK;
 994         }
 995         dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
 996         return 0;
 997 }
 998
 999 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
1000                                       u8 *sync, u8 *tslock, u8 *unlock)
1001 {
1002         u8 data = 0;
1003
1004         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1005         if (priv->state != STATE_ACTIVE_TC)
1006                 return -EINVAL;
1007         if (priv->system == SYS_DVBT) {
1008                 /* Set SLV-T Bank : 0x10 */
1009                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1010         } else {
1011                 /* Set SLV-T Bank : 0x20 */
1012                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1013         }
1014         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1015         if ((data & 0x07) == 0x07) {
1016                 dev_dbg(&priv->i2c->dev,
1017                         "%s(): invalid hardware state detected\n", __func__);
1018                 *sync = 0;
1019                 *tslock = 0;
1020                 *unlock = 0;
1021         } else {
1022                 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
1023                 *tslock = ((data & 0x20) ? 1 : 0);
1024                 *unlock = ((data & 0x10) ? 1 : 0);
1025         }
1026         return 0;
1027 }
1028
1029 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
1030 {
1031         u8 data;
1032
1033         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1034         if (priv->state != STATE_ACTIVE_TC)
1035                 return -EINVAL;
1036         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1037         cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
1038         if ((data & 0x01) == 0) {
1039                 *tslock = 0;
1040         } else {
1041                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1042                 *tslock = ((data & 0x20) ? 1 : 0);
1043         }
1044         return 0;
1045 }
1046
1047 static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
1048                 u8 *sync, u8 *tslock, u8 *unlock)
1049 {
1050         u8 data = 0;
1051
1052         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1053         if (priv->state != STATE_ACTIVE_TC)
1054                 return -EINVAL;
1055         /* Set SLV-T Bank : 0x60 */
1056         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1057         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1058         dev_dbg(&priv->i2c->dev,
1059                         "%s(): lock=0x%x\n", __func__, data);
1060         *sync = ((data & 0x02) ? 1 : 0);
1061         *tslock = ((data & 0x01) ? 1 : 0);
1062         *unlock = ((data & 0x10) ? 1 : 0);
1063         return 0;
1064 }
1065
1066 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1067                                     enum fe_status *status)
1068 {
1069         int ret = 0;
1070         u8 sync = 0;
1071         u8 tslock = 0;
1072         u8 unlock = 0;
1073         struct cxd2841er_priv *priv = fe->demodulator_priv;
1074
1075         *status = 0;
1076         if (priv->state == STATE_ACTIVE_TC) {
1077                 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1078                         ret = cxd2841er_read_status_t_t2(
1079                                 priv, &sync, &tslock, &unlock);
1080                         if (ret)
1081                                 goto done;
1082                         if (unlock)
1083                                 goto done;
1084                         if (sync)
1085                                 *status = FE_HAS_SIGNAL |
1086                                         FE_HAS_CARRIER |
1087                                         FE_HAS_VITERBI |
1088                                         FE_HAS_SYNC;
1089                         if (tslock)
1090                                 *status |= FE_HAS_LOCK;
1091                 } else if (priv->system == SYS_ISDBT) {
1092                         ret = cxd2841er_read_status_i(
1093                                         priv, &sync, &tslock, &unlock);
1094                         if (ret)
1095                                 goto done;
1096                         if (unlock)
1097                                 goto done;
1098                         if (sync)
1099                                 *status = FE_HAS_SIGNAL |
1100                                         FE_HAS_CARRIER |
1101                                         FE_HAS_VITERBI |
1102                                         FE_HAS_SYNC;
1103                         if (tslock)
1104                                 *status |= FE_HAS_LOCK;
1105                 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1106                         ret = cxd2841er_read_status_c(priv, &tslock);
1107                         if (ret)
1108                                 goto done;
1109                         if (tslock)
1110                                 *status = FE_HAS_SIGNAL |
1111                                         FE_HAS_CARRIER |
1112                                         FE_HAS_VITERBI |
1113                                         FE_HAS_SYNC |
1114                                         FE_HAS_LOCK;
1115                 }
1116         }
1117 done:
1118         dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1119         return ret;
1120 }
1121
1122 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1123                                              int *offset)
1124 {
1125         u8 data[3];
1126         u8 is_hs_mode;
1127         s32 cfrl_ctrlval;
1128         s32 temp_div, temp_q, temp_r;
1129
1130         if (priv->state != STATE_ACTIVE_S) {
1131                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1132                         __func__, priv->state);
1133                 return -EINVAL;
1134         }
1135         /*
1136          * Get High Sampling Rate mode
1137          *  slave     Bank      Addr      Bit      Signal name
1138          * <SLV-T>    A0h       10h       [0]      ITRL_LOCK
1139          */
1140         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1141         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1142         if (data[0] & 0x01) {
1143                 /*
1144                  *  slave     Bank      Addr      Bit      Signal name
1145                  * <SLV-T>    A0h       50h       [4]      IHSMODE
1146                  */
1147                 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1148                 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1149         } else {
1150                 dev_dbg(&priv->i2c->dev,
1151                         "%s(): unable to detect sampling rate mode\n",
1152                         __func__);
1153                 return -EINVAL;
1154         }
1155         /*
1156          *  slave     Bank      Addr      Bit      Signal name
1157          * <SLV-T>    A0h       45h       [4:0]    ICFRL_CTRLVAL[20:16]
1158          * <SLV-T>    A0h       46h       [7:0]    ICFRL_CTRLVAL[15:8]
1159          * <SLV-T>    A0h       47h       [7:0]    ICFRL_CTRLVAL[7:0]
1160          */
1161         cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1162         cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1163                                 (((u32)data[1] & 0xFF) <<  8) |
1164                                 ((u32)data[2] & 0xFF), 20);
1165         temp_div = (is_hs_mode ? 1048576 : 1572864);
1166         if (cfrl_ctrlval > 0) {
1167                 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1168                         temp_div, &temp_r);
1169         } else {
1170                 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1171                         temp_div, &temp_r);
1172         }
1173         if (temp_r >= temp_div / 2)
1174                 temp_q++;
1175         if (cfrl_ctrlval > 0)
1176                 temp_q *= -1;
1177         *offset = temp_q;
1178         return 0;
1179 }
1180
1181 static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1182                                            u32 bandwidth, int *offset)
1183 {
1184         u8 data[4];
1185
1186         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1187         if (priv->state != STATE_ACTIVE_TC) {
1188                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1189                         __func__, priv->state);
1190                 return -EINVAL;
1191         }
1192         if (priv->system != SYS_ISDBT) {
1193                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1194                         __func__, priv->system);
1195                 return -EINVAL;
1196         }
1197         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1198         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1199         *offset = -1 * sign_extend32(
1200                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1201                 ((u32)data[2] << 8) | (u32)data[3], 29);
1202
1203         switch (bandwidth) {
1204         case 6000000:
1205                 *offset = -1 * ((*offset) * 8/264);
1206                 break;
1207         case 7000000:
1208                 *offset = -1 * ((*offset) * 8/231);
1209                 break;
1210         case 8000000:
1211                 *offset = -1 * ((*offset) * 8/198);
1212                 break;
1213         default:
1214                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1215                                 __func__, bandwidth);
1216                 return -EINVAL;
1217         }
1218
1219         dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1220                         __func__, bandwidth, *offset);
1221
1222         return 0;
1223 }
1224
1225 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1226                                            u32 bandwidth, int *offset)
1227 {
1228         u8 data[4];
1229
1230         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1231         if (priv->state != STATE_ACTIVE_TC) {
1232                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1233                         __func__, priv->state);
1234                 return -EINVAL;
1235         }
1236         if (priv->system != SYS_DVBT) {
1237                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1238                         __func__, priv->system);
1239                 return -EINVAL;
1240         }
1241         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1242         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1243         *offset = -1 * sign_extend32(
1244                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1245                 ((u32)data[2] << 8) | (u32)data[3], 29);
1246         *offset *= (bandwidth / 1000000);
1247         *offset /= 235;
1248         return 0;
1249 }
1250
1251 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1252                                            u32 bandwidth, int *offset)
1253 {
1254         u8 data[4];
1255
1256         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1257         if (priv->state != STATE_ACTIVE_TC) {
1258                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1259                         __func__, priv->state);
1260                 return -EINVAL;
1261         }
1262         if (priv->system != SYS_DVBT2) {
1263                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1264                         __func__, priv->system);
1265                 return -EINVAL;
1266         }
1267         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1268         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1269         *offset = -1 * sign_extend32(
1270                 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1271                 ((u32)data[2] << 8) | (u32)data[3], 27);
1272         switch (bandwidth) {
1273         case 1712000:
1274                 *offset /= 582;
1275                 break;
1276         case 5000000:
1277         case 6000000:
1278         case 7000000:
1279         case 8000000:
1280                 *offset *= (bandwidth / 1000000);
1281                 *offset /= 940;
1282                 break;
1283         default:
1284                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1285                         __func__, bandwidth);
1286                 return -EINVAL;
1287         }
1288         return 0;
1289 }
1290
1291 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1292                                           int *offset)
1293 {
1294         u8 data[2];
1295
1296         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1297         if (priv->state != STATE_ACTIVE_TC) {
1298                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1299                         __func__, priv->state);
1300                 return -EINVAL;
1301         }
1302         if (priv->system != SYS_DVBC_ANNEX_A) {
1303                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1304                         __func__, priv->system);
1305                 return -EINVAL;
1306         }
1307         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1308         cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1309         *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1310                                                 | (u32)data[1], 13), 16384);
1311         return 0;
1312 }
1313
1314 static int cxd2841er_read_packet_errors_c(
1315                 struct cxd2841er_priv *priv, u32 *penum)
1316 {
1317         u8 data[3];
1318
1319         *penum = 0;
1320         if (priv->state != STATE_ACTIVE_TC) {
1321                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1322                                 __func__, priv->state);
1323                 return -EINVAL;
1324         }
1325         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1326         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1327         if (data[2] & 0x01)
1328                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1329         return 0;
1330 }
1331
1332 static int cxd2841er_read_packet_errors_t(
1333                 struct cxd2841er_priv *priv, u32 *penum)
1334 {
1335         u8 data[3];
1336
1337         *penum = 0;
1338         if (priv->state != STATE_ACTIVE_TC) {
1339                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1340                         __func__, priv->state);
1341                 return -EINVAL;
1342         }
1343         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1344         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1345         if (data[2] & 0x01)
1346                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1347         return 0;
1348 }
1349
1350 static int cxd2841er_read_packet_errors_t2(
1351                 struct cxd2841er_priv *priv, u32 *penum)
1352 {
1353         u8 data[3];
1354
1355         *penum = 0;
1356         if (priv->state != STATE_ACTIVE_TC) {
1357                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1358                         __func__, priv->state);
1359                 return -EINVAL;
1360         }
1361         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1362         cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1363         if (data[0] & 0x01)
1364                 *penum = ((u32)data[1] << 8) | (u32)data[2];
1365         return 0;
1366 }
1367
1368 static int cxd2841er_read_packet_errors_i(
1369                 struct cxd2841er_priv *priv, u32 *penum)
1370 {
1371         u8 data[2];
1372
1373         *penum = 0;
1374         if (priv->state != STATE_ACTIVE_TC) {
1375                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1376                                 __func__, priv->state);
1377                 return -EINVAL;
1378         }
1379         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1380         cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1381
1382         if (!(data[0] & 0x01))
1383                 return 0;
1384
1385         /* Layer A */
1386         cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1387         *penum = ((u32)data[0] << 8) | (u32)data[1];
1388
1389         /* Layer B */
1390         cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1391         *penum += ((u32)data[0] << 8) | (u32)data[1];
1392
1393         /* Layer C */
1394         cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1395         *penum += ((u32)data[0] << 8) | (u32)data[1];
1396
1397         return 0;
1398 }
1399
1400 static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
1401                 u32 *bit_error, u32 *bit_count)
1402 {
1403         u8 data[3];
1404         u32 bit_err, period_exp;
1405
1406         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1407         if (priv->state != STATE_ACTIVE_TC) {
1408                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1409                                 __func__, priv->state);
1410                 return -EINVAL;
1411         }
1412         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1413         cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
1414         if (!(data[0] & 0x80)) {
1415                 dev_dbg(&priv->i2c->dev,
1416                                 "%s(): no valid BER data\n", __func__);
1417                 return -EINVAL;
1418         }
1419         bit_err = ((u32)(data[0] & 0x3f) << 16) |
1420                 ((u32)data[1] << 8) |
1421                 (u32)data[2];
1422         cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
1423         period_exp = data[0] & 0x1f;
1424
1425         if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
1426                 dev_dbg(&priv->i2c->dev,
1427                                 "%s(): period_exp(%u) or bit_err(%u)  not in range. no valid BER data\n",
1428                                 __func__, period_exp, bit_err);
1429                 return -EINVAL;
1430         }
1431
1432         dev_dbg(&priv->i2c->dev,
1433                         "%s(): period_exp(%u) or bit_err(%u) count=%d\n",
1434                         __func__, period_exp, bit_err,
1435                         ((1 << period_exp) * 204 * 8));
1436
1437         *bit_error = bit_err;
1438         *bit_count = ((1 << period_exp) * 204 * 8);
1439
1440         return 0;
1441 }
1442
1443 static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv,
1444                 u32 *bit_error, u32 *bit_count)
1445 {
1446         u8 data[3];
1447         u8 pktnum[2];
1448
1449         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1450         if (priv->state != STATE_ACTIVE_TC) {
1451                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1452                                 __func__, priv->state);
1453                 return -EINVAL;
1454         }
1455
1456         cxd2841er_freeze_regs(priv);
1457         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1458         cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum));
1459         cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data));
1460         cxd2841er_unfreeze_regs(priv);
1461
1462         if (!pktnum[0] && !pktnum[1]) {
1463                 dev_dbg(&priv->i2c->dev,
1464                                 "%s(): no valid BER data\n", __func__);
1465                 return -EINVAL;
1466         }
1467
1468         *bit_error = ((u32)(data[0] & 0x7F) << 16) |
1469                 ((u32)data[1] << 8) | data[2];
1470         *bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8);
1471         dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n",
1472                         __func__, *bit_error, *bit_count);
1473
1474         return 0;
1475 }
1476
1477 static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
1478                                     u32 *bit_error, u32 *bit_count)
1479 {
1480         u8 data[11];
1481
1482         /* Set SLV-T Bank : 0xA0 */
1483         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1484         /*
1485          *  slave     Bank      Addr      Bit      Signal name
1486          * <SLV-T>    A0h       35h       [0]      IFVBER_VALID
1487          * <SLV-T>    A0h       36h       [5:0]    IFVBER_BITERR[21:16]
1488          * <SLV-T>    A0h       37h       [7:0]    IFVBER_BITERR[15:8]
1489          * <SLV-T>    A0h       38h       [7:0]    IFVBER_BITERR[7:0]
1490          * <SLV-T>    A0h       3Dh       [5:0]    IFVBER_BITNUM[21:16]
1491          * <SLV-T>    A0h       3Eh       [7:0]    IFVBER_BITNUM[15:8]
1492          * <SLV-T>    A0h       3Fh       [7:0]    IFVBER_BITNUM[7:0]
1493          */
1494         cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1495         if (data[0] & 0x01) {
1496                 *bit_error = ((u32)(data[1]  & 0x3F) << 16) |
1497                              ((u32)(data[2]  & 0xFF) <<  8) |
1498                              (u32)(data[3]  & 0xFF);
1499                 *bit_count = ((u32)(data[8]  & 0x3F) << 16) |
1500                              ((u32)(data[9]  & 0xFF) <<  8) |
1501                              (u32)(data[10] & 0xFF);
1502                 if ((*bit_count == 0) || (*bit_error > *bit_count)) {
1503                         dev_dbg(&priv->i2c->dev,
1504                                 "%s(): invalid bit_error %d, bit_count %d\n",
1505                                 __func__, *bit_error, *bit_count);
1506                         return -EINVAL;
1507                 }
1508                 return 0;
1509         }
1510         dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1511         return -EINVAL;
1512 }
1513
1514
1515 static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
1516                                      u32 *bit_error, u32 *bit_count)
1517 {
1518         u8 data[5];
1519         u32 period;
1520
1521         /* Set SLV-T Bank : 0xB2 */
1522         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1523         /*
1524          *  slave     Bank      Addr      Bit      Signal name
1525          * <SLV-T>    B2h       30h       [0]      IFLBER_VALID
1526          * <SLV-T>    B2h       31h       [3:0]    IFLBER_BITERR[27:24]
1527          * <SLV-T>    B2h       32h       [7:0]    IFLBER_BITERR[23:16]
1528          * <SLV-T>    B2h       33h       [7:0]    IFLBER_BITERR[15:8]
1529          * <SLV-T>    B2h       34h       [7:0]    IFLBER_BITERR[7:0]
1530          */
1531         cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1532         if (data[0] & 0x01) {
1533                 /* Bit error count */
1534                 *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1535                              ((u32)(data[2] & 0xFF) << 16) |
1536                              ((u32)(data[3] & 0xFF) <<  8) |
1537                              (u32)(data[4] & 0xFF);
1538
1539                 /* Set SLV-T Bank : 0xA0 */
1540                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1541                 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1542                 /* Measurement period */
1543                 period = (u32)(1 << (data[0] & 0x0F));
1544                 if (period == 0) {
1545                         dev_dbg(&priv->i2c->dev,
1546                                 "%s(): period is 0\n", __func__);
1547                         return -EINVAL;
1548                 }
1549                 if (*bit_error > (period * 64800)) {
1550                         dev_dbg(&priv->i2c->dev,
1551                                 "%s(): invalid bit_err 0x%x period 0x%x\n",
1552                                 __func__, *bit_error, period);
1553                         return -EINVAL;
1554                 }
1555                 *bit_count = period * 64800;
1556
1557                 return 0;
1558         } else {
1559                 dev_dbg(&priv->i2c->dev,
1560                         "%s(): no data available\n", __func__);
1561         }
1562         return -EINVAL;
1563 }
1564
1565 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
1566                                  u32 *bit_error, u32 *bit_count)
1567 {
1568         u8 data[4];
1569         u32 period_exp, n_ldpc;
1570
1571         if (priv->state != STATE_ACTIVE_TC) {
1572                 dev_dbg(&priv->i2c->dev,
1573                         "%s(): invalid state %d\n", __func__, priv->state);
1574                 return -EINVAL;
1575         }
1576         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1577         cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1578         if (!(data[0] & 0x10)) {
1579                 dev_dbg(&priv->i2c->dev,
1580                         "%s(): no valid BER data\n", __func__);
1581                 return -EINVAL;
1582         }
1583         *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1584                      ((u32)data[1] << 16) |
1585                      ((u32)data[2] << 8) |
1586                      (u32)data[3];
1587         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1588         period_exp = data[0] & 0x0f;
1589         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1590         cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1591         n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1592         if (*bit_error > ((1U << period_exp) * n_ldpc)) {
1593                 dev_dbg(&priv->i2c->dev,
1594                         "%s(): invalid BER value\n", __func__);
1595                 return -EINVAL;
1596         }
1597
1598         /*
1599          * FIXME: the right thing would be to return bit_error untouched,
1600          * but, as we don't know the scale returned by the counters, let's
1601          * at least preserver BER = bit_error/bit_count.
1602          */
1603         if (period_exp >= 4) {
1604                 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
1605                 *bit_error *= 3125ULL;
1606         } else {
1607                 *bit_count = (1U << period_exp) * (n_ldpc / 200);
1608                 *bit_error *= 50000ULL;
1609         }
1610         return 0;
1611 }
1612
1613 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
1614                                 u32 *bit_error, u32 *bit_count)
1615 {
1616         u8 data[2];
1617         u32 period;
1618
1619         if (priv->state != STATE_ACTIVE_TC) {
1620                 dev_dbg(&priv->i2c->dev,
1621                         "%s(): invalid state %d\n", __func__, priv->state);
1622                 return -EINVAL;
1623         }
1624         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1625         cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1626         if (!(data[0] & 0x01)) {
1627                 dev_dbg(&priv->i2c->dev,
1628                         "%s(): no valid BER data\n", __func__);
1629                 return 0;
1630         }
1631         cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1632         *bit_error = ((u32)data[0] << 8) | (u32)data[1];
1633         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1634         period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1635
1636         /*
1637          * FIXME: the right thing would be to return bit_error untouched,
1638          * but, as we don't know the scale returned by the counters, let's
1639          * at least preserver BER = bit_error/bit_count.
1640          */
1641         *bit_count = period / 128;
1642         *bit_error *= 78125ULL;
1643         return 0;
1644 }
1645
1646 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv)
1647 {
1648         /*
1649          * Freeze registers: ensure multiple separate register reads
1650          * are from the same snapshot
1651          */
1652         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1653         return 0;
1654 }
1655
1656 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv)
1657 {
1658         /*
1659          * un-freeze registers
1660          */
1661         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00);
1662         return 0;
1663 }
1664
1665 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
1666                 u8 delsys, u32 *snr)
1667 {
1668         u8 data[3];
1669         u32 res = 0, value;
1670         int min_index, max_index, index;
1671         static const struct cxd2841er_cnr_data *cn_data;
1672
1673         cxd2841er_freeze_regs(priv);
1674         /* Set SLV-T Bank : 0xA1 */
1675         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1676         /*
1677          *  slave     Bank      Addr      Bit     Signal name
1678          * <SLV-T>    A1h       10h       [0]     ICPM_QUICKRDY
1679          * <SLV-T>    A1h       11h       [4:0]   ICPM_QUICKCNDT[12:8]
1680          * <SLV-T>    A1h       12h       [7:0]   ICPM_QUICKCNDT[7:0]
1681          */
1682         cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1683         cxd2841er_unfreeze_regs(priv);
1684
1685         if (data[0] & 0x01) {
1686                 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1687                 min_index = 0;
1688                 if (delsys == SYS_DVBS) {
1689                         cn_data = s_cn_data;
1690                         max_index = ARRAY_SIZE(s_cn_data) - 1;
1691                 } else {
1692                         cn_data = s2_cn_data;
1693                         max_index = ARRAY_SIZE(s2_cn_data) - 1;
1694                 }
1695                 if (value >= cn_data[min_index].value) {
1696                         res = cn_data[min_index].cnr_x1000;
1697                         goto done;
1698                 }
1699                 if (value <= cn_data[max_index].value) {
1700                         res = cn_data[max_index].cnr_x1000;
1701                         goto done;
1702                 }
1703                 while ((max_index - min_index) > 1) {
1704                         index = (max_index + min_index) / 2;
1705                         if (value == cn_data[index].value) {
1706                                 res = cn_data[index].cnr_x1000;
1707                                 goto done;
1708                         } else if (value > cn_data[index].value)
1709                                 max_index = index;
1710                         else
1711                                 min_index = index;
1712                         if ((max_index - min_index) <= 1) {
1713                                 if (value == cn_data[max_index].value) {
1714                                         res = cn_data[max_index].cnr_x1000;
1715                                         goto done;
1716                                 } else {
1717                                         res = cn_data[min_index].cnr_x1000;
1718                                         goto done;
1719                                 }
1720                         }
1721                 }
1722         } else {
1723                 dev_dbg(&priv->i2c->dev,
1724                         "%s(): no data available\n", __func__);
1725                 return -EINVAL;
1726         }
1727 done:
1728         *snr = res;
1729         return 0;
1730 }
1731
1732 static uint32_t sony_log(uint32_t x)
1733 {
1734         return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
1735 }
1736
1737 static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
1738 {
1739         u32 reg;
1740         u8 data[2];
1741         enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
1742
1743         *snr = 0;
1744         if (priv->state != STATE_ACTIVE_TC) {
1745                 dev_dbg(&priv->i2c->dev,
1746                                 "%s(): invalid state %d\n",
1747                                 __func__, priv->state);
1748                 return -EINVAL;
1749         }
1750
1751         cxd2841er_freeze_regs(priv);
1752         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1753         cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
1754         qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
1755         cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
1756         cxd2841er_unfreeze_regs(priv);
1757
1758         reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
1759         if (reg == 0) {
1760                 dev_dbg(&priv->i2c->dev,
1761                                 "%s(): reg value out of range\n", __func__);
1762                 return 0;
1763         }
1764
1765         switch (qam) {
1766         case SONY_DVBC_CONSTELLATION_16QAM:
1767         case SONY_DVBC_CONSTELLATION_64QAM:
1768         case SONY_DVBC_CONSTELLATION_256QAM:
1769                 /* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */
1770                 if (reg < 126)
1771                         reg = 126;
1772                 *snr = -95 * (int32_t)sony_log(reg) + 95941;
1773                 break;
1774         case SONY_DVBC_CONSTELLATION_32QAM:
1775         case SONY_DVBC_CONSTELLATION_128QAM:
1776                 /* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */
1777                 if (reg < 69)
1778                         reg = 69;
1779                 *snr = -88 * (int32_t)sony_log(reg) + 86999;
1780                 break;
1781         default:
1782                 return -EINVAL;
1783         }
1784
1785         return 0;
1786 }
1787
1788 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1789 {
1790         u32 reg;
1791         u8 data[2];
1792
1793         *snr = 0;
1794         if (priv->state != STATE_ACTIVE_TC) {
1795                 dev_dbg(&priv->i2c->dev,
1796                         "%s(): invalid state %d\n", __func__, priv->state);
1797                 return -EINVAL;
1798         }
1799
1800         cxd2841er_freeze_regs(priv);
1801         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1802         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1803         cxd2841er_unfreeze_regs(priv);
1804
1805         reg = ((u32)data[0] << 8) | (u32)data[1];
1806         if (reg == 0) {
1807                 dev_dbg(&priv->i2c->dev,
1808                         "%s(): reg value out of range\n", __func__);
1809                 return 0;
1810         }
1811         if (reg > 4996)
1812                 reg = 4996;
1813         *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(5350 - reg)) + 285);
1814         return 0;
1815 }
1816
1817 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1818 {
1819         u32 reg;
1820         u8 data[2];
1821
1822         *snr = 0;
1823         if (priv->state != STATE_ACTIVE_TC) {
1824                 dev_dbg(&priv->i2c->dev,
1825                         "%s(): invalid state %d\n", __func__, priv->state);
1826                 return -EINVAL;
1827         }
1828
1829         cxd2841er_freeze_regs(priv);
1830         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1831         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1832         cxd2841er_unfreeze_regs(priv);
1833
1834         reg = ((u32)data[0] << 8) | (u32)data[1];
1835         if (reg == 0) {
1836                 dev_dbg(&priv->i2c->dev,
1837                         "%s(): reg value out of range\n", __func__);
1838                 return 0;
1839         }
1840         if (reg > 10876)
1841                 reg = 10876;
1842         *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(12600 - reg)) + 320);
1843         return 0;
1844 }
1845
1846 static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1847 {
1848         u32 reg;
1849         u8 data[2];
1850
1851         *snr = 0;
1852         if (priv->state != STATE_ACTIVE_TC) {
1853                 dev_dbg(&priv->i2c->dev,
1854                                 "%s(): invalid state %d\n", __func__,
1855                                 priv->state);
1856                 return -EINVAL;
1857         }
1858
1859         cxd2841er_freeze_regs(priv);
1860         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1861         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1862         cxd2841er_unfreeze_regs(priv);
1863
1864         reg = ((u32)data[0] << 8) | (u32)data[1];
1865         if (reg == 0) {
1866                 dev_dbg(&priv->i2c->dev,
1867                                 "%s(): reg value out of range\n", __func__);
1868                 return 0;
1869         }
1870         *snr = 10000 * (intlog10(reg) >> 24) - 9031;
1871         return 0;
1872 }
1873
1874 static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1875                                         u8 delsys)
1876 {
1877         u8 data[2];
1878
1879         cxd2841er_write_reg(
1880                 priv, I2C_SLVT, 0x00, 0x40);
1881         cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1882         dev_dbg(&priv->i2c->dev,
1883                         "%s(): AGC value=%u\n",
1884                         __func__, (((u16)data[0] & 0x0F) << 8) |
1885                         (u16)(data[1] & 0xFF));
1886         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1887 }
1888
1889 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1890                                         u8 delsys)
1891 {
1892         u8 data[2];
1893
1894         cxd2841er_write_reg(
1895                 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1896         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1897         dev_dbg(&priv->i2c->dev,
1898                         "%s(): AGC value=%u\n",
1899                         __func__, (((u16)data[0] & 0x0F) << 8) |
1900                         (u16)(data[1] & 0xFF));
1901         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1902 }
1903
1904 static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1905                 u8 delsys)
1906 {
1907         u8 data[2];
1908
1909         cxd2841er_write_reg(
1910                         priv, I2C_SLVT, 0x00, 0x60);
1911         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1912
1913         dev_dbg(&priv->i2c->dev,
1914                         "%s(): AGC value=%u\n",
1915                         __func__, (((u16)data[0] & 0x0F) << 8) |
1916                         (u16)(data[1] & 0xFF));
1917         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1918 }
1919
1920 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1921 {
1922         u8 data[2];
1923
1924         /* Set SLV-T Bank : 0xA0 */
1925         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1926         /*
1927          *  slave     Bank      Addr      Bit       Signal name
1928          * <SLV-T>    A0h       1Fh       [4:0]     IRFAGC_GAIN[12:8]
1929          * <SLV-T>    A0h       20h       [7:0]     IRFAGC_GAIN[7:0]
1930          */
1931         cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1932         return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1933 }
1934
1935 static void cxd2841er_read_ber(struct dvb_frontend *fe)
1936 {
1937         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1938         struct cxd2841er_priv *priv = fe->demodulator_priv;
1939         u32 ret, bit_error = 0, bit_count = 0;
1940
1941         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1942         switch (p->delivery_system) {
1943         case SYS_DVBC_ANNEX_A:
1944         case SYS_DVBC_ANNEX_B:
1945         case SYS_DVBC_ANNEX_C:
1946                 ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
1947                 break;
1948         case SYS_ISDBT:
1949                 ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count);
1950                 break;
1951         case SYS_DVBS:
1952                 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
1953                 break;
1954         case SYS_DVBS2:
1955                 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
1956                 break;
1957         case SYS_DVBT:
1958                 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
1959                 break;
1960         case SYS_DVBT2:
1961                 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
1962                 break;
1963         default:
1964                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1965                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1966                 return;
1967         }
1968
1969         if (!ret) {
1970                 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1971                 p->post_bit_error.stat[0].uvalue += bit_error;
1972                 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1973                 p->post_bit_count.stat[0].uvalue += bit_count;
1974         } else {
1975                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1976                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1977         }
1978 }
1979
1980 static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
1981 {
1982         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1983         struct cxd2841er_priv *priv = fe->demodulator_priv;
1984         s32 strength;
1985
1986         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1987         switch (p->delivery_system) {
1988         case SYS_DVBT:
1989         case SYS_DVBT2:
1990                 strength = cxd2841er_read_agc_gain_t_t2(priv,
1991                                                         p->delivery_system);
1992                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1993                 /* Formula was empirically determinated @ 410 MHz */
1994                 p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
1995                 break;  /* Code moved out of the function */
1996         case SYS_DVBC_ANNEX_A:
1997         case SYS_DVBC_ANNEX_B:
1998         case SYS_DVBC_ANNEX_C:
1999                 strength = cxd2841er_read_agc_gain_c(priv,
2000                                                         p->delivery_system);
2001                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2002                 /*
2003                  * Formula was empirically determinated via linear regression,
2004                  * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
2005                  * stream modulated with QAM64
2006                  */
2007                 p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
2008                 break;
2009         case SYS_ISDBT:
2010                 strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
2011                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2012                 /*
2013                  * Formula was empirically determinated via linear regression,
2014                  * using frequencies: 175 MHz, 410 MHz and 800 MHz.
2015                  */
2016                 p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
2017                 break;
2018         case SYS_DVBS:
2019         case SYS_DVBS2:
2020                 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
2021                 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2022                 p->strength.stat[0].uvalue = strength;
2023                 break;
2024         default:
2025                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2026                 break;
2027         }
2028 }
2029
2030 static void cxd2841er_read_snr(struct dvb_frontend *fe)
2031 {
2032         u32 tmp = 0;
2033         int ret = 0;
2034         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2035         struct cxd2841er_priv *priv = fe->demodulator_priv;
2036
2037         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2038         switch (p->delivery_system) {
2039         case SYS_DVBC_ANNEX_A:
2040         case SYS_DVBC_ANNEX_B:
2041         case SYS_DVBC_ANNEX_C:
2042                 ret = cxd2841er_read_snr_c(priv, &tmp);
2043                 break;
2044         case SYS_DVBT:
2045                 ret = cxd2841er_read_snr_t(priv, &tmp);
2046                 break;
2047         case SYS_DVBT2:
2048                 ret = cxd2841er_read_snr_t2(priv, &tmp);
2049                 break;
2050         case SYS_ISDBT:
2051                 ret = cxd2841er_read_snr_i(priv, &tmp);
2052                 break;
2053         case SYS_DVBS:
2054         case SYS_DVBS2:
2055                 ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
2056                 break;
2057         default:
2058                 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
2059                         __func__, p->delivery_system);
2060                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2061                 return;
2062         }
2063
2064         dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n",
2065                         __func__, (int32_t)tmp);
2066
2067         if (!ret) {
2068                 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2069                 p->cnr.stat[0].svalue = tmp;
2070         } else {
2071                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2072         }
2073 }
2074
2075 static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
2076 {
2077         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2078         struct cxd2841er_priv *priv = fe->demodulator_priv;
2079         u32 ucblocks = 0;
2080
2081         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2082         switch (p->delivery_system) {
2083         case SYS_DVBC_ANNEX_A:
2084         case SYS_DVBC_ANNEX_B:
2085         case SYS_DVBC_ANNEX_C:
2086                 cxd2841er_read_packet_errors_c(priv, &ucblocks);
2087                 break;
2088         case SYS_DVBT:
2089                 cxd2841er_read_packet_errors_t(priv, &ucblocks);
2090                 break;
2091         case SYS_DVBT2:
2092                 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
2093                 break;
2094         case SYS_ISDBT:
2095                 cxd2841er_read_packet_errors_i(priv, &ucblocks);
2096                 break;
2097         default:
2098                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2099                 return;
2100         }
2101         dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks);
2102
2103         p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2104         p->block_error.stat[0].uvalue = ucblocks;
2105 }
2106
2107 static int cxd2841er_dvbt2_set_profile(
2108         struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
2109 {
2110         u8 tune_mode;
2111         u8 seq_not2d_time;
2112
2113         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2114         switch (profile) {
2115         case DVBT2_PROFILE_BASE:
2116                 tune_mode = 0x01;
2117                 /* Set early unlock time */
2118                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
2119                 break;
2120         case DVBT2_PROFILE_LITE:
2121                 tune_mode = 0x05;
2122                 /* Set early unlock time */
2123                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2124                 break;
2125         case DVBT2_PROFILE_ANY:
2126                 tune_mode = 0x00;
2127                 /* Set early unlock time */
2128                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2129                 break;
2130         default:
2131                 return -EINVAL;
2132         }
2133         /* Set SLV-T Bank : 0x2E */
2134         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
2135         /* Set profile and tune mode */
2136         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
2137         /* Set SLV-T Bank : 0x2B */
2138         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2139         /* Set early unlock detection time */
2140         cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
2141         return 0;
2142 }
2143
2144 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
2145                                           u8 is_auto, u8 plp_id)
2146 {
2147         if (is_auto) {
2148                 dev_dbg(&priv->i2c->dev,
2149                         "%s() using auto PLP selection\n", __func__);
2150         } else {
2151                 dev_dbg(&priv->i2c->dev,
2152                         "%s() using manual PLP selection, ID %d\n",
2153                         __func__, plp_id);
2154         }
2155         /* Set SLV-T Bank : 0x23 */
2156         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2157         if (!is_auto) {
2158                 /* Manual PLP selection mode. Set the data PLP Id. */
2159                 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
2160         }
2161         /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
2162         cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
2163         return 0;
2164 }
2165
2166 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
2167                                                 u32 bandwidth)
2168 {
2169         u32 iffreq, ifhz;
2170         u8 data[MAX_WRITE_REGSIZE];
2171
2172         static const uint8_t nominalRate8bw[3][5] = {
2173                 /* TRCG Nominal Rate [37:0] */
2174                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2175                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2176                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2177         };
2178
2179         static const uint8_t nominalRate7bw[3][5] = {
2180                 /* TRCG Nominal Rate [37:0] */
2181                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2182                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2183                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2184         };
2185
2186         static const uint8_t nominalRate6bw[3][5] = {
2187                 /* TRCG Nominal Rate [37:0] */
2188                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2189                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2190                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2191         };
2192
2193         static const uint8_t nominalRate5bw[3][5] = {
2194                 /* TRCG Nominal Rate [37:0] */
2195                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2196                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2197                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2198         };
2199
2200         static const uint8_t nominalRate17bw[3][5] = {
2201                 /* TRCG Nominal Rate [37:0] */
2202                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
2203                 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
2204                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}  /* 41MHz XTal */
2205         };
2206
2207         static const uint8_t itbCoef8bw[3][14] = {
2208                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2209                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2210                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
2211                         0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2212                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2213                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2214         };
2215
2216         static const uint8_t itbCoef7bw[3][14] = {
2217                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2218                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2219                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
2220                         0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2221                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2222                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2223         };
2224
2225         static const uint8_t itbCoef6bw[3][14] = {
2226                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2227                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2228                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2229                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2230                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2231                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2232         };
2233
2234         static const uint8_t itbCoef5bw[3][14] = {
2235                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2236                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2237                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2238                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2239                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2240                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2241         };
2242
2243         static const uint8_t itbCoef17bw[3][14] = {
2244                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2245                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
2246                 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
2247                         0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal   */
2248                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2249                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}  /* 41MHz XTal   */
2250         };
2251
2252         /* Set SLV-T Bank : 0x20 */
2253         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2254
2255         switch (bandwidth) {
2256         case 8000000:
2257                 /* <Timing Recovery setting> */
2258                 cxd2841er_write_regs(priv, I2C_SLVT,
2259                                 0x9F, nominalRate8bw[priv->xtal], 5);
2260
2261                 /* Set SLV-T Bank : 0x27 */
2262                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2263                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2264                                 0x7a, 0x00, 0x0f);
2265
2266                 /* Set SLV-T Bank : 0x10 */
2267                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2268
2269                 /* Group delay equaliser settings for
2270                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2271                  */
2272                 if (priv->flags & CXD2841ER_ASCOT)
2273                         cxd2841er_write_regs(priv, I2C_SLVT,
2274                                 0xA6, itbCoef8bw[priv->xtal], 14);
2275                 /* <IF freq setting> */
2276                 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2277                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2278                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2279                 data[1] = (u8)((iffreq >> 8) & 0xff);
2280                 data[2] = (u8)(iffreq & 0xff);
2281                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2282                 /* System bandwidth setting */
2283                 cxd2841er_set_reg_bits(
2284                                 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2285                 break;
2286         case 7000000:
2287                 /* <Timing Recovery setting> */
2288                 cxd2841er_write_regs(priv, I2C_SLVT,
2289                                 0x9F, nominalRate7bw[priv->xtal], 5);
2290
2291                 /* Set SLV-T Bank : 0x27 */
2292                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2293                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2294                                 0x7a, 0x00, 0x0f);
2295
2296                 /* Set SLV-T Bank : 0x10 */
2297                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2298
2299                 /* Group delay equaliser settings for
2300                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2301                  */
2302                 if (priv->flags & CXD2841ER_ASCOT)
2303                         cxd2841er_write_regs(priv, I2C_SLVT,
2304                                 0xA6, itbCoef7bw[priv->xtal], 14);
2305                 /* <IF freq setting> */
2306                 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2307                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2308                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2309                 data[1] = (u8)((iffreq >> 8) & 0xff);
2310                 data[2] = (u8)(iffreq & 0xff);
2311                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2312                 /* System bandwidth setting */
2313                 cxd2841er_set_reg_bits(
2314                                 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2315                 break;
2316         case 6000000:
2317                 /* <Timing Recovery setting> */
2318                 cxd2841er_write_regs(priv, I2C_SLVT,
2319                                 0x9F, nominalRate6bw[priv->xtal], 5);
2320
2321                 /* Set SLV-T Bank : 0x27 */
2322                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2323                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2324                                 0x7a, 0x00, 0x0f);
2325
2326                 /* Set SLV-T Bank : 0x10 */
2327                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2328
2329                 /* Group delay equaliser settings for
2330                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2331                  */
2332                 if (priv->flags & CXD2841ER_ASCOT)
2333                         cxd2841er_write_regs(priv, I2C_SLVT,
2334                                 0xA6, itbCoef6bw[priv->xtal], 14);
2335                 /* <IF freq setting> */
2336                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2337                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2338                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2339                 data[1] = (u8)((iffreq >> 8) & 0xff);
2340                 data[2] = (u8)(iffreq & 0xff);
2341                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2342                 /* System bandwidth setting */
2343                 cxd2841er_set_reg_bits(
2344                                 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2345                 break;
2346         case 5000000:
2347                 /* <Timing Recovery setting> */
2348                 cxd2841er_write_regs(priv, I2C_SLVT,
2349                                 0x9F, nominalRate5bw[priv->xtal], 5);
2350
2351                 /* Set SLV-T Bank : 0x27 */
2352                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2353                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2354                                 0x7a, 0x00, 0x0f);
2355
2356                 /* Set SLV-T Bank : 0x10 */
2357                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2358
2359                 /* Group delay equaliser settings for
2360                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2361                  */
2362                 if (priv->flags & CXD2841ER_ASCOT)
2363                         cxd2841er_write_regs(priv, I2C_SLVT,
2364                                 0xA6, itbCoef5bw[priv->xtal], 14);
2365                 /* <IF freq setting> */
2366                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2367                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2368                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2369                 data[1] = (u8)((iffreq >> 8) & 0xff);
2370                 data[2] = (u8)(iffreq & 0xff);
2371                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2372                 /* System bandwidth setting */
2373                 cxd2841er_set_reg_bits(
2374                                 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2375                 break;
2376         case 1712000:
2377                 /* <Timing Recovery setting> */
2378                 cxd2841er_write_regs(priv, I2C_SLVT,
2379                                 0x9F, nominalRate17bw[priv->xtal], 5);
2380
2381                 /* Set SLV-T Bank : 0x27 */
2382                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2383                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2384                                 0x7a, 0x03, 0x0f);
2385
2386                 /* Set SLV-T Bank : 0x10 */
2387                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2388
2389                 /* Group delay equaliser settings for
2390                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2391                  */
2392                 if (priv->flags & CXD2841ER_ASCOT)
2393                         cxd2841er_write_regs(priv, I2C_SLVT,
2394                                 0xA6, itbCoef17bw[priv->xtal], 14);
2395                 /* <IF freq setting> */
2396                 ifhz = cxd2841er_get_if_hz(priv, 3500000);
2397                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2398                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2399                 data[1] = (u8)((iffreq >> 8) & 0xff);
2400                 data[2] = (u8)(iffreq & 0xff);
2401                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2402                 /* System bandwidth setting */
2403                 cxd2841er_set_reg_bits(
2404                                 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
2405                 break;
2406         default:
2407                 return -EINVAL;
2408         }
2409         return 0;
2410 }
2411
2412 static int cxd2841er_sleep_tc_to_active_t_band(
2413                 struct cxd2841er_priv *priv, u32 bandwidth)
2414 {
2415         u8 data[MAX_WRITE_REGSIZE];
2416         u32 iffreq, ifhz;
2417         static const u8 nominalRate8bw[3][5] = {
2418                 /* TRCG Nominal Rate [37:0] */
2419                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2420                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2421                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2422         };
2423         static const u8 nominalRate7bw[3][5] = {
2424                 /* TRCG Nominal Rate [37:0] */
2425                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2426                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2427                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2428         };
2429         static const u8 nominalRate6bw[3][5] = {
2430                 /* TRCG Nominal Rate [37:0] */
2431                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2432                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2433                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2434         };
2435         static const u8 nominalRate5bw[3][5] = {
2436                 /* TRCG Nominal Rate [37:0] */
2437                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2438                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2439                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2440         };
2441
2442         static const u8 itbCoef8bw[3][14] = {
2443                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2444                         0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2445                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2446                         0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2447                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2448                         0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2449         };
2450         static const u8 itbCoef7bw[3][14] = {
2451                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2452                         0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2453                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2454                         0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2455                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2456                         0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2457         };
2458         static const u8 itbCoef6bw[3][14] = {
2459                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2460                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2461                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2462                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2463                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2464                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2465         };
2466         static const u8 itbCoef5bw[3][14] = {
2467                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2468                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2469                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2470                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2471                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2472                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2473         };
2474
2475         /* Set SLV-T Bank : 0x13 */
2476         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2477         /* Echo performance optimization setting */
2478         data[0] = 0x01;
2479         data[1] = 0x14;
2480         cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2481
2482         /* Set SLV-T Bank : 0x10 */
2483         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2484
2485         switch (bandwidth) {
2486         case 8000000:
2487                 /* <Timing Recovery setting> */
2488                 cxd2841er_write_regs(priv, I2C_SLVT,
2489                                 0x9F, nominalRate8bw[priv->xtal], 5);
2490                 /* Group delay equaliser settings for
2491                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2492                 */
2493                 if (priv->flags & CXD2841ER_ASCOT)
2494                         cxd2841er_write_regs(priv, I2C_SLVT,
2495                                 0xA6, itbCoef8bw[priv->xtal], 14);
2496                 /* <IF freq setting> */
2497                 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2498                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2499                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2500                 data[1] = (u8)((iffreq >> 8) & 0xff);
2501                 data[2] = (u8)(iffreq & 0xff);
2502                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2503                 /* System bandwidth setting */
2504                 cxd2841er_set_reg_bits(
2505                         priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2506
2507                 /* Demod core latency setting */
2508                 if (priv->xtal == SONY_XTAL_24000) {
2509                         data[0] = 0x15;
2510                         data[1] = 0x28;
2511                 } else {
2512                         data[0] = 0x01;
2513                         data[1] = 0xE0;
2514                 }
2515                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2516
2517                 /* Notch filter setting */
2518                 data[0] = 0x01;
2519                 data[1] = 0x02;
2520                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2521                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2522                 break;
2523         case 7000000:
2524                 /* <Timing Recovery setting> */
2525                 cxd2841er_write_regs(priv, I2C_SLVT,
2526                                 0x9F, nominalRate7bw[priv->xtal], 5);
2527                 /* Group delay equaliser settings for
2528                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2529                 */
2530                 if (priv->flags & CXD2841ER_ASCOT)
2531                         cxd2841er_write_regs(priv, I2C_SLVT,
2532                                 0xA6, itbCoef7bw[priv->xtal], 14);
2533                 /* <IF freq setting> */
2534                 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2535                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2536                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2537                 data[1] = (u8)((iffreq >> 8) & 0xff);
2538                 data[2] = (u8)(iffreq & 0xff);
2539                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2540                 /* System bandwidth setting */
2541                 cxd2841er_set_reg_bits(
2542                         priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2543
2544                 /* Demod core latency setting */
2545                 if (priv->xtal == SONY_XTAL_24000) {
2546                         data[0] = 0x1F;
2547                         data[1] = 0xF8;
2548                 } else {
2549                         data[0] = 0x12;
2550                         data[1] = 0xF8;
2551                 }
2552                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2553
2554                 /* Notch filter setting */
2555                 data[0] = 0x00;
2556                 data[1] = 0x03;
2557                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2558                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2559                 break;
2560         case 6000000:
2561                 /* <Timing Recovery setting> */
2562                 cxd2841er_write_regs(priv, I2C_SLVT,
2563                                 0x9F, nominalRate6bw[priv->xtal], 5);
2564                 /* Group delay equaliser settings for
2565                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2566                 */
2567                 if (priv->flags & CXD2841ER_ASCOT)
2568                         cxd2841er_write_regs(priv, I2C_SLVT,
2569                                 0xA6, itbCoef6bw[priv->xtal], 14);
2570                 /* <IF freq setting> */
2571                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2572                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2573                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2574                 data[1] = (u8)((iffreq >> 8) & 0xff);
2575                 data[2] = (u8)(iffreq & 0xff);
2576                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2577                 /* System bandwidth setting */
2578                 cxd2841er_set_reg_bits(
2579                         priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2580
2581                 /* Demod core latency setting */
2582                 if (priv->xtal == SONY_XTAL_24000) {
2583                         data[0] = 0x25;
2584                         data[1] = 0x4C;
2585                 } else {
2586                         data[0] = 0x1F;
2587                         data[1] = 0xDC;
2588                 }
2589                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2590
2591                 /* Notch filter setting */
2592                 data[0] = 0x00;
2593                 data[1] = 0x03;
2594                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2595                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2596                 break;
2597         case 5000000:
2598                 /* <Timing Recovery setting> */
2599                 cxd2841er_write_regs(priv, I2C_SLVT,
2600                                 0x9F, nominalRate5bw[priv->xtal], 5);
2601                 /* Group delay equaliser settings for
2602                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2603                 */
2604                 if (priv->flags & CXD2841ER_ASCOT)
2605                         cxd2841er_write_regs(priv, I2C_SLVT,
2606                                 0xA6, itbCoef5bw[priv->xtal], 14);
2607                 /* <IF freq setting> */
2608                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2609                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2610                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2611                 data[1] = (u8)((iffreq >> 8) & 0xff);
2612                 data[2] = (u8)(iffreq & 0xff);
2613                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2614                 /* System bandwidth setting */
2615                 cxd2841er_set_reg_bits(
2616                         priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2617
2618                 /* Demod core latency setting */
2619                 if (priv->xtal == SONY_XTAL_24000) {
2620                         data[0] = 0x2C;
2621                         data[1] = 0xC2;
2622                 } else {
2623                         data[0] = 0x26;
2624                         data[1] = 0x3C;
2625                 }
2626                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2627
2628                 /* Notch filter setting */
2629                 data[0] = 0x00;
2630                 data[1] = 0x03;
2631                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2632                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2633                 break;
2634         }
2635
2636         return 0;
2637 }
2638
2639 static int cxd2841er_sleep_tc_to_active_i_band(
2640                 struct cxd2841er_priv *priv, u32 bandwidth)
2641 {
2642         u32 iffreq, ifhz;
2643         u8 data[3];
2644
2645         /* TRCG Nominal Rate */
2646         static const u8 nominalRate8bw[3][5] = {
2647                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2648                 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2649                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2650         };
2651
2652         static const u8 nominalRate7bw[3][5] = {
2653                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2654                 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2655                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2656         };
2657
2658         static const u8 nominalRate6bw[3][5] = {
2659                 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2660                 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2661                 {0x14, 0x2E, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2662         };
2663
2664         static const u8 itbCoef8bw[3][14] = {
2665                 {0x00}, /* 20.5MHz XTal */
2666                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2667                         0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2668                 {0x0}, /* 41MHz XTal   */
2669         };
2670
2671         static const u8 itbCoef7bw[3][14] = {
2672                 {0x00}, /* 20.5MHz XTal */
2673                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2674                         0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2675                 {0x00}, /* 41MHz XTal   */
2676         };
2677
2678         static const u8 itbCoef6bw[3][14] = {
2679                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2680                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2681                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2682                         0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal   */
2683                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2684                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal   */
2685         };
2686
2687         dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2688         /* Set SLV-T Bank : 0x10 */
2689         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2690
2691         /*  20.5/41MHz Xtal support is not available
2692          *  on ISDB-T 7MHzBW and 8MHzBW
2693         */
2694         if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2695                 dev_err(&priv->i2c->dev,
2696                         "%s(): bandwidth %d supported only for 24MHz xtal\n",
2697                         __func__, bandwidth);
2698                 return -EINVAL;
2699         }
2700
2701         switch (bandwidth) {
2702         case 8000000:
2703                 /* TRCG Nominal Rate */
2704                 cxd2841er_write_regs(priv, I2C_SLVT,
2705                                 0x9F, nominalRate8bw[priv->xtal], 5);
2706                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2707                 if (priv->flags & CXD2841ER_ASCOT)
2708                         cxd2841er_write_regs(priv, I2C_SLVT,
2709                                 0xA6, itbCoef8bw[priv->xtal], 14);
2710
2711                 /* IF freq setting */
2712                 ifhz = cxd2841er_get_if_hz(priv, 4750000);
2713                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2714                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2715                 data[1] = (u8)((iffreq >> 8) & 0xff);
2716                 data[2] = (u8)(iffreq & 0xff);
2717                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2718
2719                 /* System bandwidth setting */
2720                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2721
2722                 /* Demod core latency setting */
2723                 data[0] = 0x13;
2724                 data[1] = 0xFC;
2725                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2726
2727                 /* Acquisition optimization setting */
2728                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2729                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2730                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2731                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2732                 break;
2733         case 7000000:
2734                 /* TRCG Nominal Rate */
2735                 cxd2841er_write_regs(priv, I2C_SLVT,
2736                                 0x9F, nominalRate7bw[priv->xtal], 5);
2737                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2738                 if (priv->flags & CXD2841ER_ASCOT)
2739                         cxd2841er_write_regs(priv, I2C_SLVT,
2740                                 0xA6, itbCoef7bw[priv->xtal], 14);
2741
2742                 /* IF freq setting */
2743                 ifhz = cxd2841er_get_if_hz(priv, 4150000);
2744                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2745                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2746                 data[1] = (u8)((iffreq >> 8) & 0xff);
2747                 data[2] = (u8)(iffreq & 0xff);
2748                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2749
2750                 /* System bandwidth setting */
2751                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2752
2753                 /* Demod core latency setting */
2754                 data[0] = 0x1A;
2755                 data[1] = 0xFA;
2756                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2757
2758                 /* Acquisition optimization setting */
2759                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2760                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2761                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2762                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2763                 break;
2764         case 6000000:
2765                 /* TRCG Nominal Rate */
2766                 cxd2841er_write_regs(priv, I2C_SLVT,
2767                                 0x9F, nominalRate6bw[priv->xtal], 5);
2768                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2769                 if (priv->flags & CXD2841ER_ASCOT)
2770                         cxd2841er_write_regs(priv, I2C_SLVT,
2771                                 0xA6, itbCoef6bw[priv->xtal], 14);
2772
2773                 /* IF freq setting */
2774                 ifhz = cxd2841er_get_if_hz(priv, 3550000);
2775                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2776                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2777                 data[1] = (u8)((iffreq >> 8) & 0xff);
2778                 data[2] = (u8)(iffreq & 0xff);
2779                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2780
2781                 /* System bandwidth setting */
2782                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2783
2784                 /* Demod core latency setting */
2785                 if (priv->xtal == SONY_XTAL_24000) {
2786                         data[0] = 0x1F;
2787                         data[1] = 0x79;
2788                 } else {
2789                         data[0] = 0x1A;
2790                         data[1] = 0xE2;
2791                 }
2792                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2793
2794                 /* Acquisition optimization setting */
2795                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2796                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2797                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2798                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2799                 break;
2800         default:
2801                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2802                                 __func__, bandwidth);
2803                 return -EINVAL;
2804         }
2805         return 0;
2806 }
2807
2808 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2809                                                u32 bandwidth)
2810 {
2811         u8 bw7_8mhz_b10_a6[] = {
2812                 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2813                 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2814         u8 bw6mhz_b10_a6[] = {
2815                 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2816                 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2817         u8 b10_b6[3];
2818         u32 iffreq, ifhz;
2819
2820         if (bandwidth != 6000000 &&
2821                         bandwidth != 7000000 &&
2822                         bandwidth != 8000000) {
2823                 dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n",
2824                                 __func__, bandwidth);
2825                 bandwidth = 8000000;
2826         }
2827
2828         dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
2829         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2830         switch (bandwidth) {
2831         case 8000000:
2832         case 7000000:
2833                 if (priv->flags & CXD2841ER_ASCOT)
2834                         cxd2841er_write_regs(
2835                                 priv, I2C_SLVT, 0xa6,
2836                                 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2837                 ifhz = cxd2841er_get_if_hz(priv, 4900000);
2838                 iffreq = cxd2841er_calc_iffreq(ifhz);
2839                 break;
2840         case 6000000:
2841                 if (priv->flags & CXD2841ER_ASCOT)
2842                         cxd2841er_write_regs(
2843                                 priv, I2C_SLVT, 0xa6,
2844                                 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2845                 ifhz = cxd2841er_get_if_hz(priv, 3700000);
2846                 iffreq = cxd2841er_calc_iffreq(ifhz);
2847                 break;
2848         default:
2849                 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2850                         __func__, bandwidth);
2851                 return -EINVAL;
2852         }
2853         /* <IF freq setting> */
2854         b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2855         b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2856         b10_b6[2] = (u8)(iffreq & 0xff);
2857         cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2858         /* Set SLV-T Bank : 0x11 */
2859         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2860         switch (bandwidth) {
2861         case 8000000:
2862         case 7000000:
2863                 cxd2841er_set_reg_bits(
2864                         priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2865                 break;
2866         case 6000000:
2867                 cxd2841er_set_reg_bits(
2868                         priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2869                 break;
2870         }
2871         /* Set SLV-T Bank : 0x40 */
2872         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2873         switch (bandwidth) {
2874         case 8000000:
2875                 cxd2841er_set_reg_bits(
2876                         priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2877                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x3e);
2878                 break;
2879         case 7000000:
2880                 cxd2841er_set_reg_bits(
2881                         priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2882                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0xd6);
2883                 break;
2884         case 6000000:
2885                 cxd2841er_set_reg_bits(
2886                         priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2887                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x6e);
2888                 break;
2889         }
2890         return 0;
2891 }
2892
2893 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2894                                           u32 bandwidth)
2895 {
2896         u8 data[2] = { 0x09, 0x54 };
2897         u8 data24m[3] = {0xDC, 0x6C, 0x00};
2898
2899         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2900         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2901         /* Set SLV-X Bank : 0x00 */
2902         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2903         /* Set demod mode */
2904         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2905         /* Set SLV-T Bank : 0x00 */
2906         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2907         /* Enable demod clock */
2908         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2909         /* Disable RF level monitor */
2910         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2911         /* Enable ADC clock */
2912         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2913         /* Enable ADC 1 */
2914         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2915         /* Enable ADC 2 & 3 */
2916         if (priv->xtal == SONY_XTAL_41000) {
2917                 data[0] = 0x0A;
2918                 data[1] = 0xD4;
2919         }
2920         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2921         /* Enable ADC 4 */
2922         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2923         /* Set SLV-T Bank : 0x10 */
2924         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2925         /* IFAGC gain settings */
2926         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2927         /* Set SLV-T Bank : 0x11 */
2928         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2929         /* BBAGC TARGET level setting */
2930         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2931         /* Set SLV-T Bank : 0x10 */
2932         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2933         /* ASCOT setting */
2934         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
2935                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
2936         /* Set SLV-T Bank : 0x18 */
2937         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2938         /* Pre-RS BER monitor setting */
2939         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2940         /* FEC Auto Recovery setting */
2941         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2942         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2943         /* Set SLV-T Bank : 0x00 */
2944         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2945         /* TSIF setting */
2946         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2947         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2948
2949         if (priv->xtal == SONY_XTAL_24000) {
2950                 /* Set SLV-T Bank : 0x10 */
2951                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2952                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2953                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2954                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2955         }
2956
2957         cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2958         /* Set SLV-T Bank : 0x00 */
2959         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2960         /* Disable HiZ Setting 1 */
2961         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2962         /* Disable HiZ Setting 2 */
2963         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2964         priv->state = STATE_ACTIVE_TC;
2965         return 0;
2966 }
2967
2968 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2969                                            u32 bandwidth)
2970 {
2971         u8 data[MAX_WRITE_REGSIZE];
2972
2973         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2974         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2975         /* Set SLV-X Bank : 0x00 */
2976         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2977         /* Set demod mode */
2978         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2979         /* Set SLV-T Bank : 0x00 */
2980         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2981         /* Enable demod clock */
2982         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2983         /* Disable RF level monitor */
2984         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
2985         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2986         /* Enable ADC clock */
2987         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2988         /* Enable ADC 1 */
2989         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2990
2991         if (priv->xtal == SONY_XTAL_41000) {
2992                 data[0] = 0x0A;
2993                 data[1] = 0xD4;
2994         } else {
2995                 data[0] = 0x09;
2996                 data[1] = 0x54;
2997         }
2998
2999         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3000         /* Enable ADC 4 */
3001         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3002         /* Set SLV-T Bank : 0x10 */
3003         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3004         /* IFAGC gain settings */
3005         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
3006         /* Set SLV-T Bank : 0x11 */
3007         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3008         /* BBAGC TARGET level setting */
3009         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
3010         /* Set SLV-T Bank : 0x10 */
3011         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3012         /* ASCOT setting */
3013         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3014                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3015         /* Set SLV-T Bank : 0x20 */
3016         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3017         /* Acquisition optimization setting */
3018         cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
3019         /* Set SLV-T Bank : 0x2b */
3020         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3021         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
3022         /* Set SLV-T Bank : 0x23 */
3023         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
3024         /* L1 Control setting */
3025         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
3026         /* Set SLV-T Bank : 0x00 */
3027         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3028         /* TSIF setting */
3029         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3030         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3031         /* DVB-T2 initial setting */
3032         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
3033         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
3034         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
3035         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
3036         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
3037         /* Set SLV-T Bank : 0x2a */
3038         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
3039         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
3040         /* Set SLV-T Bank : 0x2b */
3041         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3042         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
3043
3044         /* 24MHz Xtal setting */
3045         if (priv->xtal == SONY_XTAL_24000) {
3046                 /* Set SLV-T Bank : 0x11 */
3047                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3048                 data[0] = 0xEB;
3049                 data[1] = 0x03;
3050                 data[2] = 0x3B;
3051                 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
3052
3053                 /* Set SLV-T Bank : 0x20 */
3054                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3055                 data[0] = 0x5E;
3056                 data[1] = 0x5E;
3057                 data[2] = 0x47;
3058                 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
3059
3060                 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
3061
3062                 data[0] = 0x3F;
3063                 data[1] = 0xFF;
3064                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
3065
3066                 /* Set SLV-T Bank : 0x24 */
3067                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
3068                 data[0] = 0x0B;
3069                 data[1] = 0x72;
3070                 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
3071
3072                 data[0] = 0x93;
3073                 data[1] = 0xF3;
3074                 data[2] = 0x00;
3075                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
3076
3077                 data[0] = 0x05;
3078                 data[1] = 0xB8;
3079                 data[2] = 0xD8;
3080                 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
3081
3082                 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
3083
3084                 /* Set SLV-T Bank : 0x25 */
3085                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
3086                 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
3087
3088                 /* Set SLV-T Bank : 0x27 */
3089                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
3090                 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
3091
3092                 /* Set SLV-T Bank : 0x2B */
3093                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
3094                 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
3095                 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
3096
3097                 /* Set SLV-T Bank : 0x2D */
3098                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
3099                 data[0] = 0x89;
3100                 data[1] = 0x89;
3101                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
3102
3103                 /* Set SLV-T Bank : 0x5E */
3104                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
3105                 data[0] = 0x24;
3106                 data[1] = 0x95;
3107                 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
3108         }
3109
3110         cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
3111
3112         /* Set SLV-T Bank : 0x00 */
3113         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3114         /* Disable HiZ Setting 1 */
3115         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3116         /* Disable HiZ Setting 2 */
3117         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3118         priv->state = STATE_ACTIVE_TC;
3119         return 0;
3120 }
3121
3122 /* ISDB-Tb part */
3123 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
3124                 u32 bandwidth)
3125 {
3126         u8 data[2] = { 0x09, 0x54 };
3127         u8 data24m[2] = {0x60, 0x00};
3128         u8 data24m2[3] = {0xB7, 0x1B, 0x00};
3129
3130         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3131         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
3132         /* Set SLV-X Bank : 0x00 */
3133         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3134         /* Set demod mode */
3135         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
3136         /* Set SLV-T Bank : 0x00 */
3137         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3138         /* Enable demod clock */
3139         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3140         /* Enable RF level monitor */
3141         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
3142         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
3143         /* Enable ADC clock */
3144         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3145         /* Enable ADC 1 */
3146         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3147         /* xtal freq 20.5MHz or 24M */
3148         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3149         /* Enable ADC 4 */
3150         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3151         /* ASCOT setting */
3152         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3153                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3154         /* FEC Auto Recovery setting */
3155         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
3156         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
3157         /* ISDB-T initial setting */
3158         /* Set SLV-T Bank : 0x00 */
3159         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3160         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
3161         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
3162         /* Set SLV-T Bank : 0x10 */
3163         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3164         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
3165         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
3166         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
3167         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
3168         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
3169         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
3170         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
3171         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
3172         /* Set SLV-T Bank : 0x15 */
3173         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
3174         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
3175         /* Set SLV-T Bank : 0x1E */
3176         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
3177         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
3178         /* Set SLV-T Bank : 0x63 */
3179         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
3180         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
3181
3182         /* for xtal 24MHz */
3183         /* Set SLV-T Bank : 0x10 */
3184         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3185         cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
3186         /* Set SLV-T Bank : 0x60 */
3187         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
3188         cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
3189
3190         cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
3191         /* Set SLV-T Bank : 0x00 */
3192         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3193         /* Disable HiZ Setting 1 */
3194         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3195         /* Disable HiZ Setting 2 */
3196         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3197         priv->state = STATE_ACTIVE_TC;
3198         return 0;
3199 }
3200
3201 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
3202                                           u32 bandwidth)
3203 {
3204         u8 data[2] = { 0x09, 0x54 };
3205
3206         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3207         cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
3208         /* Set SLV-X Bank : 0x00 */
3209         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3210         /* Set demod mode */
3211         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
3212         /* Set SLV-T Bank : 0x00 */
3213         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3214         /* Enable demod clock */
3215         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3216         /* Disable RF level monitor */
3217         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
3218         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
3219         /* Enable ADC clock */
3220         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3221         /* Enable ADC 1 */
3222         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3223         /* xtal freq 20.5MHz */
3224         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3225         /* Enable ADC 4 */
3226         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3227         /* Set SLV-T Bank : 0x10 */
3228         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3229         /* IFAGC gain settings */
3230         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
3231         /* Set SLV-T Bank : 0x11 */
3232         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3233         /* BBAGC TARGET level setting */
3234         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
3235         /* Set SLV-T Bank : 0x10 */
3236         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3237         /* ASCOT setting */
3238         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3239                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3240         /* Set SLV-T Bank : 0x40 */
3241         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
3242         /* Demod setting */
3243         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
3244         /* Set SLV-T Bank : 0x00 */
3245         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3246         /* TSIF setting */
3247         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3248         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3249
3250         cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
3251         /* Set SLV-T Bank : 0x00 */
3252         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3253         /* Disable HiZ Setting 1 */
3254         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3255         /* Disable HiZ Setting 2 */
3256         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3257         priv->state = STATE_ACTIVE_TC;
3258         return 0;
3259 }
3260
3261 static int cxd2841er_get_frontend(struct dvb_frontend *fe,
3262                                   struct dtv_frontend_properties *p)
3263 {
3264         enum fe_status status = 0;
3265         struct cxd2841er_priv *priv = fe->demodulator_priv;
3266
3267         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3268         if (priv->state == STATE_ACTIVE_S)
3269                 cxd2841er_read_status_s(fe, &status);
3270         else if (priv->state == STATE_ACTIVE_TC)
3271                 cxd2841er_read_status_tc(fe, &status);
3272
3273         if (priv->state == STATE_ACTIVE_TC || priv->state == STATE_ACTIVE_S)
3274                 cxd2841er_read_signal_strength(fe);
3275         else
3276                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3277
3278         if (status & FE_HAS_LOCK) {
3279                 if (priv->stats_time &&
3280                     (!time_after(jiffies, priv->stats_time)))
3281                         return 0;
3282
3283                 /* Prevent retrieving stats faster than once per second */
3284                 priv->stats_time = jiffies + msecs_to_jiffies(1000);
3285
3286                 cxd2841er_read_snr(fe);
3287                 cxd2841er_read_ucblocks(fe);
3288                 cxd2841er_read_ber(fe);
3289         } else {
3290                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3291                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3292                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3293                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3294         }
3295         return 0;
3296 }
3297
3298 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
3299 {
3300         int ret = 0, i, timeout, carr_offset;
3301         enum fe_status status;
3302         struct cxd2841er_priv *priv = fe->demodulator_priv;
3303         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3304         u32 symbol_rate = p->symbol_rate/1000;
3305
3306         dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
3307                 __func__,
3308                 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
3309                  p->frequency, symbol_rate, priv->xtal);
3310
3311         if (priv->flags & CXD2841ER_EARLY_TUNE)
3312                 cxd2841er_tuner_set(fe);
3313
3314         switch (priv->state) {
3315         case STATE_SLEEP_S:
3316                 ret = cxd2841er_sleep_s_to_active_s(
3317                         priv, p->delivery_system, symbol_rate);
3318                 break;
3319         case STATE_ACTIVE_S:
3320                 ret = cxd2841er_retune_active(priv, p);
3321                 break;
3322         default:
3323                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3324                         __func__, priv->state);
3325                 ret = -EINVAL;
3326                 goto done;
3327         }
3328         if (ret) {
3329                 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3330                 goto done;
3331         }
3332
3333         if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3334                 cxd2841er_tuner_set(fe);
3335
3336         cxd2841er_tune_done(priv);
3337         timeout = DIV_ROUND_UP(3000000, symbol_rate) + 150;
3338
3339         i = 0;
3340         do {
3341                 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3342                         (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3343                 cxd2841er_read_status_s(fe, &status);
3344                 if (status & FE_HAS_LOCK)
3345                         break;
3346                 i++;
3347         } while (i < timeout / CXD2841ER_DVBS_POLLING_INVL);
3348
3349         if (status & FE_HAS_LOCK) {
3350                 if (cxd2841er_get_carrier_offset_s_s2(
3351                                 priv, &carr_offset)) {
3352                         ret = -EINVAL;
3353                         goto done;
3354                 }
3355                 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3356                         __func__, carr_offset);
3357         }
3358 done:
3359         /* Reset stats */
3360         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3361         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3362         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3363         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3364         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3365
3366         /* Reset the wait for jiffies logic */
3367         priv->stats_time = 0;
3368
3369         return ret;
3370 }
3371
3372 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3373 {
3374         int ret = 0, timeout;
3375         enum fe_status status;
3376         struct cxd2841er_priv *priv = fe->demodulator_priv;
3377         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3378
3379         dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3380                  __func__, p->delivery_system, p->bandwidth_hz);
3381
3382         if (priv->flags & CXD2841ER_EARLY_TUNE)
3383                 cxd2841er_tuner_set(fe);
3384
3385         /* deconfigure/put demod to sleep on delsys switch if active */
3386         if (priv->state == STATE_ACTIVE_TC &&
3387             priv->system != p->delivery_system) {
3388                 dev_dbg(&priv->i2c->dev, "%s(): old_delsys=%d, new_delsys=%d -> sleep\n",
3389                          __func__, priv->system, p->delivery_system);
3390                 cxd2841er_sleep_tc(fe);
3391         }
3392
3393         if (p->delivery_system == SYS_DVBT) {
3394                 priv->system = SYS_DVBT;
3395                 switch (priv->state) {
3396                 case STATE_SLEEP_TC:
3397                         ret = cxd2841er_sleep_tc_to_active_t(
3398                                 priv, p->bandwidth_hz);
3399                         break;
3400                 case STATE_ACTIVE_TC:
3401                         ret = cxd2841er_retune_active(priv, p);
3402                         break;
3403                 default:
3404                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3405                                 __func__, priv->state);
3406                         ret = -EINVAL;
3407                 }
3408         } else if (p->delivery_system == SYS_DVBT2) {
3409                 priv->system = SYS_DVBT2;
3410                 cxd2841er_dvbt2_set_plp_config(priv,
3411                         (int)(p->stream_id > 255), p->stream_id);
3412                 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3413                 switch (priv->state) {
3414                 case STATE_SLEEP_TC:
3415                         ret = cxd2841er_sleep_tc_to_active_t2(priv,
3416                                 p->bandwidth_hz);
3417                         break;
3418                 case STATE_ACTIVE_TC:
3419                         ret = cxd2841er_retune_active(priv, p);
3420                         break;
3421                 default:
3422                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3423                                 __func__, priv->state);
3424                         ret = -EINVAL;
3425                 }
3426         } else if (p->delivery_system == SYS_ISDBT) {
3427                 priv->system = SYS_ISDBT;
3428                 switch (priv->state) {
3429                 case STATE_SLEEP_TC:
3430                         ret = cxd2841er_sleep_tc_to_active_i(
3431                                         priv, p->bandwidth_hz);
3432                         break;
3433                 case STATE_ACTIVE_TC:
3434                         ret = cxd2841er_retune_active(priv, p);
3435                         break;
3436                 default:
3437                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3438                                         __func__, priv->state);
3439                         ret = -EINVAL;
3440                 }
3441         } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3442                         p->delivery_system == SYS_DVBC_ANNEX_C) {
3443                 priv->system = SYS_DVBC_ANNEX_A;
3444                 /* correct bandwidth */
3445                 if (p->bandwidth_hz != 6000000 &&
3446                                 p->bandwidth_hz != 7000000 &&
3447                                 p->bandwidth_hz != 8000000) {
3448                         p->bandwidth_hz = 8000000;
3449                         dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3450                                         __func__, p->bandwidth_hz);
3451                 }
3452
3453                 switch (priv->state) {
3454                 case STATE_SLEEP_TC:
3455                         ret = cxd2841er_sleep_tc_to_active_c(
3456                                 priv, p->bandwidth_hz);
3457                         break;
3458                 case STATE_ACTIVE_TC:
3459                         ret = cxd2841er_retune_active(priv, p);
3460                         break;
3461                 default:
3462                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3463                                 __func__, priv->state);
3464                         ret = -EINVAL;
3465                 }
3466         } else {
3467                 dev_dbg(&priv->i2c->dev,
3468                         "%s(): invalid delivery system %d\n",
3469                         __func__, p->delivery_system);
3470                 ret = -EINVAL;
3471         }
3472         if (ret)
3473                 goto done;
3474
3475         if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3476                 cxd2841er_tuner_set(fe);
3477
3478         cxd2841er_tune_done(priv);
3479
3480         if (priv->flags & CXD2841ER_NO_WAIT_LOCK)
3481                 goto done;
3482
3483         timeout = 2500;
3484         while (timeout > 0) {
3485                 ret = cxd2841er_read_status_tc(fe, &status);
3486                 if (ret)
3487                         goto done;
3488                 if (status & FE_HAS_LOCK)
3489                         break;
3490                 msleep(20);
3491                 timeout -= 20;
3492         }
3493         if (timeout < 0)
3494                 dev_dbg(&priv->i2c->dev,
3495                         "%s(): LOCK wait timeout\n", __func__);
3496 done:
3497         return ret;
3498 }
3499
3500 static int cxd2841er_tune_s(struct dvb_frontend *fe,
3501                             bool re_tune,
3502                             unsigned int mode_flags,
3503                             unsigned int *delay,
3504                             enum fe_status *status)
3505 {
3506         int ret, carrier_offset;
3507         struct cxd2841er_priv *priv = fe->demodulator_priv;
3508         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3509
3510         dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3511         if (re_tune) {
3512                 ret = cxd2841er_set_frontend_s(fe);
3513                 if (ret)
3514                         return ret;
3515                 cxd2841er_read_status_s(fe, status);
3516                 if (*status & FE_HAS_LOCK) {
3517                         if (cxd2841er_get_carrier_offset_s_s2(
3518                                         priv, &carrier_offset))
3519                                 return -EINVAL;
3520                         p->frequency += carrier_offset;
3521                         ret = cxd2841er_set_frontend_s(fe);
3522                         if (ret)
3523                                 return ret;
3524                 }
3525         }
3526         *delay = HZ / 5;
3527         return cxd2841er_read_status_s(fe, status);
3528 }
3529
3530 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3531                              bool re_tune,
3532                              unsigned int mode_flags,
3533                              unsigned int *delay,
3534                              enum fe_status *status)
3535 {
3536         int ret, carrier_offset;
3537         struct cxd2841er_priv *priv = fe->demodulator_priv;
3538         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3539
3540         dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3541                         re_tune, p->bandwidth_hz);
3542         if (re_tune) {
3543                 ret = cxd2841er_set_frontend_tc(fe);
3544                 if (ret)
3545                         return ret;
3546                 cxd2841er_read_status_tc(fe, status);
3547                 if (*status & FE_HAS_LOCK) {
3548                         switch (priv->system) {
3549                         case SYS_ISDBT:
3550                                 ret = cxd2841er_get_carrier_offset_i(
3551                                                 priv, p->bandwidth_hz,
3552                                                 &carrier_offset);
3553                                 if (ret)
3554                                         return ret;
3555                                 break;
3556                         case SYS_DVBT:
3557                                 ret = cxd2841er_get_carrier_offset_t(
3558                                         priv, p->bandwidth_hz,
3559                                         &carrier_offset);
3560                                 if (ret)
3561                                         return ret;
3562                                 break;
3563                         case SYS_DVBT2:
3564                                 ret = cxd2841er_get_carrier_offset_t2(
3565                                         priv, p->bandwidth_hz,
3566                                         &carrier_offset);
3567                                 if (ret)
3568                                         return ret;
3569                                 break;
3570                         case SYS_DVBC_ANNEX_A:
3571                                 ret = cxd2841er_get_carrier_offset_c(
3572                                         priv, &carrier_offset);
3573                                 if (ret)
3574                                         return ret;
3575                                 break;
3576                         default:
3577                                 dev_dbg(&priv->i2c->dev,
3578                                         "%s(): invalid delivery system %d\n",
3579                                         __func__, priv->system);
3580                                 return -EINVAL;
3581                         }
3582                         dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3583                                 __func__, carrier_offset);
3584                         p->frequency += carrier_offset;
3585                         ret = cxd2841er_set_frontend_tc(fe);
3586                         if (ret)
3587                                 return ret;
3588                 }
3589         }
3590         *delay = HZ / 5;
3591         return cxd2841er_read_status_tc(fe, status);
3592 }
3593
3594 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3595 {
3596         struct cxd2841er_priv *priv = fe->demodulator_priv;
3597
3598         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3599         cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3600         cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3601         return 0;
3602 }
3603
3604 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3605 {
3606         struct cxd2841er_priv *priv = fe->demodulator_priv;
3607
3608         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3609
3610         if (priv->state == STATE_ACTIVE_TC) {
3611                 switch (priv->system) {
3612                 case SYS_DVBT:
3613                         cxd2841er_active_t_to_sleep_tc(priv);
3614                         break;
3615                 case SYS_DVBT2:
3616                         cxd2841er_active_t2_to_sleep_tc(priv);
3617                         break;
3618                 case SYS_ISDBT:
3619                         cxd2841er_active_i_to_sleep_tc(priv);
3620                         break;
3621                 case SYS_DVBC_ANNEX_A:
3622                         cxd2841er_active_c_to_sleep_tc(priv);
3623                         break;
3624                 default:
3625                         dev_warn(&priv->i2c->dev,
3626                                 "%s(): unknown delivery system %d\n",
3627                                 __func__, priv->system);
3628                 }
3629         }
3630         if (priv->state != STATE_SLEEP_TC) {
3631                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3632                         __func__, priv->state);
3633                 return -EINVAL;
3634         }
3635         return 0;
3636 }
3637
3638 static int cxd2841er_shutdown_tc(struct dvb_frontend *fe)
3639 {
3640         struct cxd2841er_priv *priv = fe->demodulator_priv;
3641
3642         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3643
3644         if (!cxd2841er_sleep_tc(fe))
3645                 cxd2841er_sleep_tc_to_shutdown(priv);
3646         return 0;
3647 }
3648
3649 static int cxd2841er_send_burst(struct dvb_frontend *fe,
3650                                 enum fe_sec_mini_cmd burst)
3651 {
3652         u8 data;
3653         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3654
3655         dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3656                 (burst == SEC_MINI_A ? "A" : "B"));
3657         if (priv->state != STATE_SLEEP_S &&
3658                         priv->state != STATE_ACTIVE_S) {
3659                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3660                         __func__, priv->state);
3661                 return -EINVAL;
3662         }
3663         data = (burst == SEC_MINI_A ? 0 : 1);
3664         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3665         cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3666         cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3667         return 0;
3668 }
3669
3670 static int cxd2841er_set_tone(struct dvb_frontend *fe,
3671                               enum fe_sec_tone_mode tone)
3672 {
3673         u8 data;
3674         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3675
3676         dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3677                 (tone == SEC_TONE_ON ? "On" : "Off"));
3678         if (priv->state != STATE_SLEEP_S &&
3679                         priv->state != STATE_ACTIVE_S) {
3680                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3681                         __func__, priv->state);
3682                 return -EINVAL;
3683         }
3684         data = (tone == SEC_TONE_ON ? 1 : 0);
3685         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3686         cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3687         return 0;
3688 }
3689
3690 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3691                                      struct dvb_diseqc_master_cmd *cmd)
3692 {
3693         int i;
3694         u8 data[12];
3695         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3696
3697         if (priv->state != STATE_SLEEP_S &&
3698                         priv->state != STATE_ACTIVE_S) {
3699                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3700                         __func__, priv->state);
3701                 return -EINVAL;
3702         }
3703         dev_dbg(&priv->i2c->dev,
3704                 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3705         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3706         /* DiDEqC enable */
3707         cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3708         /* cmd1 length & data */
3709         cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3710         memset(data, 0, sizeof(data));
3711         for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3712                 data[i] = cmd->msg[i];
3713         cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3714         /* repeat count for cmd1 */
3715         cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3716         /* repeat count for cmd2: always 0 */
3717         cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3718         /* start transmit */
3719         cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3720         /* wait for 1 sec timeout */
3721         for (i = 0; i < 50; i++) {
3722                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3723                 if (!data[0]) {
3724                         dev_dbg(&priv->i2c->dev,
3725                                 "%s(): DiSEqC cmd has been sent\n", __func__);
3726                         return 0;
3727                 }
3728                 msleep(20);
3729         }
3730         dev_dbg(&priv->i2c->dev,
3731                 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3732         return -ETIMEDOUT;
3733 }
3734
3735 static void cxd2841er_release(struct dvb_frontend *fe)
3736 {
3737         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3738
3739         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3740         kfree(priv);
3741 }
3742
3743 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3744 {
3745         struct cxd2841er_priv *priv = fe->demodulator_priv;
3746
3747         dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3748         cxd2841er_set_reg_bits(
3749                 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3750         return 0;
3751 }
3752
3753 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3754 {
3755         struct cxd2841er_priv *priv = fe->demodulator_priv;
3756
3757         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3758         return DVBFE_ALGO_HW;
3759 }
3760
3761 static void cxd2841er_init_stats(struct dvb_frontend *fe)
3762 {
3763         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3764
3765         p->strength.len = 1;
3766         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3767         p->cnr.len = 1;
3768         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3769         p->block_error.len = 1;
3770         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3771         p->post_bit_error.len = 1;
3772         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3773         p->post_bit_count.len = 1;
3774         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3775 }
3776
3777
3778 static int cxd2841er_init_s(struct dvb_frontend *fe)
3779 {
3780         struct cxd2841er_priv *priv = fe->demodulator_priv;
3781
3782         /* sanity. force demod to SHUTDOWN state */
3783         if (priv->state == STATE_SLEEP_S) {
3784                 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3785                                 __func__);
3786                 cxd2841er_sleep_s_to_shutdown(priv);
3787         } else if (priv->state == STATE_ACTIVE_S) {
3788                 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3789                                 __func__);
3790                 cxd2841er_active_s_to_sleep_s(priv);
3791                 cxd2841er_sleep_s_to_shutdown(priv);
3792         }
3793
3794         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3795         cxd2841er_shutdown_to_sleep_s(priv);
3796         /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3797         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3798         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3799
3800         cxd2841er_init_stats(fe);
3801
3802         return 0;
3803 }
3804
3805 static int cxd2841er_init_tc(struct dvb_frontend *fe)
3806 {
3807         struct cxd2841er_priv *priv = fe->demodulator_priv;
3808         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3809
3810         dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3811                         __func__, p->bandwidth_hz);
3812         cxd2841er_shutdown_to_sleep_tc(priv);
3813         /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 (0 for NO_AGCNEG */
3814         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3815         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb,
3816                 ((priv->flags & CXD2841ER_NO_AGCNEG) ? 0x00 : 0x40), 0x40);
3817         /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3818         cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3819         /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3820         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3821         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
3822                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80);
3823
3824         /* clear TSCFG bits 3+4 */
3825         if (priv->flags & CXD2841ER_TSBITS)
3826                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18);
3827
3828         cxd2841er_init_stats(fe);
3829
3830         return 0;
3831 }
3832
3833 static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3834 static struct dvb_frontend_ops cxd2841er_t_c_ops;
3835
3836 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3837                                              struct i2c_adapter *i2c,
3838                                              u8 system)
3839 {
3840         u8 chip_id = 0;
3841         const char *type;
3842         const char *name;
3843         struct cxd2841er_priv *priv = NULL;
3844
3845         /* allocate memory for the internal state */
3846         priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3847         if (!priv)
3848                 return NULL;
3849         priv->i2c = i2c;
3850         priv->config = cfg;
3851         priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3852         priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
3853         priv->xtal = cfg->xtal;
3854         priv->flags = cfg->flags;
3855         priv->frontend.demodulator_priv = priv;
3856         dev_info(&priv->i2c->dev,
3857                 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3858                 __func__, priv->i2c,
3859                 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3860         chip_id = cxd2841er_chip_id(priv);
3861         switch (chip_id) {
3862         case CXD2837ER_CHIP_ID:
3863                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3864                                 "Sony CXD2837ER DVB-T/T2/C demodulator");
3865                 name = "CXD2837ER";
3866                 type = "C/T/T2";
3867                 break;
3868         case CXD2838ER_CHIP_ID:
3869                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3870                                 "Sony CXD2838ER ISDB-T demodulator");
3871                 cxd2841er_t_c_ops.delsys[0] = SYS_ISDBT;
3872                 cxd2841er_t_c_ops.delsys[1] = SYS_UNDEFINED;
3873                 cxd2841er_t_c_ops.delsys[2] = SYS_UNDEFINED;
3874                 name = "CXD2838ER";
3875                 type = "ISDB-T";
3876                 break;
3877         case CXD2841ER_CHIP_ID:
3878                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3879                                 "Sony CXD2841ER DVB-T/T2/C demodulator");
3880                 name = "CXD2841ER";
3881                 type = "T/T2/C/ISDB-T";
3882                 break;
3883         case CXD2843ER_CHIP_ID:
3884                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3885                                 "Sony CXD2843ER DVB-T/T2/C/C2 demodulator");
3886                 name = "CXD2843ER";
3887                 type = "C/C2/T/T2";
3888                 break;
3889         case CXD2854ER_CHIP_ID:
3890                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3891                                 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3892                 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3893                 name = "CXD2854ER";
3894                 type = "C/C2/T/T2/ISDB-T";
3895                 break;
3896         default:
3897                 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3898                                 __func__, chip_id);
3899                 priv->frontend.demodulator_priv = NULL;
3900                 kfree(priv);
3901                 return NULL;
3902         }
3903
3904         /* create dvb_frontend */
3905         if (system == SYS_DVBS) {
3906                 memcpy(&priv->frontend.ops,
3907                         &cxd2841er_dvbs_s2_ops,
3908                         sizeof(struct dvb_frontend_ops));
3909                 type = "S/S2";
3910         } else {
3911                 memcpy(&priv->frontend.ops,
3912                         &cxd2841er_t_c_ops,
3913                         sizeof(struct dvb_frontend_ops));
3914         }
3915
3916         dev_info(&priv->i2c->dev,
3917                 "%s(): attaching %s DVB-%s frontend\n",
3918                 __func__, name, type);
3919         dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3920                 __func__, chip_id);
3921         return &priv->frontend;
3922 }
3923
3924 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3925                                         struct i2c_adapter *i2c)
3926 {
3927         return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3928 }
3929 EXPORT_SYMBOL_GPL(cxd2841er_attach_s);
3930
3931 struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
3932                                         struct i2c_adapter *i2c)
3933 {
3934         return cxd2841er_attach(cfg, i2c, 0);
3935 }
3936 EXPORT_SYMBOL_GPL(cxd2841er_attach_t_c);
3937
3938 static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3939         .delsys = { SYS_DVBS, SYS_DVBS2 },
3940         .info = {
3941                 .name           = "Sony CXD2841ER DVB-S/S2 demodulator",
3942                 .frequency_min_hz       =  500 * MHz,
3943                 .frequency_max_hz       = 2500 * MHz,
3944                 .symbol_rate_min = 1000000,
3945                 .symbol_rate_max = 45000000,
3946                 .symbol_rate_tolerance = 500,
3947                 .caps = FE_CAN_INVERSION_AUTO |
3948                         FE_CAN_FEC_AUTO |
3949                         FE_CAN_QPSK,
3950         },
3951         .init = cxd2841er_init_s,
3952         .sleep = cxd2841er_sleep_s,
3953         .release = cxd2841er_release,
3954         .set_frontend = cxd2841er_set_frontend_s,
3955         .get_frontend = cxd2841er_get_frontend,
3956         .read_status = cxd2841er_read_status_s,
3957         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3958         .get_frontend_algo = cxd2841er_get_algo,
3959         .set_tone = cxd2841er_set_tone,
3960         .diseqc_send_burst = cxd2841er_send_burst,
3961         .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3962         .tune = cxd2841er_tune_s
3963 };
3964
3965 static struct dvb_frontend_ops cxd2841er_t_c_ops = {
3966         .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
3967         .info = {
3968                 .name   = "", /* will set in attach function */
3969                 .caps = FE_CAN_FEC_1_2 |
3970                         FE_CAN_FEC_2_3 |
3971                         FE_CAN_FEC_3_4 |
3972                         FE_CAN_FEC_5_6 |
3973                         FE_CAN_FEC_7_8 |
3974                         FE_CAN_FEC_AUTO |
3975                         FE_CAN_QPSK |
3976                         FE_CAN_QAM_16 |
3977                         FE_CAN_QAM_32 |
3978                         FE_CAN_QAM_64 |
3979                         FE_CAN_QAM_128 |
3980                         FE_CAN_QAM_256 |
3981                         FE_CAN_QAM_AUTO |
3982                         FE_CAN_TRANSMISSION_MODE_AUTO |
3983                         FE_CAN_GUARD_INTERVAL_AUTO |
3984                         FE_CAN_HIERARCHY_AUTO |
3985                         FE_CAN_MUTE_TS |
3986                         FE_CAN_2G_MODULATION,
3987                 .frequency_min_hz =   42 * MHz,
3988                 .frequency_max_hz = 1002 * MHz,
3989                 .symbol_rate_min = 870000,
3990                 .symbol_rate_max = 11700000
3991         },
3992         .init = cxd2841er_init_tc,
3993         .sleep = cxd2841er_shutdown_tc,
3994         .release = cxd2841er_release,
3995         .set_frontend = cxd2841er_set_frontend_tc,
3996         .get_frontend = cxd2841er_get_frontend,
3997         .read_status = cxd2841er_read_status_tc,
3998         .tune = cxd2841er_tune_tc,
3999         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
4000         .get_frontend_algo = cxd2841er_get_algo
4001 };
4002
4003 MODULE_DESCRIPTION("Sony CXD2837/38/41/43/54ER DVB-C/C2/T/T2/S/S2 demodulator driver");
4004 MODULE_AUTHOR("Sergey Kozlov <[email protected]>, Abylay Ospan <[email protected]>");
4005 MODULE_LICENSE("GPL");