drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_drv.h>
  32 #include <drm/drm_fb_helper.h>
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "atom.h"
  36
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/slab.h>
  39 #include <linux/uaccess.h>
  40 #include <linux/pci.h>
  41 #include <linux/pm_runtime.h>
  42 #include "amdgpu_amdkfd.h"
  43 #include "amdgpu_gem.h"
  44 #include "amdgpu_display.h"
  45 #include "amdgpu_ras.h"
  46 #include "amd_pcie.h"
  47
  48 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  49 {
  50         struct amdgpu_gpu_instance *gpu_instance;
  51         int i;
  52
  53         mutex_lock(&mgpu_info.mutex);
  54
  55         for (i = 0; i < mgpu_info.num_gpu; i++) {
  56                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  57                 if (gpu_instance->adev == adev) {
  58                         mgpu_info.gpu_ins[i] =
  59                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  60                         mgpu_info.num_gpu--;
  61                         if (adev->flags & AMD_IS_APU)
  62                                 mgpu_info.num_apu--;
  63                         else
  64                                 mgpu_info.num_dgpu--;
  65                         break;
  66                 }
  67         }
  68
  69         mutex_unlock(&mgpu_info.mutex);
  70 }
  71
  72 /**
  73  * amdgpu_driver_unload_kms - Main unload function for KMS.
  74  *
  75  * @dev: drm dev pointer
  76  *
  77  * This is the main unload function for KMS (all asics).
  78  * Returns 0 on success.
  79  */
  80 void amdgpu_driver_unload_kms(struct drm_device *dev)
  81 {
  82         struct amdgpu_device *adev = drm_to_adev(dev);
  83
  84         if (adev == NULL)
  85                 return;
  86
  87         amdgpu_unregister_gpu_instance(adev);
  88
  89         if (adev->rmmio == NULL)
  90                 return;
  91
  92         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
  93                 DRM_WARN("smart shift update failed\n");
  94
  95         amdgpu_acpi_fini(adev);
  96         amdgpu_device_fini_hw(adev);
  97 }
  98
  99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 100 {
 101         struct amdgpu_gpu_instance *gpu_instance;
 102
 103         mutex_lock(&mgpu_info.mutex);
 104
 105         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 106                 DRM_ERROR("Cannot register more gpu instance\n");
 107                 mutex_unlock(&mgpu_info.mutex);
 108                 return;
 109         }
 110
 111         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 112         gpu_instance->adev = adev;
 113         gpu_instance->mgpu_fan_enabled = 0;
 114
 115         mgpu_info.num_gpu++;
 116         if (adev->flags & AMD_IS_APU)
 117                 mgpu_info.num_apu++;
 118         else
 119                 mgpu_info.num_dgpu++;
 120
 121         mutex_unlock(&mgpu_info.mutex);
 122 }
 123
 124 /**
 125  * amdgpu_driver_load_kms - Main load function for KMS.
 126  *
 127  * @adev: pointer to struct amdgpu_device
 128  * @flags: device flags
 129  *
 130  * This is the main load function for KMS (all asics).
 131  * Returns 0 on success, error on failure.
 132  */
 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 134 {
 135         struct drm_device *dev;
 136         int r, acpi_status;
 137
 138         dev = adev_to_drm(adev);
 139
 140         /* amdgpu_device_init should report only fatal error
 141          * like memory allocation failure or iomapping failure,
 142          * or memory manager initialization failure, it must
 143          * properly initialize the GPU MC controller and permit
 144          * VRAM allocation
 145          */
 146         r = amdgpu_device_init(adev, flags);
 147         if (r) {
 148                 dev_err(dev->dev, "Fatal error during GPU init\n");
 149                 goto out;
 150         }
 151
 152         adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
 153         if (amdgpu_device_supports_px(dev) &&
 154             (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */
 155                 adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
 156                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 157         } else if (amdgpu_device_supports_boco(dev) &&
 158                    (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */
 159                 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
 160                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 161         } else if (amdgpu_device_supports_baco(dev) &&
 162                    (amdgpu_runtime_pm != 0)) {
 163                 switch (adev->asic_type) {
 164                 case CHIP_VEGA20:
 165                 case CHIP_ARCTURUS:
 166                         /* enable BACO as runpm mode if runpm=1 */
 167                         if (amdgpu_runtime_pm > 0)
 168                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 169                         break;
 170                 case CHIP_VEGA10:
 171                         /* enable BACO as runpm mode if noretry=0 */
 172                         if (!adev->gmc.noretry)
 173                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 174                         break;
 175                 default:
 176                         /* enable BACO as runpm mode on CI+ */
 177                         adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 178                         break;
 179                 }
 180
 181                 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
 182                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 183         }
 184
 185         /* Call ACPI methods: require modeset init
 186          * but failure is not fatal
 187          */
 188
 189         acpi_status = amdgpu_acpi_init(adev);
 190         if (acpi_status)
 191                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 192
 193         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
 194                 DRM_WARN("smart shift update failed\n");
 195
 196 out:
 197         if (r)
 198                 amdgpu_driver_unload_kms(dev);
 199
 200         return r;
 201 }
 202
 203 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 204                                 struct drm_amdgpu_query_fw *query_fw,
 205                                 struct amdgpu_device *adev)
 206 {
 207         switch (query_fw->fw_type) {
 208         case AMDGPU_INFO_FW_VCE:
 209                 fw_info->ver = adev->vce.fw_version;
 210                 fw_info->feature = adev->vce.fb_version;
 211                 break;
 212         case AMDGPU_INFO_FW_UVD:
 213                 fw_info->ver = adev->uvd.fw_version;
 214                 fw_info->feature = 0;
 215                 break;
 216         case AMDGPU_INFO_FW_VCN:
 217                 fw_info->ver = adev->vcn.fw_version;
 218                 fw_info->feature = 0;
 219                 break;
 220         case AMDGPU_INFO_FW_GMC:
 221                 fw_info->ver = adev->gmc.fw_version;
 222                 fw_info->feature = 0;
 223                 break;
 224         case AMDGPU_INFO_FW_GFX_ME:
 225                 fw_info->ver = adev->gfx.me_fw_version;
 226                 fw_info->feature = adev->gfx.me_feature_version;
 227                 break;
 228         case AMDGPU_INFO_FW_GFX_PFP:
 229                 fw_info->ver = adev->gfx.pfp_fw_version;
 230                 fw_info->feature = adev->gfx.pfp_feature_version;
 231                 break;
 232         case AMDGPU_INFO_FW_GFX_CE:
 233                 fw_info->ver = adev->gfx.ce_fw_version;
 234                 fw_info->feature = adev->gfx.ce_feature_version;
 235                 break;
 236         case AMDGPU_INFO_FW_GFX_RLC:
 237                 fw_info->ver = adev->gfx.rlc_fw_version;
 238                 fw_info->feature = adev->gfx.rlc_feature_version;
 239                 break;
 240         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 241                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 242                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 243                 break;
 244         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 245                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 246                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 247                 break;
 248         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 249                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 250                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 251                 break;
 252         case AMDGPU_INFO_FW_GFX_RLCP:
 253                 fw_info->ver = adev->gfx.rlcp_ucode_version;
 254                 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
 255                 break;
 256         case AMDGPU_INFO_FW_GFX_RLCV:
 257                 fw_info->ver = adev->gfx.rlcv_ucode_version;
 258                 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
 259                 break;
 260         case AMDGPU_INFO_FW_GFX_MEC:
 261                 if (query_fw->index == 0) {
 262                         fw_info->ver = adev->gfx.mec_fw_version;
 263                         fw_info->feature = adev->gfx.mec_feature_version;
 264                 } else if (query_fw->index == 1) {
 265                         fw_info->ver = adev->gfx.mec2_fw_version;
 266                         fw_info->feature = adev->gfx.mec2_feature_version;
 267                 } else
 268                         return -EINVAL;
 269                 break;
 270         case AMDGPU_INFO_FW_SMC:
 271                 fw_info->ver = adev->pm.fw_version;
 272                 fw_info->feature = 0;
 273                 break;
 274         case AMDGPU_INFO_FW_TA:
 275                 switch (query_fw->index) {
 276                 case TA_FW_TYPE_PSP_XGMI:
 277                         fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
 278                         fw_info->feature = adev->psp.xgmi_context.context
 279                                                    .bin_desc.feature_version;
 280                         break;
 281                 case TA_FW_TYPE_PSP_RAS:
 282                         fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
 283                         fw_info->feature = adev->psp.ras_context.context
 284                                                    .bin_desc.feature_version;
 285                         break;
 286                 case TA_FW_TYPE_PSP_HDCP:
 287                         fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
 288                         fw_info->feature = adev->psp.hdcp_context.context
 289                                                    .bin_desc.feature_version;
 290                         break;
 291                 case TA_FW_TYPE_PSP_DTM:
 292                         fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
 293                         fw_info->feature = adev->psp.dtm_context.context
 294                                                    .bin_desc.feature_version;
 295                         break;
 296                 case TA_FW_TYPE_PSP_RAP:
 297                         fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
 298                         fw_info->feature = adev->psp.rap_context.context
 299                                                    .bin_desc.feature_version;
 300                         break;
 301                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 302                         fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
 303                         fw_info->feature =
 304                                 adev->psp.securedisplay_context.context.bin_desc
 305                                         .feature_version;
 306                         break;
 307                 default:
 308                         return -EINVAL;
 309                 }
 310                 break;
 311         case AMDGPU_INFO_FW_SDMA:
 312                 if (query_fw->index >= adev->sdma.num_instances)
 313                         return -EINVAL;
 314                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 315                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 316                 break;
 317         case AMDGPU_INFO_FW_SOS:
 318                 fw_info->ver = adev->psp.sos.fw_version;
 319                 fw_info->feature = adev->psp.sos.feature_version;
 320                 break;
 321         case AMDGPU_INFO_FW_ASD:
 322                 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
 323                 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
 324                 break;
 325         case AMDGPU_INFO_FW_DMCU:
 326                 fw_info->ver = adev->dm.dmcu_fw_version;
 327                 fw_info->feature = 0;
 328                 break;
 329         case AMDGPU_INFO_FW_DMCUB:
 330                 fw_info->ver = adev->dm.dmcub_fw_version;
 331                 fw_info->feature = 0;
 332                 break;
 333         case AMDGPU_INFO_FW_TOC:
 334                 fw_info->ver = adev->psp.toc.fw_version;
 335                 fw_info->feature = adev->psp.toc.feature_version;
 336                 break;
 337         case AMDGPU_INFO_FW_CAP:
 338                 fw_info->ver = adev->psp.cap_fw_version;
 339                 fw_info->feature = adev->psp.cap_feature_version;
 340                 break;
 341         case AMDGPU_INFO_FW_MES_KIQ:
 342                 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
 343                 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK)
 344                                         >> AMDGPU_MES_FEAT_VERSION_SHIFT;
 345                 break;
 346         case AMDGPU_INFO_FW_MES:
 347                 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
 348                 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK)
 349                                         >> AMDGPU_MES_FEAT_VERSION_SHIFT;
 350                 break;
 351         case AMDGPU_INFO_FW_IMU:
 352                 fw_info->ver = adev->gfx.imu_fw_version;
 353                 fw_info->feature = 0;
 354                 break;
 355         case AMDGPU_INFO_FW_VPE:
 356                 fw_info->ver = adev->vpe.fw_version;
 357                 fw_info->feature = adev->vpe.feature_version;
 358                 break;
 359         default:
 360                 return -EINVAL;
 361         }
 362         return 0;
 363 }
 364
 365 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 366                              struct drm_amdgpu_info *info,
 367                              struct drm_amdgpu_info_hw_ip *result)
 368 {
 369         uint32_t ib_start_alignment = 0;
 370         uint32_t ib_size_alignment = 0;
 371         enum amd_ip_block_type type;
 372         unsigned int num_rings = 0;
 373         unsigned int i, j;
 374
 375         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 376                 return -EINVAL;
 377
 378         switch (info->query_hw_ip.type) {
 379         case AMDGPU_HW_IP_GFX:
 380                 type = AMD_IP_BLOCK_TYPE_GFX;
 381                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 382                         if (adev->gfx.gfx_ring[i].sched.ready)
 383                                 ++num_rings;
 384                 ib_start_alignment = 32;
 385                 ib_size_alignment = 32;
 386                 break;
 387         case AMDGPU_HW_IP_COMPUTE:
 388                 type = AMD_IP_BLOCK_TYPE_GFX;
 389                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 390                         if (adev->gfx.compute_ring[i].sched.ready)
 391                                 ++num_rings;
 392                 ib_start_alignment = 32;
 393                 ib_size_alignment = 32;
 394                 break;
 395         case AMDGPU_HW_IP_DMA:
 396                 type = AMD_IP_BLOCK_TYPE_SDMA;
 397                 for (i = 0; i < adev->sdma.num_instances; i++)
 398                         if (adev->sdma.instance[i].ring.sched.ready)
 399                                 ++num_rings;
 400                 ib_start_alignment = 256;
 401                 ib_size_alignment = 4;
 402                 break;
 403         case AMDGPU_HW_IP_UVD:
 404                 type = AMD_IP_BLOCK_TYPE_UVD;
 405                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 406                         if (adev->uvd.harvest_config & (1 << i))
 407                                 continue;
 408
 409                         if (adev->uvd.inst[i].ring.sched.ready)
 410                                 ++num_rings;
 411                 }
 412                 ib_start_alignment = 64;
 413                 ib_size_alignment = 64;
 414                 break;
 415         case AMDGPU_HW_IP_VCE:
 416                 type = AMD_IP_BLOCK_TYPE_VCE;
 417                 for (i = 0; i < adev->vce.num_rings; i++)
 418                         if (adev->vce.ring[i].sched.ready)
 419                                 ++num_rings;
 420                 ib_start_alignment = 4;
 421                 ib_size_alignment = 1;
 422                 break;
 423         case AMDGPU_HW_IP_UVD_ENC:
 424                 type = AMD_IP_BLOCK_TYPE_UVD;
 425                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 426                         if (adev->uvd.harvest_config & (1 << i))
 427                                 continue;
 428
 429                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 430                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 431                                         ++num_rings;
 432                 }
 433                 ib_start_alignment = 64;
 434                 ib_size_alignment = 64;
 435                 break;
 436         case AMDGPU_HW_IP_VCN_DEC:
 437                 type = AMD_IP_BLOCK_TYPE_VCN;
 438                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 439                         if (adev->vcn.harvest_config & (1 << i))
 440                                 continue;
 441
 442                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 443                                 ++num_rings;
 444                 }
 445                 ib_start_alignment = 16;
 446                 ib_size_alignment = 16;
 447                 break;
 448         case AMDGPU_HW_IP_VCN_ENC:
 449                 type = AMD_IP_BLOCK_TYPE_VCN;
 450                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 451                         if (adev->vcn.harvest_config & (1 << i))
 452                                 continue;
 453
 454                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 455                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 456                                         ++num_rings;
 457                 }
 458                 ib_start_alignment = 64;
 459                 ib_size_alignment = 1;
 460                 break;
 461         case AMDGPU_HW_IP_VCN_JPEG:
 462                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 463                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 464
 465                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 466                         if (adev->jpeg.harvest_config & (1 << i))
 467                                 continue;
 468
 469                         for (j = 0; j < adev->jpeg.num_jpeg_rings; j++)
 470                                 if (adev->jpeg.inst[i].ring_dec[j].sched.ready)
 471                                         ++num_rings;
 472                 }
 473                 ib_start_alignment = 16;
 474                 ib_size_alignment = 16;
 475                 break;
 476         case AMDGPU_HW_IP_VPE:
 477                 type = AMD_IP_BLOCK_TYPE_VPE;
 478                 if (adev->vpe.ring.sched.ready)
 479                         ++num_rings;
 480                 ib_start_alignment = 256;
 481                 ib_size_alignment = 4;
 482                 break;
 483         default:
 484                 return -EINVAL;
 485         }
 486
 487         for (i = 0; i < adev->num_ip_blocks; i++)
 488                 if (adev->ip_blocks[i].version->type == type &&
 489                     adev->ip_blocks[i].status.valid)
 490                         break;
 491
 492         if (i == adev->num_ip_blocks)
 493                 return 0;
 494
 495         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 496                         num_rings);
 497
 498         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 499         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 500
 501         if (adev->asic_type >= CHIP_VEGA10) {
 502                 switch (type) {
 503                 case AMD_IP_BLOCK_TYPE_GFX:
 504                         result->ip_discovery_version = adev->ip_versions[GC_HWIP][0];
 505                         break;
 506                 case AMD_IP_BLOCK_TYPE_SDMA:
 507                         result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0];
 508                         break;
 509                 case AMD_IP_BLOCK_TYPE_UVD:
 510                 case AMD_IP_BLOCK_TYPE_VCN:
 511                 case AMD_IP_BLOCK_TYPE_JPEG:
 512                         result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0];
 513                         break;
 514                 case AMD_IP_BLOCK_TYPE_VCE:
 515                         result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0];
 516                         break;
 517                 default:
 518                         result->ip_discovery_version = 0;
 519                         break;
 520                 }
 521         } else {
 522                 result->ip_discovery_version = 0;
 523         }
 524         result->capabilities_flags = 0;
 525         result->available_rings = (1 << num_rings) - 1;
 526         result->ib_start_alignment = ib_start_alignment;
 527         result->ib_size_alignment = ib_size_alignment;
 528         return 0;
 529 }
 530
 531 /*
 532  * Userspace get information ioctl
 533  */
 534 /**
 535  * amdgpu_info_ioctl - answer a device specific request.
 536  *
 537  * @dev: drm device pointer
 538  * @data: request object
 539  * @filp: drm filp
 540  *
 541  * This function is used to pass device specific parameters to the userspace
 542  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 543  * etc. (all asics).
 544  * Returns 0 on success, -EINVAL on failure.
 545  */
 546 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 547 {
 548         struct amdgpu_device *adev = drm_to_adev(dev);
 549         struct drm_amdgpu_info *info = data;
 550         struct amdgpu_mode_info *minfo = &adev->mode_info;
 551         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 552         uint32_t size = info->return_size;
 553         struct drm_crtc *crtc;
 554         uint32_t ui32 = 0;
 555         uint64_t ui64 = 0;
 556         int i, found;
 557         int ui32_size = sizeof(ui32);
 558
 559         if (!info->return_size || !info->return_pointer)
 560                 return -EINVAL;
 561
 562         switch (info->query) {
 563         case AMDGPU_INFO_ACCEL_WORKING:
 564                 ui32 = adev->accel_working;
 565                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 566         case AMDGPU_INFO_CRTC_FROM_ID:
 567                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 568                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 569                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 570                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 571
 572                                 ui32 = amdgpu_crtc->crtc_id;
 573                                 found = 1;
 574                                 break;
 575                         }
 576                 }
 577                 if (!found) {
 578                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 579                         return -EINVAL;
 580                 }
 581                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 582         case AMDGPU_INFO_HW_IP_INFO: {
 583                 struct drm_amdgpu_info_hw_ip ip = {};
 584                 int ret;
 585
 586                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 587                 if (ret)
 588                         return ret;
 589
 590                 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
 591                 return ret ? -EFAULT : 0;
 592         }
 593         case AMDGPU_INFO_HW_IP_COUNT: {
 594                 enum amd_ip_block_type type;
 595                 uint32_t count = 0;
 596
 597                 switch (info->query_hw_ip.type) {
 598                 case AMDGPU_HW_IP_GFX:
 599                         type = AMD_IP_BLOCK_TYPE_GFX;
 600                         break;
 601                 case AMDGPU_HW_IP_COMPUTE:
 602                         type = AMD_IP_BLOCK_TYPE_GFX;
 603                         break;
 604                 case AMDGPU_HW_IP_DMA:
 605                         type = AMD_IP_BLOCK_TYPE_SDMA;
 606                         break;
 607                 case AMDGPU_HW_IP_UVD:
 608                         type = AMD_IP_BLOCK_TYPE_UVD;
 609                         break;
 610                 case AMDGPU_HW_IP_VCE:
 611                         type = AMD_IP_BLOCK_TYPE_VCE;
 612                         break;
 613                 case AMDGPU_HW_IP_UVD_ENC:
 614                         type = AMD_IP_BLOCK_TYPE_UVD;
 615                         break;
 616                 case AMDGPU_HW_IP_VCN_DEC:
 617                 case AMDGPU_HW_IP_VCN_ENC:
 618                         type = AMD_IP_BLOCK_TYPE_VCN;
 619                         break;
 620                 case AMDGPU_HW_IP_VCN_JPEG:
 621                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 622                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 623                         break;
 624                 default:
 625                         return -EINVAL;
 626                 }
 627
 628                 for (i = 0; i < adev->num_ip_blocks; i++)
 629                         if (adev->ip_blocks[i].version->type == type &&
 630                             adev->ip_blocks[i].status.valid &&
 631                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 632                                 count++;
 633
 634                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 635         }
 636         case AMDGPU_INFO_TIMESTAMP:
 637                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 638                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 639         case AMDGPU_INFO_FW_VERSION: {
 640                 struct drm_amdgpu_info_firmware fw_info;
 641                 int ret;
 642
 643                 /* We only support one instance of each IP block right now. */
 644                 if (info->query_fw.ip_instance != 0)
 645                         return -EINVAL;
 646
 647                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 648                 if (ret)
 649                         return ret;
 650
 651                 return copy_to_user(out, &fw_info,
 652                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 653         }
 654         case AMDGPU_INFO_NUM_BYTES_MOVED:
 655                 ui64 = atomic64_read(&adev->num_bytes_moved);
 656                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 657         case AMDGPU_INFO_NUM_EVICTIONS:
 658                 ui64 = atomic64_read(&adev->num_evictions);
 659                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 660         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 661                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 662                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 663         case AMDGPU_INFO_VRAM_USAGE:
 664                 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 665                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 666         case AMDGPU_INFO_VIS_VRAM_USAGE:
 667                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 668                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 669         case AMDGPU_INFO_GTT_USAGE:
 670                 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
 671                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 672         case AMDGPU_INFO_GDS_CONFIG: {
 673                 struct drm_amdgpu_info_gds gds_info;
 674
 675                 memset(&gds_info, 0, sizeof(gds_info));
 676                 gds_info.compute_partition_size = adev->gds.gds_size;
 677                 gds_info.gds_total_size = adev->gds.gds_size;
 678                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 679                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 680                 return copy_to_user(out, &gds_info,
 681                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 682         }
 683         case AMDGPU_INFO_VRAM_GTT: {
 684                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 685
 686                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 687                         atomic64_read(&adev->vram_pin_size) -
 688                         AMDGPU_VM_RESERVED_VRAM;
 689                 vram_gtt.vram_cpu_accessible_size =
 690                         min(adev->gmc.visible_vram_size -
 691                             atomic64_read(&adev->visible_pin_size),
 692                             vram_gtt.vram_size);
 693                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 694                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 695                 return copy_to_user(out, &vram_gtt,
 696                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 697         }
 698         case AMDGPU_INFO_MEMORY: {
 699                 struct drm_amdgpu_memory_info mem;
 700                 struct ttm_resource_manager *gtt_man =
 701                         &adev->mman.gtt_mgr.manager;
 702                 struct ttm_resource_manager *vram_man =
 703                         &adev->mman.vram_mgr.manager;
 704
 705                 memset(&mem, 0, sizeof(mem));
 706                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 707                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 708                         atomic64_read(&adev->vram_pin_size) -
 709                         AMDGPU_VM_RESERVED_VRAM;
 710                 mem.vram.heap_usage =
 711                         ttm_resource_manager_usage(vram_man);
 712                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 713
 714                 mem.cpu_accessible_vram.total_heap_size =
 715                         adev->gmc.visible_vram_size;
 716                 mem.cpu_accessible_vram.usable_heap_size =
 717                         min(adev->gmc.visible_vram_size -
 718                             atomic64_read(&adev->visible_pin_size),
 719                             mem.vram.usable_heap_size);
 720                 mem.cpu_accessible_vram.heap_usage =
 721                         amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 722                 mem.cpu_accessible_vram.max_allocation =
 723                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 724
 725                 mem.gtt.total_heap_size = gtt_man->size;
 726                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 727                         atomic64_read(&adev->gart_pin_size);
 728                 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
 729                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 730
 731                 return copy_to_user(out, &mem,
 732                                     min((size_t)size, sizeof(mem)))
 733                                     ? -EFAULT : 0;
 734         }
 735         case AMDGPU_INFO_READ_MMR_REG: {
 736                 unsigned int n, alloc_size;
 737                 uint32_t *regs;
 738                 unsigned int se_num = (info->read_mmr_reg.instance >>
 739                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 740                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 741                 unsigned int sh_num = (info->read_mmr_reg.instance >>
 742                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 743                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 744
 745                 /* set full masks if the userspace set all bits
 746                  * in the bitfields
 747                  */
 748                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 749                         se_num = 0xffffffff;
 750                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 751                         return -EINVAL;
 752                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 753                         sh_num = 0xffffffff;
 754                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 755                         return -EINVAL;
 756
 757                 if (info->read_mmr_reg.count > 128)
 758                         return -EINVAL;
 759
 760                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 761                 if (!regs)
 762                         return -ENOMEM;
 763                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 764
 765                 amdgpu_gfx_off_ctrl(adev, false);
 766                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 767                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 768                                                       info->read_mmr_reg.dword_offset + i,
 769                                                       &regs[i])) {
 770                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 771                                               info->read_mmr_reg.dword_offset + i);
 772                                 kfree(regs);
 773                                 amdgpu_gfx_off_ctrl(adev, true);
 774                                 return -EFAULT;
 775                         }
 776                 }
 777                 amdgpu_gfx_off_ctrl(adev, true);
 778                 n = copy_to_user(out, regs, min(size, alloc_size));
 779                 kfree(regs);
 780                 return n ? -EFAULT : 0;
 781         }
 782         case AMDGPU_INFO_DEV_INFO: {
 783                 struct drm_amdgpu_info_device *dev_info;
 784                 uint64_t vm_size;
 785                 uint32_t pcie_gen_mask;
 786                 int ret;
 787
 788                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 789                 if (!dev_info)
 790                         return -ENOMEM;
 791
 792                 dev_info->device_id = adev->pdev->device;
 793                 dev_info->chip_rev = adev->rev_id;
 794                 dev_info->external_rev = adev->external_rev_id;
 795                 dev_info->pci_rev = adev->pdev->revision;
 796                 dev_info->family = adev->family;
 797                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 798                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 799                 /* return all clocks in KHz */
 800                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 801                 if (adev->pm.dpm_enabled) {
 802                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 803                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 804                         dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;
 805                         dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;
 806                 } else {
 807                         dev_info->max_engine_clock =
 808                                 dev_info->min_engine_clock =
 809                                         adev->clock.default_sclk * 10;
 810                         dev_info->max_memory_clock =
 811                                 dev_info->min_memory_clock =
 812                                         adev->clock.default_mclk * 10;
 813                 }
 814                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 815                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 816                         adev->gfx.config.max_shader_engines;
 817                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 818                 dev_info->ids_flags = 0;
 819                 if (adev->flags & AMD_IS_APU)
 820                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 821                 if (adev->gfx.mcbp)
 822                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 823                 if (amdgpu_is_tmz(adev))
 824                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 825                 if (adev->gfx.config.ta_cntl2_truncate_coord_mode)
 826                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;
 827
 828                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 829                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 830
 831                 /* Older VCE FW versions are buggy and can handle only 40bits */
 832                 if (adev->vce.fw_version &&
 833                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 834                         vm_size = min(vm_size, 1ULL << 40);
 835
 836                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 837                 dev_info->virtual_address_max =
 838                         min(vm_size, AMDGPU_GMC_HOLE_START);
 839
 840                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 841                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 842                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 843                 }
 844                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 845                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 846                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 847                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 848                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 849                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 850                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 851                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 852                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 853                        sizeof(adev->gfx.cu_info.bitmap));
 854                 dev_info->vram_type = adev->gmc.vram_type;
 855                 dev_info->vram_bit_width = adev->gmc.vram_width;
 856                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 857                 dev_info->gc_double_offchip_lds_buf =
 858                         adev->gfx.config.double_offchip_lds_buf;
 859                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 860                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 861                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 862                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 863                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 864                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 865                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 866
 867                 if (adev->family >= AMDGPU_FAMILY_NV)
 868                         dev_info->pa_sc_tile_steering_override =
 869                                 adev->gfx.config.pa_sc_tile_steering_override;
 870
 871                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 872
 873                 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */
 874                 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16);
 875                 dev_info->pcie_gen = fls(pcie_gen_mask);
 876                 dev_info->pcie_num_lanes =
 877                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :
 878                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
 879                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :
 880                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :
 881                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
 882                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
 883
 884                 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
 885                 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;
 886                 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
 887                 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
 888                 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *
 889                                             adev->gfx.config.gc_gl1c_per_sa;
 890                 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
 891                 dev_info->mall_size = adev->gmc.mall_size;
 892
 893
 894                 if (adev->gfx.funcs->get_gfx_shadow_info) {
 895                         struct amdgpu_gfx_shadow_info shadow_info;
 896
 897                         ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info);
 898                         if (!ret) {
 899                                 dev_info->shadow_size = shadow_info.shadow_size;
 900                                 dev_info->shadow_alignment = shadow_info.shadow_alignment;
 901                                 dev_info->csa_size = shadow_info.csa_size;
 902                                 dev_info->csa_alignment = shadow_info.csa_alignment;
 903                         }
 904                 }
 905
 906                 ret = copy_to_user(out, dev_info,
 907                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 908                 kfree(dev_info);
 909                 return ret;
 910         }
 911         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 912                 unsigned int i;
 913                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 914                 struct amd_vce_state *vce_state;
 915
 916                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 917                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 918                         if (vce_state) {
 919                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 920                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 921                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 922                                 vce_clk_table.num_valid_entries++;
 923                         }
 924                 }
 925
 926                 return copy_to_user(out, &vce_clk_table,
 927                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 928         }
 929         case AMDGPU_INFO_VBIOS: {
 930                 uint32_t bios_size = adev->bios_size;
 931
 932                 switch (info->vbios_info.type) {
 933                 case AMDGPU_INFO_VBIOS_SIZE:
 934                         return copy_to_user(out, &bios_size,
 935                                         min((size_t)size, sizeof(bios_size)))
 936                                         ? -EFAULT : 0;
 937                 case AMDGPU_INFO_VBIOS_IMAGE: {
 938                         uint8_t *bios;
 939                         uint32_t bios_offset = info->vbios_info.offset;
 940
 941                         if (bios_offset >= bios_size)
 942                                 return -EINVAL;
 943
 944                         bios = adev->bios + bios_offset;
 945                         return copy_to_user(out, bios,
 946                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 947                                         ? -EFAULT : 0;
 948                 }
 949                 case AMDGPU_INFO_VBIOS_INFO: {
 950                         struct drm_amdgpu_info_vbios vbios_info = {};
 951                         struct atom_context *atom_context;
 952
 953                         atom_context = adev->mode_info.atom_context;
 954                         memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
 955                         memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
 956                         vbios_info.version = atom_context->version;
 957                         memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
 958                                                 sizeof(atom_context->vbios_ver_str));
 959                         memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
 960
 961                         return copy_to_user(out, &vbios_info,
 962                                                 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
 963                 }
 964                 default:
 965                         DRM_DEBUG_KMS("Invalid request %d\n",
 966                                         info->vbios_info.type);
 967                         return -EINVAL;
 968                 }
 969         }
 970         case AMDGPU_INFO_NUM_HANDLES: {
 971                 struct drm_amdgpu_info_num_handles handle;
 972
 973                 switch (info->query_hw_ip.type) {
 974                 case AMDGPU_HW_IP_UVD:
 975                         /* Starting Polaris, we support unlimited UVD handles */
 976                         if (adev->asic_type < CHIP_POLARIS10) {
 977                                 handle.uvd_max_handles = adev->uvd.max_handles;
 978                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 979
 980                                 return copy_to_user(out, &handle,
 981                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 982                         } else {
 983                                 return -ENODATA;
 984                         }
 985
 986                         break;
 987                 default:
 988                         return -EINVAL;
 989                 }
 990         }
 991         case AMDGPU_INFO_SENSOR: {
 992                 if (!adev->pm.dpm_enabled)
 993                         return -ENOENT;
 994
 995                 switch (info->sensor_info.type) {
 996                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 997                         /* get sclk in Mhz */
 998                         if (amdgpu_dpm_read_sensor(adev,
 999                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
1000                                                    (void *)&ui32, &ui32_size)) {
1001                                 return -EINVAL;
1002                         }
1003                         ui32 /= 100;
1004                         break;
1005                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
1006                         /* get mclk in Mhz */
1007                         if (amdgpu_dpm_read_sensor(adev,
1008                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
1009                                                    (void *)&ui32, &ui32_size)) {
1010                                 return -EINVAL;
1011                         }
1012                         ui32 /= 100;
1013                         break;
1014                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
1015                         /* get temperature in millidegrees C */
1016                         if (amdgpu_dpm_read_sensor(adev,
1017                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
1018                                                    (void *)&ui32, &ui32_size)) {
1019                                 return -EINVAL;
1020                         }
1021                         break;
1022                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
1023                         /* get GPU load */
1024                         if (amdgpu_dpm_read_sensor(adev,
1025                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
1026                                                    (void *)&ui32, &ui32_size)) {
1027                                 return -EINVAL;
1028                         }
1029                         break;
1030                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
1031                         /* get average GPU power */
1032                         if (amdgpu_dpm_read_sensor(adev,
1033                                                    AMDGPU_PP_SENSOR_GPU_AVG_POWER,
1034                                                    (void *)&ui32, &ui32_size)) {
1035                                 return -EINVAL;
1036                         }
1037                         ui32 >>= 8;
1038                         break;
1039                 case AMDGPU_INFO_SENSOR_VDDNB:
1040                         /* get VDDNB in millivolts */
1041                         if (amdgpu_dpm_read_sensor(adev,
1042                                                    AMDGPU_PP_SENSOR_VDDNB,
1043                                                    (void *)&ui32, &ui32_size)) {
1044                                 return -EINVAL;
1045                         }
1046                         break;
1047                 case AMDGPU_INFO_SENSOR_VDDGFX:
1048                         /* get VDDGFX in millivolts */
1049                         if (amdgpu_dpm_read_sensor(adev,
1050                                                    AMDGPU_PP_SENSOR_VDDGFX,
1051                                                    (void *)&ui32, &ui32_size)) {
1052                                 return -EINVAL;
1053                         }
1054                         break;
1055                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1056                         /* get stable pstate sclk in Mhz */
1057                         if (amdgpu_dpm_read_sensor(adev,
1058                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1059                                                    (void *)&ui32, &ui32_size)) {
1060                                 return -EINVAL;
1061                         }
1062                         ui32 /= 100;
1063                         break;
1064                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1065                         /* get stable pstate mclk in Mhz */
1066                         if (amdgpu_dpm_read_sensor(adev,
1067                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1068                                                    (void *)&ui32, &ui32_size)) {
1069                                 return -EINVAL;
1070                         }
1071                         ui32 /= 100;
1072                         break;
1073                 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
1074                         /* get peak pstate sclk in Mhz */
1075                         if (amdgpu_dpm_read_sensor(adev,
1076                                                    AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
1077                                                    (void *)&ui32, &ui32_size)) {
1078                                 return -EINVAL;
1079                         }
1080                         ui32 /= 100;
1081                         break;
1082                 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
1083                         /* get peak pstate mclk in Mhz */
1084                         if (amdgpu_dpm_read_sensor(adev,
1085                                                    AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
1086                                                    (void *)&ui32, &ui32_size)) {
1087                                 return -EINVAL;
1088                         }
1089                         ui32 /= 100;
1090                         break;
1091                 default:
1092                         DRM_DEBUG_KMS("Invalid request %d\n",
1093                                       info->sensor_info.type);
1094                         return -EINVAL;
1095                 }
1096                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1097         }
1098         case AMDGPU_INFO_VRAM_LOST_COUNTER:
1099                 ui32 = atomic_read(&adev->vram_lost_counter);
1100                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1101         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1102                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1103                 uint64_t ras_mask;
1104
1105                 if (!ras)
1106                         return -EINVAL;
1107                 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1108
1109                 return copy_to_user(out, &ras_mask,
1110                                 min_t(u64, size, sizeof(ras_mask))) ?
1111                         -EFAULT : 0;
1112         }
1113         case AMDGPU_INFO_VIDEO_CAPS: {
1114                 const struct amdgpu_video_codecs *codecs;
1115                 struct drm_amdgpu_info_video_caps *caps;
1116                 int r;
1117
1118                 if (!adev->asic_funcs->query_video_codecs)
1119                         return -EINVAL;
1120
1121                 switch (info->video_cap.type) {
1122                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1123                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1124                         if (r)
1125                                 return -EINVAL;
1126                         break;
1127                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1128                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1129                         if (r)
1130                                 return -EINVAL;
1131                         break;
1132                 default:
1133                         DRM_DEBUG_KMS("Invalid request %d\n",
1134                                       info->video_cap.type);
1135                         return -EINVAL;
1136                 }
1137
1138                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1139                 if (!caps)
1140                         return -ENOMEM;
1141
1142                 for (i = 0; i < codecs->codec_count; i++) {
1143                         int idx = codecs->codec_array[i].codec_type;
1144
1145                         switch (idx) {
1146                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1147                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1148                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1149                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1150                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1151                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1152                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1153                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1154                                 caps->codec_info[idx].valid = 1;
1155                                 caps->codec_info[idx].max_width =
1156                                         codecs->codec_array[i].max_width;
1157                                 caps->codec_info[idx].max_height =
1158                                         codecs->codec_array[i].max_height;
1159                                 caps->codec_info[idx].max_pixels_per_frame =
1160                                         codecs->codec_array[i].max_pixels_per_frame;
1161                                 caps->codec_info[idx].max_level =
1162                                         codecs->codec_array[i].max_level;
1163                                 break;
1164                         default:
1165                                 break;
1166                         }
1167                 }
1168                 r = copy_to_user(out, caps,
1169                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1170                 kfree(caps);
1171                 return r;
1172         }
1173         case AMDGPU_INFO_MAX_IBS: {
1174                 uint32_t max_ibs[AMDGPU_HW_IP_NUM];
1175
1176                 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
1177                         max_ibs[i] = amdgpu_ring_max_ibs(i);
1178
1179                 return copy_to_user(out, max_ibs,
1180                                     min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0;
1181         }
1182         default:
1183                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1184                 return -EINVAL;
1185         }
1186         return 0;
1187 }
1188
1189
1190 /*
1191  * Outdated mess for old drm with Xorg being in charge (void function now).
1192  */
1193 /**
1194  * amdgpu_driver_lastclose_kms - drm callback for last close
1195  *
1196  * @dev: drm dev pointer
1197  *
1198  * Switch vga_switcheroo state after last close (all asics).
1199  */
1200 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1201 {
1202         drm_fb_helper_lastclose(dev);
1203         vga_switcheroo_process_delayed_switch();
1204 }
1205
1206 /**
1207  * amdgpu_driver_open_kms - drm callback for open
1208  *
1209  * @dev: drm dev pointer
1210  * @file_priv: drm file
1211  *
1212  * On device open, init vm on cayman+ (all asics).
1213  * Returns 0 on success, error on failure.
1214  */
1215 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1216 {
1217         struct amdgpu_device *adev = drm_to_adev(dev);
1218         struct amdgpu_fpriv *fpriv;
1219         int r, pasid;
1220
1221         /* Ensure IB tests are run on ring */
1222         flush_delayed_work(&adev->delayed_init_work);
1223
1224
1225         if (amdgpu_ras_intr_triggered()) {
1226                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1227                 return -EHWPOISON;
1228         }
1229
1230         file_priv->driver_priv = NULL;
1231
1232         r = pm_runtime_get_sync(dev->dev);
1233         if (r < 0)
1234                 goto pm_put;
1235
1236         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1237         if (unlikely(!fpriv)) {
1238                 r = -ENOMEM;
1239                 goto out_suspend;
1240         }
1241
1242         pasid = amdgpu_pasid_alloc(16);
1243         if (pasid < 0) {
1244                 dev_warn(adev->dev, "No more PASIDs available!");
1245                 pasid = 0;
1246         }
1247
1248         r = amdgpu_xcp_open_device(adev, fpriv, file_priv);
1249         if (r)
1250                 goto error_pasid;
1251
1252         r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id);
1253         if (r)
1254                 goto error_pasid;
1255
1256         r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1257         if (r)
1258                 goto error_vm;
1259
1260         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1261         if (!fpriv->prt_va) {
1262                 r = -ENOMEM;
1263                 goto error_vm;
1264         }
1265
1266         if (adev->gfx.mcbp) {
1267                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1268
1269                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1270                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1271                 if (r)
1272                         goto error_vm;
1273         }
1274
1275         mutex_init(&fpriv->bo_list_lock);
1276         idr_init_base(&fpriv->bo_list_handles, 1);
1277
1278         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1279
1280         file_priv->driver_priv = fpriv;
1281         goto out_suspend;
1282
1283 error_vm:
1284         amdgpu_vm_fini(adev, &fpriv->vm);
1285
1286 error_pasid:
1287         if (pasid) {
1288                 amdgpu_pasid_free(pasid);
1289                 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1290         }
1291
1292         kfree(fpriv);
1293
1294 out_suspend:
1295         pm_runtime_mark_last_busy(dev->dev);
1296 pm_put:
1297         pm_runtime_put_autosuspend(dev->dev);
1298
1299         return r;
1300 }
1301
1302 /**
1303  * amdgpu_driver_postclose_kms - drm callback for post close
1304  *
1305  * @dev: drm dev pointer
1306  * @file_priv: drm file
1307  *
1308  * On device post close, tear down vm on cayman+ (all asics).
1309  */
1310 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1311                                  struct drm_file *file_priv)
1312 {
1313         struct amdgpu_device *adev = drm_to_adev(dev);
1314         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1315         struct amdgpu_bo_list *list;
1316         struct amdgpu_bo *pd;
1317         u32 pasid;
1318         int handle;
1319
1320         if (!fpriv)
1321                 return;
1322
1323         pm_runtime_get_sync(dev->dev);
1324
1325         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1326                 amdgpu_uvd_free_handles(adev, file_priv);
1327         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1328                 amdgpu_vce_free_handles(adev, file_priv);
1329
1330         if (fpriv->csa_va) {
1331                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1332
1333                 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1334                                                 fpriv->csa_va, csa_addr));
1335                 fpriv->csa_va = NULL;
1336         }
1337
1338         pasid = fpriv->vm.pasid;
1339         pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1340         if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1341                 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1342                 amdgpu_bo_unreserve(pd);
1343         }
1344
1345         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1346         amdgpu_vm_fini(adev, &fpriv->vm);
1347
1348         if (pasid)
1349                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1350         amdgpu_bo_unref(&pd);
1351
1352         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1353                 amdgpu_bo_list_put(list);
1354
1355         idr_destroy(&fpriv->bo_list_handles);
1356         mutex_destroy(&fpriv->bo_list_lock);
1357
1358         kfree(fpriv);
1359         file_priv->driver_priv = NULL;
1360
1361         pm_runtime_mark_last_busy(dev->dev);
1362         pm_runtime_put_autosuspend(dev->dev);
1363 }
1364
1365
1366 void amdgpu_driver_release_kms(struct drm_device *dev)
1367 {
1368         struct amdgpu_device *adev = drm_to_adev(dev);
1369
1370         amdgpu_device_fini_sw(adev);
1371         pci_set_drvdata(adev->pdev, NULL);
1372 }
1373
1374 /*
1375  * VBlank related functions.
1376  */
1377 /**
1378  * amdgpu_get_vblank_counter_kms - get frame count
1379  *
1380  * @crtc: crtc to get the frame count from
1381  *
1382  * Gets the frame count on the requested crtc (all asics).
1383  * Returns frame count on success, -EINVAL on failure.
1384  */
1385 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1386 {
1387         struct drm_device *dev = crtc->dev;
1388         unsigned int pipe = crtc->index;
1389         struct amdgpu_device *adev = drm_to_adev(dev);
1390         int vpos, hpos, stat;
1391         u32 count;
1392
1393         if (pipe >= adev->mode_info.num_crtc) {
1394                 DRM_ERROR("Invalid crtc %u\n", pipe);
1395                 return -EINVAL;
1396         }
1397
1398         /* The hw increments its frame counter at start of vsync, not at start
1399          * of vblank, as is required by DRM core vblank counter handling.
1400          * Cook the hw count here to make it appear to the caller as if it
1401          * incremented at start of vblank. We measure distance to start of
1402          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1403          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1404          * result by 1 to give the proper appearance to caller.
1405          */
1406         if (adev->mode_info.crtcs[pipe]) {
1407                 /* Repeat readout if needed to provide stable result if
1408                  * we cross start of vsync during the queries.
1409                  */
1410                 do {
1411                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1412                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1413                          * vpos as distance to start of vblank, instead of
1414                          * regular vertical scanout pos.
1415                          */
1416                         stat = amdgpu_display_get_crtc_scanoutpos(
1417                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1418                                 &vpos, &hpos, NULL, NULL,
1419                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1420                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1421
1422                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1423                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1424                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1425                 } else {
1426                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1427                                       pipe, vpos);
1428
1429                         /* Bump counter if we are at >= leading edge of vblank,
1430                          * but before vsync where vpos would turn negative and
1431                          * the hw counter really increments.
1432                          */
1433                         if (vpos >= 0)
1434                                 count++;
1435                 }
1436         } else {
1437                 /* Fallback to use value as is. */
1438                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1439                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1440         }
1441
1442         return count;
1443 }
1444
1445 /**
1446  * amdgpu_enable_vblank_kms - enable vblank interrupt
1447  *
1448  * @crtc: crtc to enable vblank interrupt for
1449  *
1450  * Enable the interrupt on the requested crtc (all asics).
1451  * Returns 0 on success, -EINVAL on failure.
1452  */
1453 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1454 {
1455         struct drm_device *dev = crtc->dev;
1456         unsigned int pipe = crtc->index;
1457         struct amdgpu_device *adev = drm_to_adev(dev);
1458         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1459
1460         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1461 }
1462
1463 /**
1464  * amdgpu_disable_vblank_kms - disable vblank interrupt
1465  *
1466  * @crtc: crtc to disable vblank interrupt for
1467  *
1468  * Disable the interrupt on the requested crtc (all asics).
1469  */
1470 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1471 {
1472         struct drm_device *dev = crtc->dev;
1473         unsigned int pipe = crtc->index;
1474         struct amdgpu_device *adev = drm_to_adev(dev);
1475         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1476
1477         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1478 }
1479
1480 /*
1481  * Debugfs info
1482  */
1483 #if defined(CONFIG_DEBUG_FS)
1484
1485 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1486 {
1487         struct amdgpu_device *adev = m->private;
1488         struct drm_amdgpu_info_firmware fw_info;
1489         struct drm_amdgpu_query_fw query_fw;
1490         struct atom_context *ctx = adev->mode_info.atom_context;
1491         uint8_t smu_program, smu_major, smu_minor, smu_debug;
1492         int ret, i;
1493
1494         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1495 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type
1496                 TA_FW_NAME(XGMI),
1497                 TA_FW_NAME(RAS),
1498                 TA_FW_NAME(HDCP),
1499                 TA_FW_NAME(DTM),
1500                 TA_FW_NAME(RAP),
1501                 TA_FW_NAME(SECUREDISPLAY),
1502 #undef TA_FW_NAME
1503         };
1504
1505         /* VCE */
1506         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1507         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1508         if (ret)
1509                 return ret;
1510         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1511                    fw_info.feature, fw_info.ver);
1512
1513         /* UVD */
1514         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1515         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1516         if (ret)
1517                 return ret;
1518         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1519                    fw_info.feature, fw_info.ver);
1520
1521         /* GMC */
1522         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1523         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1524         if (ret)
1525                 return ret;
1526         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1527                    fw_info.feature, fw_info.ver);
1528
1529         /* ME */
1530         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1531         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1532         if (ret)
1533                 return ret;
1534         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1535                    fw_info.feature, fw_info.ver);
1536
1537         /* PFP */
1538         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1539         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1540         if (ret)
1541                 return ret;
1542         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1543                    fw_info.feature, fw_info.ver);
1544
1545         /* CE */
1546         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1547         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1548         if (ret)
1549                 return ret;
1550         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1551                    fw_info.feature, fw_info.ver);
1552
1553         /* RLC */
1554         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1555         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1556         if (ret)
1557                 return ret;
1558         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1559                    fw_info.feature, fw_info.ver);
1560
1561         /* RLC SAVE RESTORE LIST CNTL */
1562         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1563         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1564         if (ret)
1565                 return ret;
1566         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1567                    fw_info.feature, fw_info.ver);
1568
1569         /* RLC SAVE RESTORE LIST GPM MEM */
1570         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1571         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1572         if (ret)
1573                 return ret;
1574         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1575                    fw_info.feature, fw_info.ver);
1576
1577         /* RLC SAVE RESTORE LIST SRM MEM */
1578         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1579         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1580         if (ret)
1581                 return ret;
1582         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1583                    fw_info.feature, fw_info.ver);
1584
1585         /* RLCP */
1586         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1587         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1588         if (ret)
1589                 return ret;
1590         seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1591                    fw_info.feature, fw_info.ver);
1592
1593         /* RLCV */
1594         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1595         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1596         if (ret)
1597                 return ret;
1598         seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1599                    fw_info.feature, fw_info.ver);
1600
1601         /* MEC */
1602         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1603         query_fw.index = 0;
1604         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1605         if (ret)
1606                 return ret;
1607         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1608                    fw_info.feature, fw_info.ver);
1609
1610         /* MEC2 */
1611         if (adev->gfx.mec2_fw) {
1612                 query_fw.index = 1;
1613                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1614                 if (ret)
1615                         return ret;
1616                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1617                            fw_info.feature, fw_info.ver);
1618         }
1619
1620         /* IMU */
1621         query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1622         query_fw.index = 0;
1623         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1624         if (ret)
1625                 return ret;
1626         seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1627                    fw_info.feature, fw_info.ver);
1628
1629         /* PSP SOS */
1630         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1631         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1632         if (ret)
1633                 return ret;
1634         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1635                    fw_info.feature, fw_info.ver);
1636
1637
1638         /* PSP ASD */
1639         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1640         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1641         if (ret)
1642                 return ret;
1643         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1644                    fw_info.feature, fw_info.ver);
1645
1646         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1647         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1648                 query_fw.index = i;
1649                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1650                 if (ret)
1651                         continue;
1652
1653                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1654                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1655         }
1656
1657         /* SMC */
1658         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1659         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1660         if (ret)
1661                 return ret;
1662         smu_program = (fw_info.ver >> 24) & 0xff;
1663         smu_major = (fw_info.ver >> 16) & 0xff;
1664         smu_minor = (fw_info.ver >> 8) & 0xff;
1665         smu_debug = (fw_info.ver >> 0) & 0xff;
1666         seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1667                    fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1668
1669         /* SDMA */
1670         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1671         for (i = 0; i < adev->sdma.num_instances; i++) {
1672                 query_fw.index = i;
1673                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1674                 if (ret)
1675                         return ret;
1676                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1677                            i, fw_info.feature, fw_info.ver);
1678         }
1679
1680         /* VCN */
1681         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1682         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1683         if (ret)
1684                 return ret;
1685         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1686                    fw_info.feature, fw_info.ver);
1687
1688         /* DMCU */
1689         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1690         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1691         if (ret)
1692                 return ret;
1693         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1694                    fw_info.feature, fw_info.ver);
1695
1696         /* DMCUB */
1697         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1698         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1699         if (ret)
1700                 return ret;
1701         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1702                    fw_info.feature, fw_info.ver);
1703
1704         /* TOC */
1705         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1706         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1707         if (ret)
1708                 return ret;
1709         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1710                    fw_info.feature, fw_info.ver);
1711
1712         /* CAP */
1713         if (adev->psp.cap_fw) {
1714                 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1715                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1716                 if (ret)
1717                         return ret;
1718                 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1719                                 fw_info.feature, fw_info.ver);
1720         }
1721
1722         /* MES_KIQ */
1723         query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1724         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1725         if (ret)
1726                 return ret;
1727         seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1728                    fw_info.feature, fw_info.ver);
1729
1730         /* MES */
1731         query_fw.fw_type = AMDGPU_INFO_FW_MES;
1732         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1733         if (ret)
1734                 return ret;
1735         seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1736                    fw_info.feature, fw_info.ver);
1737
1738         /* VPE */
1739         query_fw.fw_type = AMDGPU_INFO_FW_VPE;
1740         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1741         if (ret)
1742                 return ret;
1743         seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n",
1744                    fw_info.feature, fw_info.ver);
1745
1746         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn);
1747
1748         return 0;
1749 }
1750
1751 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1752
1753 #endif
1754
1755 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1756 {
1757 #if defined(CONFIG_DEBUG_FS)
1758         struct drm_minor *minor = adev_to_drm(adev)->primary;
1759         struct dentry *root = minor->debugfs_root;
1760
1761         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1762                             adev, &amdgpu_debugfs_firmware_info_fops);
1763
1764 #endif
1765 }