drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_drv.h>
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/uaccess.h>
  39 #include <linux/pci.h>
  40 #include <linux/pm_runtime.h>
  41 #include "amdgpu_amdkfd.h"
  42 #include "amdgpu_gem.h"
  43 #include "amdgpu_display.h"
  44 #include "amdgpu_ras.h"
  45
  46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  47 {
  48         struct amdgpu_gpu_instance *gpu_instance;
  49         int i;
  50
  51         mutex_lock(&mgpu_info.mutex);
  52
  53         for (i = 0; i < mgpu_info.num_gpu; i++) {
  54                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  55                 if (gpu_instance->adev == adev) {
  56                         mgpu_info.gpu_ins[i] =
  57                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  58                         mgpu_info.num_gpu--;
  59                         if (adev->flags & AMD_IS_APU)
  60                                 mgpu_info.num_apu--;
  61                         else
  62                                 mgpu_info.num_dgpu--;
  63                         break;
  64                 }
  65         }
  66
  67         mutex_unlock(&mgpu_info.mutex);
  68 }
  69
  70 /**
  71  * amdgpu_driver_unload_kms - Main unload function for KMS.
  72  *
  73  * @dev: drm dev pointer
  74  *
  75  * This is the main unload function for KMS (all asics).
  76  * Returns 0 on success.
  77  */
  78 void amdgpu_driver_unload_kms(struct drm_device *dev)
  79 {
  80         struct amdgpu_device *adev = drm_to_adev(dev);
  81
  82         if (adev == NULL)
  83                 return;
  84
  85         amdgpu_unregister_gpu_instance(adev);
  86
  87         if (adev->rmmio == NULL)
  88                 return;
  89
  90         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
  91                 DRM_WARN("smart shift update failed\n");
  92
  93         amdgpu_acpi_fini(adev);
  94         amdgpu_device_fini_hw(adev);
  95 }
  96
  97 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
  98 {
  99         struct amdgpu_gpu_instance *gpu_instance;
 100
 101         mutex_lock(&mgpu_info.mutex);
 102
 103         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 104                 DRM_ERROR("Cannot register more gpu instance\n");
 105                 mutex_unlock(&mgpu_info.mutex);
 106                 return;
 107         }
 108
 109         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 110         gpu_instance->adev = adev;
 111         gpu_instance->mgpu_fan_enabled = 0;
 112
 113         mgpu_info.num_gpu++;
 114         if (adev->flags & AMD_IS_APU)
 115                 mgpu_info.num_apu++;
 116         else
 117                 mgpu_info.num_dgpu++;
 118
 119         mutex_unlock(&mgpu_info.mutex);
 120 }
 121
 122 /**
 123  * amdgpu_driver_load_kms - Main load function for KMS.
 124  *
 125  * @adev: pointer to struct amdgpu_device
 126  * @flags: device flags
 127  *
 128  * This is the main load function for KMS (all asics).
 129  * Returns 0 on success, error on failure.
 130  */
 131 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 132 {
 133         struct drm_device *dev;
 134         int r, acpi_status;
 135
 136         dev = adev_to_drm(adev);
 137
 138         /* amdgpu_device_init should report only fatal error
 139          * like memory allocation failure or iomapping failure,
 140          * or memory manager initialization failure, it must
 141          * properly initialize the GPU MC controller and permit
 142          * VRAM allocation
 143          */
 144         r = amdgpu_device_init(adev, flags);
 145         if (r) {
 146                 dev_err(dev->dev, "Fatal error during GPU init\n");
 147                 goto out;
 148         }
 149
 150         adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
 151         if (amdgpu_device_supports_px(dev) &&
 152             (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */
 153                 adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
 154                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 155         } else if (amdgpu_device_supports_boco(dev) &&
 156                    (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */
 157                 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
 158                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 159         } else if (amdgpu_device_supports_baco(dev) &&
 160                    (amdgpu_runtime_pm != 0)) {
 161                 switch (adev->asic_type) {
 162                 case CHIP_VEGA20:
 163                 case CHIP_ARCTURUS:
 164                         /* enable BACO as runpm mode if runpm=1 */
 165                         if (amdgpu_runtime_pm > 0)
 166                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 167                         break;
 168                 case CHIP_VEGA10:
 169                         /* enable BACO as runpm mode if noretry=0 */
 170                         if (!adev->gmc.noretry)
 171                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 172                         break;
 173                 default:
 174                         /* enable BACO as runpm mode on CI+ */
 175                         adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 176                         break;
 177                 }
 178
 179                 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
 180                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 181         }
 182
 183         /* Call ACPI methods: require modeset init
 184          * but failure is not fatal
 185          */
 186
 187         acpi_status = amdgpu_acpi_init(adev);
 188         if (acpi_status)
 189                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 190
 191         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
 192                 DRM_WARN("smart shift update failed\n");
 193
 194 out:
 195         if (r)
 196                 amdgpu_driver_unload_kms(dev);
 197
 198         return r;
 199 }
 200
 201 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 202                                 struct drm_amdgpu_query_fw *query_fw,
 203                                 struct amdgpu_device *adev)
 204 {
 205         switch (query_fw->fw_type) {
 206         case AMDGPU_INFO_FW_VCE:
 207                 fw_info->ver = adev->vce.fw_version;
 208                 fw_info->feature = adev->vce.fb_version;
 209                 break;
 210         case AMDGPU_INFO_FW_UVD:
 211                 fw_info->ver = adev->uvd.fw_version;
 212                 fw_info->feature = 0;
 213                 break;
 214         case AMDGPU_INFO_FW_VCN:
 215                 fw_info->ver = adev->vcn.fw_version;
 216                 fw_info->feature = 0;
 217                 break;
 218         case AMDGPU_INFO_FW_GMC:
 219                 fw_info->ver = adev->gmc.fw_version;
 220                 fw_info->feature = 0;
 221                 break;
 222         case AMDGPU_INFO_FW_GFX_ME:
 223                 fw_info->ver = adev->gfx.me_fw_version;
 224                 fw_info->feature = adev->gfx.me_feature_version;
 225                 break;
 226         case AMDGPU_INFO_FW_GFX_PFP:
 227                 fw_info->ver = adev->gfx.pfp_fw_version;
 228                 fw_info->feature = adev->gfx.pfp_feature_version;
 229                 break;
 230         case AMDGPU_INFO_FW_GFX_CE:
 231                 fw_info->ver = adev->gfx.ce_fw_version;
 232                 fw_info->feature = adev->gfx.ce_feature_version;
 233                 break;
 234         case AMDGPU_INFO_FW_GFX_RLC:
 235                 fw_info->ver = adev->gfx.rlc_fw_version;
 236                 fw_info->feature = adev->gfx.rlc_feature_version;
 237                 break;
 238         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 239                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 240                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 241                 break;
 242         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 243                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 244                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 245                 break;
 246         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 247                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 248                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 249                 break;
 250         case AMDGPU_INFO_FW_GFX_RLCP:
 251                 fw_info->ver = adev->gfx.rlcp_ucode_version;
 252                 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
 253                 break;
 254         case AMDGPU_INFO_FW_GFX_RLCV:
 255                 fw_info->ver = adev->gfx.rlcv_ucode_version;
 256                 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
 257                 break;
 258         case AMDGPU_INFO_FW_GFX_MEC:
 259                 if (query_fw->index == 0) {
 260                         fw_info->ver = adev->gfx.mec_fw_version;
 261                         fw_info->feature = adev->gfx.mec_feature_version;
 262                 } else if (query_fw->index == 1) {
 263                         fw_info->ver = adev->gfx.mec2_fw_version;
 264                         fw_info->feature = adev->gfx.mec2_feature_version;
 265                 } else
 266                         return -EINVAL;
 267                 break;
 268         case AMDGPU_INFO_FW_SMC:
 269                 fw_info->ver = adev->pm.fw_version;
 270                 fw_info->feature = 0;
 271                 break;
 272         case AMDGPU_INFO_FW_TA:
 273                 switch (query_fw->index) {
 274                 case TA_FW_TYPE_PSP_XGMI:
 275                         fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
 276                         fw_info->feature = adev->psp.xgmi_context.context
 277                                                    .bin_desc.feature_version;
 278                         break;
 279                 case TA_FW_TYPE_PSP_RAS:
 280                         fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
 281                         fw_info->feature = adev->psp.ras_context.context
 282                                                    .bin_desc.feature_version;
 283                         break;
 284                 case TA_FW_TYPE_PSP_HDCP:
 285                         fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
 286                         fw_info->feature = adev->psp.hdcp_context.context
 287                                                    .bin_desc.feature_version;
 288                         break;
 289                 case TA_FW_TYPE_PSP_DTM:
 290                         fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
 291                         fw_info->feature = adev->psp.dtm_context.context
 292                                                    .bin_desc.feature_version;
 293                         break;
 294                 case TA_FW_TYPE_PSP_RAP:
 295                         fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
 296                         fw_info->feature = adev->psp.rap_context.context
 297                                                    .bin_desc.feature_version;
 298                         break;
 299                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 300                         fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
 301                         fw_info->feature =
 302                                 adev->psp.securedisplay_context.context.bin_desc
 303                                         .feature_version;
 304                         break;
 305                 default:
 306                         return -EINVAL;
 307                 }
 308                 break;
 309         case AMDGPU_INFO_FW_SDMA:
 310                 if (query_fw->index >= adev->sdma.num_instances)
 311                         return -EINVAL;
 312                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 313                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 314                 break;
 315         case AMDGPU_INFO_FW_SOS:
 316                 fw_info->ver = adev->psp.sos.fw_version;
 317                 fw_info->feature = adev->psp.sos.feature_version;
 318                 break;
 319         case AMDGPU_INFO_FW_ASD:
 320                 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
 321                 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
 322                 break;
 323         case AMDGPU_INFO_FW_DMCU:
 324                 fw_info->ver = adev->dm.dmcu_fw_version;
 325                 fw_info->feature = 0;
 326                 break;
 327         case AMDGPU_INFO_FW_DMCUB:
 328                 fw_info->ver = adev->dm.dmcub_fw_version;
 329                 fw_info->feature = 0;
 330                 break;
 331         case AMDGPU_INFO_FW_TOC:
 332                 fw_info->ver = adev->psp.toc.fw_version;
 333                 fw_info->feature = adev->psp.toc.feature_version;
 334                 break;
 335         case AMDGPU_INFO_FW_CAP:
 336                 fw_info->ver = adev->psp.cap_fw_version;
 337                 fw_info->feature = adev->psp.cap_feature_version;
 338                 break;
 339         case AMDGPU_INFO_FW_MES_KIQ:
 340                 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
 341                 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK)
 342                                         >> AMDGPU_MES_FEAT_VERSION_SHIFT;
 343                 break;
 344         case AMDGPU_INFO_FW_MES:
 345                 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
 346                 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK)
 347                                         >> AMDGPU_MES_FEAT_VERSION_SHIFT;
 348                 break;
 349         case AMDGPU_INFO_FW_IMU:
 350                 fw_info->ver = adev->gfx.imu_fw_version;
 351                 fw_info->feature = 0;
 352                 break;
 353         default:
 354                 return -EINVAL;
 355         }
 356         return 0;
 357 }
 358
 359 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 360                              struct drm_amdgpu_info *info,
 361                              struct drm_amdgpu_info_hw_ip *result)
 362 {
 363         uint32_t ib_start_alignment = 0;
 364         uint32_t ib_size_alignment = 0;
 365         enum amd_ip_block_type type;
 366         unsigned int num_rings = 0;
 367         unsigned int i, j;
 368
 369         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 370                 return -EINVAL;
 371
 372         switch (info->query_hw_ip.type) {
 373         case AMDGPU_HW_IP_GFX:
 374                 type = AMD_IP_BLOCK_TYPE_GFX;
 375                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 376                         if (adev->gfx.gfx_ring[i].sched.ready)
 377                                 ++num_rings;
 378                 ib_start_alignment = 32;
 379                 ib_size_alignment = 32;
 380                 break;
 381         case AMDGPU_HW_IP_COMPUTE:
 382                 type = AMD_IP_BLOCK_TYPE_GFX;
 383                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 384                         if (adev->gfx.compute_ring[i].sched.ready)
 385                                 ++num_rings;
 386                 ib_start_alignment = 32;
 387                 ib_size_alignment = 32;
 388                 break;
 389         case AMDGPU_HW_IP_DMA:
 390                 type = AMD_IP_BLOCK_TYPE_SDMA;
 391                 for (i = 0; i < adev->sdma.num_instances; i++)
 392                         if (adev->sdma.instance[i].ring.sched.ready)
 393                                 ++num_rings;
 394                 ib_start_alignment = 256;
 395                 ib_size_alignment = 4;
 396                 break;
 397         case AMDGPU_HW_IP_UVD:
 398                 type = AMD_IP_BLOCK_TYPE_UVD;
 399                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 400                         if (adev->uvd.harvest_config & (1 << i))
 401                                 continue;
 402
 403                         if (adev->uvd.inst[i].ring.sched.ready)
 404                                 ++num_rings;
 405                 }
 406                 ib_start_alignment = 64;
 407                 ib_size_alignment = 64;
 408                 break;
 409         case AMDGPU_HW_IP_VCE:
 410                 type = AMD_IP_BLOCK_TYPE_VCE;
 411                 for (i = 0; i < adev->vce.num_rings; i++)
 412                         if (adev->vce.ring[i].sched.ready)
 413                                 ++num_rings;
 414                 ib_start_alignment = 4;
 415                 ib_size_alignment = 1;
 416                 break;
 417         case AMDGPU_HW_IP_UVD_ENC:
 418                 type = AMD_IP_BLOCK_TYPE_UVD;
 419                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 420                         if (adev->uvd.harvest_config & (1 << i))
 421                                 continue;
 422
 423                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 424                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 425                                         ++num_rings;
 426                 }
 427                 ib_start_alignment = 64;
 428                 ib_size_alignment = 64;
 429                 break;
 430         case AMDGPU_HW_IP_VCN_DEC:
 431                 type = AMD_IP_BLOCK_TYPE_VCN;
 432                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 433                         if (adev->uvd.harvest_config & (1 << i))
 434                                 continue;
 435
 436                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 437                                 ++num_rings;
 438                 }
 439                 ib_start_alignment = 16;
 440                 ib_size_alignment = 16;
 441                 break;
 442         case AMDGPU_HW_IP_VCN_ENC:
 443                 type = AMD_IP_BLOCK_TYPE_VCN;
 444                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 445                         if (adev->uvd.harvest_config & (1 << i))
 446                                 continue;
 447
 448                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 449                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 450                                         ++num_rings;
 451                 }
 452                 ib_start_alignment = 64;
 453                 ib_size_alignment = 1;
 454                 break;
 455         case AMDGPU_HW_IP_VCN_JPEG:
 456                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 457                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 458
 459                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 460                         if (adev->jpeg.harvest_config & (1 << i))
 461                                 continue;
 462
 463                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 464                                 ++num_rings;
 465                 }
 466                 ib_start_alignment = 16;
 467                 ib_size_alignment = 16;
 468                 break;
 469         default:
 470                 return -EINVAL;
 471         }
 472
 473         for (i = 0; i < adev->num_ip_blocks; i++)
 474                 if (adev->ip_blocks[i].version->type == type &&
 475                     adev->ip_blocks[i].status.valid)
 476                         break;
 477
 478         if (i == adev->num_ip_blocks)
 479                 return 0;
 480
 481         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 482                         num_rings);
 483
 484         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 485         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 486
 487         if (adev->asic_type >= CHIP_VEGA10) {
 488                 switch (type) {
 489                 case AMD_IP_BLOCK_TYPE_GFX:
 490                         result->ip_discovery_version = adev->ip_versions[GC_HWIP][0];
 491                         break;
 492                 case AMD_IP_BLOCK_TYPE_SDMA:
 493                         result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0];
 494                         break;
 495                 case AMD_IP_BLOCK_TYPE_UVD:
 496                 case AMD_IP_BLOCK_TYPE_VCN:
 497                 case AMD_IP_BLOCK_TYPE_JPEG:
 498                         result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0];
 499                         break;
 500                 case AMD_IP_BLOCK_TYPE_VCE:
 501                         result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0];
 502                         break;
 503                 default:
 504                         result->ip_discovery_version = 0;
 505                         break;
 506                 }
 507         } else {
 508                 result->ip_discovery_version = 0;
 509         }
 510         result->capabilities_flags = 0;
 511         result->available_rings = (1 << num_rings) - 1;
 512         result->ib_start_alignment = ib_start_alignment;
 513         result->ib_size_alignment = ib_size_alignment;
 514         return 0;
 515 }
 516
 517 /*
 518  * Userspace get information ioctl
 519  */
 520 /**
 521  * amdgpu_info_ioctl - answer a device specific request.
 522  *
 523  * @dev: drm device pointer
 524  * @data: request object
 525  * @filp: drm filp
 526  *
 527  * This function is used to pass device specific parameters to the userspace
 528  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 529  * etc. (all asics).
 530  * Returns 0 on success, -EINVAL on failure.
 531  */
 532 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 533 {
 534         struct amdgpu_device *adev = drm_to_adev(dev);
 535         struct drm_amdgpu_info *info = data;
 536         struct amdgpu_mode_info *minfo = &adev->mode_info;
 537         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 538         uint32_t size = info->return_size;
 539         struct drm_crtc *crtc;
 540         uint32_t ui32 = 0;
 541         uint64_t ui64 = 0;
 542         int i, found;
 543         int ui32_size = sizeof(ui32);
 544
 545         if (!info->return_size || !info->return_pointer)
 546                 return -EINVAL;
 547
 548         switch (info->query) {
 549         case AMDGPU_INFO_ACCEL_WORKING:
 550                 ui32 = adev->accel_working;
 551                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 552         case AMDGPU_INFO_CRTC_FROM_ID:
 553                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 554                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 555                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 556                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 557                                 ui32 = amdgpu_crtc->crtc_id;
 558                                 found = 1;
 559                                 break;
 560                         }
 561                 }
 562                 if (!found) {
 563                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 564                         return -EINVAL;
 565                 }
 566                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 567         case AMDGPU_INFO_HW_IP_INFO: {
 568                 struct drm_amdgpu_info_hw_ip ip = {};
 569                 int ret;
 570
 571                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 572                 if (ret)
 573                         return ret;
 574
 575                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 576                 return ret ? -EFAULT : 0;
 577         }
 578         case AMDGPU_INFO_HW_IP_COUNT: {
 579                 enum amd_ip_block_type type;
 580                 uint32_t count = 0;
 581
 582                 switch (info->query_hw_ip.type) {
 583                 case AMDGPU_HW_IP_GFX:
 584                         type = AMD_IP_BLOCK_TYPE_GFX;
 585                         break;
 586                 case AMDGPU_HW_IP_COMPUTE:
 587                         type = AMD_IP_BLOCK_TYPE_GFX;
 588                         break;
 589                 case AMDGPU_HW_IP_DMA:
 590                         type = AMD_IP_BLOCK_TYPE_SDMA;
 591                         break;
 592                 case AMDGPU_HW_IP_UVD:
 593                         type = AMD_IP_BLOCK_TYPE_UVD;
 594                         break;
 595                 case AMDGPU_HW_IP_VCE:
 596                         type = AMD_IP_BLOCK_TYPE_VCE;
 597                         break;
 598                 case AMDGPU_HW_IP_UVD_ENC:
 599                         type = AMD_IP_BLOCK_TYPE_UVD;
 600                         break;
 601                 case AMDGPU_HW_IP_VCN_DEC:
 602                 case AMDGPU_HW_IP_VCN_ENC:
 603                         type = AMD_IP_BLOCK_TYPE_VCN;
 604                         break;
 605                 case AMDGPU_HW_IP_VCN_JPEG:
 606                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 607                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 608                         break;
 609                 default:
 610                         return -EINVAL;
 611                 }
 612
 613                 for (i = 0; i < adev->num_ip_blocks; i++)
 614                         if (adev->ip_blocks[i].version->type == type &&
 615                             adev->ip_blocks[i].status.valid &&
 616                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 617                                 count++;
 618
 619                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 620         }
 621         case AMDGPU_INFO_TIMESTAMP:
 622                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 623                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 624         case AMDGPU_INFO_FW_VERSION: {
 625                 struct drm_amdgpu_info_firmware fw_info;
 626                 int ret;
 627
 628                 /* We only support one instance of each IP block right now. */
 629                 if (info->query_fw.ip_instance != 0)
 630                         return -EINVAL;
 631
 632                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 633                 if (ret)
 634                         return ret;
 635
 636                 return copy_to_user(out, &fw_info,
 637                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 638         }
 639         case AMDGPU_INFO_NUM_BYTES_MOVED:
 640                 ui64 = atomic64_read(&adev->num_bytes_moved);
 641                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 642         case AMDGPU_INFO_NUM_EVICTIONS:
 643                 ui64 = atomic64_read(&adev->num_evictions);
 644                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 645         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 646                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 647                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 648         case AMDGPU_INFO_VRAM_USAGE:
 649                 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 650                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 651         case AMDGPU_INFO_VIS_VRAM_USAGE:
 652                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 653                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 654         case AMDGPU_INFO_GTT_USAGE:
 655                 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
 656                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 657         case AMDGPU_INFO_GDS_CONFIG: {
 658                 struct drm_amdgpu_info_gds gds_info;
 659
 660                 memset(&gds_info, 0, sizeof(gds_info));
 661                 gds_info.compute_partition_size = adev->gds.gds_size;
 662                 gds_info.gds_total_size = adev->gds.gds_size;
 663                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 664                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 665                 return copy_to_user(out, &gds_info,
 666                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 667         }
 668         case AMDGPU_INFO_VRAM_GTT: {
 669                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 670
 671                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 672                         atomic64_read(&adev->vram_pin_size) -
 673                         AMDGPU_VM_RESERVED_VRAM;
 674                 vram_gtt.vram_cpu_accessible_size =
 675                         min(adev->gmc.visible_vram_size -
 676                             atomic64_read(&adev->visible_pin_size),
 677                             vram_gtt.vram_size);
 678                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 679                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 680                 return copy_to_user(out, &vram_gtt,
 681                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 682         }
 683         case AMDGPU_INFO_MEMORY: {
 684                 struct drm_amdgpu_memory_info mem;
 685                 struct ttm_resource_manager *gtt_man =
 686                         &adev->mman.gtt_mgr.manager;
 687                 struct ttm_resource_manager *vram_man =
 688                         &adev->mman.vram_mgr.manager;
 689
 690                 memset(&mem, 0, sizeof(mem));
 691                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 692                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 693                         atomic64_read(&adev->vram_pin_size) -
 694                         AMDGPU_VM_RESERVED_VRAM;
 695                 mem.vram.heap_usage =
 696                         ttm_resource_manager_usage(vram_man);
 697                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 698
 699                 mem.cpu_accessible_vram.total_heap_size =
 700                         adev->gmc.visible_vram_size;
 701                 mem.cpu_accessible_vram.usable_heap_size =
 702                         min(adev->gmc.visible_vram_size -
 703                             atomic64_read(&adev->visible_pin_size),
 704                             mem.vram.usable_heap_size);
 705                 mem.cpu_accessible_vram.heap_usage =
 706                         amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 707                 mem.cpu_accessible_vram.max_allocation =
 708                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 709
 710                 mem.gtt.total_heap_size = gtt_man->size;
 711                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 712                         atomic64_read(&adev->gart_pin_size);
 713                 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
 714                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 715
 716                 return copy_to_user(out, &mem,
 717                                     min((size_t)size, sizeof(mem)))
 718                                     ? -EFAULT : 0;
 719         }
 720         case AMDGPU_INFO_READ_MMR_REG: {
 721                 unsigned n, alloc_size;
 722                 uint32_t *regs;
 723                 unsigned se_num = (info->read_mmr_reg.instance >>
 724                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 725                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 726                 unsigned sh_num = (info->read_mmr_reg.instance >>
 727                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 728                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 729
 730                 /* set full masks if the userspace set all bits
 731                  * in the bitfields */
 732                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 733                         se_num = 0xffffffff;
 734                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 735                         return -EINVAL;
 736                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 737                         sh_num = 0xffffffff;
 738                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 739                         return -EINVAL;
 740
 741                 if (info->read_mmr_reg.count > 128)
 742                         return -EINVAL;
 743
 744                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 745                 if (!regs)
 746                         return -ENOMEM;
 747                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 748
 749                 amdgpu_gfx_off_ctrl(adev, false);
 750                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 751                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 752                                                       info->read_mmr_reg.dword_offset + i,
 753                                                       &regs[i])) {
 754                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 755                                               info->read_mmr_reg.dword_offset + i);
 756                                 kfree(regs);
 757                                 amdgpu_gfx_off_ctrl(adev, true);
 758                                 return -EFAULT;
 759                         }
 760                 }
 761                 amdgpu_gfx_off_ctrl(adev, true);
 762                 n = copy_to_user(out, regs, min(size, alloc_size));
 763                 kfree(regs);
 764                 return n ? -EFAULT : 0;
 765         }
 766         case AMDGPU_INFO_DEV_INFO: {
 767                 struct drm_amdgpu_info_device *dev_info;
 768                 uint64_t vm_size;
 769                 int ret;
 770
 771                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 772                 if (!dev_info)
 773                         return -ENOMEM;
 774
 775                 dev_info->device_id = adev->pdev->device;
 776                 dev_info->chip_rev = adev->rev_id;
 777                 dev_info->external_rev = adev->external_rev_id;
 778                 dev_info->pci_rev = adev->pdev->revision;
 779                 dev_info->family = adev->family;
 780                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 781                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 782                 /* return all clocks in KHz */
 783                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 784                 if (adev->pm.dpm_enabled) {
 785                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 786                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 787                 } else {
 788                         dev_info->max_engine_clock = adev->clock.default_sclk * 10;
 789                         dev_info->max_memory_clock = adev->clock.default_mclk * 10;
 790                 }
 791                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 792                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 793                         adev->gfx.config.max_shader_engines;
 794                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 795                 dev_info->_pad = 0;
 796                 dev_info->ids_flags = 0;
 797                 if (adev->flags & AMD_IS_APU)
 798                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 799                 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
 800                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 801                 if (amdgpu_is_tmz(adev))
 802                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 803
 804                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 805                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 806
 807                 /* Older VCE FW versions are buggy and can handle only 40bits */
 808                 if (adev->vce.fw_version &&
 809                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 810                         vm_size = min(vm_size, 1ULL << 40);
 811
 812                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 813                 dev_info->virtual_address_max =
 814                         min(vm_size, AMDGPU_GMC_HOLE_START);
 815
 816                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 817                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 818                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 819                 }
 820                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 821                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 822                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 823                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 824                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 825                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 826                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 827                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 828                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 829                        sizeof(adev->gfx.cu_info.bitmap));
 830                 dev_info->vram_type = adev->gmc.vram_type;
 831                 dev_info->vram_bit_width = adev->gmc.vram_width;
 832                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 833                 dev_info->gc_double_offchip_lds_buf =
 834                         adev->gfx.config.double_offchip_lds_buf;
 835                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 836                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 837                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 838                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 839                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 840                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 841                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 842
 843                 if (adev->family >= AMDGPU_FAMILY_NV)
 844                         dev_info->pa_sc_tile_steering_override =
 845                                 adev->gfx.config.pa_sc_tile_steering_override;
 846
 847                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 848
 849                 ret = copy_to_user(out, dev_info,
 850                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 851                 kfree(dev_info);
 852                 return ret;
 853         }
 854         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 855                 unsigned i;
 856                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 857                 struct amd_vce_state *vce_state;
 858
 859                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 860                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 861                         if (vce_state) {
 862                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 863                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 864                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 865                                 vce_clk_table.num_valid_entries++;
 866                         }
 867                 }
 868
 869                 return copy_to_user(out, &vce_clk_table,
 870                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 871         }
 872         case AMDGPU_INFO_VBIOS: {
 873                 uint32_t bios_size = adev->bios_size;
 874
 875                 switch (info->vbios_info.type) {
 876                 case AMDGPU_INFO_VBIOS_SIZE:
 877                         return copy_to_user(out, &bios_size,
 878                                         min((size_t)size, sizeof(bios_size)))
 879                                         ? -EFAULT : 0;
 880                 case AMDGPU_INFO_VBIOS_IMAGE: {
 881                         uint8_t *bios;
 882                         uint32_t bios_offset = info->vbios_info.offset;
 883
 884                         if (bios_offset >= bios_size)
 885                                 return -EINVAL;
 886
 887                         bios = adev->bios + bios_offset;
 888                         return copy_to_user(out, bios,
 889                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 890                                         ? -EFAULT : 0;
 891                 }
 892                 case AMDGPU_INFO_VBIOS_INFO: {
 893                         struct drm_amdgpu_info_vbios vbios_info = {};
 894                         struct atom_context *atom_context;
 895
 896                         atom_context = adev->mode_info.atom_context;
 897                         memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
 898                         memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
 899                         vbios_info.version = atom_context->version;
 900                         memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
 901                                                 sizeof(atom_context->vbios_ver_str));
 902                         memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
 903
 904                         return copy_to_user(out, &vbios_info,
 905                                                 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
 906                 }
 907                 default:
 908                         DRM_DEBUG_KMS("Invalid request %d\n",
 909                                         info->vbios_info.type);
 910                         return -EINVAL;
 911                 }
 912         }
 913         case AMDGPU_INFO_NUM_HANDLES: {
 914                 struct drm_amdgpu_info_num_handles handle;
 915
 916                 switch (info->query_hw_ip.type) {
 917                 case AMDGPU_HW_IP_UVD:
 918                         /* Starting Polaris, we support unlimited UVD handles */
 919                         if (adev->asic_type < CHIP_POLARIS10) {
 920                                 handle.uvd_max_handles = adev->uvd.max_handles;
 921                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 922
 923                                 return copy_to_user(out, &handle,
 924                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 925                         } else {
 926                                 return -ENODATA;
 927                         }
 928
 929                         break;
 930                 default:
 931                         return -EINVAL;
 932                 }
 933         }
 934         case AMDGPU_INFO_SENSOR: {
 935                 if (!adev->pm.dpm_enabled)
 936                         return -ENOENT;
 937
 938                 switch (info->sensor_info.type) {
 939                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 940                         /* get sclk in Mhz */
 941                         if (amdgpu_dpm_read_sensor(adev,
 942                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 943                                                    (void *)&ui32, &ui32_size)) {
 944                                 return -EINVAL;
 945                         }
 946                         ui32 /= 100;
 947                         break;
 948                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 949                         /* get mclk in Mhz */
 950                         if (amdgpu_dpm_read_sensor(adev,
 951                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 952                                                    (void *)&ui32, &ui32_size)) {
 953                                 return -EINVAL;
 954                         }
 955                         ui32 /= 100;
 956                         break;
 957                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 958                         /* get temperature in millidegrees C */
 959                         if (amdgpu_dpm_read_sensor(adev,
 960                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 961                                                    (void *)&ui32, &ui32_size)) {
 962                                 return -EINVAL;
 963                         }
 964                         break;
 965                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 966                         /* get GPU load */
 967                         if (amdgpu_dpm_read_sensor(adev,
 968                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 969                                                    (void *)&ui32, &ui32_size)) {
 970                                 return -EINVAL;
 971                         }
 972                         break;
 973                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 974                         /* get average GPU power */
 975                         if (amdgpu_dpm_read_sensor(adev,
 976                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 977                                                    (void *)&ui32, &ui32_size)) {
 978                                 return -EINVAL;
 979                         }
 980                         ui32 >>= 8;
 981                         break;
 982                 case AMDGPU_INFO_SENSOR_VDDNB:
 983                         /* get VDDNB in millivolts */
 984                         if (amdgpu_dpm_read_sensor(adev,
 985                                                    AMDGPU_PP_SENSOR_VDDNB,
 986                                                    (void *)&ui32, &ui32_size)) {
 987                                 return -EINVAL;
 988                         }
 989                         break;
 990                 case AMDGPU_INFO_SENSOR_VDDGFX:
 991                         /* get VDDGFX in millivolts */
 992                         if (amdgpu_dpm_read_sensor(adev,
 993                                                    AMDGPU_PP_SENSOR_VDDGFX,
 994                                                    (void *)&ui32, &ui32_size)) {
 995                                 return -EINVAL;
 996                         }
 997                         break;
 998                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 999                         /* get stable pstate sclk in Mhz */
1000                         if (amdgpu_dpm_read_sensor(adev,
1001                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1002                                                    (void *)&ui32, &ui32_size)) {
1003                                 return -EINVAL;
1004                         }
1005                         ui32 /= 100;
1006                         break;
1007                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1008                         /* get stable pstate mclk in Mhz */
1009                         if (amdgpu_dpm_read_sensor(adev,
1010                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1011                                                    (void *)&ui32, &ui32_size)) {
1012                                 return -EINVAL;
1013                         }
1014                         ui32 /= 100;
1015                         break;
1016                 default:
1017                         DRM_DEBUG_KMS("Invalid request %d\n",
1018                                       info->sensor_info.type);
1019                         return -EINVAL;
1020                 }
1021                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1022         }
1023         case AMDGPU_INFO_VRAM_LOST_COUNTER:
1024                 ui32 = atomic_read(&adev->vram_lost_counter);
1025                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1026         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1027                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1028                 uint64_t ras_mask;
1029
1030                 if (!ras)
1031                         return -EINVAL;
1032                 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1033
1034                 return copy_to_user(out, &ras_mask,
1035                                 min_t(u64, size, sizeof(ras_mask))) ?
1036                         -EFAULT : 0;
1037         }
1038         case AMDGPU_INFO_VIDEO_CAPS: {
1039                 const struct amdgpu_video_codecs *codecs;
1040                 struct drm_amdgpu_info_video_caps *caps;
1041                 int r;
1042
1043                 switch (info->video_cap.type) {
1044                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1045                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1046                         if (r)
1047                                 return -EINVAL;
1048                         break;
1049                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1050                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1051                         if (r)
1052                                 return -EINVAL;
1053                         break;
1054                 default:
1055                         DRM_DEBUG_KMS("Invalid request %d\n",
1056                                       info->video_cap.type);
1057                         return -EINVAL;
1058                 }
1059
1060                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1061                 if (!caps)
1062                         return -ENOMEM;
1063
1064                 for (i = 0; i < codecs->codec_count; i++) {
1065                         int idx = codecs->codec_array[i].codec_type;
1066
1067                         switch (idx) {
1068                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1069                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1070                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1071                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1072                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1073                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1074                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1075                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1076                                 caps->codec_info[idx].valid = 1;
1077                                 caps->codec_info[idx].max_width =
1078                                         codecs->codec_array[i].max_width;
1079                                 caps->codec_info[idx].max_height =
1080                                         codecs->codec_array[i].max_height;
1081                                 caps->codec_info[idx].max_pixels_per_frame =
1082                                         codecs->codec_array[i].max_pixels_per_frame;
1083                                 caps->codec_info[idx].max_level =
1084                                         codecs->codec_array[i].max_level;
1085                                 break;
1086                         default:
1087                                 break;
1088                         }
1089                 }
1090                 r = copy_to_user(out, caps,
1091                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1092                 kfree(caps);
1093                 return r;
1094         }
1095         default:
1096                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1097                 return -EINVAL;
1098         }
1099         return 0;
1100 }
1101
1102
1103 /*
1104  * Outdated mess for old drm with Xorg being in charge (void function now).
1105  */
1106 /**
1107  * amdgpu_driver_lastclose_kms - drm callback for last close
1108  *
1109  * @dev: drm dev pointer
1110  *
1111  * Switch vga_switcheroo state after last close (all asics).
1112  */
1113 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1114 {
1115         drm_fb_helper_lastclose(dev);
1116         vga_switcheroo_process_delayed_switch();
1117 }
1118
1119 /**
1120  * amdgpu_driver_open_kms - drm callback for open
1121  *
1122  * @dev: drm dev pointer
1123  * @file_priv: drm file
1124  *
1125  * On device open, init vm on cayman+ (all asics).
1126  * Returns 0 on success, error on failure.
1127  */
1128 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1129 {
1130         struct amdgpu_device *adev = drm_to_adev(dev);
1131         struct amdgpu_fpriv *fpriv;
1132         int r, pasid;
1133
1134         /* Ensure IB tests are run on ring */
1135         flush_delayed_work(&adev->delayed_init_work);
1136
1137
1138         if (amdgpu_ras_intr_triggered()) {
1139                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1140                 return -EHWPOISON;
1141         }
1142
1143         file_priv->driver_priv = NULL;
1144
1145         r = pm_runtime_get_sync(dev->dev);
1146         if (r < 0)
1147                 goto pm_put;
1148
1149         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1150         if (unlikely(!fpriv)) {
1151                 r = -ENOMEM;
1152                 goto out_suspend;
1153         }
1154
1155         pasid = amdgpu_pasid_alloc(16);
1156         if (pasid < 0) {
1157                 dev_warn(adev->dev, "No more PASIDs available!");
1158                 pasid = 0;
1159         }
1160
1161         r = amdgpu_vm_init(adev, &fpriv->vm);
1162         if (r)
1163                 goto error_pasid;
1164
1165         r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1166         if (r)
1167                 goto error_vm;
1168
1169         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1170         if (!fpriv->prt_va) {
1171                 r = -ENOMEM;
1172                 goto error_vm;
1173         }
1174
1175         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1176                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1177
1178                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1179                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1180                 if (r)
1181                         goto error_vm;
1182         }
1183
1184         mutex_init(&fpriv->bo_list_lock);
1185         idr_init_base(&fpriv->bo_list_handles, 1);
1186
1187         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1188
1189         file_priv->driver_priv = fpriv;
1190         goto out_suspend;
1191
1192 error_vm:
1193         amdgpu_vm_fini(adev, &fpriv->vm);
1194
1195 error_pasid:
1196         if (pasid) {
1197                 amdgpu_pasid_free(pasid);
1198                 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1199         }
1200
1201         kfree(fpriv);
1202
1203 out_suspend:
1204         pm_runtime_mark_last_busy(dev->dev);
1205 pm_put:
1206         pm_runtime_put_autosuspend(dev->dev);
1207
1208         return r;
1209 }
1210
1211 /**
1212  * amdgpu_driver_postclose_kms - drm callback for post close
1213  *
1214  * @dev: drm dev pointer
1215  * @file_priv: drm file
1216  *
1217  * On device post close, tear down vm on cayman+ (all asics).
1218  */
1219 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1220                                  struct drm_file *file_priv)
1221 {
1222         struct amdgpu_device *adev = drm_to_adev(dev);
1223         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1224         struct amdgpu_bo_list *list;
1225         struct amdgpu_bo *pd;
1226         u32 pasid;
1227         int handle;
1228
1229         if (!fpriv)
1230                 return;
1231
1232         pm_runtime_get_sync(dev->dev);
1233
1234         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1235                 amdgpu_uvd_free_handles(adev, file_priv);
1236         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1237                 amdgpu_vce_free_handles(adev, file_priv);
1238
1239         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1240                 /* TODO: how to handle reserve failure */
1241                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1242                 amdgpu_vm_bo_del(adev, fpriv->csa_va);
1243                 fpriv->csa_va = NULL;
1244                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1245         }
1246
1247         pasid = fpriv->vm.pasid;
1248         pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1249         if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1250                 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1251                 amdgpu_bo_unreserve(pd);
1252         }
1253
1254         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1255         amdgpu_vm_fini(adev, &fpriv->vm);
1256
1257         if (pasid)
1258                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1259         amdgpu_bo_unref(&pd);
1260
1261         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1262                 amdgpu_bo_list_put(list);
1263
1264         idr_destroy(&fpriv->bo_list_handles);
1265         mutex_destroy(&fpriv->bo_list_lock);
1266
1267         kfree(fpriv);
1268         file_priv->driver_priv = NULL;
1269
1270         pm_runtime_mark_last_busy(dev->dev);
1271         pm_runtime_put_autosuspend(dev->dev);
1272 }
1273
1274
1275 void amdgpu_driver_release_kms(struct drm_device *dev)
1276 {
1277         struct amdgpu_device *adev = drm_to_adev(dev);
1278
1279         amdgpu_device_fini_sw(adev);
1280         pci_set_drvdata(adev->pdev, NULL);
1281 }
1282
1283 /*
1284  * VBlank related functions.
1285  */
1286 /**
1287  * amdgpu_get_vblank_counter_kms - get frame count
1288  *
1289  * @crtc: crtc to get the frame count from
1290  *
1291  * Gets the frame count on the requested crtc (all asics).
1292  * Returns frame count on success, -EINVAL on failure.
1293  */
1294 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1295 {
1296         struct drm_device *dev = crtc->dev;
1297         unsigned int pipe = crtc->index;
1298         struct amdgpu_device *adev = drm_to_adev(dev);
1299         int vpos, hpos, stat;
1300         u32 count;
1301
1302         if (pipe >= adev->mode_info.num_crtc) {
1303                 DRM_ERROR("Invalid crtc %u\n", pipe);
1304                 return -EINVAL;
1305         }
1306
1307         /* The hw increments its frame counter at start of vsync, not at start
1308          * of vblank, as is required by DRM core vblank counter handling.
1309          * Cook the hw count here to make it appear to the caller as if it
1310          * incremented at start of vblank. We measure distance to start of
1311          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1312          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1313          * result by 1 to give the proper appearance to caller.
1314          */
1315         if (adev->mode_info.crtcs[pipe]) {
1316                 /* Repeat readout if needed to provide stable result if
1317                  * we cross start of vsync during the queries.
1318                  */
1319                 do {
1320                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1321                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1322                          * vpos as distance to start of vblank, instead of
1323                          * regular vertical scanout pos.
1324                          */
1325                         stat = amdgpu_display_get_crtc_scanoutpos(
1326                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1327                                 &vpos, &hpos, NULL, NULL,
1328                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1329                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1330
1331                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1332                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1333                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1334                 } else {
1335                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1336                                       pipe, vpos);
1337
1338                         /* Bump counter if we are at >= leading edge of vblank,
1339                          * but before vsync where vpos would turn negative and
1340                          * the hw counter really increments.
1341                          */
1342                         if (vpos >= 0)
1343                                 count++;
1344                 }
1345         } else {
1346                 /* Fallback to use value as is. */
1347                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1348                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1349         }
1350
1351         return count;
1352 }
1353
1354 /**
1355  * amdgpu_enable_vblank_kms - enable vblank interrupt
1356  *
1357  * @crtc: crtc to enable vblank interrupt for
1358  *
1359  * Enable the interrupt on the requested crtc (all asics).
1360  * Returns 0 on success, -EINVAL on failure.
1361  */
1362 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1363 {
1364         struct drm_device *dev = crtc->dev;
1365         unsigned int pipe = crtc->index;
1366         struct amdgpu_device *adev = drm_to_adev(dev);
1367         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1368
1369         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1370 }
1371
1372 /**
1373  * amdgpu_disable_vblank_kms - disable vblank interrupt
1374  *
1375  * @crtc: crtc to disable vblank interrupt for
1376  *
1377  * Disable the interrupt on the requested crtc (all asics).
1378  */
1379 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1380 {
1381         struct drm_device *dev = crtc->dev;
1382         unsigned int pipe = crtc->index;
1383         struct amdgpu_device *adev = drm_to_adev(dev);
1384         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1385
1386         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1387 }
1388
1389 /*
1390  * Debugfs info
1391  */
1392 #if defined(CONFIG_DEBUG_FS)
1393
1394 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1395 {
1396         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1397         struct drm_amdgpu_info_firmware fw_info;
1398         struct drm_amdgpu_query_fw query_fw;
1399         struct atom_context *ctx = adev->mode_info.atom_context;
1400         uint8_t smu_program, smu_major, smu_minor, smu_debug;
1401         int ret, i;
1402
1403         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1404 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1405                 TA_FW_NAME(XGMI),
1406                 TA_FW_NAME(RAS),
1407                 TA_FW_NAME(HDCP),
1408                 TA_FW_NAME(DTM),
1409                 TA_FW_NAME(RAP),
1410                 TA_FW_NAME(SECUREDISPLAY),
1411 #undef TA_FW_NAME
1412         };
1413
1414         /* VCE */
1415         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1416         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1417         if (ret)
1418                 return ret;
1419         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1420                    fw_info.feature, fw_info.ver);
1421
1422         /* UVD */
1423         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1424         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1425         if (ret)
1426                 return ret;
1427         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1428                    fw_info.feature, fw_info.ver);
1429
1430         /* GMC */
1431         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1432         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1433         if (ret)
1434                 return ret;
1435         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1436                    fw_info.feature, fw_info.ver);
1437
1438         /* ME */
1439         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1440         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1441         if (ret)
1442                 return ret;
1443         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1444                    fw_info.feature, fw_info.ver);
1445
1446         /* PFP */
1447         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1448         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1449         if (ret)
1450                 return ret;
1451         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1452                    fw_info.feature, fw_info.ver);
1453
1454         /* CE */
1455         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1456         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1457         if (ret)
1458                 return ret;
1459         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1460                    fw_info.feature, fw_info.ver);
1461
1462         /* RLC */
1463         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1464         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1465         if (ret)
1466                 return ret;
1467         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1468                    fw_info.feature, fw_info.ver);
1469
1470         /* RLC SAVE RESTORE LIST CNTL */
1471         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1472         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1473         if (ret)
1474                 return ret;
1475         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1476                    fw_info.feature, fw_info.ver);
1477
1478         /* RLC SAVE RESTORE LIST GPM MEM */
1479         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1480         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1481         if (ret)
1482                 return ret;
1483         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1484                    fw_info.feature, fw_info.ver);
1485
1486         /* RLC SAVE RESTORE LIST SRM MEM */
1487         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1488         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1489         if (ret)
1490                 return ret;
1491         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1492                    fw_info.feature, fw_info.ver);
1493
1494         /* RLCP */
1495         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1496         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1497         if (ret)
1498                 return ret;
1499         seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1500                    fw_info.feature, fw_info.ver);
1501
1502         /* RLCV */
1503         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1504         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1505         if (ret)
1506                 return ret;
1507         seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1508                    fw_info.feature, fw_info.ver);
1509
1510         /* MEC */
1511         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1512         query_fw.index = 0;
1513         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1514         if (ret)
1515                 return ret;
1516         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1517                    fw_info.feature, fw_info.ver);
1518
1519         /* MEC2 */
1520         if (adev->gfx.mec2_fw) {
1521                 query_fw.index = 1;
1522                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1523                 if (ret)
1524                         return ret;
1525                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1526                            fw_info.feature, fw_info.ver);
1527         }
1528
1529         /* IMU */
1530         query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1531         query_fw.index = 0;
1532         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1533         if (ret)
1534                 return ret;
1535         seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1536                    fw_info.feature, fw_info.ver);
1537
1538         /* PSP SOS */
1539         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1540         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1541         if (ret)
1542                 return ret;
1543         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1544                    fw_info.feature, fw_info.ver);
1545
1546
1547         /* PSP ASD */
1548         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1549         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1550         if (ret)
1551                 return ret;
1552         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1553                    fw_info.feature, fw_info.ver);
1554
1555         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1556         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1557                 query_fw.index = i;
1558                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1559                 if (ret)
1560                         continue;
1561
1562                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1563                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1564         }
1565
1566         /* SMC */
1567         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1568         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1569         if (ret)
1570                 return ret;
1571         smu_program = (fw_info.ver >> 24) & 0xff;
1572         smu_major = (fw_info.ver >> 16) & 0xff;
1573         smu_minor = (fw_info.ver >> 8) & 0xff;
1574         smu_debug = (fw_info.ver >> 0) & 0xff;
1575         seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1576                    fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1577
1578         /* SDMA */
1579         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1580         for (i = 0; i < adev->sdma.num_instances; i++) {
1581                 query_fw.index = i;
1582                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1583                 if (ret)
1584                         return ret;
1585                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1586                            i, fw_info.feature, fw_info.ver);
1587         }
1588
1589         /* VCN */
1590         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1591         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1592         if (ret)
1593                 return ret;
1594         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1595                    fw_info.feature, fw_info.ver);
1596
1597         /* DMCU */
1598         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1599         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1600         if (ret)
1601                 return ret;
1602         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1603                    fw_info.feature, fw_info.ver);
1604
1605         /* DMCUB */
1606         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1607         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1608         if (ret)
1609                 return ret;
1610         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1611                    fw_info.feature, fw_info.ver);
1612
1613         /* TOC */
1614         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1615         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1616         if (ret)
1617                 return ret;
1618         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1619                    fw_info.feature, fw_info.ver);
1620
1621         /* CAP */
1622         if (adev->psp.cap_fw) {
1623                 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1624                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1625                 if (ret)
1626                         return ret;
1627                 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1628                                 fw_info.feature, fw_info.ver);
1629         }
1630
1631         /* MES_KIQ */
1632         query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1633         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1634         if (ret)
1635                 return ret;
1636         seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1637                    fw_info.feature, fw_info.ver);
1638
1639         /* MES */
1640         query_fw.fw_type = AMDGPU_INFO_FW_MES;
1641         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1642         if (ret)
1643                 return ret;
1644         seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1645                    fw_info.feature, fw_info.ver);
1646
1647         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1648
1649         return 0;
1650 }
1651
1652 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1653
1654 #endif
1655
1656 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1657 {
1658 #if defined(CONFIG_DEBUG_FS)
1659         struct drm_minor *minor = adev_to_drm(adev)->primary;
1660         struct dentry *root = minor->debugfs_root;
1661
1662         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1663                             adev, &amdgpu_debugfs_firmware_info_fops);
1664
1665 #endif
1666 }