drivers/gpu/drm/amd/amdkfd/kfd_device.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/bsearch.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include "kfd_priv.h"
  27 #include "kfd_device_queue_manager.h"
  28 #include "kfd_pm4_headers_vi.h"
  29 #include "kfd_pm4_headers_aldebaran.h"
  30 #include "cwsr_trap_handler.h"
  31 #include "kfd_iommu.h"
  32 #include "amdgpu_amdkfd.h"
  33 #include "kfd_smi_events.h"
  34 #include "kfd_migrate.h"
  35
  36 #define MQD_SIZE_ALIGNED 768
  37
  38 /*
  39  * kfd_locked is used to lock the kfd driver during suspend or reset
  40  * once locked, kfd driver will stop any further GPU execution.
  41  * create process (open) will return -EAGAIN.
  42  */
  43 static atomic_t kfd_locked = ATOMIC_INIT(0);
  44
  45 #ifdef CONFIG_DRM_AMDGPU_CIK
  46 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
  47 #endif
  48 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
  49 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
  50 extern const struct kfd2kgd_calls arcturus_kfd2kgd;
  51 extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
  52 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
  53 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
  54
  55 static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
  56 #ifdef KFD_SUPPORT_IOMMU_V2
  57 #ifdef CONFIG_DRM_AMDGPU_CIK
  58         [CHIP_KAVERI] = &gfx_v7_kfd2kgd,
  59 #endif
  60         [CHIP_CARRIZO] = &gfx_v8_kfd2kgd,
  61         [CHIP_RAVEN] = &gfx_v9_kfd2kgd,
  62 #endif
  63 #ifdef CONFIG_DRM_AMDGPU_CIK
  64         [CHIP_HAWAII] = &gfx_v7_kfd2kgd,
  65 #endif
  66         [CHIP_TONGA] = &gfx_v8_kfd2kgd,
  67         [CHIP_FIJI] = &gfx_v8_kfd2kgd,
  68         [CHIP_POLARIS10] = &gfx_v8_kfd2kgd,
  69         [CHIP_POLARIS11] = &gfx_v8_kfd2kgd,
  70         [CHIP_POLARIS12] = &gfx_v8_kfd2kgd,
  71         [CHIP_VEGAM] = &gfx_v8_kfd2kgd,
  72         [CHIP_VEGA10] = &gfx_v9_kfd2kgd,
  73         [CHIP_VEGA12] = &gfx_v9_kfd2kgd,
  74         [CHIP_VEGA20] = &gfx_v9_kfd2kgd,
  75         [CHIP_RENOIR] = &gfx_v9_kfd2kgd,
  76         [CHIP_ARCTURUS] = &arcturus_kfd2kgd,
  77         [CHIP_ALDEBARAN] = &aldebaran_kfd2kgd,
  78         [CHIP_NAVI10] = &gfx_v10_kfd2kgd,
  79         [CHIP_NAVI12] = &gfx_v10_kfd2kgd,
  80         [CHIP_NAVI14] = &gfx_v10_kfd2kgd,
  81         [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd,
  82         [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd,
  83         [CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd,
  84         [CHIP_DIMGREY_CAVEFISH] = &gfx_v10_3_kfd2kgd,
  85         [CHIP_BEIGE_GOBY] = &gfx_v10_3_kfd2kgd,
  86         [CHIP_YELLOW_CARP] = &gfx_v10_3_kfd2kgd,
  87 };
  88
  89 #ifdef KFD_SUPPORT_IOMMU_V2
  90 static const struct kfd_device_info kaveri_device_info = {
  91         .asic_family = CHIP_KAVERI,
  92         .asic_name = "kaveri",
  93         .max_pasid_bits = 16,
  94         /* max num of queues for KV.TODO should be a dynamic value */
  95         .max_no_of_hqd  = 24,
  96         .doorbell_size  = 4,
  97         .ih_ring_entry_size = 4 * sizeof(uint32_t),
  98         .event_interrupt_class = &event_interrupt_class_cik,
  99         .num_of_watch_points = 4,
 100         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 101         .supports_cwsr = false,
 102         .needs_iommu_device = true,
 103         .needs_pci_atomics = false,
 104         .num_sdma_engines = 2,
 105         .num_xgmi_sdma_engines = 0,
 106         .num_sdma_queues_per_engine = 2,
 107 };
 108
 109 static const struct kfd_device_info carrizo_device_info = {
 110         .asic_family = CHIP_CARRIZO,
 111         .asic_name = "carrizo",
 112         .max_pasid_bits = 16,
 113         /* max num of queues for CZ.TODO should be a dynamic value */
 114         .max_no_of_hqd  = 24,
 115         .doorbell_size  = 4,
 116         .ih_ring_entry_size = 4 * sizeof(uint32_t),
 117         .event_interrupt_class = &event_interrupt_class_cik,
 118         .num_of_watch_points = 4,
 119         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 120         .supports_cwsr = true,
 121         .needs_iommu_device = true,
 122         .needs_pci_atomics = false,
 123         .num_sdma_engines = 2,
 124         .num_xgmi_sdma_engines = 0,
 125         .num_sdma_queues_per_engine = 2,
 126 };
 127 #endif
 128
 129 static const struct kfd_device_info raven_device_info = {
 130         .asic_family = CHIP_RAVEN,
 131         .asic_name = "raven",
 132         .max_pasid_bits = 16,
 133         .max_no_of_hqd  = 24,
 134         .doorbell_size  = 8,
 135         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 136         .event_interrupt_class = &event_interrupt_class_v9,
 137         .num_of_watch_points = 4,
 138         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 139         .supports_cwsr = true,
 140         .needs_iommu_device = true,
 141         .needs_pci_atomics = true,
 142         .num_sdma_engines = 1,
 143         .num_xgmi_sdma_engines = 0,
 144         .num_sdma_queues_per_engine = 2,
 145 };
 146
 147 static const struct kfd_device_info hawaii_device_info = {
 148         .asic_family = CHIP_HAWAII,
 149         .asic_name = "hawaii",
 150         .max_pasid_bits = 16,
 151         /* max num of queues for KV.TODO should be a dynamic value */
 152         .max_no_of_hqd  = 24,
 153         .doorbell_size  = 4,
 154         .ih_ring_entry_size = 4 * sizeof(uint32_t),
 155         .event_interrupt_class = &event_interrupt_class_cik,
 156         .num_of_watch_points = 4,
 157         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 158         .supports_cwsr = false,
 159         .needs_iommu_device = false,
 160         .needs_pci_atomics = false,
 161         .num_sdma_engines = 2,
 162         .num_xgmi_sdma_engines = 0,
 163         .num_sdma_queues_per_engine = 2,
 164 };
 165
 166 static const struct kfd_device_info tonga_device_info = {
 167         .asic_family = CHIP_TONGA,
 168         .asic_name = "tonga",
 169         .max_pasid_bits = 16,
 170         .max_no_of_hqd  = 24,
 171         .doorbell_size  = 4,
 172         .ih_ring_entry_size = 4 * sizeof(uint32_t),
 173         .event_interrupt_class = &event_interrupt_class_cik,
 174         .num_of_watch_points = 4,
 175         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 176         .supports_cwsr = false,
 177         .needs_iommu_device = false,
 178         .needs_pci_atomics = true,
 179         .num_sdma_engines = 2,
 180         .num_xgmi_sdma_engines = 0,
 181         .num_sdma_queues_per_engine = 2,
 182 };
 183
 184 static const struct kfd_device_info fiji_device_info = {
 185         .asic_family = CHIP_FIJI,
 186         .asic_name = "fiji",
 187         .max_pasid_bits = 16,
 188         .max_no_of_hqd  = 24,
 189         .doorbell_size  = 4,
 190         .ih_ring_entry_size = 4 * sizeof(uint32_t),
 191         .event_interrupt_class = &event_interrupt_class_cik,
 192         .num_of_watch_points = 4,
 193         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 194         .supports_cwsr = true,
 195         .needs_iommu_device = false,
 196         .needs_pci_atomics = true,
 197         .num_sdma_engines = 2,
 198         .num_xgmi_sdma_engines = 0,
 199         .num_sdma_queues_per_engine = 2,
 200 };
 201
 202 static const struct kfd_device_info fiji_vf_device_info = {
 203         .asic_family = CHIP_FIJI,
 204         .asic_name = "fiji",
 205         .max_pasid_bits = 16,
 206         .max_no_of_hqd  = 24,
 207         .doorbell_size  = 4,
 208         .ih_ring_entry_size = 4 * sizeof(uint32_t),
 209         .event_interrupt_class = &event_interrupt_class_cik,
 210         .num_of_watch_points = 4,
 211         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 212         .supports_cwsr = true,
 213         .needs_iommu_device = false,
 214         .needs_pci_atomics = false,
 215         .num_sdma_engines = 2,
 216         .num_xgmi_sdma_engines = 0,
 217         .num_sdma_queues_per_engine = 2,
 218 };
 219
 220
 221 static const struct kfd_device_info polaris10_device_info = {
 222         .asic_family = CHIP_POLARIS10,
 223         .asic_name = "polaris10",
 224         .max_pasid_bits = 16,
 225         .max_no_of_hqd  = 24,
 226         .doorbell_size  = 4,
 227         .ih_ring_entry_size = 4 * sizeof(uint32_t),
 228         .event_interrupt_class = &event_interrupt_class_cik,
 229         .num_of_watch_points = 4,
 230         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 231         .supports_cwsr = true,
 232         .needs_iommu_device = false,
 233         .needs_pci_atomics = true,
 234         .num_sdma_engines = 2,
 235         .num_xgmi_sdma_engines = 0,
 236         .num_sdma_queues_per_engine = 2,
 237 };
 238
 239 static const struct kfd_device_info polaris10_vf_device_info = {
 240         .asic_family = CHIP_POLARIS10,
 241         .asic_name = "polaris10",
 242         .max_pasid_bits = 16,
 243         .max_no_of_hqd  = 24,
 244         .doorbell_size  = 4,
 245         .ih_ring_entry_size = 4 * sizeof(uint32_t),
 246         .event_interrupt_class = &event_interrupt_class_cik,
 247         .num_of_watch_points = 4,
 248         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 249         .supports_cwsr = true,
 250         .needs_iommu_device = false,
 251         .needs_pci_atomics = false,
 252         .num_sdma_engines = 2,
 253         .num_xgmi_sdma_engines = 0,
 254         .num_sdma_queues_per_engine = 2,
 255 };
 256
 257 static const struct kfd_device_info polaris11_device_info = {
 258         .asic_family = CHIP_POLARIS11,
 259         .asic_name = "polaris11",
 260         .max_pasid_bits = 16,
 261         .max_no_of_hqd  = 24,
 262         .doorbell_size  = 4,
 263         .ih_ring_entry_size = 4 * sizeof(uint32_t),
 264         .event_interrupt_class = &event_interrupt_class_cik,
 265         .num_of_watch_points = 4,
 266         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 267         .supports_cwsr = true,
 268         .needs_iommu_device = false,
 269         .needs_pci_atomics = true,
 270         .num_sdma_engines = 2,
 271         .num_xgmi_sdma_engines = 0,
 272         .num_sdma_queues_per_engine = 2,
 273 };
 274
 275 static const struct kfd_device_info polaris12_device_info = {
 276         .asic_family = CHIP_POLARIS12,
 277         .asic_name = "polaris12",
 278         .max_pasid_bits = 16,
 279         .max_no_of_hqd  = 24,
 280         .doorbell_size  = 4,
 281         .ih_ring_entry_size = 4 * sizeof(uint32_t),
 282         .event_interrupt_class = &event_interrupt_class_cik,
 283         .num_of_watch_points = 4,
 284         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 285         .supports_cwsr = true,
 286         .needs_iommu_device = false,
 287         .needs_pci_atomics = true,
 288         .num_sdma_engines = 2,
 289         .num_xgmi_sdma_engines = 0,
 290         .num_sdma_queues_per_engine = 2,
 291 };
 292
 293 static const struct kfd_device_info vegam_device_info = {
 294         .asic_family = CHIP_VEGAM,
 295         .asic_name = "vegam",
 296         .max_pasid_bits = 16,
 297         .max_no_of_hqd  = 24,
 298         .doorbell_size  = 4,
 299         .ih_ring_entry_size = 4 * sizeof(uint32_t),
 300         .event_interrupt_class = &event_interrupt_class_cik,
 301         .num_of_watch_points = 4,
 302         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 303         .supports_cwsr = true,
 304         .needs_iommu_device = false,
 305         .needs_pci_atomics = true,
 306         .num_sdma_engines = 2,
 307         .num_xgmi_sdma_engines = 0,
 308         .num_sdma_queues_per_engine = 2,
 309 };
 310
 311 static const struct kfd_device_info vega10_device_info = {
 312         .asic_family = CHIP_VEGA10,
 313         .asic_name = "vega10",
 314         .max_pasid_bits = 16,
 315         .max_no_of_hqd  = 24,
 316         .doorbell_size  = 8,
 317         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 318         .event_interrupt_class = &event_interrupt_class_v9,
 319         .num_of_watch_points = 4,
 320         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 321         .supports_cwsr = true,
 322         .needs_iommu_device = false,
 323         .needs_pci_atomics = false,
 324         .num_sdma_engines = 2,
 325         .num_xgmi_sdma_engines = 0,
 326         .num_sdma_queues_per_engine = 2,
 327 };
 328
 329 static const struct kfd_device_info vega10_vf_device_info = {
 330         .asic_family = CHIP_VEGA10,
 331         .asic_name = "vega10",
 332         .max_pasid_bits = 16,
 333         .max_no_of_hqd  = 24,
 334         .doorbell_size  = 8,
 335         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 336         .event_interrupt_class = &event_interrupt_class_v9,
 337         .num_of_watch_points = 4,
 338         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 339         .supports_cwsr = true,
 340         .needs_iommu_device = false,
 341         .needs_pci_atomics = false,
 342         .num_sdma_engines = 2,
 343         .num_xgmi_sdma_engines = 0,
 344         .num_sdma_queues_per_engine = 2,
 345 };
 346
 347 static const struct kfd_device_info vega12_device_info = {
 348         .asic_family = CHIP_VEGA12,
 349         .asic_name = "vega12",
 350         .max_pasid_bits = 16,
 351         .max_no_of_hqd  = 24,
 352         .doorbell_size  = 8,
 353         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 354         .event_interrupt_class = &event_interrupt_class_v9,
 355         .num_of_watch_points = 4,
 356         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 357         .supports_cwsr = true,
 358         .needs_iommu_device = false,
 359         .needs_pci_atomics = false,
 360         .num_sdma_engines = 2,
 361         .num_xgmi_sdma_engines = 0,
 362         .num_sdma_queues_per_engine = 2,
 363 };
 364
 365 static const struct kfd_device_info vega20_device_info = {
 366         .asic_family = CHIP_VEGA20,
 367         .asic_name = "vega20",
 368         .max_pasid_bits = 16,
 369         .max_no_of_hqd  = 24,
 370         .doorbell_size  = 8,
 371         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 372         .event_interrupt_class = &event_interrupt_class_v9,
 373         .num_of_watch_points = 4,
 374         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 375         .supports_cwsr = true,
 376         .needs_iommu_device = false,
 377         .needs_pci_atomics = false,
 378         .num_sdma_engines = 2,
 379         .num_xgmi_sdma_engines = 0,
 380         .num_sdma_queues_per_engine = 8,
 381 };
 382
 383 static const struct kfd_device_info arcturus_device_info = {
 384         .asic_family = CHIP_ARCTURUS,
 385         .asic_name = "arcturus",
 386         .max_pasid_bits = 16,
 387         .max_no_of_hqd  = 24,
 388         .doorbell_size  = 8,
 389         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 390         .event_interrupt_class = &event_interrupt_class_v9,
 391         .num_of_watch_points = 4,
 392         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 393         .supports_cwsr = true,
 394         .needs_iommu_device = false,
 395         .needs_pci_atomics = false,
 396         .num_sdma_engines = 2,
 397         .num_xgmi_sdma_engines = 6,
 398         .num_sdma_queues_per_engine = 8,
 399 };
 400
 401 static const struct kfd_device_info aldebaran_device_info = {
 402         .asic_family = CHIP_ALDEBARAN,
 403         .asic_name = "aldebaran",
 404         .max_pasid_bits = 16,
 405         .max_no_of_hqd  = 24,
 406         .doorbell_size  = 8,
 407         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 408         .event_interrupt_class = &event_interrupt_class_v9,
 409         .num_of_watch_points = 4,
 410         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 411         .supports_cwsr = true,
 412         .needs_iommu_device = false,
 413         .needs_pci_atomics = false,
 414         .num_sdma_engines = 2,
 415         .num_xgmi_sdma_engines = 3,
 416         .num_sdma_queues_per_engine = 8,
 417 };
 418
 419 static const struct kfd_device_info renoir_device_info = {
 420         .asic_family = CHIP_RENOIR,
 421         .asic_name = "renoir",
 422         .max_pasid_bits = 16,
 423         .max_no_of_hqd  = 24,
 424         .doorbell_size  = 8,
 425         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 426         .event_interrupt_class = &event_interrupt_class_v9,
 427         .num_of_watch_points = 4,
 428         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 429         .supports_cwsr = true,
 430         .needs_iommu_device = false,
 431         .needs_pci_atomics = false,
 432         .num_sdma_engines = 1,
 433         .num_xgmi_sdma_engines = 0,
 434         .num_sdma_queues_per_engine = 2,
 435 };
 436
 437 static const struct kfd_device_info navi10_device_info = {
 438         .asic_family = CHIP_NAVI10,
 439         .asic_name = "navi10",
 440         .max_pasid_bits = 16,
 441         .max_no_of_hqd  = 24,
 442         .doorbell_size  = 8,
 443         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 444         .event_interrupt_class = &event_interrupt_class_v9,
 445         .num_of_watch_points = 4,
 446         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 447         .needs_iommu_device = false,
 448         .supports_cwsr = true,
 449         .needs_pci_atomics = true,
 450         .num_sdma_engines = 2,
 451         .num_xgmi_sdma_engines = 0,
 452         .num_sdma_queues_per_engine = 8,
 453 };
 454
 455 static const struct kfd_device_info navi12_device_info = {
 456         .asic_family = CHIP_NAVI12,
 457         .asic_name = "navi12",
 458         .max_pasid_bits = 16,
 459         .max_no_of_hqd  = 24,
 460         .doorbell_size  = 8,
 461         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 462         .event_interrupt_class = &event_interrupt_class_v9,
 463         .num_of_watch_points = 4,
 464         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 465         .needs_iommu_device = false,
 466         .supports_cwsr = true,
 467         .needs_pci_atomics = true,
 468         .num_sdma_engines = 2,
 469         .num_xgmi_sdma_engines = 0,
 470         .num_sdma_queues_per_engine = 8,
 471 };
 472
 473 static const struct kfd_device_info navi14_device_info = {
 474         .asic_family = CHIP_NAVI14,
 475         .asic_name = "navi14",
 476         .max_pasid_bits = 16,
 477         .max_no_of_hqd  = 24,
 478         .doorbell_size  = 8,
 479         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 480         .event_interrupt_class = &event_interrupt_class_v9,
 481         .num_of_watch_points = 4,
 482         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 483         .needs_iommu_device = false,
 484         .supports_cwsr = true,
 485         .needs_pci_atomics = true,
 486         .num_sdma_engines = 2,
 487         .num_xgmi_sdma_engines = 0,
 488         .num_sdma_queues_per_engine = 8,
 489 };
 490
 491 static const struct kfd_device_info sienna_cichlid_device_info = {
 492         .asic_family = CHIP_SIENNA_CICHLID,
 493         .asic_name = "sienna_cichlid",
 494         .max_pasid_bits = 16,
 495         .max_no_of_hqd  = 24,
 496         .doorbell_size  = 8,
 497         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 498         .event_interrupt_class = &event_interrupt_class_v9,
 499         .num_of_watch_points = 4,
 500         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 501         .needs_iommu_device = false,
 502         .supports_cwsr = true,
 503         .needs_pci_atomics = true,
 504         .num_sdma_engines = 4,
 505         .num_xgmi_sdma_engines = 0,
 506         .num_sdma_queues_per_engine = 8,
 507 };
 508
 509 static const struct kfd_device_info navy_flounder_device_info = {
 510         .asic_family = CHIP_NAVY_FLOUNDER,
 511         .asic_name = "navy_flounder",
 512         .max_pasid_bits = 16,
 513         .max_no_of_hqd  = 24,
 514         .doorbell_size  = 8,
 515         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 516         .event_interrupt_class = &event_interrupt_class_v9,
 517         .num_of_watch_points = 4,
 518         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 519         .needs_iommu_device = false,
 520         .supports_cwsr = true,
 521         .needs_pci_atomics = true,
 522         .num_sdma_engines = 2,
 523         .num_xgmi_sdma_engines = 0,
 524         .num_sdma_queues_per_engine = 8,
 525 };
 526
 527 static const struct kfd_device_info vangogh_device_info = {
 528         .asic_family = CHIP_VANGOGH,
 529         .asic_name = "vangogh",
 530         .max_pasid_bits = 16,
 531         .max_no_of_hqd  = 24,
 532         .doorbell_size  = 8,
 533         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 534         .event_interrupt_class = &event_interrupt_class_v9,
 535         .num_of_watch_points = 4,
 536         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 537         .needs_iommu_device = false,
 538         .supports_cwsr = true,
 539         .needs_pci_atomics = false,
 540         .num_sdma_engines = 1,
 541         .num_xgmi_sdma_engines = 0,
 542         .num_sdma_queues_per_engine = 2,
 543 };
 544
 545 static const struct kfd_device_info dimgrey_cavefish_device_info = {
 546         .asic_family = CHIP_DIMGREY_CAVEFISH,
 547         .asic_name = "dimgrey_cavefish",
 548         .max_pasid_bits = 16,
 549         .max_no_of_hqd  = 24,
 550         .doorbell_size  = 8,
 551         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 552         .event_interrupt_class = &event_interrupt_class_v9,
 553         .num_of_watch_points = 4,
 554         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 555         .needs_iommu_device = false,
 556         .supports_cwsr = true,
 557         .needs_pci_atomics = true,
 558         .num_sdma_engines = 2,
 559         .num_xgmi_sdma_engines = 0,
 560         .num_sdma_queues_per_engine = 8,
 561 };
 562
 563 static const struct kfd_device_info beige_goby_device_info = {
 564         .asic_family = CHIP_BEIGE_GOBY,
 565         .asic_name = "beige_goby",
 566         .max_pasid_bits = 16,
 567         .max_no_of_hqd  = 24,
 568         .doorbell_size  = 8,
 569         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 570         .event_interrupt_class = &event_interrupt_class_v9,
 571         .num_of_watch_points = 4,
 572         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 573         .needs_iommu_device = false,
 574         .supports_cwsr = true,
 575         .needs_pci_atomics = true,
 576         .num_sdma_engines = 1,
 577         .num_xgmi_sdma_engines = 0,
 578         .num_sdma_queues_per_engine = 8,
 579 };
 580
 581 static const struct kfd_device_info yellow_carp_device_info = {
 582         .asic_family = CHIP_YELLOW_CARP,
 583         .asic_name = "yellow_carp",
 584         .max_pasid_bits = 16,
 585         .max_no_of_hqd  = 24,
 586         .doorbell_size  = 8,
 587         .ih_ring_entry_size = 8 * sizeof(uint32_t),
 588         .event_interrupt_class = &event_interrupt_class_v9,
 589         .num_of_watch_points = 4,
 590         .mqd_size_aligned = MQD_SIZE_ALIGNED,
 591         .needs_iommu_device = false,
 592         .supports_cwsr = true,
 593         .needs_pci_atomics = false,
 594         .num_sdma_engines = 1,
 595         .num_xgmi_sdma_engines = 0,
 596         .num_sdma_queues_per_engine = 2,
 597 };
 598
 599 /* For each entry, [0] is regular and [1] is virtualisation device. */
 600 static const struct kfd_device_info *kfd_supported_devices[][2] = {
 601 #ifdef KFD_SUPPORT_IOMMU_V2
 602         [CHIP_KAVERI] = {&kaveri_device_info, NULL},
 603         [CHIP_CARRIZO] = {&carrizo_device_info, NULL},
 604 #endif
 605         [CHIP_RAVEN] = {&raven_device_info, NULL},
 606         [CHIP_HAWAII] = {&hawaii_device_info, NULL},
 607         [CHIP_TONGA] = {&tonga_device_info, NULL},
 608         [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info},
 609         [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info},
 610         [CHIP_POLARIS11] = {&polaris11_device_info, NULL},
 611         [CHIP_POLARIS12] = {&polaris12_device_info, NULL},
 612         [CHIP_VEGAM] = {&vegam_device_info, NULL},
 613         [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info},
 614         [CHIP_VEGA12] = {&vega12_device_info, NULL},
 615         [CHIP_VEGA20] = {&vega20_device_info, NULL},
 616         [CHIP_RENOIR] = {&renoir_device_info, NULL},
 617         [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
 618         [CHIP_ALDEBARAN] = {&aldebaran_device_info, &aldebaran_device_info},
 619         [CHIP_NAVI10] = {&navi10_device_info, NULL},
 620         [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info},
 621         [CHIP_NAVI14] = {&navi14_device_info, NULL},
 622         [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info},
 623         [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info},
 624         [CHIP_VANGOGH] = {&vangogh_device_info, NULL},
 625         [CHIP_DIMGREY_CAVEFISH] = {&dimgrey_cavefish_device_info, &dimgrey_cavefish_device_info},
 626         [CHIP_BEIGE_GOBY] = {&beige_goby_device_info, &beige_goby_device_info},
 627         [CHIP_YELLOW_CARP] = {&yellow_carp_device_info, NULL},
 628 };
 629
 630 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
 631                                 unsigned int chunk_size);
 632 static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
 633
 634 static int kfd_resume(struct kfd_dev *kfd);
 635
 636 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
 637         struct pci_dev *pdev, unsigned int asic_type, bool vf)
 638 {
 639         struct kfd_dev *kfd;
 640         const struct kfd_device_info *device_info;
 641         const struct kfd2kgd_calls *f2g;
 642
 643         if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2)
 644                 || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) {
 645                 dev_err(kfd_device, "asic_type %d out of range\n", asic_type);
 646                 return NULL; /* asic_type out of range */
 647         }
 648
 649         device_info = kfd_supported_devices[asic_type][vf];
 650         f2g = kfd2kgd_funcs[asic_type];
 651
 652         if (!device_info || !f2g) {
 653                 dev_err(kfd_device, "%s %s not supported in kfd\n",
 654                         amdgpu_asic_name[asic_type], vf ? "VF" : "");
 655                 return NULL;
 656         }
 657
 658         kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
 659         if (!kfd)
 660                 return NULL;
 661
 662         /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
 663          * 32 and 64-bit requests are possible and must be
 664          * supported.
 665          */
 666         kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kgd);
 667         if (device_info->needs_pci_atomics &&
 668             !kfd->pci_atomic_requested) {
 669                 dev_info(kfd_device,
 670                          "skipped device %x:%x, PCI rejects atomics\n",
 671                          pdev->vendor, pdev->device);
 672                 kfree(kfd);
 673                 return NULL;
 674         }
 675
 676         kfd->kgd = kgd;
 677         kfd->device_info = device_info;
 678         kfd->pdev = pdev;
 679         kfd->init_complete = false;
 680         kfd->kfd2kgd = f2g;
 681         atomic_set(&kfd->compute_profile, 0);
 682
 683         mutex_init(&kfd->doorbell_mutex);
 684         memset(&kfd->doorbell_available_index, 0,
 685                 sizeof(kfd->doorbell_available_index));
 686
 687         atomic_set(&kfd->sram_ecc_flag, 0);
 688
 689         ida_init(&kfd->doorbell_ida);
 690
 691         return kfd;
 692 }
 693
 694 static void kfd_cwsr_init(struct kfd_dev *kfd)
 695 {
 696         if (cwsr_enable && kfd->device_info->supports_cwsr) {
 697                 if (kfd->device_info->asic_family < CHIP_VEGA10) {
 698                         BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
 699                         kfd->cwsr_isa = cwsr_trap_gfx8_hex;
 700                         kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
 701                 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) {
 702                         BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
 703                         kfd->cwsr_isa = cwsr_trap_arcturus_hex;
 704                         kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
 705                 } else if (kfd->device_info->asic_family == CHIP_ALDEBARAN) {
 706                         BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE);
 707                         kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
 708                         kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
 709                 } else if (kfd->device_info->asic_family < CHIP_NAVI10) {
 710                         BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
 711                         kfd->cwsr_isa = cwsr_trap_gfx9_hex;
 712                         kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
 713                 } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) {
 714                         BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
 715                         kfd->cwsr_isa = cwsr_trap_nv1x_hex;
 716                         kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
 717                 } else {
 718                         BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE);
 719                         kfd->cwsr_isa = cwsr_trap_gfx10_hex;
 720                         kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
 721                 }
 722
 723                 kfd->cwsr_enabled = true;
 724         }
 725 }
 726
 727 static int kfd_gws_init(struct kfd_dev *kfd)
 728 {
 729         int ret = 0;
 730
 731         if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
 732                 return 0;
 733
 734         if (hws_gws_support
 735                 || (kfd->device_info->asic_family == CHIP_VEGA10
 736                         && kfd->mec2_fw_version >= 0x81b3)
 737                 || (kfd->device_info->asic_family >= CHIP_VEGA12
 738                         && kfd->device_info->asic_family <= CHIP_RAVEN
 739                         && kfd->mec2_fw_version >= 0x1b3)
 740                 || (kfd->device_info->asic_family == CHIP_ARCTURUS
 741                         && kfd->mec2_fw_version >= 0x30)
 742                 || (kfd->device_info->asic_family == CHIP_ALDEBARAN
 743                         && kfd->mec2_fw_version >= 0x28))
 744                 ret = amdgpu_amdkfd_alloc_gws(kfd->kgd,
 745                                 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws);
 746
 747         return ret;
 748 }
 749
 750 static void kfd_smi_init(struct kfd_dev *dev) {
 751         INIT_LIST_HEAD(&dev->smi_clients);
 752         spin_lock_init(&dev->smi_lock);
 753 }
 754
 755 bool kgd2kfd_device_init(struct kfd_dev *kfd,
 756                          struct drm_device *ddev,
 757                          const struct kgd2kfd_shared_resources *gpu_resources)
 758 {
 759         unsigned int size, map_process_packet_size;
 760
 761         kfd->ddev = ddev;
 762         kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
 763                         KGD_ENGINE_MEC1);
 764         kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
 765                         KGD_ENGINE_MEC2);
 766         kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
 767                         KGD_ENGINE_SDMA1);
 768         kfd->shared_resources = *gpu_resources;
 769
 770         kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
 771         kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
 772         kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
 773                         - kfd->vm_info.first_vmid_kfd + 1;
 774
 775         /* Verify module parameters regarding mapped process number*/
 776         if ((hws_max_conc_proc < 0)
 777                         || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) {
 778                 dev_err(kfd_device,
 779                         "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n",
 780                         hws_max_conc_proc, kfd->vm_info.vmid_num_kfd,
 781                         kfd->vm_info.vmid_num_kfd);
 782                 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;
 783         } else
 784                 kfd->max_proc_per_quantum = hws_max_conc_proc;
 785
 786         /* calculate max size of mqds needed for queues */
 787         size = max_num_of_queues_per_device *
 788                         kfd->device_info->mqd_size_aligned;
 789
 790         /*
 791          * calculate max size of runlist packet.
 792          * There can be only 2 packets at once
 793          */
 794         map_process_packet_size =
 795                         kfd->device_info->asic_family == CHIP_ALDEBARAN ?
 796                                 sizeof(struct pm4_mes_map_process_aldebaran) :
 797                                         sizeof(struct pm4_mes_map_process);
 798         size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
 799                 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
 800                 + sizeof(struct pm4_mes_runlist)) * 2;
 801
 802         /* Add size of HIQ & DIQ */
 803         size += KFD_KERNEL_QUEUE_SIZE * 2;
 804
 805         /* add another 512KB for all other allocations on gart (HPD, fences) */
 806         size += 512 * 1024;
 807
 808         if (amdgpu_amdkfd_alloc_gtt_mem(
 809                         kfd->kgd, size, &kfd->gtt_mem,
 810                         &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
 811                         false)) {
 812                 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
 813                 goto alloc_gtt_mem_failure;
 814         }
 815
 816         dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
 817
 818         /* Initialize GTT sa with 512 byte chunk size */
 819         if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
 820                 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
 821                 goto kfd_gtt_sa_init_error;
 822         }
 823
 824         if (kfd_doorbell_init(kfd)) {
 825                 dev_err(kfd_device,
 826                         "Error initializing doorbell aperture\n");
 827                 goto kfd_doorbell_error;
 828         }
 829
 830         kfd->hive_id = amdgpu_amdkfd_get_hive_id(kfd->kgd);
 831
 832         kfd->noretry = amdgpu_amdkfd_get_noretry(kfd->kgd);
 833
 834         if (kfd_interrupt_init(kfd)) {
 835                 dev_err(kfd_device, "Error initializing interrupts\n");
 836                 goto kfd_interrupt_error;
 837         }
 838
 839         kfd->dqm = device_queue_manager_init(kfd);
 840         if (!kfd->dqm) {
 841                 dev_err(kfd_device, "Error initializing queue manager\n");
 842                 goto device_queue_manager_error;
 843         }
 844
 845         /* If supported on this device, allocate global GWS that is shared
 846          * by all KFD processes
 847          */
 848         if (kfd_gws_init(kfd)) {
 849                 dev_err(kfd_device, "Could not allocate %d gws\n",
 850                         amdgpu_amdkfd_get_num_gws(kfd->kgd));
 851                 goto gws_error;
 852         }
 853
 854         /* If CRAT is broken, won't set iommu enabled */
 855         kfd_double_confirm_iommu_support(kfd);
 856
 857         if (kfd_iommu_device_init(kfd)) {
 858                 dev_err(kfd_device, "Error initializing iommuv2\n");
 859                 goto device_iommu_error;
 860         }
 861
 862         kfd_cwsr_init(kfd);
 863
 864         svm_migrate_init((struct amdgpu_device *)kfd->kgd);
 865
 866         if (kfd_resume(kfd))
 867                 goto kfd_resume_error;
 868
 869         kfd->dbgmgr = NULL;
 870
 871         if (kfd_topology_add_device(kfd)) {
 872                 dev_err(kfd_device, "Error adding device to topology\n");
 873                 goto kfd_topology_add_device_error;
 874         }
 875
 876         kfd_smi_init(kfd);
 877
 878         kfd->init_complete = true;
 879         dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor,
 880                  kfd->pdev->device);
 881
 882         pr_debug("Starting kfd with the following scheduling policy %d\n",
 883                 kfd->dqm->sched_policy);
 884
 885         goto out;
 886
 887 kfd_topology_add_device_error:
 888 kfd_resume_error:
 889 device_iommu_error:
 890 gws_error:
 891         device_queue_manager_uninit(kfd->dqm);
 892 device_queue_manager_error:
 893         kfd_interrupt_exit(kfd);
 894 kfd_interrupt_error:
 895         kfd_doorbell_fini(kfd);
 896 kfd_doorbell_error:
 897         kfd_gtt_sa_fini(kfd);
 898 kfd_gtt_sa_init_error:
 899         amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
 900 alloc_gtt_mem_failure:
 901         if (kfd->gws)
 902                 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws);
 903         dev_err(kfd_device,
 904                 "device %x:%x NOT added due to errors\n",
 905                 kfd->pdev->vendor, kfd->pdev->device);
 906 out:
 907         return kfd->init_complete;
 908 }
 909
 910 void kgd2kfd_device_exit(struct kfd_dev *kfd)
 911 {
 912         if (kfd->init_complete) {
 913                 svm_migrate_fini((struct amdgpu_device *)kfd->kgd);
 914                 device_queue_manager_uninit(kfd->dqm);
 915                 kfd_interrupt_exit(kfd);
 916                 kfd_topology_remove_device(kfd);
 917                 kfd_doorbell_fini(kfd);
 918                 ida_destroy(&kfd->doorbell_ida);
 919                 kfd_gtt_sa_fini(kfd);
 920                 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
 921                 if (kfd->gws)
 922                         amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws);
 923         }
 924
 925         kfree(kfd);
 926 }
 927
 928 int kgd2kfd_pre_reset(struct kfd_dev *kfd)
 929 {
 930         if (!kfd->init_complete)
 931                 return 0;
 932
 933         kfd_smi_event_update_gpu_reset(kfd, false);
 934
 935         kfd->dqm->ops.pre_reset(kfd->dqm);
 936
 937         kgd2kfd_suspend(kfd, false);
 938
 939         kfd_signal_reset_event(kfd);
 940         return 0;
 941 }
 942
 943 /*
 944  * Fix me. KFD won't be able to resume existing process for now.
 945  * We will keep all existing process in a evicted state and
 946  * wait the process to be terminated.
 947  */
 948
 949 int kgd2kfd_post_reset(struct kfd_dev *kfd)
 950 {
 951         int ret;
 952
 953         if (!kfd->init_complete)
 954                 return 0;
 955
 956         ret = kfd_resume(kfd);
 957         if (ret)
 958                 return ret;
 959         atomic_dec(&kfd_locked);
 960
 961         atomic_set(&kfd->sram_ecc_flag, 0);
 962
 963         kfd_smi_event_update_gpu_reset(kfd, true);
 964
 965         return 0;
 966 }
 967
 968 bool kfd_is_locked(void)
 969 {
 970         return  (atomic_read(&kfd_locked) > 0);
 971 }
 972
 973 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
 974 {
 975         if (!kfd->init_complete)
 976                 return;
 977
 978         /* for runtime suspend, skip locking kfd */
 979         if (!run_pm) {
 980                 /* For first KFD device suspend all the KFD processes */
 981                 if (atomic_inc_return(&kfd_locked) == 1)
 982                         kfd_suspend_all_processes();
 983         }
 984
 985         kfd->dqm->ops.stop(kfd->dqm);
 986         kfd_iommu_suspend(kfd);
 987 }
 988
 989 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
 990 {
 991         int ret, count;
 992
 993         if (!kfd->init_complete)
 994                 return 0;
 995
 996         ret = kfd_resume(kfd);
 997         if (ret)
 998                 return ret;
 999
1000         /* for runtime resume, skip unlocking kfd */
1001         if (!run_pm) {
1002                 count = atomic_dec_return(&kfd_locked);
1003                 WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
1004                 if (count == 0)
1005                         ret = kfd_resume_all_processes();
1006         }
1007
1008         return ret;
1009 }
1010
1011 static int kfd_resume(struct kfd_dev *kfd)
1012 {
1013         int err = 0;
1014
1015         err = kfd_iommu_resume(kfd);
1016         if (err) {
1017                 dev_err(kfd_device,
1018                         "Failed to resume IOMMU for device %x:%x\n",
1019                         kfd->pdev->vendor, kfd->pdev->device);
1020                 return err;
1021         }
1022
1023         err = kfd->dqm->ops.start(kfd->dqm);
1024         if (err) {
1025                 dev_err(kfd_device,
1026                         "Error starting queue manager for device %x:%x\n",
1027                         kfd->pdev->vendor, kfd->pdev->device);
1028                 goto dqm_start_error;
1029         }
1030
1031         return err;
1032
1033 dqm_start_error:
1034         kfd_iommu_suspend(kfd);
1035         return err;
1036 }
1037
1038 static inline void kfd_queue_work(struct workqueue_struct *wq,
1039                                   struct work_struct *work)
1040 {
1041         int cpu, new_cpu;
1042
1043         cpu = new_cpu = smp_processor_id();
1044         do {
1045                 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids;
1046                 if (cpu_to_node(new_cpu) == numa_node_id())
1047                         break;
1048         } while (cpu != new_cpu);
1049
1050         queue_work_on(new_cpu, wq, work);
1051 }
1052
1053 /* This is called directly from KGD at ISR. */
1054 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
1055 {
1056         uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE];
1057         bool is_patched = false;
1058         unsigned long flags;
1059
1060         if (!kfd->init_complete)
1061                 return;
1062
1063         if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) {
1064                 dev_err_once(kfd_device, "Ring entry too small\n");
1065                 return;
1066         }
1067
1068         spin_lock_irqsave(&kfd->interrupt_lock, flags);
1069
1070         if (kfd->interrupts_active
1071             && interrupt_is_wanted(kfd, ih_ring_entry,
1072                                    patched_ihre, &is_patched)
1073             && enqueue_ih_ring_entry(kfd,
1074                                      is_patched ? patched_ihre : ih_ring_entry))
1075                 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work);
1076
1077         spin_unlock_irqrestore(&kfd->interrupt_lock, flags);
1078 }
1079
1080 int kgd2kfd_quiesce_mm(struct mm_struct *mm)
1081 {
1082         struct kfd_process *p;
1083         int r;
1084
1085         /* Because we are called from arbitrary context (workqueue) as opposed
1086          * to process context, kfd_process could attempt to exit while we are
1087          * running so the lookup function increments the process ref count.
1088          */
1089         p = kfd_lookup_process_by_mm(mm);
1090         if (!p)
1091                 return -ESRCH;
1092
1093         WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
1094         r = kfd_process_evict_queues(p);
1095
1096         kfd_unref_process(p);
1097         return r;
1098 }
1099
1100 int kgd2kfd_resume_mm(struct mm_struct *mm)
1101 {
1102         struct kfd_process *p;
1103         int r;
1104
1105         /* Because we are called from arbitrary context (workqueue) as opposed
1106          * to process context, kfd_process could attempt to exit while we are
1107          * running so the lookup function increments the process ref count.
1108          */
1109         p = kfd_lookup_process_by_mm(mm);
1110         if (!p)
1111                 return -ESRCH;
1112
1113         r = kfd_process_restore_queues(p);
1114
1115         kfd_unref_process(p);
1116         return r;
1117 }
1118
1119 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
1120  *   prepare for safe eviction of KFD BOs that belong to the specified
1121  *   process.
1122  *
1123  * @mm: mm_struct that identifies the specified KFD process
1124  * @fence: eviction fence attached to KFD process BOs
1125  *
1126  */
1127 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
1128                                                struct dma_fence *fence)
1129 {
1130         struct kfd_process *p;
1131         unsigned long active_time;
1132         unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
1133
1134         if (!fence)
1135                 return -EINVAL;
1136
1137         if (dma_fence_is_signaled(fence))
1138                 return 0;
1139
1140         p = kfd_lookup_process_by_mm(mm);
1141         if (!p)
1142                 return -ENODEV;
1143
1144         if (fence->seqno == p->last_eviction_seqno)
1145                 goto out;
1146
1147         p->last_eviction_seqno = fence->seqno;
1148
1149         /* Avoid KFD process starvation. Wait for at least
1150          * PROCESS_ACTIVE_TIME_MS before evicting the process again
1151          */
1152         active_time = get_jiffies_64() - p->last_restore_timestamp;
1153         if (delay_jiffies > active_time)
1154                 delay_jiffies -= active_time;
1155         else
1156                 delay_jiffies = 0;
1157
1158         /* During process initialization eviction_work.dwork is initialized
1159          * to kfd_evict_bo_worker
1160          */
1161         WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
1162              p->lead_thread->pid, delay_jiffies);
1163         schedule_delayed_work(&p->eviction_work, delay_jiffies);
1164 out:
1165         kfd_unref_process(p);
1166         return 0;
1167 }
1168
1169 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
1170                                 unsigned int chunk_size)
1171 {
1172         unsigned int num_of_longs;
1173
1174         if (WARN_ON(buf_size < chunk_size))
1175                 return -EINVAL;
1176         if (WARN_ON(buf_size == 0))
1177                 return -EINVAL;
1178         if (WARN_ON(chunk_size == 0))
1179                 return -EINVAL;
1180
1181         kfd->gtt_sa_chunk_size = chunk_size;
1182         kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
1183
1184         num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) /
1185                 BITS_PER_LONG;
1186
1187         kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL);
1188
1189         if (!kfd->gtt_sa_bitmap)
1190                 return -ENOMEM;
1191
1192         pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
1193                         kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
1194
1195         mutex_init(&kfd->gtt_sa_lock);
1196
1197         return 0;
1198
1199 }
1200
1201 static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
1202 {
1203         mutex_destroy(&kfd->gtt_sa_lock);
1204         kfree(kfd->gtt_sa_bitmap);
1205 }
1206
1207 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
1208                                                 unsigned int bit_num,
1209                                                 unsigned int chunk_size)
1210 {
1211         return start_addr + bit_num * chunk_size;
1212 }
1213
1214 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
1215                                                 unsigned int bit_num,
1216                                                 unsigned int chunk_size)
1217 {
1218         return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
1219 }
1220
1221 int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
1222                         struct kfd_mem_obj **mem_obj)
1223 {
1224         unsigned int found, start_search, cur_size;
1225
1226         if (size == 0)
1227                 return -EINVAL;
1228
1229         if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
1230                 return -ENOMEM;
1231
1232         *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
1233         if (!(*mem_obj))
1234                 return -ENOMEM;
1235
1236         pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1237
1238         start_search = 0;
1239
1240         mutex_lock(&kfd->gtt_sa_lock);
1241
1242 kfd_gtt_restart_search:
1243         /* Find the first chunk that is free */
1244         found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1245                                         kfd->gtt_sa_num_of_chunks,
1246                                         start_search);
1247
1248         pr_debug("Found = %d\n", found);
1249
1250         /* If there wasn't any free chunk, bail out */
1251         if (found == kfd->gtt_sa_num_of_chunks)
1252                 goto kfd_gtt_no_free_chunk;
1253
1254         /* Update fields of mem_obj */
1255         (*mem_obj)->range_start = found;
1256         (*mem_obj)->range_end = found;
1257         (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1258                                         kfd->gtt_start_gpu_addr,
1259                                         found,
1260                                         kfd->gtt_sa_chunk_size);
1261         (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1262                                         kfd->gtt_start_cpu_ptr,
1263                                         found,
1264                                         kfd->gtt_sa_chunk_size);
1265
1266         pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1267                         (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1268
1269         /* If we need only one chunk, mark it as allocated and get out */
1270         if (size <= kfd->gtt_sa_chunk_size) {
1271                 pr_debug("Single bit\n");
1272                 set_bit(found, kfd->gtt_sa_bitmap);
1273                 goto kfd_gtt_out;
1274         }
1275
1276         /* Otherwise, try to see if we have enough contiguous chunks */
1277         cur_size = size - kfd->gtt_sa_chunk_size;
1278         do {
1279                 (*mem_obj)->range_end =
1280                         find_next_zero_bit(kfd->gtt_sa_bitmap,
1281                                         kfd->gtt_sa_num_of_chunks, ++found);
1282                 /*
1283                  * If next free chunk is not contiguous than we need to
1284                  * restart our search from the last free chunk we found (which
1285                  * wasn't contiguous to the previous ones
1286                  */
1287                 if ((*mem_obj)->range_end != found) {
1288                         start_search = found;
1289                         goto kfd_gtt_restart_search;
1290                 }
1291
1292                 /*
1293                  * If we reached end of buffer, bail out with error
1294                  */
1295                 if (found == kfd->gtt_sa_num_of_chunks)
1296                         goto kfd_gtt_no_free_chunk;
1297
1298                 /* Check if we don't need another chunk */
1299                 if (cur_size <= kfd->gtt_sa_chunk_size)
1300                         cur_size = 0;
1301                 else
1302                         cur_size -= kfd->gtt_sa_chunk_size;
1303
1304         } while (cur_size > 0);
1305
1306         pr_debug("range_start = %d, range_end = %d\n",
1307                 (*mem_obj)->range_start, (*mem_obj)->range_end);
1308
1309         /* Mark the chunks as allocated */
1310         for (found = (*mem_obj)->range_start;
1311                 found <= (*mem_obj)->range_end;
1312                 found++)
1313                 set_bit(found, kfd->gtt_sa_bitmap);
1314
1315 kfd_gtt_out:
1316         mutex_unlock(&kfd->gtt_sa_lock);
1317         return 0;
1318
1319 kfd_gtt_no_free_chunk:
1320         pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1321         mutex_unlock(&kfd->gtt_sa_lock);
1322         kfree(*mem_obj);
1323         return -ENOMEM;
1324 }
1325
1326 int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
1327 {
1328         unsigned int bit;
1329
1330         /* Act like kfree when trying to free a NULL object */
1331         if (!mem_obj)
1332                 return 0;
1333
1334         pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1335                         mem_obj, mem_obj->range_start, mem_obj->range_end);
1336
1337         mutex_lock(&kfd->gtt_sa_lock);
1338
1339         /* Mark the chunks as free */
1340         for (bit = mem_obj->range_start;
1341                 bit <= mem_obj->range_end;
1342                 bit++)
1343                 clear_bit(bit, kfd->gtt_sa_bitmap);
1344
1345         mutex_unlock(&kfd->gtt_sa_lock);
1346
1347         kfree(mem_obj);
1348         return 0;
1349 }
1350
1351 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1352 {
1353         if (kfd)
1354                 atomic_inc(&kfd->sram_ecc_flag);
1355 }
1356
1357 void kfd_inc_compute_active(struct kfd_dev *kfd)
1358 {
1359         if (atomic_inc_return(&kfd->compute_profile) == 1)
1360                 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false);
1361 }
1362
1363 void kfd_dec_compute_active(struct kfd_dev *kfd)
1364 {
1365         int count = atomic_dec_return(&kfd->compute_profile);
1366
1367         if (count == 0)
1368                 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true);
1369         WARN_ONCE(count < 0, "Compute profile ref. count error");
1370 }
1371
1372 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask)
1373 {
1374         if (kfd && kfd->init_complete)
1375                 kfd_smi_event_update_thermal_throttling(kfd, throttle_bitmask);
1376 }
1377
1378 #if defined(CONFIG_DEBUG_FS)
1379
1380 /* This function will send a package to HIQ to hang the HWS
1381  * which will trigger a GPU reset and bring the HWS back to normal state
1382  */
1383 int kfd_debugfs_hang_hws(struct kfd_dev *dev)
1384 {
1385         int r = 0;
1386
1387         if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1388                 pr_err("HWS is not enabled");
1389                 return -EINVAL;
1390         }
1391
1392         r = pm_debugfs_hang_hws(&dev->dqm->packets);
1393         if (!r)
1394                 r = dqm_debugfs_execute_queues(dev->dqm);
1395
1396         return r;
1397 }
1398
1399 #endif