drivers/gpu/drm/xlnx/zynqmp_dp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ZynqMP DisplayPort Driver
   4  *
   5  * Copyright (C) 2017 - 2020 Xilinx, Inc.
   6  *
   7  * Authors:
   8  * - Hyun Woo Kwon <[email protected]>
   9  * - Laurent Pinchart <[email protected]>
  10  */
  11
  12 #include <drm/drm_atomic_helper.h>
  13 #include <drm/drm_connector.h>
  14 #include <drm/drm_crtc.h>
  15 #include <drm/drm_device.h>
  16 #include <drm/drm_dp_helper.h>
  17 #include <drm/drm_edid.h>
  18 #include <drm/drm_encoder.h>
  19 #include <drm/drm_managed.h>
  20 #include <drm/drm_modes.h>
  21 #include <drm/drm_of.h>
  22 #include <drm/drm_probe_helper.h>
  23 #include <drm/drm_simple_kms_helper.h>
  24
  25 #include <linux/clk.h>
  26 #include <linux/delay.h>
  27 #include <linux/device.h>
  28 #include <linux/module.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/phy/phy.h>
  32 #include <linux/reset.h>
  33
  34 #include "zynqmp_disp.h"
  35 #include "zynqmp_dp.h"
  36 #include "zynqmp_dpsub.h"
  37
  38 static uint zynqmp_dp_aux_timeout_ms = 50;
  39 module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444);
  40 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
  41
  42 /*
  43  * Some sink requires a delay after power on request
  44  */
  45 static uint zynqmp_dp_power_on_delay_ms = 4;
  46 module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444);
  47 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
  48
  49 /* Link configuration registers */
  50 #define ZYNQMP_DP_LINK_BW_SET                           0x0
  51 #define ZYNQMP_DP_LANE_COUNT_SET                        0x4
  52 #define ZYNQMP_DP_ENHANCED_FRAME_EN                     0x8
  53 #define ZYNQMP_DP_TRAINING_PATTERN_SET                  0xc
  54 #define ZYNQMP_DP_SCRAMBLING_DISABLE                    0x14
  55 #define ZYNQMP_DP_DOWNSPREAD_CTL                        0x18
  56 #define ZYNQMP_DP_SOFTWARE_RESET                        0x1c
  57 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM1                BIT(0)
  58 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM2                BIT(1)
  59 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM3                BIT(2)
  60 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM4                BIT(3)
  61 #define ZYNQMP_DP_SOFTWARE_RESET_AUX                    BIT(7)
  62 #define ZYNQMP_DP_SOFTWARE_RESET_ALL                    (ZYNQMP_DP_SOFTWARE_RESET_STREAM1 | \
  63                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM2 | \
  64                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM3 | \
  65                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM4 | \
  66                                                          ZYNQMP_DP_SOFTWARE_RESET_AUX)
  67
  68 /* Core enable registers */
  69 #define ZYNQMP_DP_TRANSMITTER_ENABLE                    0x80
  70 #define ZYNQMP_DP_MAIN_STREAM_ENABLE                    0x84
  71 #define ZYNQMP_DP_FORCE_SCRAMBLER_RESET                 0xc0
  72 #define ZYNQMP_DP_VERSION                               0xf8
  73 #define ZYNQMP_DP_VERSION_MAJOR_MASK                    GENMASK(31, 24)
  74 #define ZYNQMP_DP_VERSION_MAJOR_SHIFT                   24
  75 #define ZYNQMP_DP_VERSION_MINOR_MASK                    GENMASK(23, 16)
  76 #define ZYNQMP_DP_VERSION_MINOR_SHIFT                   16
  77 #define ZYNQMP_DP_VERSION_REVISION_MASK                 GENMASK(15, 12)
  78 #define ZYNQMP_DP_VERSION_REVISION_SHIFT                12
  79 #define ZYNQMP_DP_VERSION_PATCH_MASK                    GENMASK(11, 8)
  80 #define ZYNQMP_DP_VERSION_PATCH_SHIFT                   8
  81 #define ZYNQMP_DP_VERSION_INTERNAL_MASK                 GENMASK(7, 0)
  82 #define ZYNQMP_DP_VERSION_INTERNAL_SHIFT                0
  83
  84 /* Core ID registers */
  85 #define ZYNQMP_DP_CORE_ID                               0xfc
  86 #define ZYNQMP_DP_CORE_ID_MAJOR_MASK                    GENMASK(31, 24)
  87 #define ZYNQMP_DP_CORE_ID_MAJOR_SHIFT                   24
  88 #define ZYNQMP_DP_CORE_ID_MINOR_MASK                    GENMASK(23, 16)
  89 #define ZYNQMP_DP_CORE_ID_MINOR_SHIFT                   16
  90 #define ZYNQMP_DP_CORE_ID_REVISION_MASK                 GENMASK(15, 8)
  91 #define ZYNQMP_DP_CORE_ID_REVISION_SHIFT                8
  92 #define ZYNQMP_DP_CORE_ID_DIRECTION                     GENMASK(1)
  93
  94 /* AUX channel interface registers */
  95 #define ZYNQMP_DP_AUX_COMMAND                           0x100
  96 #define ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT                 8
  97 #define ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY              BIT(12)
  98 #define ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT               0
  99 #define ZYNQMP_DP_AUX_WRITE_FIFO                        0x104
 100 #define ZYNQMP_DP_AUX_ADDRESS                           0x108
 101 #define ZYNQMP_DP_AUX_CLK_DIVIDER                       0x10c
 102 #define ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT      8
 103 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE                0x130
 104 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD            BIT(0)
 105 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST        BIT(1)
 106 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY          BIT(2)
 107 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT  BIT(3)
 108 #define ZYNQMP_DP_AUX_REPLY_DATA                        0x134
 109 #define ZYNQMP_DP_AUX_REPLY_CODE                        0x138
 110 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK                (0)
 111 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_NACK               BIT(0)
 112 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_DEFER              BIT(1)
 113 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK                (0)
 114 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_NACK               BIT(2)
 115 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_DEFER              BIT(3)
 116 #define ZYNQMP_DP_AUX_REPLY_COUNT                       0x13c
 117 #define ZYNQMP_DP_REPLY_DATA_COUNT                      0x148
 118 #define ZYNQMP_DP_REPLY_DATA_COUNT_MASK                 0xff
 119 #define ZYNQMP_DP_INT_STATUS                            0x3a0
 120 #define ZYNQMP_DP_INT_MASK                              0x3a4
 121 #define ZYNQMP_DP_INT_EN                                0x3a8
 122 #define ZYNQMP_DP_INT_DS                                0x3ac
 123 #define ZYNQMP_DP_INT_HPD_IRQ                           BIT(0)
 124 #define ZYNQMP_DP_INT_HPD_EVENT                         BIT(1)
 125 #define ZYNQMP_DP_INT_REPLY_RECEIVED                    BIT(2)
 126 #define ZYNQMP_DP_INT_REPLY_TIMEOUT                     BIT(3)
 127 #define ZYNQMP_DP_INT_HPD_PULSE_DET                     BIT(4)
 128 #define ZYNQMP_DP_INT_EXT_PKT_TXD                       BIT(5)
 129 #define ZYNQMP_DP_INT_LIV_ABUF_UNDRFLW                  BIT(12)
 130 #define ZYNQMP_DP_INT_VBLANK_START                      BIT(13)
 131 #define ZYNQMP_DP_INT_PIXEL1_MATCH                      BIT(14)
 132 #define ZYNQMP_DP_INT_PIXEL0_MATCH                      BIT(15)
 133 #define ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK               0x3f0000
 134 #define ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK                0xfc00000
 135 #define ZYNQMP_DP_INT_CUST_TS_2                         BIT(28)
 136 #define ZYNQMP_DP_INT_CUST_TS                           BIT(29)
 137 #define ZYNQMP_DP_INT_EXT_VSYNC_TS                      BIT(30)
 138 #define ZYNQMP_DP_INT_VSYNC_TS                          BIT(31)
 139 #define ZYNQMP_DP_INT_ALL                               (ZYNQMP_DP_INT_HPD_IRQ | \
 140                                                          ZYNQMP_DP_INT_HPD_EVENT | \
 141                                                          ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK | \
 142                                                          ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK)
 143
 144 /* Main stream attribute registers */
 145 #define ZYNQMP_DP_MAIN_STREAM_HTOTAL                    0x180
 146 #define ZYNQMP_DP_MAIN_STREAM_VTOTAL                    0x184
 147 #define ZYNQMP_DP_MAIN_STREAM_POLARITY                  0x188
 148 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT      0
 149 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT      1
 150 #define ZYNQMP_DP_MAIN_STREAM_HSWIDTH                   0x18c
 151 #define ZYNQMP_DP_MAIN_STREAM_VSWIDTH                   0x190
 152 #define ZYNQMP_DP_MAIN_STREAM_HRES                      0x194
 153 #define ZYNQMP_DP_MAIN_STREAM_VRES                      0x198
 154 #define ZYNQMP_DP_MAIN_STREAM_HSTART                    0x19c
 155 #define ZYNQMP_DP_MAIN_STREAM_VSTART                    0x1a0
 156 #define ZYNQMP_DP_MAIN_STREAM_MISC0                     0x1a4
 157 #define ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK           BIT(0)
 158 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB     (0 << 1)
 159 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422       (5 << 1)
 160 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444       (6 << 1)
 161 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK    (7 << 1)
 162 #define ZYNQMP_DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE       BIT(3)
 163 #define ZYNQMP_DP_MAIN_STREAM_MISC0_YCBCR_COLR          BIT(4)
 164 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6               (0 << 5)
 165 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8               (1 << 5)
 166 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10              (2 << 5)
 167 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12              (3 << 5)
 168 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16              (4 << 5)
 169 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK            (7 << 5)
 170 #define ZYNQMP_DP_MAIN_STREAM_MISC1                     0x1a8
 171 #define ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN           BIT(7)
 172 #define ZYNQMP_DP_MAIN_STREAM_M_VID                     0x1ac
 173 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE                0x1b0
 174 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF    64
 175 #define ZYNQMP_DP_MAIN_STREAM_N_VID                     0x1b4
 176 #define ZYNQMP_DP_USER_PIX_WIDTH                        0x1b8
 177 #define ZYNQMP_DP_USER_DATA_COUNT_PER_LANE              0x1bc
 178 #define ZYNQMP_DP_MIN_BYTES_PER_TU                      0x1c4
 179 #define ZYNQMP_DP_FRAC_BYTES_PER_TU                     0x1c8
 180 #define ZYNQMP_DP_INIT_WAIT                             0x1cc
 181
 182 /* PHY configuration and status registers */
 183 #define ZYNQMP_DP_PHY_RESET                             0x200
 184 #define ZYNQMP_DP_PHY_RESET_PHY_RESET                   BIT(0)
 185 #define ZYNQMP_DP_PHY_RESET_GTTX_RESET                  BIT(1)
 186 #define ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET               BIT(8)
 187 #define ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET               BIT(9)
 188 #define ZYNQMP_DP_PHY_RESET_ALL_RESET                   (ZYNQMP_DP_PHY_RESET_PHY_RESET | \
 189                                                          ZYNQMP_DP_PHY_RESET_GTTX_RESET | \
 190                                                          ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET | \
 191                                                          ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET)
 192 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_0                0x210
 193 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_1                0x214
 194 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_2                0x218
 195 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_3                0x21c
 196 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_0               0x220
 197 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_1               0x224
 198 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_2               0x228
 199 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_3               0x22c
 200 #define ZYNQMP_DP_PHY_CLOCK_SELECT                      0x234
 201 #define ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G                0x1
 202 #define ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G                0x3
 203 #define ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G                0x5
 204 #define ZYNQMP_DP_TX_PHY_POWER_DOWN                     0x238
 205 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_0              BIT(0)
 206 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_1              BIT(1)
 207 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_2              BIT(2)
 208 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_3              BIT(3)
 209 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL                 0xf
 210 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_0                  0x23c
 211 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_1                  0x240
 212 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_2                  0x244
 213 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_3                  0x248
 214 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_0                 0x24c
 215 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_1                 0x250
 216 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_2                 0x254
 217 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_3                 0x258
 218 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0           0x24c
 219 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_1           0x250
 220 #define ZYNQMP_DP_PHY_STATUS                            0x280
 221 #define ZYNQMP_DP_PHY_STATUS_PLL_LOCKED_SHIFT           4
 222 #define ZYNQMP_DP_PHY_STATUS_FPGA_PLL_LOCKED            BIT(6)
 223
 224 /* Audio registers */
 225 #define ZYNQMP_DP_TX_AUDIO_CONTROL                      0x300
 226 #define ZYNQMP_DP_TX_AUDIO_CHANNELS                     0x304
 227 #define ZYNQMP_DP_TX_AUDIO_INFO_DATA                    0x308
 228 #define ZYNQMP_DP_TX_M_AUD                              0x328
 229 #define ZYNQMP_DP_TX_N_AUD                              0x32c
 230 #define ZYNQMP_DP_TX_AUDIO_EXT_DATA                     0x330
 231
 232 #define ZYNQMP_DP_MAX_LANES                             2
 233 #define ZYNQMP_MAX_FREQ                                 3000000
 234
 235 #define DP_REDUCED_BIT_RATE                             162000
 236 #define DP_HIGH_BIT_RATE                                270000
 237 #define DP_HIGH_BIT_RATE2                               540000
 238 #define DP_MAX_TRAINING_TRIES                           5
 239 #define DP_V1_2                                         0x12
 240
 241 /**
 242  * struct zynqmp_dp_link_config - Common link config between source and sink
 243  * @max_rate: maximum link rate
 244  * @max_lanes: maximum number of lanes
 245  */
 246 struct zynqmp_dp_link_config {
 247         int max_rate;
 248         u8 max_lanes;
 249 };
 250
 251 /**
 252  * struct zynqmp_dp_mode - Configured mode of DisplayPort
 253  * @bw_code: code for bandwidth(link rate)
 254  * @lane_cnt: number of lanes
 255  * @pclock: pixel clock frequency of current mode
 256  * @fmt: format identifier string
 257  */
 258 struct zynqmp_dp_mode {
 259         u8 bw_code;
 260         u8 lane_cnt;
 261         int pclock;
 262         const char *fmt;
 263 };
 264
 265 /**
 266  * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
 267  * @misc0: misc0 configuration (per DP v1.2 spec)
 268  * @misc1: misc1 configuration (per DP v1.2 spec)
 269  * @bpp: bits per pixel
 270  */
 271 struct zynqmp_dp_config {
 272         u8 misc0;
 273         u8 misc1;
 274         u8 bpp;
 275 };
 276
 277 /**
 278  * struct zynqmp_dp - Xilinx DisplayPort core
 279  * @encoder: the drm encoder structure
 280  * @connector: the drm connector structure
 281  * @dev: device structure
 282  * @dpsub: Display subsystem
 283  * @drm: DRM core
 284  * @iomem: device I/O memory for register access
 285  * @reset: reset controller
 286  * @irq: irq
 287  * @config: IP core configuration from DTS
 288  * @aux: aux channel
 289  * @phy: PHY handles for DP lanes
 290  * @num_lanes: number of enabled phy lanes
 291  * @hpd_work: hot plug detection worker
 292  * @status: connection status
 293  * @enabled: flag to indicate if the device is enabled
 294  * @dpcd: DP configuration data from currently connected sink device
 295  * @link_config: common link configuration between IP core and sink device
 296  * @mode: current mode between IP core and sink device
 297  * @train_set: set of training data
 298  */
 299 struct zynqmp_dp {
 300         struct drm_encoder encoder;
 301         struct drm_connector connector;
 302         struct device *dev;
 303         struct zynqmp_dpsub *dpsub;
 304         struct drm_device *drm;
 305         void __iomem *iomem;
 306         struct reset_control *reset;
 307         int irq;
 308
 309         struct zynqmp_dp_config config;
 310         struct drm_dp_aux aux;
 311         struct phy *phy[ZYNQMP_DP_MAX_LANES];
 312         u8 num_lanes;
 313         struct delayed_work hpd_work;
 314         enum drm_connector_status status;
 315         bool enabled;
 316
 317         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 318         struct zynqmp_dp_link_config link_config;
 319         struct zynqmp_dp_mode mode;
 320         u8 train_set[ZYNQMP_DP_MAX_LANES];
 321 };
 322
 323 static inline struct zynqmp_dp *encoder_to_dp(struct drm_encoder *encoder)
 324 {
 325         return container_of(encoder, struct zynqmp_dp, encoder);
 326 }
 327
 328 static inline struct zynqmp_dp *connector_to_dp(struct drm_connector *connector)
 329 {
 330         return container_of(connector, struct zynqmp_dp, connector);
 331 }
 332
 333 static void zynqmp_dp_write(struct zynqmp_dp *dp, int offset, u32 val)
 334 {
 335         writel(val, dp->iomem + offset);
 336 }
 337
 338 static u32 zynqmp_dp_read(struct zynqmp_dp *dp, int offset)
 339 {
 340         return readl(dp->iomem + offset);
 341 }
 342
 343 static void zynqmp_dp_clr(struct zynqmp_dp *dp, int offset, u32 clr)
 344 {
 345         zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) & ~clr);
 346 }
 347
 348 static void zynqmp_dp_set(struct zynqmp_dp *dp, int offset, u32 set)
 349 {
 350         zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) | set);
 351 }
 352
 353 /* -----------------------------------------------------------------------------
 354  * PHY Handling
 355  */
 356
 357 #define RST_TIMEOUT_MS                  1000
 358
 359 static int zynqmp_dp_reset(struct zynqmp_dp *dp, bool assert)
 360 {
 361         unsigned long timeout;
 362
 363         if (assert)
 364                 reset_control_assert(dp->reset);
 365         else
 366                 reset_control_deassert(dp->reset);
 367
 368         /* Wait for the (de)assert to complete. */
 369         timeout = jiffies + msecs_to_jiffies(RST_TIMEOUT_MS);
 370         while (!time_after_eq(jiffies, timeout)) {
 371                 bool status = !!reset_control_status(dp->reset);
 372
 373                 if (assert == status)
 374                         return 0;
 375
 376                 cpu_relax();
 377         }
 378
 379         dev_err(dp->dev, "reset %s timeout\n", assert ? "assert" : "deassert");
 380         return -ETIMEDOUT;
 381 }
 382
 383 /**
 384  * zynqmp_dp_phy_init - Initialize the phy
 385  * @dp: DisplayPort IP core structure
 386  *
 387  * Initialize the phy.
 388  *
 389  * Return: 0 if the phy instances are initialized correctly, or the error code
 390  * returned from the callee functions.
 391  */
 392 static int zynqmp_dp_phy_init(struct zynqmp_dp *dp)
 393 {
 394         int ret;
 395         int i;
 396
 397         for (i = 0; i < dp->num_lanes; i++) {
 398                 ret = phy_init(dp->phy[i]);
 399                 if (ret) {
 400                         dev_err(dp->dev, "failed to init phy lane %d\n", i);
 401                         return ret;
 402                 }
 403         }
 404
 405         ret = zynqmp_dp_reset(dp, false);
 406         if (ret < 0)
 407                 return ret;
 408
 409         zynqmp_dp_clr(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET);
 410
 411         /*
 412          * Power on lanes in reverse order as only lane 0 waits for the PLL to
 413          * lock.
 414          */
 415         for (i = dp->num_lanes - 1; i >= 0; i--) {
 416                 ret = phy_power_on(dp->phy[i]);
 417                 if (ret) {
 418                         dev_err(dp->dev, "failed to power on phy lane %d\n", i);
 419                         return ret;
 420                 }
 421         }
 422
 423         return 0;
 424 }
 425
 426 /**
 427  * zynqmp_dp_phy_exit - Exit the phy
 428  * @dp: DisplayPort IP core structure
 429  *
 430  * Exit the phy.
 431  */
 432 static void zynqmp_dp_phy_exit(struct zynqmp_dp *dp)
 433 {
 434         unsigned int i;
 435         int ret;
 436
 437         for (i = 0; i < dp->num_lanes; i++) {
 438                 ret = phy_power_off(dp->phy[i]);
 439                 if (ret)
 440                         dev_err(dp->dev, "failed to power off phy(%d) %d\n", i,
 441                                 ret);
 442         }
 443
 444         zynqmp_dp_reset(dp, true);
 445
 446         for (i = 0; i < dp->num_lanes; i++) {
 447                 ret = phy_exit(dp->phy[i]);
 448                 if (ret)
 449                         dev_err(dp->dev, "failed to exit phy(%d) %d\n", i, ret);
 450         }
 451 }
 452
 453 /**
 454  * zynqmp_dp_phy_probe - Probe the PHYs
 455  * @dp: DisplayPort IP core structure
 456  *
 457  * Probe PHYs for all lanes. Less PHYs may be available than the number of
 458  * lanes, which is not considered an error as long as at least one PHY is
 459  * found. The caller can check dp->num_lanes to check how many PHYs were found.
 460  *
 461  * Return:
 462  * * 0                          - Success
 463  * * -ENXIO                     - No PHY found
 464  * * -EPROBE_DEFER              - Probe deferral requested
 465  * * Other negative value       - PHY retrieval failure
 466  */
 467 static int zynqmp_dp_phy_probe(struct zynqmp_dp *dp)
 468 {
 469         unsigned int i;
 470
 471         for (i = 0; i < ZYNQMP_DP_MAX_LANES; i++) {
 472                 char phy_name[16];
 473                 struct phy *phy;
 474
 475                 snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i);
 476                 phy = devm_phy_get(dp->dev, phy_name);
 477
 478                 if (IS_ERR(phy)) {
 479                         switch (PTR_ERR(phy)) {
 480                         case -ENODEV:
 481                                 if (dp->num_lanes)
 482                                         return 0;
 483
 484                                 dev_err(dp->dev, "no PHY found\n");
 485                                 return -ENXIO;
 486
 487                         case -EPROBE_DEFER:
 488                                 return -EPROBE_DEFER;
 489
 490                         default:
 491                                 dev_err(dp->dev, "failed to get PHY lane %u\n",
 492                                         i);
 493                                 return PTR_ERR(phy);
 494                         }
 495                 }
 496
 497                 dp->phy[i] = phy;
 498                 dp->num_lanes++;
 499         }
 500
 501         return 0;
 502 }
 503
 504 /**
 505  * zynqmp_dp_phy_ready - Check if PHY is ready
 506  * @dp: DisplayPort IP core structure
 507  *
 508  * Check if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times.
 509  * This amount of delay was suggested by IP designer.
 510  *
 511  * Return: 0 if PHY is ready, or -ENODEV if PHY is not ready.
 512  */
 513 static int zynqmp_dp_phy_ready(struct zynqmp_dp *dp)
 514 {
 515         u32 i, reg, ready;
 516
 517         ready = (1 << dp->num_lanes) - 1;
 518
 519         /* Wait for 100 * 1ms. This should be enough time for PHY to be ready */
 520         for (i = 0; ; i++) {
 521                 reg = zynqmp_dp_read(dp, ZYNQMP_DP_PHY_STATUS);
 522                 if ((reg & ready) == ready)
 523                         return 0;
 524
 525                 if (i == 100) {
 526                         dev_err(dp->dev, "PHY isn't ready\n");
 527                         return -ENODEV;
 528                 }
 529
 530                 usleep_range(1000, 1100);
 531         }
 532
 533         return 0;
 534 }
 535
 536 /* -----------------------------------------------------------------------------
 537  * DisplayPort Link Training
 538  */
 539
 540 /**
 541  * zynqmp_dp_max_rate - Calculate and return available max pixel clock
 542  * @link_rate: link rate (Kilo-bytes / sec)
 543  * @lane_num: number of lanes
 544  * @bpp: bits per pixel
 545  *
 546  * Return: max pixel clock (KHz) supported by current link config.
 547  */
 548 static inline int zynqmp_dp_max_rate(int link_rate, u8 lane_num, u8 bpp)
 549 {
 550         return link_rate * lane_num * 8 / bpp;
 551 }
 552
 553 /**
 554  * zynqmp_dp_mode_configure - Configure the link values
 555  * @dp: DisplayPort IP core structure
 556  * @pclock: pixel clock for requested display mode
 557  * @current_bw: current link rate
 558  *
 559  * Find the link configuration values, rate and lane count for requested pixel
 560  * clock @pclock. The @pclock is stored in the mode to be used in other
 561  * functions later. The returned rate is downshifted from the current rate
 562  * @current_bw.
 563  *
 564  * Return: Current link rate code, or -EINVAL.
 565  */
 566 static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock,
 567                                     u8 current_bw)
 568 {
 569         int max_rate = dp->link_config.max_rate;
 570         u8 bw_code;
 571         u8 max_lanes = dp->link_config.max_lanes;
 572         u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
 573         u8 bpp = dp->config.bpp;
 574         u8 lane_cnt;
 575
 576         /* Downshift from current bandwidth */
 577         switch (current_bw) {
 578         case DP_LINK_BW_5_4:
 579                 bw_code = DP_LINK_BW_2_7;
 580                 break;
 581         case DP_LINK_BW_2_7:
 582                 bw_code = DP_LINK_BW_1_62;
 583                 break;
 584         case DP_LINK_BW_1_62:
 585                 dev_err(dp->dev, "can't downshift. already lowest link rate\n");
 586                 return -EINVAL;
 587         default:
 588                 /* If not given, start with max supported */
 589                 bw_code = max_link_rate_code;
 590                 break;
 591         }
 592
 593         for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
 594                 int bw;
 595                 u32 rate;
 596
 597                 bw = drm_dp_bw_code_to_link_rate(bw_code);
 598                 rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp);
 599                 if (pclock <= rate) {
 600                         dp->mode.bw_code = bw_code;
 601                         dp->mode.lane_cnt = lane_cnt;
 602                         dp->mode.pclock = pclock;
 603                         return dp->mode.bw_code;
 604                 }
 605         }
 606
 607         dev_err(dp->dev, "failed to configure link values\n");
 608
 609         return -EINVAL;
 610 }
 611
 612 /**
 613  * zynqmp_dp_adjust_train - Adjust train values
 614  * @dp: DisplayPort IP core structure
 615  * @link_status: link status from sink which contains requested training values
 616  */
 617 static void zynqmp_dp_adjust_train(struct zynqmp_dp *dp,
 618                                    u8 link_status[DP_LINK_STATUS_SIZE])
 619 {
 620         u8 *train_set = dp->train_set;
 621         u8 voltage = 0, preemphasis = 0;
 622         u8 i;
 623
 624         for (i = 0; i < dp->mode.lane_cnt; i++) {
 625                 u8 v = drm_dp_get_adjust_request_voltage(link_status, i);
 626                 u8 p = drm_dp_get_adjust_request_pre_emphasis(link_status, i);
 627
 628                 if (v > voltage)
 629                         voltage = v;
 630
 631                 if (p > preemphasis)
 632                         preemphasis = p;
 633         }
 634
 635         if (voltage >= DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
 636                 voltage |= DP_TRAIN_MAX_SWING_REACHED;
 637
 638         if (preemphasis >= DP_TRAIN_PRE_EMPH_LEVEL_2)
 639                 preemphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 640
 641         for (i = 0; i < dp->mode.lane_cnt; i++)
 642                 train_set[i] = voltage | preemphasis;
 643 }
 644
 645 /**
 646  * zynqmp_dp_update_vs_emph - Update the training values
 647  * @dp: DisplayPort IP core structure
 648  *
 649  * Update the training values based on the request from sink. The mapped values
 650  * are predefined, and values(vs, pe, pc) are from the device manual.
 651  *
 652  * Return: 0 if vs and emph are updated successfully, or the error code returned
 653  * by drm_dp_dpcd_write().
 654  */
 655 static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp)
 656 {
 657         unsigned int i;
 658         int ret;
 659
 660         ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set,
 661                                 dp->mode.lane_cnt);
 662         if (ret < 0)
 663                 return ret;
 664
 665         for (i = 0; i < dp->mode.lane_cnt; i++) {
 666                 u32 reg = ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 + i * 4;
 667                 union phy_configure_opts opts = { 0 };
 668                 u8 train = dp->train_set[i];
 669
 670                 opts.dp.voltage[0] = (train & DP_TRAIN_VOLTAGE_SWING_MASK)
 671                                    >> DP_TRAIN_VOLTAGE_SWING_SHIFT;
 672                 opts.dp.pre[0] = (train & DP_TRAIN_PRE_EMPHASIS_MASK)
 673                                >> DP_TRAIN_PRE_EMPHASIS_SHIFT;
 674
 675                 phy_configure(dp->phy[i], &opts);
 676
 677                 zynqmp_dp_write(dp, reg, 0x2);
 678         }
 679
 680         return 0;
 681 }
 682
 683 /**
 684  * zynqmp_dp_link_train_cr - Train clock recovery
 685  * @dp: DisplayPort IP core structure
 686  *
 687  * Return: 0 if clock recovery train is done successfully, or corresponding
 688  * error code.
 689  */
 690 static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp)
 691 {
 692         u8 link_status[DP_LINK_STATUS_SIZE];
 693         u8 lane_cnt = dp->mode.lane_cnt;
 694         u8 vs = 0, tries = 0;
 695         u16 max_tries, i;
 696         bool cr_done;
 697         int ret;
 698
 699         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET,
 700                         DP_TRAINING_PATTERN_1);
 701         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 702                                  DP_TRAINING_PATTERN_1 |
 703                                  DP_LINK_SCRAMBLING_DISABLE);
 704         if (ret < 0)
 705                 return ret;
 706
 707         /*
 708          * 256 loops should be maximum iterations for 4 lanes and 4 values.
 709          * So, This loop should exit before 512 iterations
 710          */
 711         for (max_tries = 0; max_tries < 512; max_tries++) {
 712                 ret = zynqmp_dp_update_vs_emph(dp);
 713                 if (ret)
 714                         return ret;
 715
 716                 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd);
 717                 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
 718                 if (ret < 0)
 719                         return ret;
 720
 721                 cr_done = drm_dp_clock_recovery_ok(link_status, lane_cnt);
 722                 if (cr_done)
 723                         break;
 724
 725                 for (i = 0; i < lane_cnt; i++)
 726                         if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED))
 727                                 break;
 728                 if (i == lane_cnt)
 729                         break;
 730
 731                 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs)
 732                         tries++;
 733                 else
 734                         tries = 0;
 735
 736                 if (tries == DP_MAX_TRAINING_TRIES)
 737                         break;
 738
 739                 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 740                 zynqmp_dp_adjust_train(dp, link_status);
 741         }
 742
 743         if (!cr_done)
 744                 return -EIO;
 745
 746         return 0;
 747 }
 748
 749 /**
 750  * zynqmp_dp_link_train_ce - Train channel equalization
 751  * @dp: DisplayPort IP core structure
 752  *
 753  * Return: 0 if channel equalization train is done successfully, or
 754  * corresponding error code.
 755  */
 756 static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp)
 757 {
 758         u8 link_status[DP_LINK_STATUS_SIZE];
 759         u8 lane_cnt = dp->mode.lane_cnt;
 760         u32 pat, tries;
 761         int ret;
 762         bool ce_done;
 763
 764         if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 &&
 765             dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED)
 766                 pat = DP_TRAINING_PATTERN_3;
 767         else
 768                 pat = DP_TRAINING_PATTERN_2;
 769
 770         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, pat);
 771         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 772                                  pat | DP_LINK_SCRAMBLING_DISABLE);
 773         if (ret < 0)
 774                 return ret;
 775
 776         for (tries = 0; tries < DP_MAX_TRAINING_TRIES; tries++) {
 777                 ret = zynqmp_dp_update_vs_emph(dp);
 778                 if (ret)
 779                         return ret;
 780
 781                 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd);
 782                 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
 783                 if (ret < 0)
 784                         return ret;
 785
 786                 ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt);
 787                 if (ce_done)
 788                         break;
 789
 790                 zynqmp_dp_adjust_train(dp, link_status);
 791         }
 792
 793         if (!ce_done)
 794                 return -EIO;
 795
 796         return 0;
 797 }
 798
 799 /**
 800  * zynqmp_dp_link_train - Train the link
 801  * @dp: DisplayPort IP core structure
 802  *
 803  * Return: 0 if all trains are done successfully, or corresponding error code.
 804  */
 805 static int zynqmp_dp_train(struct zynqmp_dp *dp)
 806 {
 807         u32 reg;
 808         u8 bw_code = dp->mode.bw_code;
 809         u8 lane_cnt = dp->mode.lane_cnt;
 810         u8 aux_lane_cnt = lane_cnt;
 811         bool enhanced;
 812         int ret;
 813
 814         zynqmp_dp_write(dp, ZYNQMP_DP_LANE_COUNT_SET, lane_cnt);
 815         enhanced = drm_dp_enhanced_frame_cap(dp->dpcd);
 816         if (enhanced) {
 817                 zynqmp_dp_write(dp, ZYNQMP_DP_ENHANCED_FRAME_EN, 1);
 818                 aux_lane_cnt |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 819         }
 820
 821         if (dp->dpcd[3] & 0x1) {
 822                 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 1);
 823                 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL,
 824                                    DP_SPREAD_AMP_0_5);
 825         } else {
 826                 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 0);
 827                 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0);
 828         }
 829
 830         ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt);
 831         if (ret < 0) {
 832                 dev_err(dp->dev, "failed to set lane count\n");
 833                 return ret;
 834         }
 835
 836         ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
 837                                  DP_SET_ANSI_8B10B);
 838         if (ret < 0) {
 839                 dev_err(dp->dev, "failed to set ANSI 8B/10B encoding\n");
 840                 return ret;
 841         }
 842
 843         ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code);
 844         if (ret < 0) {
 845                 dev_err(dp->dev, "failed to set DP bandwidth\n");
 846                 return ret;
 847         }
 848
 849         zynqmp_dp_write(dp, ZYNQMP_DP_LINK_BW_SET, bw_code);
 850         switch (bw_code) {
 851         case DP_LINK_BW_1_62:
 852                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G;
 853                 break;
 854         case DP_LINK_BW_2_7:
 855                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G;
 856                 break;
 857         case DP_LINK_BW_5_4:
 858         default:
 859                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G;
 860                 break;
 861         }
 862
 863         zynqmp_dp_write(dp, ZYNQMP_DP_PHY_CLOCK_SELECT, reg);
 864         ret = zynqmp_dp_phy_ready(dp);
 865         if (ret < 0)
 866                 return ret;
 867
 868         zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 1);
 869         memset(dp->train_set, 0, sizeof(dp->train_set));
 870         ret = zynqmp_dp_link_train_cr(dp);
 871         if (ret)
 872                 return ret;
 873
 874         ret = zynqmp_dp_link_train_ce(dp);
 875         if (ret)
 876                 return ret;
 877
 878         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 879                                  DP_TRAINING_PATTERN_DISABLE);
 880         if (ret < 0) {
 881                 dev_err(dp->dev, "failed to disable training pattern\n");
 882                 return ret;
 883         }
 884         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET,
 885                         DP_TRAINING_PATTERN_DISABLE);
 886
 887         zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 0);
 888
 889         return 0;
 890 }
 891
 892 /**
 893  * zynqmp_dp_train_loop - Downshift the link rate during training
 894  * @dp: DisplayPort IP core structure
 895  *
 896  * Train the link by downshifting the link rate if training is not successful.
 897  */
 898 static void zynqmp_dp_train_loop(struct zynqmp_dp *dp)
 899 {
 900         struct zynqmp_dp_mode *mode = &dp->mode;
 901         u8 bw = mode->bw_code;
 902         int ret;
 903
 904         do {
 905                 if (dp->status == connector_status_disconnected ||
 906                     !dp->enabled)
 907                         return;
 908
 909                 ret = zynqmp_dp_train(dp);
 910                 if (!ret)
 911                         return;
 912
 913                 ret = zynqmp_dp_mode_configure(dp, mode->pclock, bw);
 914                 if (ret < 0)
 915                         goto err_out;
 916
 917                 bw = ret;
 918         } while (bw >= DP_LINK_BW_1_62);
 919
 920 err_out:
 921         dev_err(dp->dev, "failed to train the DP link\n");
 922 }
 923
 924 /* -----------------------------------------------------------------------------
 925  * DisplayPort AUX
 926  */
 927
 928 #define AUX_READ_BIT    0x1
 929
 930 /**
 931  * zynqmp_dp_aux_cmd_submit - Submit aux command
 932  * @dp: DisplayPort IP core structure
 933  * @cmd: aux command
 934  * @addr: aux address
 935  * @buf: buffer for command data
 936  * @bytes: number of bytes for @buf
 937  * @reply: reply code to be returned
 938  *
 939  * Submit an aux command. All aux related commands, native or i2c aux
 940  * read/write, are submitted through this function. The function is mapped to
 941  * the transfer function of struct drm_dp_aux. This function involves in
 942  * multiple register reads/writes, thus synchronization is needed, and it is
 943  * done by drm_dp_helper using @hw_mutex. The calling thread goes into sleep
 944  * if there's no immediate reply to the command submission. The reply code is
 945  * returned at @reply if @reply != NULL.
 946  *
 947  * Return: 0 if the command is submitted properly, or corresponding error code:
 948  * -EBUSY when there is any request already being processed
 949  * -ETIMEDOUT when receiving reply is timed out
 950  * -EIO when received bytes are less than requested
 951  */
 952 static int zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr,
 953                                     u8 *buf, u8 bytes, u8 *reply)
 954 {
 955         bool is_read = (cmd & AUX_READ_BIT) ? true : false;
 956         u32 reg, i;
 957
 958         reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
 959         if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST)
 960                 return -EBUSY;
 961
 962         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_ADDRESS, addr);
 963         if (!is_read)
 964                 for (i = 0; i < bytes; i++)
 965                         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_WRITE_FIFO,
 966                                         buf[i]);
 967
 968         reg = cmd << ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT;
 969         if (!buf || !bytes)
 970                 reg |= ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY;
 971         else
 972                 reg |= (bytes - 1) << ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT;
 973         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_COMMAND, reg);
 974
 975         /* Wait for reply to be delivered upto 2ms */
 976         for (i = 0; ; i++) {
 977                 reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
 978                 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY)
 979                         break;
 980
 981                 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT ||
 982                     i == 2)
 983                         return -ETIMEDOUT;
 984
 985                 usleep_range(1000, 1100);
 986         }
 987
 988         reg = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_CODE);
 989         if (reply)
 990                 *reply = reg;
 991
 992         if (is_read &&
 993             (reg == ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK ||
 994              reg == ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK)) {
 995                 reg = zynqmp_dp_read(dp, ZYNQMP_DP_REPLY_DATA_COUNT);
 996                 if ((reg & ZYNQMP_DP_REPLY_DATA_COUNT_MASK) != bytes)
 997                         return -EIO;
 998
 999                 for (i = 0; i < bytes; i++)
1000                         buf[i] = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_DATA);
1001         }
1002
1003         return 0;
1004 }
1005
1006 static ssize_t
1007 zynqmp_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1008 {
1009         struct zynqmp_dp *dp = container_of(aux, struct zynqmp_dp, aux);
1010         int ret;
1011         unsigned int i, iter;
1012
1013         /* Number of loops = timeout in msec / aux delay (400 usec) */
1014         iter = zynqmp_dp_aux_timeout_ms * 1000 / 400;
1015         iter = iter ? iter : 1;
1016
1017         for (i = 0; i < iter; i++) {
1018                 ret = zynqmp_dp_aux_cmd_submit(dp, msg->request, msg->address,
1019                                                msg->buffer, msg->size,
1020                                                &msg->reply);
1021                 if (!ret) {
1022                         dev_dbg(dp->dev, "aux %d retries\n", i);
1023                         return msg->size;
1024                 }
1025
1026                 if (dp->status == connector_status_disconnected) {
1027                         dev_dbg(dp->dev, "no connected aux device\n");
1028                         return -ENODEV;
1029                 }
1030
1031                 usleep_range(400, 500);
1032         }
1033
1034         dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret);
1035
1036         return ret;
1037 }
1038
1039 /**
1040  * zynqmp_dp_aux_init - Initialize and register the DP AUX
1041  * @dp: DisplayPort IP core structure
1042  *
1043  * Program the AUX clock divider and filter and register the DP AUX adapter.
1044  *
1045  * Return: 0 on success, error value otherwise
1046  */
1047 static int zynqmp_dp_aux_init(struct zynqmp_dp *dp)
1048 {
1049         unsigned long rate;
1050         unsigned int w;
1051
1052         /*
1053          * The AUX_SIGNAL_WIDTH_FILTER is the number of APB clock cycles
1054          * corresponding to the AUX pulse. Allowable values are 8, 16, 24, 32,
1055          * 40 and 48. The AUX pulse width must be between 0.4µs and 0.6µs,
1056          * compute the w / 8 value corresponding to 0.4µs rounded up, and make
1057          * sure it stays below 0.6µs and within the allowable values.
1058          */
1059         rate = clk_get_rate(dp->dpsub->apb_clk);
1060         w = DIV_ROUND_UP(4 * rate, 1000 * 1000 * 10 * 8) * 8;
1061         if (w > 6 * rate / (1000 * 1000 * 10) || w > 48) {
1062                 dev_err(dp->dev, "aclk frequency too high\n");
1063                 return -EINVAL;
1064         }
1065
1066         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_CLK_DIVIDER,
1067                         (w << ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT) |
1068                         (rate / (1000 * 1000)));
1069
1070         dp->aux.name = "ZynqMP DP AUX";
1071         dp->aux.dev = dp->dev;
1072         dp->aux.drm_dev = dp->drm;
1073         dp->aux.transfer = zynqmp_dp_aux_transfer;
1074
1075         return drm_dp_aux_register(&dp->aux);
1076 }
1077
1078 /**
1079  * zynqmp_dp_aux_cleanup - Cleanup the DP AUX
1080  * @dp: DisplayPort IP core structure
1081  *
1082  * Unregister the DP AUX adapter.
1083  */
1084 static void zynqmp_dp_aux_cleanup(struct zynqmp_dp *dp)
1085 {
1086         drm_dp_aux_unregister(&dp->aux);
1087 }
1088
1089 /* -----------------------------------------------------------------------------
1090  * DisplayPort Generic Support
1091  */
1092
1093 /**
1094  * zynqmp_dp_update_misc - Write the misc registers
1095  * @dp: DisplayPort IP core structure
1096  *
1097  * The misc register values are stored in the structure, and this
1098  * function applies the values into the registers.
1099  */
1100 static void zynqmp_dp_update_misc(struct zynqmp_dp *dp)
1101 {
1102         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC0, dp->config.misc0);
1103         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC1, dp->config.misc1);
1104 }
1105
1106 /**
1107  * zynqmp_dp_set_format - Set the input format
1108  * @dp: DisplayPort IP core structure
1109  * @format: input format
1110  * @bpc: bits per component
1111  *
1112  * Update misc register values based on input @format and @bpc.
1113  *
1114  * Return: 0 on success, or -EINVAL.
1115  */
1116 static int zynqmp_dp_set_format(struct zynqmp_dp *dp,
1117                                 enum zynqmp_dpsub_format format,
1118                                 unsigned int bpc)
1119 {
1120         static const struct drm_display_info *display;
1121         struct zynqmp_dp_config *config = &dp->config;
1122         unsigned int num_colors;
1123
1124         config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK;
1125         config->misc1 &= ~ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1126
1127         switch (format) {
1128         case ZYNQMP_DPSUB_FORMAT_RGB:
1129                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB;
1130                 num_colors = 3;
1131                 break;
1132
1133         case ZYNQMP_DPSUB_FORMAT_YCRCB444:
1134                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444;
1135                 num_colors = 3;
1136                 break;
1137
1138         case ZYNQMP_DPSUB_FORMAT_YCRCB422:
1139                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422;
1140                 num_colors = 2;
1141                 break;
1142
1143         case ZYNQMP_DPSUB_FORMAT_YONLY:
1144                 config->misc1 |= ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1145                 num_colors = 1;
1146                 break;
1147
1148         default:
1149                 dev_err(dp->dev, "Invalid colormetry in DT\n");
1150                 return -EINVAL;
1151         }
1152
1153         display = &dp->connector.display_info;
1154         if (display->bpc && bpc > display->bpc) {
1155                 dev_warn(dp->dev,
1156                          "downgrading requested %ubpc to display limit %ubpc\n",
1157                          bpc, display->bpc);
1158                 bpc = display->bpc;
1159         }
1160
1161         config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK;
1162
1163         switch (bpc) {
1164         case 6:
1165                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6;
1166                 break;
1167         case 8:
1168                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1169                 break;
1170         case 10:
1171                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10;
1172                 break;
1173         case 12:
1174                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12;
1175                 break;
1176         case 16:
1177                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16;
1178                 break;
1179         default:
1180                 dev_warn(dp->dev, "Not supported bpc (%u). fall back to 8bpc\n",
1181                          bpc);
1182                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1183                 bpc = 8;
1184                 break;
1185         }
1186
1187         /* Update the current bpp based on the format. */
1188         config->bpp = bpc * num_colors;
1189
1190         return 0;
1191 }
1192
1193 /**
1194  * zynqmp_dp_encoder_mode_set_transfer_unit - Set the transfer unit values
1195  * @dp: DisplayPort IP core structure
1196  * @mode: requested display mode
1197  *
1198  * Set the transfer unit, and calculate all transfer unit size related values.
1199  * Calculation is based on DP and IP core specification.
1200  */
1201 static void
1202 zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp,
1203                                          struct drm_display_mode *mode)
1204 {
1205         u32 tu = ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF;
1206         u32 bw, vid_kbytes, avg_bytes_per_tu, init_wait;
1207
1208         /* Use the max transfer unit size (default) */
1209         zynqmp_dp_write(dp, ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE, tu);
1210
1211         vid_kbytes = mode->clock * (dp->config.bpp / 8);
1212         bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1213         avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000);
1214         zynqmp_dp_write(dp, ZYNQMP_DP_MIN_BYTES_PER_TU,
1215                         avg_bytes_per_tu / 1000);
1216         zynqmp_dp_write(dp, ZYNQMP_DP_FRAC_BYTES_PER_TU,
1217                         avg_bytes_per_tu % 1000);
1218
1219         /* Configure the initial wait cycle based on transfer unit size */
1220         if (tu < (avg_bytes_per_tu / 1000))
1221                 init_wait = 0;
1222         else if ((avg_bytes_per_tu / 1000) <= 4)
1223                 init_wait = tu;
1224         else
1225                 init_wait = tu - avg_bytes_per_tu / 1000;
1226
1227         zynqmp_dp_write(dp, ZYNQMP_DP_INIT_WAIT, init_wait);
1228 }
1229
1230 /**
1231  * zynqmp_dp_encoder_mode_set_stream - Configure the main stream
1232  * @dp: DisplayPort IP core structure
1233  * @mode: requested display mode
1234  *
1235  * Configure the main stream based on the requested mode @mode. Calculation is
1236  * based on IP core specification.
1237  */
1238 static void zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp,
1239                                               const struct drm_display_mode *mode)
1240 {
1241         u8 lane_cnt = dp->mode.lane_cnt;
1242         u32 reg, wpl;
1243         unsigned int rate;
1244
1245         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HTOTAL, mode->htotal);
1246         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VTOTAL, mode->vtotal);
1247         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_POLARITY,
1248                         (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) <<
1249                          ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT) |
1250                         (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) <<
1251                          ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT));
1252         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSWIDTH,
1253                         mode->hsync_end - mode->hsync_start);
1254         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSWIDTH,
1255                         mode->vsync_end - mode->vsync_start);
1256         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HRES, mode->hdisplay);
1257         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VRES, mode->vdisplay);
1258         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSTART,
1259                         mode->htotal - mode->hsync_start);
1260         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSTART,
1261                         mode->vtotal - mode->vsync_start);
1262
1263         /* In synchronous mode, set the diviers */
1264         if (dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK) {
1265                 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1266                 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_N_VID, reg);
1267                 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_M_VID, mode->clock);
1268                 rate = zynqmp_disp_get_audio_clk_rate(dp->dpsub->disp);
1269                 if (rate) {
1270                         dev_dbg(dp->dev, "Audio rate: %d\n", rate / 512);
1271                         zynqmp_dp_write(dp, ZYNQMP_DP_TX_N_AUD, reg);
1272                         zynqmp_dp_write(dp, ZYNQMP_DP_TX_M_AUD, rate / 1000);
1273                 }
1274         }
1275
1276         /* Only 2 channel audio is supported now */
1277         if (zynqmp_disp_audio_enabled(dp->dpsub->disp))
1278                 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CHANNELS, 1);
1279
1280         zynqmp_dp_write(dp, ZYNQMP_DP_USER_PIX_WIDTH, 1);
1281
1282         /* Translate to the native 16 bit datapath based on IP core spec */
1283         wpl = (mode->hdisplay * dp->config.bpp + 15) / 16;
1284         reg = wpl + wpl % lane_cnt - lane_cnt;
1285         zynqmp_dp_write(dp, ZYNQMP_DP_USER_DATA_COUNT_PER_LANE, reg);
1286 }
1287
1288 /* -----------------------------------------------------------------------------
1289  * DRM Connector
1290  */
1291
1292 static enum drm_connector_status
1293 zynqmp_dp_connector_detect(struct drm_connector *connector, bool force)
1294 {
1295         struct zynqmp_dp *dp = connector_to_dp(connector);
1296         struct zynqmp_dp_link_config *link_config = &dp->link_config;
1297         u32 state, i;
1298         int ret;
1299
1300         /*
1301          * This is from heuristic. It takes some delay (ex, 100 ~ 500 msec) to
1302          * get the HPD signal with some monitors.
1303          */
1304         for (i = 0; i < 10; i++) {
1305                 state = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
1306                 if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD)
1307                         break;
1308                 msleep(100);
1309         }
1310
1311         if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD) {
1312                 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd,
1313                                        sizeof(dp->dpcd));
1314                 if (ret < 0) {
1315                         dev_dbg(dp->dev, "DPCD read failed");
1316                         goto disconnected;
1317                 }
1318
1319                 link_config->max_rate = min_t(int,
1320                                               drm_dp_max_link_rate(dp->dpcd),
1321                                               DP_HIGH_BIT_RATE2);
1322                 link_config->max_lanes = min_t(u8,
1323                                                drm_dp_max_lane_count(dp->dpcd),
1324                                                dp->num_lanes);
1325
1326                 dp->status = connector_status_connected;
1327                 return connector_status_connected;
1328         }
1329
1330 disconnected:
1331         dp->status = connector_status_disconnected;
1332         return connector_status_disconnected;
1333 }
1334
1335 static int zynqmp_dp_connector_get_modes(struct drm_connector *connector)
1336 {
1337         struct zynqmp_dp *dp = connector_to_dp(connector);
1338         struct edid *edid;
1339         int ret;
1340
1341         edid = drm_get_edid(connector, &dp->aux.ddc);
1342         if (!edid)
1343                 return 0;
1344
1345         drm_connector_update_edid_property(connector, edid);
1346         ret = drm_add_edid_modes(connector, edid);
1347         kfree(edid);
1348
1349         return ret;
1350 }
1351
1352 static struct drm_encoder *
1353 zynqmp_dp_connector_best_encoder(struct drm_connector *connector)
1354 {
1355         struct zynqmp_dp *dp = connector_to_dp(connector);
1356
1357         return &dp->encoder;
1358 }
1359
1360 static int zynqmp_dp_connector_mode_valid(struct drm_connector *connector,
1361                                           struct drm_display_mode *mode)
1362 {
1363         struct zynqmp_dp *dp = connector_to_dp(connector);
1364         u8 max_lanes = dp->link_config.max_lanes;
1365         u8 bpp = dp->config.bpp;
1366         int max_rate = dp->link_config.max_rate;
1367         int rate;
1368
1369         if (mode->clock > ZYNQMP_MAX_FREQ) {
1370                 dev_dbg(dp->dev, "filtered the mode, %s,for high pixel rate\n",
1371                         mode->name);
1372                 drm_mode_debug_printmodeline(mode);
1373                 return MODE_CLOCK_HIGH;
1374         }
1375
1376         /* Check with link rate and lane count */
1377         rate = zynqmp_dp_max_rate(max_rate, max_lanes, bpp);
1378         if (mode->clock > rate) {
1379                 dev_dbg(dp->dev, "filtered the mode, %s,for high pixel rate\n",
1380                         mode->name);
1381                 drm_mode_debug_printmodeline(mode);
1382                 return MODE_CLOCK_HIGH;
1383         }
1384
1385         return MODE_OK;
1386 }
1387
1388 static const struct drm_connector_funcs zynqmp_dp_connector_funcs = {
1389         .detect                 = zynqmp_dp_connector_detect,
1390         .fill_modes             = drm_helper_probe_single_connector_modes,
1391         .destroy                = drm_connector_cleanup,
1392         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1393         .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
1394         .reset                  = drm_atomic_helper_connector_reset,
1395 };
1396
1397 static const struct drm_connector_helper_funcs
1398 zynqmp_dp_connector_helper_funcs = {
1399         .get_modes      = zynqmp_dp_connector_get_modes,
1400         .best_encoder   = zynqmp_dp_connector_best_encoder,
1401         .mode_valid     = zynqmp_dp_connector_mode_valid,
1402 };
1403
1404 /* -----------------------------------------------------------------------------
1405  * DRM Encoder
1406  */
1407
1408 static void zynqmp_dp_encoder_enable(struct drm_encoder *encoder)
1409 {
1410         struct zynqmp_dp *dp = encoder_to_dp(encoder);
1411         unsigned int i;
1412         int ret = 0;
1413
1414         pm_runtime_get_sync(dp->dev);
1415         dp->enabled = true;
1416         zynqmp_dp_update_misc(dp);
1417         if (zynqmp_disp_audio_enabled(dp->dpsub->disp))
1418                 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 1);
1419         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 0);
1420         if (dp->status == connector_status_connected) {
1421                 for (i = 0; i < 3; i++) {
1422                         ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER,
1423                                                  DP_SET_POWER_D0);
1424                         if (ret == 1)
1425                                 break;
1426                         usleep_range(300, 500);
1427                 }
1428                 /* Some monitors take time to wake up properly */
1429                 msleep(zynqmp_dp_power_on_delay_ms);
1430         }
1431         if (ret != 1)
1432                 dev_dbg(dp->dev, "DP aux failed\n");
1433         else
1434                 zynqmp_dp_train_loop(dp);
1435         zynqmp_dp_write(dp, ZYNQMP_DP_SOFTWARE_RESET,
1436                         ZYNQMP_DP_SOFTWARE_RESET_ALL);
1437         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 1);
1438 }
1439
1440 static void zynqmp_dp_encoder_disable(struct drm_encoder *encoder)
1441 {
1442         struct zynqmp_dp *dp = encoder_to_dp(encoder);
1443
1444         dp->enabled = false;
1445         cancel_delayed_work(&dp->hpd_work);
1446         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 0);
1447         drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3);
1448         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN,
1449                         ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
1450         if (zynqmp_disp_audio_enabled(dp->dpsub->disp))
1451                 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 0);
1452         pm_runtime_put_sync(dp->dev);
1453 }
1454
1455 static void
1456 zynqmp_dp_encoder_atomic_mode_set(struct drm_encoder *encoder,
1457                                   struct drm_crtc_state *crtc_state,
1458                                   struct drm_connector_state *connector_state)
1459 {
1460         struct zynqmp_dp *dp = encoder_to_dp(encoder);
1461         struct drm_display_mode *mode = &crtc_state->mode;
1462         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1463         u8 max_lanes = dp->link_config.max_lanes;
1464         u8 bpp = dp->config.bpp;
1465         int rate, max_rate = dp->link_config.max_rate;
1466         int ret;
1467
1468         zynqmp_dp_set_format(dp, ZYNQMP_DPSUB_FORMAT_RGB, 8);
1469
1470         /* Check again as bpp or format might have been chagned */
1471         rate = zynqmp_dp_max_rate(max_rate, max_lanes, bpp);
1472         if (mode->clock > rate) {
1473                 dev_err(dp->dev, "the mode, %s,has too high pixel rate\n",
1474                         mode->name);
1475                 drm_mode_debug_printmodeline(mode);
1476         }
1477
1478         ret = zynqmp_dp_mode_configure(dp, adjusted_mode->clock, 0);
1479         if (ret < 0)
1480                 return;
1481
1482         zynqmp_dp_encoder_mode_set_transfer_unit(dp, adjusted_mode);
1483         zynqmp_dp_encoder_mode_set_stream(dp, adjusted_mode);
1484 }
1485
1486 #define ZYNQMP_DP_MIN_H_BACKPORCH       20
1487
1488 static int
1489 zynqmp_dp_encoder_atomic_check(struct drm_encoder *encoder,
1490                                struct drm_crtc_state *crtc_state,
1491                                struct drm_connector_state *conn_state)
1492 {
1493         struct drm_display_mode *mode = &crtc_state->mode;
1494         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1495         int diff = mode->htotal - mode->hsync_end;
1496
1497         /*
1498          * ZynqMP DP requires horizontal backporch to be greater than 12.
1499          * This limitation may not be compatible with the sink device.
1500          */
1501         if (diff < ZYNQMP_DP_MIN_H_BACKPORCH) {
1502                 int vrefresh = (adjusted_mode->clock * 1000) /
1503                                (adjusted_mode->vtotal * adjusted_mode->htotal);
1504
1505                 dev_dbg(encoder->dev->dev, "hbackporch adjusted: %d to %d",
1506                         diff, ZYNQMP_DP_MIN_H_BACKPORCH - diff);
1507                 diff = ZYNQMP_DP_MIN_H_BACKPORCH - diff;
1508                 adjusted_mode->htotal += diff;
1509                 adjusted_mode->clock = adjusted_mode->vtotal *
1510                                        adjusted_mode->htotal * vrefresh / 1000;
1511         }
1512
1513         return 0;
1514 }
1515
1516 static const struct drm_encoder_helper_funcs zynqmp_dp_encoder_helper_funcs = {
1517         .enable                 = zynqmp_dp_encoder_enable,
1518         .disable                = zynqmp_dp_encoder_disable,
1519         .atomic_mode_set        = zynqmp_dp_encoder_atomic_mode_set,
1520         .atomic_check           = zynqmp_dp_encoder_atomic_check,
1521 };
1522
1523 /* -----------------------------------------------------------------------------
1524  * Interrupt Handling
1525  */
1526
1527 /**
1528  * zynqmp_dp_enable_vblank - Enable vblank
1529  * @dp: DisplayPort IP core structure
1530  *
1531  * Enable vblank interrupt
1532  */
1533 void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp)
1534 {
1535         zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_VBLANK_START);
1536 }
1537
1538 /**
1539  * zynqmp_dp_disable_vblank - Disable vblank
1540  * @dp: DisplayPort IP core structure
1541  *
1542  * Disable vblank interrupt
1543  */
1544 void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp)
1545 {
1546         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_VBLANK_START);
1547 }
1548
1549 static void zynqmp_dp_hpd_work_func(struct work_struct *work)
1550 {
1551         struct zynqmp_dp *dp;
1552
1553         dp = container_of(work, struct zynqmp_dp, hpd_work.work);
1554
1555         if (dp->drm)
1556                 drm_helper_hpd_irq_event(dp->drm);
1557 }
1558
1559 static irqreturn_t zynqmp_dp_irq_handler(int irq, void *data)
1560 {
1561         struct zynqmp_dp *dp = (struct zynqmp_dp *)data;
1562         u32 status, mask;
1563
1564         status = zynqmp_dp_read(dp, ZYNQMP_DP_INT_STATUS);
1565         mask = zynqmp_dp_read(dp, ZYNQMP_DP_INT_MASK);
1566         if (!(status & ~mask))
1567                 return IRQ_NONE;
1568
1569         /* dbg for diagnostic, but not much that the driver can do */
1570         if (status & ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK)
1571                 dev_dbg_ratelimited(dp->dev, "underflow interrupt\n");
1572         if (status & ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK)
1573                 dev_dbg_ratelimited(dp->dev, "overflow interrupt\n");
1574
1575         zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status);
1576
1577         if (status & ZYNQMP_DP_INT_VBLANK_START)
1578                 zynqmp_disp_handle_vblank(dp->dpsub->disp);
1579
1580         if (status & ZYNQMP_DP_INT_HPD_EVENT)
1581                 schedule_delayed_work(&dp->hpd_work, 0);
1582
1583         if (status & ZYNQMP_DP_INT_HPD_IRQ) {
1584                 int ret;
1585                 u8 status[DP_LINK_STATUS_SIZE + 2];
1586
1587                 ret = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status,
1588                                        DP_LINK_STATUS_SIZE + 2);
1589                 if (ret < 0)
1590                         goto handled;
1591
1592                 if (status[4] & DP_LINK_STATUS_UPDATED ||
1593                     !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) ||
1594                     !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) {
1595                         zynqmp_dp_train_loop(dp);
1596                 }
1597         }
1598
1599 handled:
1600         return IRQ_HANDLED;
1601 }
1602
1603 /* -----------------------------------------------------------------------------
1604  * Initialization & Cleanup
1605  */
1606
1607 int zynqmp_dp_drm_init(struct zynqmp_dpsub *dpsub)
1608 {
1609         struct zynqmp_dp *dp = dpsub->dp;
1610         struct drm_encoder *encoder = &dp->encoder;
1611         struct drm_connector *connector = &dp->connector;
1612         int ret;
1613
1614         dp->config.misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK;
1615         zynqmp_dp_set_format(dp, ZYNQMP_DPSUB_FORMAT_RGB, 8);
1616
1617         /* Create the DRM encoder and connector. */
1618         encoder->possible_crtcs |= zynqmp_disp_get_crtc_mask(dpsub->disp);
1619         drm_simple_encoder_init(dp->drm, encoder, DRM_MODE_ENCODER_TMDS);
1620         drm_encoder_helper_add(encoder, &zynqmp_dp_encoder_helper_funcs);
1621
1622         connector->polled = DRM_CONNECTOR_POLL_HPD;
1623         ret = drm_connector_init(encoder->dev, connector,
1624                                  &zynqmp_dp_connector_funcs,
1625                                  DRM_MODE_CONNECTOR_DisplayPort);
1626         if (ret) {
1627                 dev_err(dp->dev, "failed to create the DRM connector\n");
1628                 return ret;
1629         }
1630
1631         drm_connector_helper_add(connector, &zynqmp_dp_connector_helper_funcs);
1632         drm_connector_register(connector);
1633         drm_connector_attach_encoder(connector, encoder);
1634
1635         /* Initialize and register the AUX adapter. */
1636         ret = zynqmp_dp_aux_init(dp);
1637         if (ret) {
1638                 dev_err(dp->dev, "failed to initialize DP aux\n");
1639                 return ret;
1640         }
1641
1642         /* Now that initialisation is complete, enable interrupts. */
1643         zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_ALL);
1644
1645         return 0;
1646 }
1647
1648 int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub, struct drm_device *drm)
1649 {
1650         struct platform_device *pdev = to_platform_device(dpsub->dev);
1651         struct zynqmp_dp *dp;
1652         struct resource *res;
1653         int ret;
1654
1655         dp = drmm_kzalloc(drm, sizeof(*dp), GFP_KERNEL);
1656         if (!dp)
1657                 return -ENOMEM;
1658
1659         dp->dev = &pdev->dev;
1660         dp->dpsub = dpsub;
1661         dp->status = connector_status_disconnected;
1662         dp->drm = drm;
1663
1664         INIT_DELAYED_WORK(&dp->hpd_work, zynqmp_dp_hpd_work_func);
1665
1666         dpsub->dp = dp;
1667
1668         /* Acquire all resources (IOMEM, IRQ and PHYs). */
1669         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dp");
1670         dp->iomem = devm_ioremap_resource(dp->dev, res);
1671         if (IS_ERR(dp->iomem))
1672                 return PTR_ERR(dp->iomem);
1673
1674         dp->irq = platform_get_irq(pdev, 0);
1675         if (dp->irq < 0)
1676                 return dp->irq;
1677
1678         dp->reset = devm_reset_control_get(dp->dev, NULL);
1679         if (IS_ERR(dp->reset)) {
1680                 if (PTR_ERR(dp->reset) != -EPROBE_DEFER)
1681                         dev_err(dp->dev, "failed to get reset: %ld\n",
1682                                 PTR_ERR(dp->reset));
1683                 return PTR_ERR(dp->reset);
1684         }
1685
1686         ret = zynqmp_dp_phy_probe(dp);
1687         if (ret)
1688                 return ret;
1689
1690         /* Initialize the hardware. */
1691         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN,
1692                         ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
1693         zynqmp_dp_set(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET);
1694         zynqmp_dp_write(dp, ZYNQMP_DP_FORCE_SCRAMBLER_RESET, 1);
1695         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0);
1696         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff);
1697
1698         ret = zynqmp_dp_phy_init(dp);
1699         if (ret)
1700                 return ret;
1701
1702         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 1);
1703
1704         /*
1705          * Now that the hardware is initialized and won't generate spurious
1706          * interrupts, request the IRQ.
1707          */
1708         ret = devm_request_threaded_irq(dp->dev, dp->irq, NULL,
1709                                         zynqmp_dp_irq_handler, IRQF_ONESHOT,
1710                                         dev_name(dp->dev), dp);
1711         if (ret < 0)
1712                 goto error;
1713
1714         dev_dbg(dp->dev, "ZynqMP DisplayPort Tx probed with %u lanes\n",
1715                 dp->num_lanes);
1716
1717         return 0;
1718
1719 error:
1720         zynqmp_dp_phy_exit(dp);
1721         return ret;
1722 }
1723
1724 void zynqmp_dp_remove(struct zynqmp_dpsub *dpsub)
1725 {
1726         struct zynqmp_dp *dp = dpsub->dp;
1727
1728         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_ALL);
1729         disable_irq(dp->irq);
1730
1731         cancel_delayed_work_sync(&dp->hpd_work);
1732         zynqmp_dp_aux_cleanup(dp);
1733
1734         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0);
1735         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff);
1736
1737         zynqmp_dp_phy_exit(dp);
1738 }