drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_sched.h"
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/pm_runtime.h>
  39 #include "amdgpu_amdkfd.h"
  40
  41 /**
  42  * amdgpu_driver_unload_kms - Main unload function for KMS.
  43  *
  44  * @dev: drm dev pointer
  45  *
  46  * This is the main unload function for KMS (all asics).
  47  * Returns 0 on success.
  48  */
  49 void amdgpu_driver_unload_kms(struct drm_device *dev)
  50 {
  51         struct amdgpu_device *adev = dev->dev_private;
  52
  53         if (adev == NULL)
  54                 return;
  55
  56         if (adev->rmmio == NULL)
  57                 goto done_free;
  58
  59         if (amdgpu_sriov_vf(adev))
  60                 amdgpu_virt_request_full_gpu(adev, false);
  61
  62         if (amdgpu_device_is_px(dev)) {
  63                 pm_runtime_get_sync(dev->dev);
  64                 pm_runtime_forbid(dev->dev);
  65         }
  66
  67         amdgpu_acpi_fini(adev);
  68
  69         amdgpu_device_fini(adev);
  70
  71 done_free:
  72         kfree(adev);
  73         dev->dev_private = NULL;
  74 }
  75
  76 /**
  77  * amdgpu_driver_load_kms - Main load function for KMS.
  78  *
  79  * @dev: drm dev pointer
  80  * @flags: device flags
  81  *
  82  * This is the main load function for KMS (all asics).
  83  * Returns 0 on success, error on failure.
  84  */
  85 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
  86 {
  87         struct amdgpu_device *adev;
  88         int r, acpi_status;
  89
  90 #ifdef CONFIG_DRM_AMDGPU_SI
  91         if (!amdgpu_si_support) {
  92                 switch (flags & AMD_ASIC_MASK) {
  93                 case CHIP_TAHITI:
  94                 case CHIP_PITCAIRN:
  95                 case CHIP_VERDE:
  96                 case CHIP_OLAND:
  97                 case CHIP_HAINAN:
  98                         dev_info(dev->dev,
  99                                  "SI support provided by radeon.\n");
 100                         dev_info(dev->dev,
 101                                  "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
 102                                 );
 103                         return -ENODEV;
 104                 }
 105         }
 106 #endif
 107 #ifdef CONFIG_DRM_AMDGPU_CIK
 108         if (!amdgpu_cik_support) {
 109                 switch (flags & AMD_ASIC_MASK) {
 110                 case CHIP_KAVERI:
 111                 case CHIP_BONAIRE:
 112                 case CHIP_HAWAII:
 113                 case CHIP_KABINI:
 114                 case CHIP_MULLINS:
 115                         dev_info(dev->dev,
 116                                  "CIK support provided by radeon.\n");
 117                         dev_info(dev->dev,
 118                                  "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
 119                                 );
 120                         return -ENODEV;
 121                 }
 122         }
 123 #endif
 124
 125         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 126         if (adev == NULL) {
 127                 return -ENOMEM;
 128         }
 129         dev->dev_private = (void *)adev;
 130
 131         if ((amdgpu_runtime_pm != 0) &&
 132             amdgpu_has_atpx() &&
 133             (amdgpu_is_atpx_hybrid() ||
 134              amdgpu_has_atpx_dgpu_power_cntl()) &&
 135             ((flags & AMD_IS_APU) == 0) &&
 136             !pci_is_thunderbolt_attached(dev->pdev))
 137                 flags |= AMD_IS_PX;
 138
 139         /* amdgpu_device_init should report only fatal error
 140          * like memory allocation failure or iomapping failure,
 141          * or memory manager initialization failure, it must
 142          * properly initialize the GPU MC controller and permit
 143          * VRAM allocation
 144          */
 145         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 146         if (r) {
 147                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 148                 goto out;
 149         }
 150
 151         /* Call ACPI methods: require modeset init
 152          * but failure is not fatal
 153          */
 154         if (!r) {
 155                 acpi_status = amdgpu_acpi_init(adev);
 156                 if (acpi_status)
 157                 dev_dbg(&dev->pdev->dev,
 158                                 "Error during ACPI methods call\n");
 159         }
 160
 161         if (amdgpu_device_is_px(dev)) {
 162                 pm_runtime_use_autosuspend(dev->dev);
 163                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 164                 pm_runtime_set_active(dev->dev);
 165                 pm_runtime_allow(dev->dev);
 166                 pm_runtime_mark_last_busy(dev->dev);
 167                 pm_runtime_put_autosuspend(dev->dev);
 168         }
 169
 170 out:
 171         if (r) {
 172                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 173                 if (adev->rmmio && amdgpu_device_is_px(dev))
 174                         pm_runtime_put_noidle(dev->dev);
 175                 amdgpu_driver_unload_kms(dev);
 176         }
 177
 178         return r;
 179 }
 180
 181 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 182                                 struct drm_amdgpu_query_fw *query_fw,
 183                                 struct amdgpu_device *adev)
 184 {
 185         switch (query_fw->fw_type) {
 186         case AMDGPU_INFO_FW_VCE:
 187                 fw_info->ver = adev->vce.fw_version;
 188                 fw_info->feature = adev->vce.fb_version;
 189                 break;
 190         case AMDGPU_INFO_FW_UVD:
 191                 fw_info->ver = adev->uvd.fw_version;
 192                 fw_info->feature = 0;
 193                 break;
 194         case AMDGPU_INFO_FW_VCN:
 195                 fw_info->ver = adev->vcn.fw_version;
 196                 fw_info->feature = 0;
 197                 break;
 198         case AMDGPU_INFO_FW_GMC:
 199                 fw_info->ver = adev->gmc.fw_version;
 200                 fw_info->feature = 0;
 201                 break;
 202         case AMDGPU_INFO_FW_GFX_ME:
 203                 fw_info->ver = adev->gfx.me_fw_version;
 204                 fw_info->feature = adev->gfx.me_feature_version;
 205                 break;
 206         case AMDGPU_INFO_FW_GFX_PFP:
 207                 fw_info->ver = adev->gfx.pfp_fw_version;
 208                 fw_info->feature = adev->gfx.pfp_feature_version;
 209                 break;
 210         case AMDGPU_INFO_FW_GFX_CE:
 211                 fw_info->ver = adev->gfx.ce_fw_version;
 212                 fw_info->feature = adev->gfx.ce_feature_version;
 213                 break;
 214         case AMDGPU_INFO_FW_GFX_RLC:
 215                 fw_info->ver = adev->gfx.rlc_fw_version;
 216                 fw_info->feature = adev->gfx.rlc_feature_version;
 217                 break;
 218         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 219                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 220                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 221                 break;
 222         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 223                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 224                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 225                 break;
 226         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 227                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 228                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 229                 break;
 230         case AMDGPU_INFO_FW_GFX_MEC:
 231                 if (query_fw->index == 0) {
 232                         fw_info->ver = adev->gfx.mec_fw_version;
 233                         fw_info->feature = adev->gfx.mec_feature_version;
 234                 } else if (query_fw->index == 1) {
 235                         fw_info->ver = adev->gfx.mec2_fw_version;
 236                         fw_info->feature = adev->gfx.mec2_feature_version;
 237                 } else
 238                         return -EINVAL;
 239                 break;
 240         case AMDGPU_INFO_FW_SMC:
 241                 fw_info->ver = adev->pm.fw_version;
 242                 fw_info->feature = 0;
 243                 break;
 244         case AMDGPU_INFO_FW_SDMA:
 245                 if (query_fw->index >= adev->sdma.num_instances)
 246                         return -EINVAL;
 247                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 248                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 249                 break;
 250         case AMDGPU_INFO_FW_SOS:
 251                 fw_info->ver = adev->psp.sos_fw_version;
 252                 fw_info->feature = adev->psp.sos_feature_version;
 253                 break;
 254         case AMDGPU_INFO_FW_ASD:
 255                 fw_info->ver = adev->psp.asd_fw_version;
 256                 fw_info->feature = adev->psp.asd_feature_version;
 257                 break;
 258         default:
 259                 return -EINVAL;
 260         }
 261         return 0;
 262 }
 263
 264 /*
 265  * Userspace get information ioctl
 266  */
 267 /**
 268  * amdgpu_info_ioctl - answer a device specific request.
 269  *
 270  * @adev: amdgpu device pointer
 271  * @data: request object
 272  * @filp: drm filp
 273  *
 274  * This function is used to pass device specific parameters to the userspace
 275  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 276  * etc. (all asics).
 277  * Returns 0 on success, -EINVAL on failure.
 278  */
 279 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 280 {
 281         struct amdgpu_device *adev = dev->dev_private;
 282         struct drm_amdgpu_info *info = data;
 283         struct amdgpu_mode_info *minfo = &adev->mode_info;
 284         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 285         uint32_t size = info->return_size;
 286         struct drm_crtc *crtc;
 287         uint32_t ui32 = 0;
 288         uint64_t ui64 = 0;
 289         int i, found;
 290         int ui32_size = sizeof(ui32);
 291
 292         if (!info->return_size || !info->return_pointer)
 293                 return -EINVAL;
 294
 295         /* Ensure IB tests are run on ring */
 296         flush_delayed_work(&adev->late_init_work);
 297
 298         switch (info->query) {
 299         case AMDGPU_INFO_ACCEL_WORKING:
 300                 ui32 = adev->accel_working;
 301                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 302         case AMDGPU_INFO_CRTC_FROM_ID:
 303                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 304                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 305                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 306                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 307                                 ui32 = amdgpu_crtc->crtc_id;
 308                                 found = 1;
 309                                 break;
 310                         }
 311                 }
 312                 if (!found) {
 313                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 314                         return -EINVAL;
 315                 }
 316                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 317         case AMDGPU_INFO_HW_IP_INFO: {
 318                 struct drm_amdgpu_info_hw_ip ip = {};
 319                 enum amd_ip_block_type type;
 320                 uint32_t ring_mask = 0;
 321                 uint32_t ib_start_alignment = 0;
 322                 uint32_t ib_size_alignment = 0;
 323
 324                 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 325                         return -EINVAL;
 326
 327                 switch (info->query_hw_ip.type) {
 328                 case AMDGPU_HW_IP_GFX:
 329                         type = AMD_IP_BLOCK_TYPE_GFX;
 330                         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 331                                 ring_mask |= adev->gfx.gfx_ring[i].ready << i;
 332                         ib_start_alignment = 32;
 333                         ib_size_alignment = 32;
 334                         break;
 335                 case AMDGPU_HW_IP_COMPUTE:
 336                         type = AMD_IP_BLOCK_TYPE_GFX;
 337                         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 338                                 ring_mask |= adev->gfx.compute_ring[i].ready << i;
 339                         ib_start_alignment = 32;
 340                         ib_size_alignment = 32;
 341                         break;
 342                 case AMDGPU_HW_IP_DMA:
 343                         type = AMD_IP_BLOCK_TYPE_SDMA;
 344                         for (i = 0; i < adev->sdma.num_instances; i++)
 345                                 ring_mask |= adev->sdma.instance[i].ring.ready << i;
 346                         ib_start_alignment = 256;
 347                         ib_size_alignment = 4;
 348                         break;
 349                 case AMDGPU_HW_IP_UVD:
 350                         type = AMD_IP_BLOCK_TYPE_UVD;
 351                         ring_mask |= adev->uvd.inst[0].ring.ready;
 352                         ib_start_alignment = 64;
 353                         ib_size_alignment = 64;
 354                         break;
 355                 case AMDGPU_HW_IP_VCE:
 356                         type = AMD_IP_BLOCK_TYPE_VCE;
 357                         for (i = 0; i < adev->vce.num_rings; i++)
 358                                 ring_mask |= adev->vce.ring[i].ready << i;
 359                         ib_start_alignment = 4;
 360                         ib_size_alignment = 1;
 361                         break;
 362                 case AMDGPU_HW_IP_UVD_ENC:
 363                         type = AMD_IP_BLOCK_TYPE_UVD;
 364                         for (i = 0; i < adev->uvd.num_enc_rings; i++)
 365                                 ring_mask |=
 366                                         adev->uvd.inst[0].ring_enc[i].ready << i;
 367                         ib_start_alignment = 64;
 368                         ib_size_alignment = 64;
 369                         break;
 370                 case AMDGPU_HW_IP_VCN_DEC:
 371                         type = AMD_IP_BLOCK_TYPE_VCN;
 372                         ring_mask = adev->vcn.ring_dec.ready;
 373                         ib_start_alignment = 16;
 374                         ib_size_alignment = 16;
 375                         break;
 376                 case AMDGPU_HW_IP_VCN_ENC:
 377                         type = AMD_IP_BLOCK_TYPE_VCN;
 378                         for (i = 0; i < adev->vcn.num_enc_rings; i++)
 379                                 ring_mask |= adev->vcn.ring_enc[i].ready << i;
 380                         ib_start_alignment = 64;
 381                         ib_size_alignment = 1;
 382                         break;
 383                 case AMDGPU_HW_IP_VCN_JPEG:
 384                         type = AMD_IP_BLOCK_TYPE_VCN;
 385                         ring_mask = adev->vcn.ring_jpeg.ready;
 386                         ib_start_alignment = 16;
 387                         ib_size_alignment = 16;
 388                         break;
 389                 default:
 390                         return -EINVAL;
 391                 }
 392
 393                 for (i = 0; i < adev->num_ip_blocks; i++) {
 394                         if (adev->ip_blocks[i].version->type == type &&
 395                             adev->ip_blocks[i].status.valid) {
 396                                 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
 397                                 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 398                                 ip.capabilities_flags = 0;
 399                                 ip.available_rings = ring_mask;
 400                                 ip.ib_start_alignment = ib_start_alignment;
 401                                 ip.ib_size_alignment = ib_size_alignment;
 402                                 break;
 403                         }
 404                 }
 405                 return copy_to_user(out, &ip,
 406                                     min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
 407         }
 408         case AMDGPU_INFO_HW_IP_COUNT: {
 409                 enum amd_ip_block_type type;
 410                 uint32_t count = 0;
 411
 412                 switch (info->query_hw_ip.type) {
 413                 case AMDGPU_HW_IP_GFX:
 414                         type = AMD_IP_BLOCK_TYPE_GFX;
 415                         break;
 416                 case AMDGPU_HW_IP_COMPUTE:
 417                         type = AMD_IP_BLOCK_TYPE_GFX;
 418                         break;
 419                 case AMDGPU_HW_IP_DMA:
 420                         type = AMD_IP_BLOCK_TYPE_SDMA;
 421                         break;
 422                 case AMDGPU_HW_IP_UVD:
 423                         type = AMD_IP_BLOCK_TYPE_UVD;
 424                         break;
 425                 case AMDGPU_HW_IP_VCE:
 426                         type = AMD_IP_BLOCK_TYPE_VCE;
 427                         break;
 428                 case AMDGPU_HW_IP_UVD_ENC:
 429                         type = AMD_IP_BLOCK_TYPE_UVD;
 430                         break;
 431                 case AMDGPU_HW_IP_VCN_DEC:
 432                 case AMDGPU_HW_IP_VCN_ENC:
 433                 case AMDGPU_HW_IP_VCN_JPEG:
 434                         type = AMD_IP_BLOCK_TYPE_VCN;
 435                         break;
 436                 default:
 437                         return -EINVAL;
 438                 }
 439
 440                 for (i = 0; i < adev->num_ip_blocks; i++)
 441                         if (adev->ip_blocks[i].version->type == type &&
 442                             adev->ip_blocks[i].status.valid &&
 443                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 444                                 count++;
 445
 446                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 447         }
 448         case AMDGPU_INFO_TIMESTAMP:
 449                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 450                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 451         case AMDGPU_INFO_FW_VERSION: {
 452                 struct drm_amdgpu_info_firmware fw_info;
 453                 int ret;
 454
 455                 /* We only support one instance of each IP block right now. */
 456                 if (info->query_fw.ip_instance != 0)
 457                         return -EINVAL;
 458
 459                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 460                 if (ret)
 461                         return ret;
 462
 463                 return copy_to_user(out, &fw_info,
 464                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 465         }
 466         case AMDGPU_INFO_NUM_BYTES_MOVED:
 467                 ui64 = atomic64_read(&adev->num_bytes_moved);
 468                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 469         case AMDGPU_INFO_NUM_EVICTIONS:
 470                 ui64 = atomic64_read(&adev->num_evictions);
 471                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 472         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 473                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 474                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 475         case AMDGPU_INFO_VRAM_USAGE:
 476                 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 477                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 478         case AMDGPU_INFO_VIS_VRAM_USAGE:
 479                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 480                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 481         case AMDGPU_INFO_GTT_USAGE:
 482                 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 483                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 484         case AMDGPU_INFO_GDS_CONFIG: {
 485                 struct drm_amdgpu_info_gds gds_info;
 486
 487                 memset(&gds_info, 0, sizeof(gds_info));
 488                 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
 489                 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
 490                 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
 491                 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
 492                 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
 493                 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
 494                 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
 495                 return copy_to_user(out, &gds_info,
 496                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 497         }
 498         case AMDGPU_INFO_VRAM_GTT: {
 499                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 500
 501                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 502                         atomic64_read(&adev->vram_pin_size);
 503                 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
 504                         atomic64_read(&adev->visible_pin_size);
 505                 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
 506                 vram_gtt.gtt_size *= PAGE_SIZE;
 507                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 508                 return copy_to_user(out, &vram_gtt,
 509                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 510         }
 511         case AMDGPU_INFO_MEMORY: {
 512                 struct drm_amdgpu_memory_info mem;
 513
 514                 memset(&mem, 0, sizeof(mem));
 515                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 516                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 517                         atomic64_read(&adev->vram_pin_size);
 518                 mem.vram.heap_usage =
 519                         amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 520                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 521
 522                 mem.cpu_accessible_vram.total_heap_size =
 523                         adev->gmc.visible_vram_size;
 524                 mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
 525                         atomic64_read(&adev->visible_pin_size);
 526                 mem.cpu_accessible_vram.heap_usage =
 527                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 528                 mem.cpu_accessible_vram.max_allocation =
 529                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 530
 531                 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
 532                 mem.gtt.total_heap_size *= PAGE_SIZE;
 533                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 534                         atomic64_read(&adev->gart_pin_size);
 535                 mem.gtt.heap_usage =
 536                         amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 537                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 538
 539                 return copy_to_user(out, &mem,
 540                                     min((size_t)size, sizeof(mem)))
 541                                     ? -EFAULT : 0;
 542         }
 543         case AMDGPU_INFO_READ_MMR_REG: {
 544                 unsigned n, alloc_size;
 545                 uint32_t *regs;
 546                 unsigned se_num = (info->read_mmr_reg.instance >>
 547                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 548                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 549                 unsigned sh_num = (info->read_mmr_reg.instance >>
 550                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 551                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 552
 553                 /* set full masks if the userspace set all bits
 554                  * in the bitfields */
 555                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 556                         se_num = 0xffffffff;
 557                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 558                         sh_num = 0xffffffff;
 559
 560                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 561                 if (!regs)
 562                         return -ENOMEM;
 563                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 564
 565                 for (i = 0; i < info->read_mmr_reg.count; i++)
 566                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 567                                                       info->read_mmr_reg.dword_offset + i,
 568                                                       &regs[i])) {
 569                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 570                                               info->read_mmr_reg.dword_offset + i);
 571                                 kfree(regs);
 572                                 return -EFAULT;
 573                         }
 574                 n = copy_to_user(out, regs, min(size, alloc_size));
 575                 kfree(regs);
 576                 return n ? -EFAULT : 0;
 577         }
 578         case AMDGPU_INFO_DEV_INFO: {
 579                 struct drm_amdgpu_info_device dev_info = {};
 580                 uint64_t vm_size;
 581
 582                 dev_info.device_id = dev->pdev->device;
 583                 dev_info.chip_rev = adev->rev_id;
 584                 dev_info.external_rev = adev->external_rev_id;
 585                 dev_info.pci_rev = dev->pdev->revision;
 586                 dev_info.family = adev->family;
 587                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 588                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 589                 /* return all clocks in KHz */
 590                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 591                 if (adev->pm.dpm_enabled) {
 592                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 593                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 594                 } else {
 595                         dev_info.max_engine_clock = adev->clock.default_sclk * 10;
 596                         dev_info.max_memory_clock = adev->clock.default_mclk * 10;
 597                 }
 598                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 599                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 600                         adev->gfx.config.max_shader_engines;
 601                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 602                 dev_info._pad = 0;
 603                 dev_info.ids_flags = 0;
 604                 if (adev->flags & AMD_IS_APU)
 605                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 606                 if (amdgpu_sriov_vf(adev))
 607                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 608
 609                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 610                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 611
 612                 /* Older VCE FW versions are buggy and can handle only 40bits */
 613                 if (adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 614                         vm_size = min(vm_size, 1ULL << 40);
 615
 616                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 617                 dev_info.virtual_address_max =
 618                         min(vm_size, AMDGPU_VA_HOLE_START);
 619
 620                 if (vm_size > AMDGPU_VA_HOLE_START) {
 621                         dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
 622                         dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;
 623                 }
 624                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 625                 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 626                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 627                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 628                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 629                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 630                 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 631                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 632                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 633                        sizeof(adev->gfx.cu_info.bitmap));
 634                 dev_info.vram_type = adev->gmc.vram_type;
 635                 dev_info.vram_bit_width = adev->gmc.vram_width;
 636                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 637                 dev_info.gc_double_offchip_lds_buf =
 638                         adev->gfx.config.double_offchip_lds_buf;
 639
 640                 if (amdgpu_ngg) {
 641                         dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
 642                         dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
 643                         dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
 644                         dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
 645                         dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
 646                         dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
 647                         dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
 648                         dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
 649                 }
 650                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
 651                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 652                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 653                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 654                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 655                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 656                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 657
 658                 return copy_to_user(out, &dev_info,
 659                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 660         }
 661         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 662                 unsigned i;
 663                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 664                 struct amd_vce_state *vce_state;
 665
 666                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 667                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 668                         if (vce_state) {
 669                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 670                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 671                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 672                                 vce_clk_table.num_valid_entries++;
 673                         }
 674                 }
 675
 676                 return copy_to_user(out, &vce_clk_table,
 677                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 678         }
 679         case AMDGPU_INFO_VBIOS: {
 680                 uint32_t bios_size = adev->bios_size;
 681
 682                 switch (info->vbios_info.type) {
 683                 case AMDGPU_INFO_VBIOS_SIZE:
 684                         return copy_to_user(out, &bios_size,
 685                                         min((size_t)size, sizeof(bios_size)))
 686                                         ? -EFAULT : 0;
 687                 case AMDGPU_INFO_VBIOS_IMAGE: {
 688                         uint8_t *bios;
 689                         uint32_t bios_offset = info->vbios_info.offset;
 690
 691                         if (bios_offset >= bios_size)
 692                                 return -EINVAL;
 693
 694                         bios = adev->bios + bios_offset;
 695                         return copy_to_user(out, bios,
 696                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 697                                         ? -EFAULT : 0;
 698                 }
 699                 default:
 700                         DRM_DEBUG_KMS("Invalid request %d\n",
 701                                         info->vbios_info.type);
 702                         return -EINVAL;
 703                 }
 704         }
 705         case AMDGPU_INFO_NUM_HANDLES: {
 706                 struct drm_amdgpu_info_num_handles handle;
 707
 708                 switch (info->query_hw_ip.type) {
 709                 case AMDGPU_HW_IP_UVD:
 710                         /* Starting Polaris, we support unlimited UVD handles */
 711                         if (adev->asic_type < CHIP_POLARIS10) {
 712                                 handle.uvd_max_handles = adev->uvd.max_handles;
 713                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 714
 715                                 return copy_to_user(out, &handle,
 716                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 717                         } else {
 718                                 return -ENODATA;
 719                         }
 720
 721                         break;
 722                 default:
 723                         return -EINVAL;
 724                 }
 725         }
 726         case AMDGPU_INFO_SENSOR: {
 727                 if (!adev->pm.dpm_enabled)
 728                         return -ENOENT;
 729
 730                 switch (info->sensor_info.type) {
 731                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 732                         /* get sclk in Mhz */
 733                         if (amdgpu_dpm_read_sensor(adev,
 734                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 735                                                    (void *)&ui32, &ui32_size)) {
 736                                 return -EINVAL;
 737                         }
 738                         ui32 /= 100;
 739                         break;
 740                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 741                         /* get mclk in Mhz */
 742                         if (amdgpu_dpm_read_sensor(adev,
 743                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 744                                                    (void *)&ui32, &ui32_size)) {
 745                                 return -EINVAL;
 746                         }
 747                         ui32 /= 100;
 748                         break;
 749                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 750                         /* get temperature in millidegrees C */
 751                         if (amdgpu_dpm_read_sensor(adev,
 752                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 753                                                    (void *)&ui32, &ui32_size)) {
 754                                 return -EINVAL;
 755                         }
 756                         break;
 757                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 758                         /* get GPU load */
 759                         if (amdgpu_dpm_read_sensor(adev,
 760                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 761                                                    (void *)&ui32, &ui32_size)) {
 762                                 return -EINVAL;
 763                         }
 764                         break;
 765                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 766                         /* get average GPU power */
 767                         if (amdgpu_dpm_read_sensor(adev,
 768                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 769                                                    (void *)&ui32, &ui32_size)) {
 770                                 return -EINVAL;
 771                         }
 772                         ui32 >>= 8;
 773                         break;
 774                 case AMDGPU_INFO_SENSOR_VDDNB:
 775                         /* get VDDNB in millivolts */
 776                         if (amdgpu_dpm_read_sensor(adev,
 777                                                    AMDGPU_PP_SENSOR_VDDNB,
 778                                                    (void *)&ui32, &ui32_size)) {
 779                                 return -EINVAL;
 780                         }
 781                         break;
 782                 case AMDGPU_INFO_SENSOR_VDDGFX:
 783                         /* get VDDGFX in millivolts */
 784                         if (amdgpu_dpm_read_sensor(adev,
 785                                                    AMDGPU_PP_SENSOR_VDDGFX,
 786                                                    (void *)&ui32, &ui32_size)) {
 787                                 return -EINVAL;
 788                         }
 789                         break;
 790                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 791                         /* get stable pstate sclk in Mhz */
 792                         if (amdgpu_dpm_read_sensor(adev,
 793                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 794                                                    (void *)&ui32, &ui32_size)) {
 795                                 return -EINVAL;
 796                         }
 797                         ui32 /= 100;
 798                         break;
 799                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 800                         /* get stable pstate mclk in Mhz */
 801                         if (amdgpu_dpm_read_sensor(adev,
 802                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 803                                                    (void *)&ui32, &ui32_size)) {
 804                                 return -EINVAL;
 805                         }
 806                         ui32 /= 100;
 807                         break;
 808                 default:
 809                         DRM_DEBUG_KMS("Invalid request %d\n",
 810                                       info->sensor_info.type);
 811                         return -EINVAL;
 812                 }
 813                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 814         }
 815         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 816                 ui32 = atomic_read(&adev->vram_lost_counter);
 817                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 818         default:
 819                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 820                 return -EINVAL;
 821         }
 822         return 0;
 823 }
 824
 825
 826 /*
 827  * Outdated mess for old drm with Xorg being in charge (void function now).
 828  */
 829 /**
 830  * amdgpu_driver_lastclose_kms - drm callback for last close
 831  *
 832  * @dev: drm dev pointer
 833  *
 834  * Switch vga_switcheroo state after last close (all asics).
 835  */
 836 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 837 {
 838         drm_fb_helper_lastclose(dev);
 839         vga_switcheroo_process_delayed_switch();
 840 }
 841
 842 /**
 843  * amdgpu_driver_open_kms - drm callback for open
 844  *
 845  * @dev: drm dev pointer
 846  * @file_priv: drm file
 847  *
 848  * On device open, init vm on cayman+ (all asics).
 849  * Returns 0 on success, error on failure.
 850  */
 851 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 852 {
 853         struct amdgpu_device *adev = dev->dev_private;
 854         struct amdgpu_fpriv *fpriv;
 855         int r, pasid;
 856
 857         file_priv->driver_priv = NULL;
 858
 859         r = pm_runtime_get_sync(dev->dev);
 860         if (r < 0)
 861                 return r;
 862
 863         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 864         if (unlikely(!fpriv)) {
 865                 r = -ENOMEM;
 866                 goto out_suspend;
 867         }
 868
 869         pasid = amdgpu_pasid_alloc(16);
 870         if (pasid < 0) {
 871                 dev_warn(adev->dev, "No more PASIDs available!");
 872                 pasid = 0;
 873         }
 874         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
 875         if (r)
 876                 goto error_pasid;
 877
 878         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
 879         if (!fpriv->prt_va) {
 880                 r = -ENOMEM;
 881                 goto error_vm;
 882         }
 883
 884         if (amdgpu_sriov_vf(adev)) {
 885                 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
 886                 if (r)
 887                         goto error_vm;
 888         }
 889
 890         mutex_init(&fpriv->bo_list_lock);
 891         idr_init(&fpriv->bo_list_handles);
 892
 893         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
 894
 895         file_priv->driver_priv = fpriv;
 896         goto out_suspend;
 897
 898 error_vm:
 899         amdgpu_vm_fini(adev, &fpriv->vm);
 900
 901 error_pasid:
 902         if (pasid)
 903                 amdgpu_pasid_free(pasid);
 904
 905         kfree(fpriv);
 906
 907 out_suspend:
 908         pm_runtime_mark_last_busy(dev->dev);
 909         pm_runtime_put_autosuspend(dev->dev);
 910
 911         return r;
 912 }
 913
 914 /**
 915  * amdgpu_driver_postclose_kms - drm callback for post close
 916  *
 917  * @dev: drm dev pointer
 918  * @file_priv: drm file
 919  *
 920  * On device post close, tear down vm on cayman+ (all asics).
 921  */
 922 void amdgpu_driver_postclose_kms(struct drm_device *dev,
 923                                  struct drm_file *file_priv)
 924 {
 925         struct amdgpu_device *adev = dev->dev_private;
 926         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 927         struct amdgpu_bo_list *list;
 928         struct amdgpu_bo *pd;
 929         unsigned int pasid;
 930         int handle;
 931
 932         if (!fpriv)
 933                 return;
 934
 935         pm_runtime_get_sync(dev->dev);
 936
 937         if (adev->asic_type != CHIP_RAVEN) {
 938                 amdgpu_uvd_free_handles(adev, file_priv);
 939                 amdgpu_vce_free_handles(adev, file_priv);
 940         }
 941
 942         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
 943
 944         if (amdgpu_sriov_vf(adev)) {
 945                 /* TODO: how to handle reserve failure */
 946                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
 947                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
 948                 fpriv->csa_va = NULL;
 949                 amdgpu_bo_unreserve(adev->virt.csa_obj);
 950         }
 951
 952         pasid = fpriv->vm.pasid;
 953         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
 954
 955         amdgpu_vm_fini(adev, &fpriv->vm);
 956         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
 957
 958         if (pasid)
 959                 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
 960         amdgpu_bo_unref(&pd);
 961
 962         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
 963                 amdgpu_bo_list_free(list);
 964
 965         idr_destroy(&fpriv->bo_list_handles);
 966         mutex_destroy(&fpriv->bo_list_lock);
 967
 968         kfree(fpriv);
 969         file_priv->driver_priv = NULL;
 970
 971         pm_runtime_mark_last_busy(dev->dev);
 972         pm_runtime_put_autosuspend(dev->dev);
 973 }
 974
 975 /*
 976  * VBlank related functions.
 977  */
 978 /**
 979  * amdgpu_get_vblank_counter_kms - get frame count
 980  *
 981  * @dev: drm dev pointer
 982  * @pipe: crtc to get the frame count from
 983  *
 984  * Gets the frame count on the requested crtc (all asics).
 985  * Returns frame count on success, -EINVAL on failure.
 986  */
 987 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
 988 {
 989         struct amdgpu_device *adev = dev->dev_private;
 990         int vpos, hpos, stat;
 991         u32 count;
 992
 993         if (pipe >= adev->mode_info.num_crtc) {
 994                 DRM_ERROR("Invalid crtc %u\n", pipe);
 995                 return -EINVAL;
 996         }
 997
 998         /* The hw increments its frame counter at start of vsync, not at start
 999          * of vblank, as is required by DRM core vblank counter handling.
1000          * Cook the hw count here to make it appear to the caller as if it
1001          * incremented at start of vblank. We measure distance to start of
1002          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1003          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1004          * result by 1 to give the proper appearance to caller.
1005          */
1006         if (adev->mode_info.crtcs[pipe]) {
1007                 /* Repeat readout if needed to provide stable result if
1008                  * we cross start of vsync during the queries.
1009                  */
1010                 do {
1011                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1012                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1013                          * vpos as distance to start of vblank, instead of
1014                          * regular vertical scanout pos.
1015                          */
1016                         stat = amdgpu_display_get_crtc_scanoutpos(
1017                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1018                                 &vpos, &hpos, NULL, NULL,
1019                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1020                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1021
1022                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1023                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1024                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1025                 } else {
1026                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1027                                       pipe, vpos);
1028
1029                         /* Bump counter if we are at >= leading edge of vblank,
1030                          * but before vsync where vpos would turn negative and
1031                          * the hw counter really increments.
1032                          */
1033                         if (vpos >= 0)
1034                                 count++;
1035                 }
1036         } else {
1037                 /* Fallback to use value as is. */
1038                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1039                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1040         }
1041
1042         return count;
1043 }
1044
1045 /**
1046  * amdgpu_enable_vblank_kms - enable vblank interrupt
1047  *
1048  * @dev: drm dev pointer
1049  * @pipe: crtc to enable vblank interrupt for
1050  *
1051  * Enable the interrupt on the requested crtc (all asics).
1052  * Returns 0 on success, -EINVAL on failure.
1053  */
1054 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1055 {
1056         struct amdgpu_device *adev = dev->dev_private;
1057         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1058
1059         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1060 }
1061
1062 /**
1063  * amdgpu_disable_vblank_kms - disable vblank interrupt
1064  *
1065  * @dev: drm dev pointer
1066  * @pipe: crtc to disable vblank interrupt for
1067  *
1068  * Disable the interrupt on the requested crtc (all asics).
1069  */
1070 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1071 {
1072         struct amdgpu_device *adev = dev->dev_private;
1073         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1074
1075         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1076 }
1077
1078 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1079         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1080         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1081         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1082         DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1083         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1084         DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1085         /* KMS */
1086         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1087         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1088         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1089         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1090         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1091         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1092         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1093         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1094         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1095         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1096 };
1097 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1098
1099 /*
1100  * Debugfs info
1101  */
1102 #if defined(CONFIG_DEBUG_FS)
1103
1104 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1105 {
1106         struct drm_info_node *node = (struct drm_info_node *) m->private;
1107         struct drm_device *dev = node->minor->dev;
1108         struct amdgpu_device *adev = dev->dev_private;
1109         struct drm_amdgpu_info_firmware fw_info;
1110         struct drm_amdgpu_query_fw query_fw;
1111         struct atom_context *ctx = adev->mode_info.atom_context;
1112         int ret, i;
1113
1114         /* VCE */
1115         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1116         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1117         if (ret)
1118                 return ret;
1119         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1120                    fw_info.feature, fw_info.ver);
1121
1122         /* UVD */
1123         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1124         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1125         if (ret)
1126                 return ret;
1127         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1128                    fw_info.feature, fw_info.ver);
1129
1130         /* GMC */
1131         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1132         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1133         if (ret)
1134                 return ret;
1135         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1136                    fw_info.feature, fw_info.ver);
1137
1138         /* ME */
1139         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1140         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1141         if (ret)
1142                 return ret;
1143         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1144                    fw_info.feature, fw_info.ver);
1145
1146         /* PFP */
1147         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1148         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1149         if (ret)
1150                 return ret;
1151         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1152                    fw_info.feature, fw_info.ver);
1153
1154         /* CE */
1155         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1156         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1157         if (ret)
1158                 return ret;
1159         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1160                    fw_info.feature, fw_info.ver);
1161
1162         /* RLC */
1163         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1164         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1165         if (ret)
1166                 return ret;
1167         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1168                    fw_info.feature, fw_info.ver);
1169
1170         /* RLC SAVE RESTORE LIST CNTL */
1171         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1172         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1173         if (ret)
1174                 return ret;
1175         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1176                    fw_info.feature, fw_info.ver);
1177
1178         /* RLC SAVE RESTORE LIST GPM MEM */
1179         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1180         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1181         if (ret)
1182                 return ret;
1183         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1184                    fw_info.feature, fw_info.ver);
1185
1186         /* RLC SAVE RESTORE LIST SRM MEM */
1187         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1188         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1189         if (ret)
1190                 return ret;
1191         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1192                    fw_info.feature, fw_info.ver);
1193
1194         /* MEC */
1195         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1196         query_fw.index = 0;
1197         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1198         if (ret)
1199                 return ret;
1200         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1201                    fw_info.feature, fw_info.ver);
1202
1203         /* MEC2 */
1204         if (adev->asic_type == CHIP_KAVERI ||
1205             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1206                 query_fw.index = 1;
1207                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1208                 if (ret)
1209                         return ret;
1210                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1211                            fw_info.feature, fw_info.ver);
1212         }
1213
1214         /* PSP SOS */
1215         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1216         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1217         if (ret)
1218                 return ret;
1219         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1220                    fw_info.feature, fw_info.ver);
1221
1222
1223         /* PSP ASD */
1224         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1225         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1226         if (ret)
1227                 return ret;
1228         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1229                    fw_info.feature, fw_info.ver);
1230
1231         /* SMC */
1232         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1233         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1234         if (ret)
1235                 return ret;
1236         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1237                    fw_info.feature, fw_info.ver);
1238
1239         /* SDMA */
1240         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1241         for (i = 0; i < adev->sdma.num_instances; i++) {
1242                 query_fw.index = i;
1243                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1244                 if (ret)
1245                         return ret;
1246                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1247                            i, fw_info.feature, fw_info.ver);
1248         }
1249
1250         /* VCN */
1251         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1252         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1253         if (ret)
1254                 return ret;
1255         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1256                    fw_info.feature, fw_info.ver);
1257
1258
1259         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1260
1261         return 0;
1262 }
1263
1264 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1265         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1266 };
1267 #endif
1268
1269 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1270 {
1271 #if defined(CONFIG_DEBUG_FS)
1272         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1273                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1274 #else
1275         return 0;
1276 #endif
1277 }