drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include "amdgpu_sched.h"
  32 #include "amdgpu_uvd.h"
  33 #include "amdgpu_vce.h"
  34 #include "atom.h"
  35
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/slab.h>
  38 #include <linux/pm_runtime.h>
  39 #include "amdgpu_amdkfd.h"
  40 #include "amdgpu_gem.h"
  41
  42 /**
  43  * amdgpu_driver_unload_kms - Main unload function for KMS.
  44  *
  45  * @dev: drm dev pointer
  46  *
  47  * This is the main unload function for KMS (all asics).
  48  * Returns 0 on success.
  49  */
  50 void amdgpu_driver_unload_kms(struct drm_device *dev)
  51 {
  52         struct amdgpu_device *adev = dev->dev_private;
  53
  54         if (adev == NULL)
  55                 return;
  56
  57         if (adev->rmmio == NULL)
  58                 goto done_free;
  59
  60         if (amdgpu_sriov_vf(adev))
  61                 amdgpu_virt_request_full_gpu(adev, false);
  62
  63         if (amdgpu_device_is_px(dev)) {
  64                 pm_runtime_get_sync(dev->dev);
  65                 pm_runtime_forbid(dev->dev);
  66         }
  67
  68         amdgpu_acpi_fini(adev);
  69
  70         amdgpu_device_fini(adev);
  71
  72 done_free:
  73         kfree(adev);
  74         dev->dev_private = NULL;
  75 }
  76
  77 /**
  78  * amdgpu_driver_load_kms - Main load function for KMS.
  79  *
  80  * @dev: drm dev pointer
  81  * @flags: device flags
  82  *
  83  * This is the main load function for KMS (all asics).
  84  * Returns 0 on success, error on failure.
  85  */
  86 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
  87 {
  88         struct amdgpu_device *adev;
  89         int r, acpi_status;
  90
  91 #ifdef CONFIG_DRM_AMDGPU_SI
  92         if (!amdgpu_si_support) {
  93                 switch (flags & AMD_ASIC_MASK) {
  94                 case CHIP_TAHITI:
  95                 case CHIP_PITCAIRN:
  96                 case CHIP_VERDE:
  97                 case CHIP_OLAND:
  98                 case CHIP_HAINAN:
  99                         dev_info(dev->dev,
 100                                  "SI support provided by radeon.\n");
 101                         dev_info(dev->dev,
 102                                  "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
 103                                 );
 104                         return -ENODEV;
 105                 }
 106         }
 107 #endif
 108 #ifdef CONFIG_DRM_AMDGPU_CIK
 109         if (!amdgpu_cik_support) {
 110                 switch (flags & AMD_ASIC_MASK) {
 111                 case CHIP_KAVERI:
 112                 case CHIP_BONAIRE:
 113                 case CHIP_HAWAII:
 114                 case CHIP_KABINI:
 115                 case CHIP_MULLINS:
 116                         dev_info(dev->dev,
 117                                  "CIK support provided by radeon.\n");
 118                         dev_info(dev->dev,
 119                                  "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
 120                                 );
 121                         return -ENODEV;
 122                 }
 123         }
 124 #endif
 125
 126         adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 127         if (adev == NULL) {
 128                 return -ENOMEM;
 129         }
 130         dev->dev_private = (void *)adev;
 131
 132         if ((amdgpu_runtime_pm != 0) &&
 133             amdgpu_has_atpx() &&
 134             (amdgpu_is_atpx_hybrid() ||
 135              amdgpu_has_atpx_dgpu_power_cntl()) &&
 136             ((flags & AMD_IS_APU) == 0) &&
 137             !pci_is_thunderbolt_attached(dev->pdev))
 138                 flags |= AMD_IS_PX;
 139
 140         /* amdgpu_device_init should report only fatal error
 141          * like memory allocation failure or iomapping failure,
 142          * or memory manager initialization failure, it must
 143          * properly initialize the GPU MC controller and permit
 144          * VRAM allocation
 145          */
 146         r = amdgpu_device_init(adev, dev, dev->pdev, flags);
 147         if (r) {
 148                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 149                 goto out;
 150         }
 151
 152         /* Call ACPI methods: require modeset init
 153          * but failure is not fatal
 154          */
 155         if (!r) {
 156                 acpi_status = amdgpu_acpi_init(adev);
 157                 if (acpi_status)
 158                 dev_dbg(&dev->pdev->dev,
 159                                 "Error during ACPI methods call\n");
 160         }
 161
 162         if (amdgpu_device_is_px(dev)) {
 163                 pm_runtime_use_autosuspend(dev->dev);
 164                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 165                 pm_runtime_set_active(dev->dev);
 166                 pm_runtime_allow(dev->dev);
 167                 pm_runtime_mark_last_busy(dev->dev);
 168                 pm_runtime_put_autosuspend(dev->dev);
 169         }
 170
 171 out:
 172         if (r) {
 173                 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
 174                 if (adev->rmmio && amdgpu_device_is_px(dev))
 175                         pm_runtime_put_noidle(dev->dev);
 176                 amdgpu_driver_unload_kms(dev);
 177         }
 178
 179         return r;
 180 }
 181
 182 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 183                                 struct drm_amdgpu_query_fw *query_fw,
 184                                 struct amdgpu_device *adev)
 185 {
 186         switch (query_fw->fw_type) {
 187         case AMDGPU_INFO_FW_VCE:
 188                 fw_info->ver = adev->vce.fw_version;
 189                 fw_info->feature = adev->vce.fb_version;
 190                 break;
 191         case AMDGPU_INFO_FW_UVD:
 192                 fw_info->ver = adev->uvd.fw_version;
 193                 fw_info->feature = 0;
 194                 break;
 195         case AMDGPU_INFO_FW_VCN:
 196                 fw_info->ver = adev->vcn.fw_version;
 197                 fw_info->feature = 0;
 198                 break;
 199         case AMDGPU_INFO_FW_GMC:
 200                 fw_info->ver = adev->gmc.fw_version;
 201                 fw_info->feature = 0;
 202                 break;
 203         case AMDGPU_INFO_FW_GFX_ME:
 204                 fw_info->ver = adev->gfx.me_fw_version;
 205                 fw_info->feature = adev->gfx.me_feature_version;
 206                 break;
 207         case AMDGPU_INFO_FW_GFX_PFP:
 208                 fw_info->ver = adev->gfx.pfp_fw_version;
 209                 fw_info->feature = adev->gfx.pfp_feature_version;
 210                 break;
 211         case AMDGPU_INFO_FW_GFX_CE:
 212                 fw_info->ver = adev->gfx.ce_fw_version;
 213                 fw_info->feature = adev->gfx.ce_feature_version;
 214                 break;
 215         case AMDGPU_INFO_FW_GFX_RLC:
 216                 fw_info->ver = adev->gfx.rlc_fw_version;
 217                 fw_info->feature = adev->gfx.rlc_feature_version;
 218                 break;
 219         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 220                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 221                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 222                 break;
 223         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 224                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 225                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 226                 break;
 227         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 228                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 229                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 230                 break;
 231         case AMDGPU_INFO_FW_GFX_MEC:
 232                 if (query_fw->index == 0) {
 233                         fw_info->ver = adev->gfx.mec_fw_version;
 234                         fw_info->feature = adev->gfx.mec_feature_version;
 235                 } else if (query_fw->index == 1) {
 236                         fw_info->ver = adev->gfx.mec2_fw_version;
 237                         fw_info->feature = adev->gfx.mec2_feature_version;
 238                 } else
 239                         return -EINVAL;
 240                 break;
 241         case AMDGPU_INFO_FW_SMC:
 242                 fw_info->ver = adev->pm.fw_version;
 243                 fw_info->feature = 0;
 244                 break;
 245         case AMDGPU_INFO_FW_SDMA:
 246                 if (query_fw->index >= adev->sdma.num_instances)
 247                         return -EINVAL;
 248                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 249                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 250                 break;
 251         case AMDGPU_INFO_FW_SOS:
 252                 fw_info->ver = adev->psp.sos_fw_version;
 253                 fw_info->feature = adev->psp.sos_feature_version;
 254                 break;
 255         case AMDGPU_INFO_FW_ASD:
 256                 fw_info->ver = adev->psp.asd_fw_version;
 257                 fw_info->feature = adev->psp.asd_feature_version;
 258                 break;
 259         default:
 260                 return -EINVAL;
 261         }
 262         return 0;
 263 }
 264
 265 /*
 266  * Userspace get information ioctl
 267  */
 268 /**
 269  * amdgpu_info_ioctl - answer a device specific request.
 270  *
 271  * @adev: amdgpu device pointer
 272  * @data: request object
 273  * @filp: drm filp
 274  *
 275  * This function is used to pass device specific parameters to the userspace
 276  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 277  * etc. (all asics).
 278  * Returns 0 on success, -EINVAL on failure.
 279  */
 280 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 281 {
 282         struct amdgpu_device *adev = dev->dev_private;
 283         struct drm_amdgpu_info *info = data;
 284         struct amdgpu_mode_info *minfo = &adev->mode_info;
 285         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 286         uint32_t size = info->return_size;
 287         struct drm_crtc *crtc;
 288         uint32_t ui32 = 0;
 289         uint64_t ui64 = 0;
 290         int i, j, found;
 291         int ui32_size = sizeof(ui32);
 292
 293         if (!info->return_size || !info->return_pointer)
 294                 return -EINVAL;
 295
 296         /* Ensure IB tests are run on ring */
 297         flush_delayed_work(&adev->late_init_work);
 298
 299         switch (info->query) {
 300         case AMDGPU_INFO_ACCEL_WORKING:
 301                 ui32 = adev->accel_working;
 302                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 303         case AMDGPU_INFO_CRTC_FROM_ID:
 304                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 305                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 306                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 307                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 308                                 ui32 = amdgpu_crtc->crtc_id;
 309                                 found = 1;
 310                                 break;
 311                         }
 312                 }
 313                 if (!found) {
 314                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 315                         return -EINVAL;
 316                 }
 317                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 318         case AMDGPU_INFO_HW_IP_INFO: {
 319                 struct drm_amdgpu_info_hw_ip ip = {};
 320                 enum amd_ip_block_type type;
 321                 uint32_t ring_mask = 0;
 322                 uint32_t ib_start_alignment = 0;
 323                 uint32_t ib_size_alignment = 0;
 324
 325                 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 326                         return -EINVAL;
 327
 328                 switch (info->query_hw_ip.type) {
 329                 case AMDGPU_HW_IP_GFX:
 330                         type = AMD_IP_BLOCK_TYPE_GFX;
 331                         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 332                                 ring_mask |= adev->gfx.gfx_ring[i].ready << i;
 333                         ib_start_alignment = 32;
 334                         ib_size_alignment = 32;
 335                         break;
 336                 case AMDGPU_HW_IP_COMPUTE:
 337                         type = AMD_IP_BLOCK_TYPE_GFX;
 338                         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 339                                 ring_mask |= adev->gfx.compute_ring[i].ready << i;
 340                         ib_start_alignment = 32;
 341                         ib_size_alignment = 32;
 342                         break;
 343                 case AMDGPU_HW_IP_DMA:
 344                         type = AMD_IP_BLOCK_TYPE_SDMA;
 345                         for (i = 0; i < adev->sdma.num_instances; i++)
 346                                 ring_mask |= adev->sdma.instance[i].ring.ready << i;
 347                         ib_start_alignment = 256;
 348                         ib_size_alignment = 4;
 349                         break;
 350                 case AMDGPU_HW_IP_UVD:
 351                         type = AMD_IP_BLOCK_TYPE_UVD;
 352                         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 353                                 if (adev->uvd.harvest_config & (1 << i))
 354                                         continue;
 355                                 ring_mask |= adev->uvd.inst[i].ring.ready;
 356                         }
 357                         ib_start_alignment = 64;
 358                         ib_size_alignment = 64;
 359                         break;
 360                 case AMDGPU_HW_IP_VCE:
 361                         type = AMD_IP_BLOCK_TYPE_VCE;
 362                         for (i = 0; i < adev->vce.num_rings; i++)
 363                                 ring_mask |= adev->vce.ring[i].ready << i;
 364                         ib_start_alignment = 4;
 365                         ib_size_alignment = 1;
 366                         break;
 367                 case AMDGPU_HW_IP_UVD_ENC:
 368                         type = AMD_IP_BLOCK_TYPE_UVD;
 369                         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 370                                 if (adev->uvd.harvest_config & (1 << i))
 371                                         continue;
 372                                 for (j = 0; j < adev->uvd.num_enc_rings; j++)
 373                                         ring_mask |= adev->uvd.inst[i].ring_enc[j].ready << j;
 374                         }
 375                         ib_start_alignment = 64;
 376                         ib_size_alignment = 64;
 377                         break;
 378                 case AMDGPU_HW_IP_VCN_DEC:
 379                         type = AMD_IP_BLOCK_TYPE_VCN;
 380                         ring_mask = adev->vcn.ring_dec.ready;
 381                         ib_start_alignment = 16;
 382                         ib_size_alignment = 16;
 383                         break;
 384                 case AMDGPU_HW_IP_VCN_ENC:
 385                         type = AMD_IP_BLOCK_TYPE_VCN;
 386                         for (i = 0; i < adev->vcn.num_enc_rings; i++)
 387                                 ring_mask |= adev->vcn.ring_enc[i].ready << i;
 388                         ib_start_alignment = 64;
 389                         ib_size_alignment = 1;
 390                         break;
 391                 case AMDGPU_HW_IP_VCN_JPEG:
 392                         type = AMD_IP_BLOCK_TYPE_VCN;
 393                         ring_mask = adev->vcn.ring_jpeg.ready;
 394                         ib_start_alignment = 16;
 395                         ib_size_alignment = 16;
 396                         break;
 397                 default:
 398                         return -EINVAL;
 399                 }
 400
 401                 for (i = 0; i < adev->num_ip_blocks; i++) {
 402                         if (adev->ip_blocks[i].version->type == type &&
 403                             adev->ip_blocks[i].status.valid) {
 404                                 ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
 405                                 ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 406                                 ip.capabilities_flags = 0;
 407                                 ip.available_rings = ring_mask;
 408                                 ip.ib_start_alignment = ib_start_alignment;
 409                                 ip.ib_size_alignment = ib_size_alignment;
 410                                 break;
 411                         }
 412                 }
 413                 return copy_to_user(out, &ip,
 414                                     min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
 415         }
 416         case AMDGPU_INFO_HW_IP_COUNT: {
 417                 enum amd_ip_block_type type;
 418                 uint32_t count = 0;
 419
 420                 switch (info->query_hw_ip.type) {
 421                 case AMDGPU_HW_IP_GFX:
 422                         type = AMD_IP_BLOCK_TYPE_GFX;
 423                         break;
 424                 case AMDGPU_HW_IP_COMPUTE:
 425                         type = AMD_IP_BLOCK_TYPE_GFX;
 426                         break;
 427                 case AMDGPU_HW_IP_DMA:
 428                         type = AMD_IP_BLOCK_TYPE_SDMA;
 429                         break;
 430                 case AMDGPU_HW_IP_UVD:
 431                         type = AMD_IP_BLOCK_TYPE_UVD;
 432                         break;
 433                 case AMDGPU_HW_IP_VCE:
 434                         type = AMD_IP_BLOCK_TYPE_VCE;
 435                         break;
 436                 case AMDGPU_HW_IP_UVD_ENC:
 437                         type = AMD_IP_BLOCK_TYPE_UVD;
 438                         break;
 439                 case AMDGPU_HW_IP_VCN_DEC:
 440                 case AMDGPU_HW_IP_VCN_ENC:
 441                 case AMDGPU_HW_IP_VCN_JPEG:
 442                         type = AMD_IP_BLOCK_TYPE_VCN;
 443                         break;
 444                 default:
 445                         return -EINVAL;
 446                 }
 447
 448                 for (i = 0; i < adev->num_ip_blocks; i++)
 449                         if (adev->ip_blocks[i].version->type == type &&
 450                             adev->ip_blocks[i].status.valid &&
 451                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 452                                 count++;
 453
 454                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 455         }
 456         case AMDGPU_INFO_TIMESTAMP:
 457                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 458                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 459         case AMDGPU_INFO_FW_VERSION: {
 460                 struct drm_amdgpu_info_firmware fw_info;
 461                 int ret;
 462
 463                 /* We only support one instance of each IP block right now. */
 464                 if (info->query_fw.ip_instance != 0)
 465                         return -EINVAL;
 466
 467                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 468                 if (ret)
 469                         return ret;
 470
 471                 return copy_to_user(out, &fw_info,
 472                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 473         }
 474         case AMDGPU_INFO_NUM_BYTES_MOVED:
 475                 ui64 = atomic64_read(&adev->num_bytes_moved);
 476                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 477         case AMDGPU_INFO_NUM_EVICTIONS:
 478                 ui64 = atomic64_read(&adev->num_evictions);
 479                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 480         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 481                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 482                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 483         case AMDGPU_INFO_VRAM_USAGE:
 484                 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 485                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 486         case AMDGPU_INFO_VIS_VRAM_USAGE:
 487                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 488                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 489         case AMDGPU_INFO_GTT_USAGE:
 490                 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 491                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 492         case AMDGPU_INFO_GDS_CONFIG: {
 493                 struct drm_amdgpu_info_gds gds_info;
 494
 495                 memset(&gds_info, 0, sizeof(gds_info));
 496                 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
 497                 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
 498                 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
 499                 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
 500                 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
 501                 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
 502                 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
 503                 return copy_to_user(out, &gds_info,
 504                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 505         }
 506         case AMDGPU_INFO_VRAM_GTT: {
 507                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 508
 509                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 510                         atomic64_read(&adev->vram_pin_size);
 511                 vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
 512                         atomic64_read(&adev->visible_pin_size);
 513                 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
 514                 vram_gtt.gtt_size *= PAGE_SIZE;
 515                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 516                 return copy_to_user(out, &vram_gtt,
 517                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 518         }
 519         case AMDGPU_INFO_MEMORY: {
 520                 struct drm_amdgpu_memory_info mem;
 521
 522                 memset(&mem, 0, sizeof(mem));
 523                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 524                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 525                         atomic64_read(&adev->vram_pin_size);
 526                 mem.vram.heap_usage =
 527                         amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 528                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 529
 530                 mem.cpu_accessible_vram.total_heap_size =
 531                         adev->gmc.visible_vram_size;
 532                 mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
 533                         atomic64_read(&adev->visible_pin_size);
 534                 mem.cpu_accessible_vram.heap_usage =
 535                         amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
 536                 mem.cpu_accessible_vram.max_allocation =
 537                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 538
 539                 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
 540                 mem.gtt.total_heap_size *= PAGE_SIZE;
 541                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 542                         atomic64_read(&adev->gart_pin_size);
 543                 mem.gtt.heap_usage =
 544                         amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
 545                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 546
 547                 return copy_to_user(out, &mem,
 548                                     min((size_t)size, sizeof(mem)))
 549                                     ? -EFAULT : 0;
 550         }
 551         case AMDGPU_INFO_READ_MMR_REG: {
 552                 unsigned n, alloc_size;
 553                 uint32_t *regs;
 554                 unsigned se_num = (info->read_mmr_reg.instance >>
 555                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 556                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 557                 unsigned sh_num = (info->read_mmr_reg.instance >>
 558                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 559                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 560
 561                 /* set full masks if the userspace set all bits
 562                  * in the bitfields */
 563                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 564                         se_num = 0xffffffff;
 565                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 566                         sh_num = 0xffffffff;
 567
 568                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 569                 if (!regs)
 570                         return -ENOMEM;
 571                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 572
 573                 for (i = 0; i < info->read_mmr_reg.count; i++)
 574                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 575                                                       info->read_mmr_reg.dword_offset + i,
 576                                                       &regs[i])) {
 577                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 578                                               info->read_mmr_reg.dword_offset + i);
 579                                 kfree(regs);
 580                                 return -EFAULT;
 581                         }
 582                 n = copy_to_user(out, regs, min(size, alloc_size));
 583                 kfree(regs);
 584                 return n ? -EFAULT : 0;
 585         }
 586         case AMDGPU_INFO_DEV_INFO: {
 587                 struct drm_amdgpu_info_device dev_info = {};
 588                 uint64_t vm_size;
 589
 590                 dev_info.device_id = dev->pdev->device;
 591                 dev_info.chip_rev = adev->rev_id;
 592                 dev_info.external_rev = adev->external_rev_id;
 593                 dev_info.pci_rev = dev->pdev->revision;
 594                 dev_info.family = adev->family;
 595                 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
 596                 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 597                 /* return all clocks in KHz */
 598                 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 599                 if (adev->pm.dpm_enabled) {
 600                         dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 601                         dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 602                 } else {
 603                         dev_info.max_engine_clock = adev->clock.default_sclk * 10;
 604                         dev_info.max_memory_clock = adev->clock.default_mclk * 10;
 605                 }
 606                 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 607                 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
 608                         adev->gfx.config.max_shader_engines;
 609                 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 610                 dev_info._pad = 0;
 611                 dev_info.ids_flags = 0;
 612                 if (adev->flags & AMD_IS_APU)
 613                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 614                 if (amdgpu_sriov_vf(adev))
 615                         dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 616
 617                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 618                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 619
 620                 /* Older VCE FW versions are buggy and can handle only 40bits */
 621                 if (adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 622                         vm_size = min(vm_size, 1ULL << 40);
 623
 624                 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 625                 dev_info.virtual_address_max =
 626                         min(vm_size, AMDGPU_VA_HOLE_START);
 627
 628                 if (vm_size > AMDGPU_VA_HOLE_START) {
 629                         dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
 630                         dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;
 631                 }
 632                 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 633                 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 634                 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
 635                 dev_info.cu_active_number = adev->gfx.cu_info.number;
 636                 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 637                 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
 638                 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 639                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 640                 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 641                        sizeof(adev->gfx.cu_info.bitmap));
 642                 dev_info.vram_type = adev->gmc.vram_type;
 643                 dev_info.vram_bit_width = adev->gmc.vram_width;
 644                 dev_info.vce_harvest_config = adev->vce.harvest_config;
 645                 dev_info.gc_double_offchip_lds_buf =
 646                         adev->gfx.config.double_offchip_lds_buf;
 647
 648                 if (amdgpu_ngg) {
 649                         dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
 650                         dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
 651                         dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
 652                         dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
 653                         dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
 654                         dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
 655                         dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
 656                         dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
 657                 }
 658                 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
 659                 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 660                 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 661                 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 662                 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 663                 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 664                 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 665
 666                 return copy_to_user(out, &dev_info,
 667                                     min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
 668         }
 669         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 670                 unsigned i;
 671                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 672                 struct amd_vce_state *vce_state;
 673
 674                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 675                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 676                         if (vce_state) {
 677                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 678                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 679                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 680                                 vce_clk_table.num_valid_entries++;
 681                         }
 682                 }
 683
 684                 return copy_to_user(out, &vce_clk_table,
 685                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 686         }
 687         case AMDGPU_INFO_VBIOS: {
 688                 uint32_t bios_size = adev->bios_size;
 689
 690                 switch (info->vbios_info.type) {
 691                 case AMDGPU_INFO_VBIOS_SIZE:
 692                         return copy_to_user(out, &bios_size,
 693                                         min((size_t)size, sizeof(bios_size)))
 694                                         ? -EFAULT : 0;
 695                 case AMDGPU_INFO_VBIOS_IMAGE: {
 696                         uint8_t *bios;
 697                         uint32_t bios_offset = info->vbios_info.offset;
 698
 699                         if (bios_offset >= bios_size)
 700                                 return -EINVAL;
 701
 702                         bios = adev->bios + bios_offset;
 703                         return copy_to_user(out, bios,
 704                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 705                                         ? -EFAULT : 0;
 706                 }
 707                 default:
 708                         DRM_DEBUG_KMS("Invalid request %d\n",
 709                                         info->vbios_info.type);
 710                         return -EINVAL;
 711                 }
 712         }
 713         case AMDGPU_INFO_NUM_HANDLES: {
 714                 struct drm_amdgpu_info_num_handles handle;
 715
 716                 switch (info->query_hw_ip.type) {
 717                 case AMDGPU_HW_IP_UVD:
 718                         /* Starting Polaris, we support unlimited UVD handles */
 719                         if (adev->asic_type < CHIP_POLARIS10) {
 720                                 handle.uvd_max_handles = adev->uvd.max_handles;
 721                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 722
 723                                 return copy_to_user(out, &handle,
 724                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 725                         } else {
 726                                 return -ENODATA;
 727                         }
 728
 729                         break;
 730                 default:
 731                         return -EINVAL;
 732                 }
 733         }
 734         case AMDGPU_INFO_SENSOR: {
 735                 if (!adev->pm.dpm_enabled)
 736                         return -ENOENT;
 737
 738                 switch (info->sensor_info.type) {
 739                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 740                         /* get sclk in Mhz */
 741                         if (amdgpu_dpm_read_sensor(adev,
 742                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 743                                                    (void *)&ui32, &ui32_size)) {
 744                                 return -EINVAL;
 745                         }
 746                         ui32 /= 100;
 747                         break;
 748                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 749                         /* get mclk in Mhz */
 750                         if (amdgpu_dpm_read_sensor(adev,
 751                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 752                                                    (void *)&ui32, &ui32_size)) {
 753                                 return -EINVAL;
 754                         }
 755                         ui32 /= 100;
 756                         break;
 757                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
 758                         /* get temperature in millidegrees C */
 759                         if (amdgpu_dpm_read_sensor(adev,
 760                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
 761                                                    (void *)&ui32, &ui32_size)) {
 762                                 return -EINVAL;
 763                         }
 764                         break;
 765                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
 766                         /* get GPU load */
 767                         if (amdgpu_dpm_read_sensor(adev,
 768                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
 769                                                    (void *)&ui32, &ui32_size)) {
 770                                 return -EINVAL;
 771                         }
 772                         break;
 773                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
 774                         /* get average GPU power */
 775                         if (amdgpu_dpm_read_sensor(adev,
 776                                                    AMDGPU_PP_SENSOR_GPU_POWER,
 777                                                    (void *)&ui32, &ui32_size)) {
 778                                 return -EINVAL;
 779                         }
 780                         ui32 >>= 8;
 781                         break;
 782                 case AMDGPU_INFO_SENSOR_VDDNB:
 783                         /* get VDDNB in millivolts */
 784                         if (amdgpu_dpm_read_sensor(adev,
 785                                                    AMDGPU_PP_SENSOR_VDDNB,
 786                                                    (void *)&ui32, &ui32_size)) {
 787                                 return -EINVAL;
 788                         }
 789                         break;
 790                 case AMDGPU_INFO_SENSOR_VDDGFX:
 791                         /* get VDDGFX in millivolts */
 792                         if (amdgpu_dpm_read_sensor(adev,
 793                                                    AMDGPU_PP_SENSOR_VDDGFX,
 794                                                    (void *)&ui32, &ui32_size)) {
 795                                 return -EINVAL;
 796                         }
 797                         break;
 798                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
 799                         /* get stable pstate sclk in Mhz */
 800                         if (amdgpu_dpm_read_sensor(adev,
 801                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 802                                                    (void *)&ui32, &ui32_size)) {
 803                                 return -EINVAL;
 804                         }
 805                         ui32 /= 100;
 806                         break;
 807                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
 808                         /* get stable pstate mclk in Mhz */
 809                         if (amdgpu_dpm_read_sensor(adev,
 810                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 811                                                    (void *)&ui32, &ui32_size)) {
 812                                 return -EINVAL;
 813                         }
 814                         ui32 /= 100;
 815                         break;
 816                 default:
 817                         DRM_DEBUG_KMS("Invalid request %d\n",
 818                                       info->sensor_info.type);
 819                         return -EINVAL;
 820                 }
 821                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 822         }
 823         case AMDGPU_INFO_VRAM_LOST_COUNTER:
 824                 ui32 = atomic_read(&adev->vram_lost_counter);
 825                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 826         default:
 827                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
 828                 return -EINVAL;
 829         }
 830         return 0;
 831 }
 832
 833
 834 /*
 835  * Outdated mess for old drm with Xorg being in charge (void function now).
 836  */
 837 /**
 838  * amdgpu_driver_lastclose_kms - drm callback for last close
 839  *
 840  * @dev: drm dev pointer
 841  *
 842  * Switch vga_switcheroo state after last close (all asics).
 843  */
 844 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 845 {
 846         drm_fb_helper_lastclose(dev);
 847         vga_switcheroo_process_delayed_switch();
 848 }
 849
 850 /**
 851  * amdgpu_driver_open_kms - drm callback for open
 852  *
 853  * @dev: drm dev pointer
 854  * @file_priv: drm file
 855  *
 856  * On device open, init vm on cayman+ (all asics).
 857  * Returns 0 on success, error on failure.
 858  */
 859 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 860 {
 861         struct amdgpu_device *adev = dev->dev_private;
 862         struct amdgpu_fpriv *fpriv;
 863         int r, pasid;
 864
 865         file_priv->driver_priv = NULL;
 866
 867         r = pm_runtime_get_sync(dev->dev);
 868         if (r < 0)
 869                 return r;
 870
 871         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 872         if (unlikely(!fpriv)) {
 873                 r = -ENOMEM;
 874                 goto out_suspend;
 875         }
 876
 877         pasid = amdgpu_pasid_alloc(16);
 878         if (pasid < 0) {
 879                 dev_warn(adev->dev, "No more PASIDs available!");
 880                 pasid = 0;
 881         }
 882         r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
 883         if (r)
 884                 goto error_pasid;
 885
 886         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
 887         if (!fpriv->prt_va) {
 888                 r = -ENOMEM;
 889                 goto error_vm;
 890         }
 891
 892         if (amdgpu_sriov_vf(adev)) {
 893                 r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
 894                 if (r)
 895                         goto error_vm;
 896         }
 897
 898         mutex_init(&fpriv->bo_list_lock);
 899         idr_init(&fpriv->bo_list_handles);
 900
 901         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
 902
 903         file_priv->driver_priv = fpriv;
 904         goto out_suspend;
 905
 906 error_vm:
 907         amdgpu_vm_fini(adev, &fpriv->vm);
 908
 909 error_pasid:
 910         if (pasid)
 911                 amdgpu_pasid_free(pasid);
 912
 913         kfree(fpriv);
 914
 915 out_suspend:
 916         pm_runtime_mark_last_busy(dev->dev);
 917         pm_runtime_put_autosuspend(dev->dev);
 918
 919         return r;
 920 }
 921
 922 /**
 923  * amdgpu_driver_postclose_kms - drm callback for post close
 924  *
 925  * @dev: drm dev pointer
 926  * @file_priv: drm file
 927  *
 928  * On device post close, tear down vm on cayman+ (all asics).
 929  */
 930 void amdgpu_driver_postclose_kms(struct drm_device *dev,
 931                                  struct drm_file *file_priv)
 932 {
 933         struct amdgpu_device *adev = dev->dev_private;
 934         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
 935         struct amdgpu_bo_list *list;
 936         struct amdgpu_bo *pd;
 937         unsigned int pasid;
 938         int handle;
 939
 940         if (!fpriv)
 941                 return;
 942
 943         pm_runtime_get_sync(dev->dev);
 944
 945         if (adev->asic_type != CHIP_RAVEN) {
 946                 amdgpu_uvd_free_handles(adev, file_priv);
 947                 amdgpu_vce_free_handles(adev, file_priv);
 948         }
 949
 950         amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
 951
 952         if (amdgpu_sriov_vf(adev)) {
 953                 /* TODO: how to handle reserve failure */
 954                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
 955                 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
 956                 fpriv->csa_va = NULL;
 957                 amdgpu_bo_unreserve(adev->virt.csa_obj);
 958         }
 959
 960         pasid = fpriv->vm.pasid;
 961         pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
 962
 963         amdgpu_vm_fini(adev, &fpriv->vm);
 964         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
 965
 966         if (pasid)
 967                 amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
 968         amdgpu_bo_unref(&pd);
 969
 970         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
 971                 amdgpu_bo_list_put(list);
 972
 973         idr_destroy(&fpriv->bo_list_handles);
 974         mutex_destroy(&fpriv->bo_list_lock);
 975
 976         kfree(fpriv);
 977         file_priv->driver_priv = NULL;
 978
 979         pm_runtime_mark_last_busy(dev->dev);
 980         pm_runtime_put_autosuspend(dev->dev);
 981 }
 982
 983 /*
 984  * VBlank related functions.
 985  */
 986 /**
 987  * amdgpu_get_vblank_counter_kms - get frame count
 988  *
 989  * @dev: drm dev pointer
 990  * @pipe: crtc to get the frame count from
 991  *
 992  * Gets the frame count on the requested crtc (all asics).
 993  * Returns frame count on success, -EINVAL on failure.
 994  */
 995 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
 996 {
 997         struct amdgpu_device *adev = dev->dev_private;
 998         int vpos, hpos, stat;
 999         u32 count;
1000
1001         if (pipe >= adev->mode_info.num_crtc) {
1002                 DRM_ERROR("Invalid crtc %u\n", pipe);
1003                 return -EINVAL;
1004         }
1005
1006         /* The hw increments its frame counter at start of vsync, not at start
1007          * of vblank, as is required by DRM core vblank counter handling.
1008          * Cook the hw count here to make it appear to the caller as if it
1009          * incremented at start of vblank. We measure distance to start of
1010          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1011          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1012          * result by 1 to give the proper appearance to caller.
1013          */
1014         if (adev->mode_info.crtcs[pipe]) {
1015                 /* Repeat readout if needed to provide stable result if
1016                  * we cross start of vsync during the queries.
1017                  */
1018                 do {
1019                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1020                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1021                          * vpos as distance to start of vblank, instead of
1022                          * regular vertical scanout pos.
1023                          */
1024                         stat = amdgpu_display_get_crtc_scanoutpos(
1025                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1026                                 &vpos, &hpos, NULL, NULL,
1027                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1028                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1029
1030                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1031                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1032                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1033                 } else {
1034                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1035                                       pipe, vpos);
1036
1037                         /* Bump counter if we are at >= leading edge of vblank,
1038                          * but before vsync where vpos would turn negative and
1039                          * the hw counter really increments.
1040                          */
1041                         if (vpos >= 0)
1042                                 count++;
1043                 }
1044         } else {
1045                 /* Fallback to use value as is. */
1046                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1047                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1048         }
1049
1050         return count;
1051 }
1052
1053 /**
1054  * amdgpu_enable_vblank_kms - enable vblank interrupt
1055  *
1056  * @dev: drm dev pointer
1057  * @pipe: crtc to enable vblank interrupt for
1058  *
1059  * Enable the interrupt on the requested crtc (all asics).
1060  * Returns 0 on success, -EINVAL on failure.
1061  */
1062 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1063 {
1064         struct amdgpu_device *adev = dev->dev_private;
1065         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1066
1067         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1068 }
1069
1070 /**
1071  * amdgpu_disable_vblank_kms - disable vblank interrupt
1072  *
1073  * @dev: drm dev pointer
1074  * @pipe: crtc to disable vblank interrupt for
1075  *
1076  * Disable the interrupt on the requested crtc (all asics).
1077  */
1078 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1079 {
1080         struct amdgpu_device *adev = dev->dev_private;
1081         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1082
1083         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1084 }
1085
1086 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1087         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1088         DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1089         DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1090         DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1091         DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1092         DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1093         /* KMS */
1094         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1095         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1096         DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1097         DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1098         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1099         DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1100         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1101         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1102         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1103         DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1104 };
1105 const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1106
1107 /*
1108  * Debugfs info
1109  */
1110 #if defined(CONFIG_DEBUG_FS)
1111
1112 static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1113 {
1114         struct drm_info_node *node = (struct drm_info_node *) m->private;
1115         struct drm_device *dev = node->minor->dev;
1116         struct amdgpu_device *adev = dev->dev_private;
1117         struct drm_amdgpu_info_firmware fw_info;
1118         struct drm_amdgpu_query_fw query_fw;
1119         struct atom_context *ctx = adev->mode_info.atom_context;
1120         int ret, i;
1121
1122         /* VCE */
1123         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1124         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1125         if (ret)
1126                 return ret;
1127         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1128                    fw_info.feature, fw_info.ver);
1129
1130         /* UVD */
1131         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1132         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1133         if (ret)
1134                 return ret;
1135         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1136                    fw_info.feature, fw_info.ver);
1137
1138         /* GMC */
1139         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1140         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1141         if (ret)
1142                 return ret;
1143         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1144                    fw_info.feature, fw_info.ver);
1145
1146         /* ME */
1147         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1148         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1149         if (ret)
1150                 return ret;
1151         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1152                    fw_info.feature, fw_info.ver);
1153
1154         /* PFP */
1155         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1156         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1157         if (ret)
1158                 return ret;
1159         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1160                    fw_info.feature, fw_info.ver);
1161
1162         /* CE */
1163         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1164         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1165         if (ret)
1166                 return ret;
1167         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1168                    fw_info.feature, fw_info.ver);
1169
1170         /* RLC */
1171         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1172         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1173         if (ret)
1174                 return ret;
1175         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1176                    fw_info.feature, fw_info.ver);
1177
1178         /* RLC SAVE RESTORE LIST CNTL */
1179         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1180         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1181         if (ret)
1182                 return ret;
1183         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1184                    fw_info.feature, fw_info.ver);
1185
1186         /* RLC SAVE RESTORE LIST GPM MEM */
1187         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1188         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1189         if (ret)
1190                 return ret;
1191         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1192                    fw_info.feature, fw_info.ver);
1193
1194         /* RLC SAVE RESTORE LIST SRM MEM */
1195         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1196         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1197         if (ret)
1198                 return ret;
1199         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1200                    fw_info.feature, fw_info.ver);
1201
1202         /* MEC */
1203         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1204         query_fw.index = 0;
1205         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1206         if (ret)
1207                 return ret;
1208         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1209                    fw_info.feature, fw_info.ver);
1210
1211         /* MEC2 */
1212         if (adev->asic_type == CHIP_KAVERI ||
1213             (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1214                 query_fw.index = 1;
1215                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1216                 if (ret)
1217                         return ret;
1218                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1219                            fw_info.feature, fw_info.ver);
1220         }
1221
1222         /* PSP SOS */
1223         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1224         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1225         if (ret)
1226                 return ret;
1227         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1228                    fw_info.feature, fw_info.ver);
1229
1230
1231         /* PSP ASD */
1232         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1233         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1234         if (ret)
1235                 return ret;
1236         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1237                    fw_info.feature, fw_info.ver);
1238
1239         /* SMC */
1240         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1241         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1242         if (ret)
1243                 return ret;
1244         seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1245                    fw_info.feature, fw_info.ver);
1246
1247         /* SDMA */
1248         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1249         for (i = 0; i < adev->sdma.num_instances; i++) {
1250                 query_fw.index = i;
1251                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1252                 if (ret)
1253                         return ret;
1254                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1255                            i, fw_info.feature, fw_info.ver);
1256         }
1257
1258         /* VCN */
1259         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1260         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1261         if (ret)
1262                 return ret;
1263         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1264                    fw_info.feature, fw_info.ver);
1265
1266
1267         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1268
1269         return 0;
1270 }
1271
1272 static const struct drm_info_list amdgpu_firmware_info_list[] = {
1273         {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1274 };
1275 #endif
1276
1277 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1278 {
1279 #if defined(CONFIG_DEBUG_FS)
1280         return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1281                                         ARRAY_SIZE(amdgpu_firmware_info_list));
1282 #else
1283         return 0;
1284 #endif
1285 }