drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include "amdgpu.h"
  30 #include <drm/amdgpu_drm.h>
  31 #include <drm/drm_drv.h>
  32 #include <drm/drm_fb_helper.h>
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "atom.h"
  36
  37 #include <linux/vga_switcheroo.h>
  38 #include <linux/slab.h>
  39 #include <linux/uaccess.h>
  40 #include <linux/pci.h>
  41 #include <linux/pm_runtime.h>
  42 #include "amdgpu_amdkfd.h"
  43 #include "amdgpu_gem.h"
  44 #include "amdgpu_display.h"
  45 #include "amdgpu_ras.h"
  46 #include "amd_pcie.h"
  47
  48 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
  49 {
  50         struct amdgpu_gpu_instance *gpu_instance;
  51         int i;
  52
  53         mutex_lock(&mgpu_info.mutex);
  54
  55         for (i = 0; i < mgpu_info.num_gpu; i++) {
  56                 gpu_instance = &(mgpu_info.gpu_ins[i]);
  57                 if (gpu_instance->adev == adev) {
  58                         mgpu_info.gpu_ins[i] =
  59                                 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
  60                         mgpu_info.num_gpu--;
  61                         if (adev->flags & AMD_IS_APU)
  62                                 mgpu_info.num_apu--;
  63                         else
  64                                 mgpu_info.num_dgpu--;
  65                         break;
  66                 }
  67         }
  68
  69         mutex_unlock(&mgpu_info.mutex);
  70 }
  71
  72 /**
  73  * amdgpu_driver_unload_kms - Main unload function for KMS.
  74  *
  75  * @dev: drm dev pointer
  76  *
  77  * This is the main unload function for KMS (all asics).
  78  * Returns 0 on success.
  79  */
  80 void amdgpu_driver_unload_kms(struct drm_device *dev)
  81 {
  82         struct amdgpu_device *adev = drm_to_adev(dev);
  83
  84         if (adev == NULL)
  85                 return;
  86
  87         amdgpu_unregister_gpu_instance(adev);
  88
  89         if (adev->rmmio == NULL)
  90                 return;
  91
  92         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
  93                 DRM_WARN("smart shift update failed\n");
  94
  95         amdgpu_acpi_fini(adev);
  96         amdgpu_device_fini_hw(adev);
  97 }
  98
  99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
 100 {
 101         struct amdgpu_gpu_instance *gpu_instance;
 102
 103         mutex_lock(&mgpu_info.mutex);
 104
 105         if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
 106                 DRM_ERROR("Cannot register more gpu instance\n");
 107                 mutex_unlock(&mgpu_info.mutex);
 108                 return;
 109         }
 110
 111         gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
 112         gpu_instance->adev = adev;
 113         gpu_instance->mgpu_fan_enabled = 0;
 114
 115         mgpu_info.num_gpu++;
 116         if (adev->flags & AMD_IS_APU)
 117                 mgpu_info.num_apu++;
 118         else
 119                 mgpu_info.num_dgpu++;
 120
 121         mutex_unlock(&mgpu_info.mutex);
 122 }
 123
 124 /**
 125  * amdgpu_driver_load_kms - Main load function for KMS.
 126  *
 127  * @adev: pointer to struct amdgpu_device
 128  * @flags: device flags
 129  *
 130  * This is the main load function for KMS (all asics).
 131  * Returns 0 on success, error on failure.
 132  */
 133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
 134 {
 135         struct drm_device *dev;
 136         int r, acpi_status;
 137
 138         dev = adev_to_drm(adev);
 139
 140         /* amdgpu_device_init should report only fatal error
 141          * like memory allocation failure or iomapping failure,
 142          * or memory manager initialization failure, it must
 143          * properly initialize the GPU MC controller and permit
 144          * VRAM allocation
 145          */
 146         r = amdgpu_device_init(adev, flags);
 147         if (r) {
 148                 dev_err(dev->dev, "Fatal error during GPU init\n");
 149                 goto out;
 150         }
 151
 152         adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
 153         if (amdgpu_device_supports_px(dev) &&
 154             (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */
 155                 adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
 156                 dev_info(adev->dev, "Using ATPX for runtime pm\n");
 157         } else if (amdgpu_device_supports_boco(dev) &&
 158                    (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */
 159                 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
 160                 dev_info(adev->dev, "Using BOCO for runtime pm\n");
 161         } else if (amdgpu_device_supports_baco(dev) &&
 162                    (amdgpu_runtime_pm != 0)) {
 163                 switch (adev->asic_type) {
 164                 case CHIP_VEGA20:
 165                 case CHIP_ARCTURUS:
 166                         /* enable BACO as runpm mode if runpm=1 */
 167                         if (amdgpu_runtime_pm > 0)
 168                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 169                         break;
 170                 case CHIP_VEGA10:
 171                         /* enable BACO as runpm mode if noretry=0 */
 172                         if (!adev->gmc.noretry)
 173                                 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 174                         break;
 175                 default:
 176                         /* enable BACO as runpm mode on CI+ */
 177                         adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
 178                         break;
 179                 }
 180
 181                 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
 182                         dev_info(adev->dev, "Using BACO for runtime pm\n");
 183         }
 184
 185         /* Call ACPI methods: require modeset init
 186          * but failure is not fatal
 187          */
 188
 189         acpi_status = amdgpu_acpi_init(adev);
 190         if (acpi_status)
 191                 dev_dbg(dev->dev, "Error during ACPI methods call\n");
 192
 193         if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
 194                 DRM_WARN("smart shift update failed\n");
 195
 196 out:
 197         if (r)
 198                 amdgpu_driver_unload_kms(dev);
 199
 200         return r;
 201 }
 202
 203 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
 204                                 struct drm_amdgpu_query_fw *query_fw,
 205                                 struct amdgpu_device *adev)
 206 {
 207         switch (query_fw->fw_type) {
 208         case AMDGPU_INFO_FW_VCE:
 209                 fw_info->ver = adev->vce.fw_version;
 210                 fw_info->feature = adev->vce.fb_version;
 211                 break;
 212         case AMDGPU_INFO_FW_UVD:
 213                 fw_info->ver = adev->uvd.fw_version;
 214                 fw_info->feature = 0;
 215                 break;
 216         case AMDGPU_INFO_FW_VCN:
 217                 fw_info->ver = adev->vcn.fw_version;
 218                 fw_info->feature = 0;
 219                 break;
 220         case AMDGPU_INFO_FW_GMC:
 221                 fw_info->ver = adev->gmc.fw_version;
 222                 fw_info->feature = 0;
 223                 break;
 224         case AMDGPU_INFO_FW_GFX_ME:
 225                 fw_info->ver = adev->gfx.me_fw_version;
 226                 fw_info->feature = adev->gfx.me_feature_version;
 227                 break;
 228         case AMDGPU_INFO_FW_GFX_PFP:
 229                 fw_info->ver = adev->gfx.pfp_fw_version;
 230                 fw_info->feature = adev->gfx.pfp_feature_version;
 231                 break;
 232         case AMDGPU_INFO_FW_GFX_CE:
 233                 fw_info->ver = adev->gfx.ce_fw_version;
 234                 fw_info->feature = adev->gfx.ce_feature_version;
 235                 break;
 236         case AMDGPU_INFO_FW_GFX_RLC:
 237                 fw_info->ver = adev->gfx.rlc_fw_version;
 238                 fw_info->feature = adev->gfx.rlc_feature_version;
 239                 break;
 240         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
 241                 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
 242                 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
 243                 break;
 244         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
 245                 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
 246                 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
 247                 break;
 248         case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
 249                 fw_info->ver = adev->gfx.rlc_srls_fw_version;
 250                 fw_info->feature = adev->gfx.rlc_srls_feature_version;
 251                 break;
 252         case AMDGPU_INFO_FW_GFX_RLCP:
 253                 fw_info->ver = adev->gfx.rlcp_ucode_version;
 254                 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
 255                 break;
 256         case AMDGPU_INFO_FW_GFX_RLCV:
 257                 fw_info->ver = adev->gfx.rlcv_ucode_version;
 258                 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
 259                 break;
 260         case AMDGPU_INFO_FW_GFX_MEC:
 261                 if (query_fw->index == 0) {
 262                         fw_info->ver = adev->gfx.mec_fw_version;
 263                         fw_info->feature = adev->gfx.mec_feature_version;
 264                 } else if (query_fw->index == 1) {
 265                         fw_info->ver = adev->gfx.mec2_fw_version;
 266                         fw_info->feature = adev->gfx.mec2_feature_version;
 267                 } else
 268                         return -EINVAL;
 269                 break;
 270         case AMDGPU_INFO_FW_SMC:
 271                 fw_info->ver = adev->pm.fw_version;
 272                 fw_info->feature = 0;
 273                 break;
 274         case AMDGPU_INFO_FW_TA:
 275                 switch (query_fw->index) {
 276                 case TA_FW_TYPE_PSP_XGMI:
 277                         fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
 278                         fw_info->feature = adev->psp.xgmi_context.context
 279                                                    .bin_desc.feature_version;
 280                         break;
 281                 case TA_FW_TYPE_PSP_RAS:
 282                         fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
 283                         fw_info->feature = adev->psp.ras_context.context
 284                                                    .bin_desc.feature_version;
 285                         break;
 286                 case TA_FW_TYPE_PSP_HDCP:
 287                         fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
 288                         fw_info->feature = adev->psp.hdcp_context.context
 289                                                    .bin_desc.feature_version;
 290                         break;
 291                 case TA_FW_TYPE_PSP_DTM:
 292                         fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
 293                         fw_info->feature = adev->psp.dtm_context.context
 294                                                    .bin_desc.feature_version;
 295                         break;
 296                 case TA_FW_TYPE_PSP_RAP:
 297                         fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
 298                         fw_info->feature = adev->psp.rap_context.context
 299                                                    .bin_desc.feature_version;
 300                         break;
 301                 case TA_FW_TYPE_PSP_SECUREDISPLAY:
 302                         fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
 303                         fw_info->feature =
 304                                 adev->psp.securedisplay_context.context.bin_desc
 305                                         .feature_version;
 306                         break;
 307                 default:
 308                         return -EINVAL;
 309                 }
 310                 break;
 311         case AMDGPU_INFO_FW_SDMA:
 312                 if (query_fw->index >= adev->sdma.num_instances)
 313                         return -EINVAL;
 314                 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
 315                 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
 316                 break;
 317         case AMDGPU_INFO_FW_SOS:
 318                 fw_info->ver = adev->psp.sos.fw_version;
 319                 fw_info->feature = adev->psp.sos.feature_version;
 320                 break;
 321         case AMDGPU_INFO_FW_ASD:
 322                 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
 323                 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
 324                 break;
 325         case AMDGPU_INFO_FW_DMCU:
 326                 fw_info->ver = adev->dm.dmcu_fw_version;
 327                 fw_info->feature = 0;
 328                 break;
 329         case AMDGPU_INFO_FW_DMCUB:
 330                 fw_info->ver = adev->dm.dmcub_fw_version;
 331                 fw_info->feature = 0;
 332                 break;
 333         case AMDGPU_INFO_FW_TOC:
 334                 fw_info->ver = adev->psp.toc.fw_version;
 335                 fw_info->feature = adev->psp.toc.feature_version;
 336                 break;
 337         case AMDGPU_INFO_FW_CAP:
 338                 fw_info->ver = adev->psp.cap_fw_version;
 339                 fw_info->feature = adev->psp.cap_feature_version;
 340                 break;
 341         case AMDGPU_INFO_FW_MES_KIQ:
 342                 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
 343                 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK)
 344                                         >> AMDGPU_MES_FEAT_VERSION_SHIFT;
 345                 break;
 346         case AMDGPU_INFO_FW_MES:
 347                 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
 348                 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK)
 349                                         >> AMDGPU_MES_FEAT_VERSION_SHIFT;
 350                 break;
 351         case AMDGPU_INFO_FW_IMU:
 352                 fw_info->ver = adev->gfx.imu_fw_version;
 353                 fw_info->feature = 0;
 354                 break;
 355         default:
 356                 return -EINVAL;
 357         }
 358         return 0;
 359 }
 360
 361 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
 362                              struct drm_amdgpu_info *info,
 363                              struct drm_amdgpu_info_hw_ip *result)
 364 {
 365         uint32_t ib_start_alignment = 0;
 366         uint32_t ib_size_alignment = 0;
 367         enum amd_ip_block_type type;
 368         unsigned int num_rings = 0;
 369         unsigned int i, j;
 370
 371         if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 372                 return -EINVAL;
 373
 374         switch (info->query_hw_ip.type) {
 375         case AMDGPU_HW_IP_GFX:
 376                 type = AMD_IP_BLOCK_TYPE_GFX;
 377                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 378                         if (adev->gfx.gfx_ring[i].sched.ready)
 379                                 ++num_rings;
 380                 ib_start_alignment = 32;
 381                 ib_size_alignment = 32;
 382                 break;
 383         case AMDGPU_HW_IP_COMPUTE:
 384                 type = AMD_IP_BLOCK_TYPE_GFX;
 385                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
 386                         if (adev->gfx.compute_ring[i].sched.ready)
 387                                 ++num_rings;
 388                 ib_start_alignment = 32;
 389                 ib_size_alignment = 32;
 390                 break;
 391         case AMDGPU_HW_IP_DMA:
 392                 type = AMD_IP_BLOCK_TYPE_SDMA;
 393                 for (i = 0; i < adev->sdma.num_instances; i++)
 394                         if (adev->sdma.instance[i].ring.sched.ready)
 395                                 ++num_rings;
 396                 ib_start_alignment = 256;
 397                 ib_size_alignment = 4;
 398                 break;
 399         case AMDGPU_HW_IP_UVD:
 400                 type = AMD_IP_BLOCK_TYPE_UVD;
 401                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 402                         if (adev->uvd.harvest_config & (1 << i))
 403                                 continue;
 404
 405                         if (adev->uvd.inst[i].ring.sched.ready)
 406                                 ++num_rings;
 407                 }
 408                 ib_start_alignment = 64;
 409                 ib_size_alignment = 64;
 410                 break;
 411         case AMDGPU_HW_IP_VCE:
 412                 type = AMD_IP_BLOCK_TYPE_VCE;
 413                 for (i = 0; i < adev->vce.num_rings; i++)
 414                         if (adev->vce.ring[i].sched.ready)
 415                                 ++num_rings;
 416                 ib_start_alignment = 4;
 417                 ib_size_alignment = 1;
 418                 break;
 419         case AMDGPU_HW_IP_UVD_ENC:
 420                 type = AMD_IP_BLOCK_TYPE_UVD;
 421                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 422                         if (adev->uvd.harvest_config & (1 << i))
 423                                 continue;
 424
 425                         for (j = 0; j < adev->uvd.num_enc_rings; j++)
 426                                 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
 427                                         ++num_rings;
 428                 }
 429                 ib_start_alignment = 64;
 430                 ib_size_alignment = 64;
 431                 break;
 432         case AMDGPU_HW_IP_VCN_DEC:
 433                 type = AMD_IP_BLOCK_TYPE_VCN;
 434                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 435                         if (adev->vcn.harvest_config & (1 << i))
 436                                 continue;
 437
 438                         if (adev->vcn.inst[i].ring_dec.sched.ready)
 439                                 ++num_rings;
 440                 }
 441                 ib_start_alignment = 16;
 442                 ib_size_alignment = 16;
 443                 break;
 444         case AMDGPU_HW_IP_VCN_ENC:
 445                 type = AMD_IP_BLOCK_TYPE_VCN;
 446                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 447                         if (adev->vcn.harvest_config & (1 << i))
 448                                 continue;
 449
 450                         for (j = 0; j < adev->vcn.num_enc_rings; j++)
 451                                 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
 452                                         ++num_rings;
 453                 }
 454                 ib_start_alignment = 64;
 455                 ib_size_alignment = 1;
 456                 break;
 457         case AMDGPU_HW_IP_VCN_JPEG:
 458                 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 459                         AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 460
 461                 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
 462                         if (adev->jpeg.harvest_config & (1 << i))
 463                                 continue;
 464
 465                         if (adev->jpeg.inst[i].ring_dec.sched.ready)
 466                                 ++num_rings;
 467                 }
 468                 ib_start_alignment = 16;
 469                 ib_size_alignment = 16;
 470                 break;
 471         default:
 472                 return -EINVAL;
 473         }
 474
 475         for (i = 0; i < adev->num_ip_blocks; i++)
 476                 if (adev->ip_blocks[i].version->type == type &&
 477                     adev->ip_blocks[i].status.valid)
 478                         break;
 479
 480         if (i == adev->num_ip_blocks)
 481                 return 0;
 482
 483         num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
 484                         num_rings);
 485
 486         result->hw_ip_version_major = adev->ip_blocks[i].version->major;
 487         result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
 488
 489         if (adev->asic_type >= CHIP_VEGA10) {
 490                 switch (type) {
 491                 case AMD_IP_BLOCK_TYPE_GFX:
 492                         result->ip_discovery_version = adev->ip_versions[GC_HWIP][0];
 493                         break;
 494                 case AMD_IP_BLOCK_TYPE_SDMA:
 495                         result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0];
 496                         break;
 497                 case AMD_IP_BLOCK_TYPE_UVD:
 498                 case AMD_IP_BLOCK_TYPE_VCN:
 499                 case AMD_IP_BLOCK_TYPE_JPEG:
 500                         result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0];
 501                         break;
 502                 case AMD_IP_BLOCK_TYPE_VCE:
 503                         result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0];
 504                         break;
 505                 default:
 506                         result->ip_discovery_version = 0;
 507                         break;
 508                 }
 509         } else {
 510                 result->ip_discovery_version = 0;
 511         }
 512         result->capabilities_flags = 0;
 513         result->available_rings = (1 << num_rings) - 1;
 514         result->ib_start_alignment = ib_start_alignment;
 515         result->ib_size_alignment = ib_size_alignment;
 516         return 0;
 517 }
 518
 519 /*
 520  * Userspace get information ioctl
 521  */
 522 /**
 523  * amdgpu_info_ioctl - answer a device specific request.
 524  *
 525  * @dev: drm device pointer
 526  * @data: request object
 527  * @filp: drm filp
 528  *
 529  * This function is used to pass device specific parameters to the userspace
 530  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 531  * etc. (all asics).
 532  * Returns 0 on success, -EINVAL on failure.
 533  */
 534 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 535 {
 536         struct amdgpu_device *adev = drm_to_adev(dev);
 537         struct drm_amdgpu_info *info = data;
 538         struct amdgpu_mode_info *minfo = &adev->mode_info;
 539         void __user *out = (void __user *)(uintptr_t)info->return_pointer;
 540         uint32_t size = info->return_size;
 541         struct drm_crtc *crtc;
 542         uint32_t ui32 = 0;
 543         uint64_t ui64 = 0;
 544         int i, found;
 545         int ui32_size = sizeof(ui32);
 546
 547         if (!info->return_size || !info->return_pointer)
 548                 return -EINVAL;
 549
 550         switch (info->query) {
 551         case AMDGPU_INFO_ACCEL_WORKING:
 552                 ui32 = adev->accel_working;
 553                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 554         case AMDGPU_INFO_CRTC_FROM_ID:
 555                 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
 556                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 557                         if (crtc && crtc->base.id == info->mode_crtc.id) {
 558                                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 559                                 ui32 = amdgpu_crtc->crtc_id;
 560                                 found = 1;
 561                                 break;
 562                         }
 563                 }
 564                 if (!found) {
 565                         DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
 566                         return -EINVAL;
 567                 }
 568                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
 569         case AMDGPU_INFO_HW_IP_INFO: {
 570                 struct drm_amdgpu_info_hw_ip ip = {};
 571                 int ret;
 572
 573                 ret = amdgpu_hw_ip_info(adev, info, &ip);
 574                 if (ret)
 575                         return ret;
 576
 577                 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
 578                 return ret ? -EFAULT : 0;
 579         }
 580         case AMDGPU_INFO_HW_IP_COUNT: {
 581                 enum amd_ip_block_type type;
 582                 uint32_t count = 0;
 583
 584                 switch (info->query_hw_ip.type) {
 585                 case AMDGPU_HW_IP_GFX:
 586                         type = AMD_IP_BLOCK_TYPE_GFX;
 587                         break;
 588                 case AMDGPU_HW_IP_COMPUTE:
 589                         type = AMD_IP_BLOCK_TYPE_GFX;
 590                         break;
 591                 case AMDGPU_HW_IP_DMA:
 592                         type = AMD_IP_BLOCK_TYPE_SDMA;
 593                         break;
 594                 case AMDGPU_HW_IP_UVD:
 595                         type = AMD_IP_BLOCK_TYPE_UVD;
 596                         break;
 597                 case AMDGPU_HW_IP_VCE:
 598                         type = AMD_IP_BLOCK_TYPE_VCE;
 599                         break;
 600                 case AMDGPU_HW_IP_UVD_ENC:
 601                         type = AMD_IP_BLOCK_TYPE_UVD;
 602                         break;
 603                 case AMDGPU_HW_IP_VCN_DEC:
 604                 case AMDGPU_HW_IP_VCN_ENC:
 605                         type = AMD_IP_BLOCK_TYPE_VCN;
 606                         break;
 607                 case AMDGPU_HW_IP_VCN_JPEG:
 608                         type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
 609                                 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
 610                         break;
 611                 default:
 612                         return -EINVAL;
 613                 }
 614
 615                 for (i = 0; i < adev->num_ip_blocks; i++)
 616                         if (adev->ip_blocks[i].version->type == type &&
 617                             adev->ip_blocks[i].status.valid &&
 618                             count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
 619                                 count++;
 620
 621                 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
 622         }
 623         case AMDGPU_INFO_TIMESTAMP:
 624                 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
 625                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 626         case AMDGPU_INFO_FW_VERSION: {
 627                 struct drm_amdgpu_info_firmware fw_info;
 628                 int ret;
 629
 630                 /* We only support one instance of each IP block right now. */
 631                 if (info->query_fw.ip_instance != 0)
 632                         return -EINVAL;
 633
 634                 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
 635                 if (ret)
 636                         return ret;
 637
 638                 return copy_to_user(out, &fw_info,
 639                                     min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
 640         }
 641         case AMDGPU_INFO_NUM_BYTES_MOVED:
 642                 ui64 = atomic64_read(&adev->num_bytes_moved);
 643                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 644         case AMDGPU_INFO_NUM_EVICTIONS:
 645                 ui64 = atomic64_read(&adev->num_evictions);
 646                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 647         case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
 648                 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
 649                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 650         case AMDGPU_INFO_VRAM_USAGE:
 651                 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 652                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 653         case AMDGPU_INFO_VIS_VRAM_USAGE:
 654                 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 655                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 656         case AMDGPU_INFO_GTT_USAGE:
 657                 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
 658                 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
 659         case AMDGPU_INFO_GDS_CONFIG: {
 660                 struct drm_amdgpu_info_gds gds_info;
 661
 662                 memset(&gds_info, 0, sizeof(gds_info));
 663                 gds_info.compute_partition_size = adev->gds.gds_size;
 664                 gds_info.gds_total_size = adev->gds.gds_size;
 665                 gds_info.gws_per_compute_partition = adev->gds.gws_size;
 666                 gds_info.oa_per_compute_partition = adev->gds.oa_size;
 667                 return copy_to_user(out, &gds_info,
 668                                     min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
 669         }
 670         case AMDGPU_INFO_VRAM_GTT: {
 671                 struct drm_amdgpu_info_vram_gtt vram_gtt;
 672
 673                 vram_gtt.vram_size = adev->gmc.real_vram_size -
 674                         atomic64_read(&adev->vram_pin_size) -
 675                         AMDGPU_VM_RESERVED_VRAM;
 676                 vram_gtt.vram_cpu_accessible_size =
 677                         min(adev->gmc.visible_vram_size -
 678                             atomic64_read(&adev->visible_pin_size),
 679                             vram_gtt.vram_size);
 680                 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
 681                 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
 682                 return copy_to_user(out, &vram_gtt,
 683                                     min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
 684         }
 685         case AMDGPU_INFO_MEMORY: {
 686                 struct drm_amdgpu_memory_info mem;
 687                 struct ttm_resource_manager *gtt_man =
 688                         &adev->mman.gtt_mgr.manager;
 689                 struct ttm_resource_manager *vram_man =
 690                         &adev->mman.vram_mgr.manager;
 691
 692                 memset(&mem, 0, sizeof(mem));
 693                 mem.vram.total_heap_size = adev->gmc.real_vram_size;
 694                 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
 695                         atomic64_read(&adev->vram_pin_size) -
 696                         AMDGPU_VM_RESERVED_VRAM;
 697                 mem.vram.heap_usage =
 698                         ttm_resource_manager_usage(vram_man);
 699                 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
 700
 701                 mem.cpu_accessible_vram.total_heap_size =
 702                         adev->gmc.visible_vram_size;
 703                 mem.cpu_accessible_vram.usable_heap_size =
 704                         min(adev->gmc.visible_vram_size -
 705                             atomic64_read(&adev->visible_pin_size),
 706                             mem.vram.usable_heap_size);
 707                 mem.cpu_accessible_vram.heap_usage =
 708                         amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 709                 mem.cpu_accessible_vram.max_allocation =
 710                         mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
 711
 712                 mem.gtt.total_heap_size = gtt_man->size;
 713                 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
 714                         atomic64_read(&adev->gart_pin_size);
 715                 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
 716                 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
 717
 718                 return copy_to_user(out, &mem,
 719                                     min((size_t)size, sizeof(mem)))
 720                                     ? -EFAULT : 0;
 721         }
 722         case AMDGPU_INFO_READ_MMR_REG: {
 723                 unsigned n, alloc_size;
 724                 uint32_t *regs;
 725                 unsigned se_num = (info->read_mmr_reg.instance >>
 726                                    AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 727                                   AMDGPU_INFO_MMR_SE_INDEX_MASK;
 728                 unsigned sh_num = (info->read_mmr_reg.instance >>
 729                                    AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 730                                   AMDGPU_INFO_MMR_SH_INDEX_MASK;
 731
 732                 /* set full masks if the userspace set all bits
 733                  * in the bitfields */
 734                 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 735                         se_num = 0xffffffff;
 736                 else if (se_num >= AMDGPU_GFX_MAX_SE)
 737                         return -EINVAL;
 738                 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 739                         sh_num = 0xffffffff;
 740                 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
 741                         return -EINVAL;
 742
 743                 if (info->read_mmr_reg.count > 128)
 744                         return -EINVAL;
 745
 746                 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
 747                 if (!regs)
 748                         return -ENOMEM;
 749                 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
 750
 751                 amdgpu_gfx_off_ctrl(adev, false);
 752                 for (i = 0; i < info->read_mmr_reg.count; i++) {
 753                         if (amdgpu_asic_read_register(adev, se_num, sh_num,
 754                                                       info->read_mmr_reg.dword_offset + i,
 755                                                       &regs[i])) {
 756                                 DRM_DEBUG_KMS("unallowed offset %#x\n",
 757                                               info->read_mmr_reg.dword_offset + i);
 758                                 kfree(regs);
 759                                 amdgpu_gfx_off_ctrl(adev, true);
 760                                 return -EFAULT;
 761                         }
 762                 }
 763                 amdgpu_gfx_off_ctrl(adev, true);
 764                 n = copy_to_user(out, regs, min(size, alloc_size));
 765                 kfree(regs);
 766                 return n ? -EFAULT : 0;
 767         }
 768         case AMDGPU_INFO_DEV_INFO: {
 769                 struct drm_amdgpu_info_device *dev_info;
 770                 uint64_t vm_size;
 771                 uint32_t pcie_gen_mask;
 772                 int ret;
 773
 774                 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
 775                 if (!dev_info)
 776                         return -ENOMEM;
 777
 778                 dev_info->device_id = adev->pdev->device;
 779                 dev_info->chip_rev = adev->rev_id;
 780                 dev_info->external_rev = adev->external_rev_id;
 781                 dev_info->pci_rev = adev->pdev->revision;
 782                 dev_info->family = adev->family;
 783                 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
 784                 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
 785                 /* return all clocks in KHz */
 786                 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
 787                 if (adev->pm.dpm_enabled) {
 788                         dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
 789                         dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
 790                         dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;
 791                         dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;
 792                 } else {
 793                         dev_info->max_engine_clock =
 794                                 dev_info->min_engine_clock =
 795                                         adev->clock.default_sclk * 10;
 796                         dev_info->max_memory_clock =
 797                                 dev_info->min_memory_clock =
 798                                         adev->clock.default_mclk * 10;
 799                 }
 800                 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
 801                 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
 802                         adev->gfx.config.max_shader_engines;
 803                 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
 804                 dev_info->ids_flags = 0;
 805                 if (adev->flags & AMD_IS_APU)
 806                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
 807                 if (amdgpu_mcbp)
 808                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
 809                 if (amdgpu_is_tmz(adev))
 810                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
 811                 if (adev->gfx.config.ta_cntl2_truncate_coord_mode)
 812                         dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;
 813
 814                 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
 815                 vm_size -= AMDGPU_VA_RESERVED_SIZE;
 816
 817                 /* Older VCE FW versions are buggy and can handle only 40bits */
 818                 if (adev->vce.fw_version &&
 819                     adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
 820                         vm_size = min(vm_size, 1ULL << 40);
 821
 822                 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 823                 dev_info->virtual_address_max =
 824                         min(vm_size, AMDGPU_GMC_HOLE_START);
 825
 826                 if (vm_size > AMDGPU_GMC_HOLE_START) {
 827                         dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
 828                         dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 829                 }
 830                 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 831                 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
 832                 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 833                 dev_info->cu_active_number = adev->gfx.cu_info.number;
 834                 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
 835                 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
 836                 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
 837                        sizeof(adev->gfx.cu_info.ao_cu_bitmap));
 838                 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
 839                        sizeof(adev->gfx.cu_info.bitmap));
 840                 dev_info->vram_type = adev->gmc.vram_type;
 841                 dev_info->vram_bit_width = adev->gmc.vram_width;
 842                 dev_info->vce_harvest_config = adev->vce.harvest_config;
 843                 dev_info->gc_double_offchip_lds_buf =
 844                         adev->gfx.config.double_offchip_lds_buf;
 845                 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
 846                 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
 847                 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
 848                 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
 849                 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
 850                 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
 851                 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
 852
 853                 if (adev->family >= AMDGPU_FAMILY_NV)
 854                         dev_info->pa_sc_tile_steering_override =
 855                                 adev->gfx.config.pa_sc_tile_steering_override;
 856
 857                 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
 858
 859                 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */
 860                 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16);
 861                 dev_info->pcie_gen = fls(pcie_gen_mask);
 862                 dev_info->pcie_num_lanes =
 863                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :
 864                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
 865                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :
 866                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :
 867                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
 868                         adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
 869
 870                 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
 871                 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;
 872                 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
 873                 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
 874                 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *
 875                                             adev->gfx.config.gc_gl1c_per_sa;
 876                 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
 877                 dev_info->mall_size = adev->gmc.mall_size;
 878
 879
 880                 if (adev->gfx.funcs->get_gfx_shadow_info) {
 881                         struct amdgpu_gfx_shadow_info shadow_info;
 882
 883                         ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info);
 884                         if (!ret) {
 885                                 dev_info->shadow_size = shadow_info.shadow_size;
 886                                 dev_info->shadow_alignment = shadow_info.shadow_alignment;
 887                                 dev_info->csa_size = shadow_info.csa_size;
 888                                 dev_info->csa_alignment = shadow_info.csa_alignment;
 889                         }
 890                 }
 891
 892                 ret = copy_to_user(out, dev_info,
 893                                    min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
 894                 kfree(dev_info);
 895                 return ret;
 896         }
 897         case AMDGPU_INFO_VCE_CLOCK_TABLE: {
 898                 unsigned i;
 899                 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
 900                 struct amd_vce_state *vce_state;
 901
 902                 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
 903                         vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
 904                         if (vce_state) {
 905                                 vce_clk_table.entries[i].sclk = vce_state->sclk;
 906                                 vce_clk_table.entries[i].mclk = vce_state->mclk;
 907                                 vce_clk_table.entries[i].eclk = vce_state->evclk;
 908                                 vce_clk_table.num_valid_entries++;
 909                         }
 910                 }
 911
 912                 return copy_to_user(out, &vce_clk_table,
 913                                     min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
 914         }
 915         case AMDGPU_INFO_VBIOS: {
 916                 uint32_t bios_size = adev->bios_size;
 917
 918                 switch (info->vbios_info.type) {
 919                 case AMDGPU_INFO_VBIOS_SIZE:
 920                         return copy_to_user(out, &bios_size,
 921                                         min((size_t)size, sizeof(bios_size)))
 922                                         ? -EFAULT : 0;
 923                 case AMDGPU_INFO_VBIOS_IMAGE: {
 924                         uint8_t *bios;
 925                         uint32_t bios_offset = info->vbios_info.offset;
 926
 927                         if (bios_offset >= bios_size)
 928                                 return -EINVAL;
 929
 930                         bios = adev->bios + bios_offset;
 931                         return copy_to_user(out, bios,
 932                                             min((size_t)size, (size_t)(bios_size - bios_offset)))
 933                                         ? -EFAULT : 0;
 934                 }
 935                 case AMDGPU_INFO_VBIOS_INFO: {
 936                         struct drm_amdgpu_info_vbios vbios_info = {};
 937                         struct atom_context *atom_context;
 938
 939                         atom_context = adev->mode_info.atom_context;
 940                         memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
 941                         memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
 942                         vbios_info.version = atom_context->version;
 943                         memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
 944                                                 sizeof(atom_context->vbios_ver_str));
 945                         memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
 946
 947                         return copy_to_user(out, &vbios_info,
 948                                                 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
 949                 }
 950                 default:
 951                         DRM_DEBUG_KMS("Invalid request %d\n",
 952                                         info->vbios_info.type);
 953                         return -EINVAL;
 954                 }
 955         }
 956         case AMDGPU_INFO_NUM_HANDLES: {
 957                 struct drm_amdgpu_info_num_handles handle;
 958
 959                 switch (info->query_hw_ip.type) {
 960                 case AMDGPU_HW_IP_UVD:
 961                         /* Starting Polaris, we support unlimited UVD handles */
 962                         if (adev->asic_type < CHIP_POLARIS10) {
 963                                 handle.uvd_max_handles = adev->uvd.max_handles;
 964                                 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
 965
 966                                 return copy_to_user(out, &handle,
 967                                         min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
 968                         } else {
 969                                 return -ENODATA;
 970                         }
 971
 972                         break;
 973                 default:
 974                         return -EINVAL;
 975                 }
 976         }
 977         case AMDGPU_INFO_SENSOR: {
 978                 if (!adev->pm.dpm_enabled)
 979                         return -ENOENT;
 980
 981                 switch (info->sensor_info.type) {
 982                 case AMDGPU_INFO_SENSOR_GFX_SCLK:
 983                         /* get sclk in Mhz */
 984                         if (amdgpu_dpm_read_sensor(adev,
 985                                                    AMDGPU_PP_SENSOR_GFX_SCLK,
 986                                                    (void *)&ui32, &ui32_size)) {
 987                                 return -EINVAL;
 988                         }
 989                         ui32 /= 100;
 990                         break;
 991                 case AMDGPU_INFO_SENSOR_GFX_MCLK:
 992                         /* get mclk in Mhz */
 993                         if (amdgpu_dpm_read_sensor(adev,
 994                                                    AMDGPU_PP_SENSOR_GFX_MCLK,
 995                                                    (void *)&ui32, &ui32_size)) {
 996                                 return -EINVAL;
 997                         }
 998                         ui32 /= 100;
 999                         break;
1000                 case AMDGPU_INFO_SENSOR_GPU_TEMP:
1001                         /* get temperature in millidegrees C */
1002                         if (amdgpu_dpm_read_sensor(adev,
1003                                                    AMDGPU_PP_SENSOR_GPU_TEMP,
1004                                                    (void *)&ui32, &ui32_size)) {
1005                                 return -EINVAL;
1006                         }
1007                         break;
1008                 case AMDGPU_INFO_SENSOR_GPU_LOAD:
1009                         /* get GPU load */
1010                         if (amdgpu_dpm_read_sensor(adev,
1011                                                    AMDGPU_PP_SENSOR_GPU_LOAD,
1012                                                    (void *)&ui32, &ui32_size)) {
1013                                 return -EINVAL;
1014                         }
1015                         break;
1016                 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
1017                         /* get average GPU power */
1018                         if (amdgpu_dpm_read_sensor(adev,
1019                                                    AMDGPU_PP_SENSOR_GPU_POWER,
1020                                                    (void *)&ui32, &ui32_size)) {
1021                                 return -EINVAL;
1022                         }
1023                         ui32 >>= 8;
1024                         break;
1025                 case AMDGPU_INFO_SENSOR_VDDNB:
1026                         /* get VDDNB in millivolts */
1027                         if (amdgpu_dpm_read_sensor(adev,
1028                                                    AMDGPU_PP_SENSOR_VDDNB,
1029                                                    (void *)&ui32, &ui32_size)) {
1030                                 return -EINVAL;
1031                         }
1032                         break;
1033                 case AMDGPU_INFO_SENSOR_VDDGFX:
1034                         /* get VDDGFX in millivolts */
1035                         if (amdgpu_dpm_read_sensor(adev,
1036                                                    AMDGPU_PP_SENSOR_VDDGFX,
1037                                                    (void *)&ui32, &ui32_size)) {
1038                                 return -EINVAL;
1039                         }
1040                         break;
1041                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1042                         /* get stable pstate sclk in Mhz */
1043                         if (amdgpu_dpm_read_sensor(adev,
1044                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1045                                                    (void *)&ui32, &ui32_size)) {
1046                                 return -EINVAL;
1047                         }
1048                         ui32 /= 100;
1049                         break;
1050                 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1051                         /* get stable pstate mclk in Mhz */
1052                         if (amdgpu_dpm_read_sensor(adev,
1053                                                    AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1054                                                    (void *)&ui32, &ui32_size)) {
1055                                 return -EINVAL;
1056                         }
1057                         ui32 /= 100;
1058                         break;
1059                 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
1060                         /* get peak pstate sclk in Mhz */
1061                         if (amdgpu_dpm_read_sensor(adev,
1062                                                    AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
1063                                                    (void *)&ui32, &ui32_size)) {
1064                                 return -EINVAL;
1065                         }
1066                         ui32 /= 100;
1067                         break;
1068                 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
1069                         /* get peak pstate mclk in Mhz */
1070                         if (amdgpu_dpm_read_sensor(adev,
1071                                                    AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
1072                                                    (void *)&ui32, &ui32_size)) {
1073                                 return -EINVAL;
1074                         }
1075                         ui32 /= 100;
1076                         break;
1077                 default:
1078                         DRM_DEBUG_KMS("Invalid request %d\n",
1079                                       info->sensor_info.type);
1080                         return -EINVAL;
1081                 }
1082                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1083         }
1084         case AMDGPU_INFO_VRAM_LOST_COUNTER:
1085                 ui32 = atomic_read(&adev->vram_lost_counter);
1086                 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1087         case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1088                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1089                 uint64_t ras_mask;
1090
1091                 if (!ras)
1092                         return -EINVAL;
1093                 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1094
1095                 return copy_to_user(out, &ras_mask,
1096                                 min_t(u64, size, sizeof(ras_mask))) ?
1097                         -EFAULT : 0;
1098         }
1099         case AMDGPU_INFO_VIDEO_CAPS: {
1100                 const struct amdgpu_video_codecs *codecs;
1101                 struct drm_amdgpu_info_video_caps *caps;
1102                 int r;
1103
1104                 switch (info->video_cap.type) {
1105                 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1106                         r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1107                         if (r)
1108                                 return -EINVAL;
1109                         break;
1110                 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1111                         r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1112                         if (r)
1113                                 return -EINVAL;
1114                         break;
1115                 default:
1116                         DRM_DEBUG_KMS("Invalid request %d\n",
1117                                       info->video_cap.type);
1118                         return -EINVAL;
1119                 }
1120
1121                 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1122                 if (!caps)
1123                         return -ENOMEM;
1124
1125                 for (i = 0; i < codecs->codec_count; i++) {
1126                         int idx = codecs->codec_array[i].codec_type;
1127
1128                         switch (idx) {
1129                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1130                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1131                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1132                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1133                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1134                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1135                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1136                         case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1137                                 caps->codec_info[idx].valid = 1;
1138                                 caps->codec_info[idx].max_width =
1139                                         codecs->codec_array[i].max_width;
1140                                 caps->codec_info[idx].max_height =
1141                                         codecs->codec_array[i].max_height;
1142                                 caps->codec_info[idx].max_pixels_per_frame =
1143                                         codecs->codec_array[i].max_pixels_per_frame;
1144                                 caps->codec_info[idx].max_level =
1145                                         codecs->codec_array[i].max_level;
1146                                 break;
1147                         default:
1148                                 break;
1149                         }
1150                 }
1151                 r = copy_to_user(out, caps,
1152                                  min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1153                 kfree(caps);
1154                 return r;
1155         }
1156         case AMDGPU_INFO_MAX_IBS: {
1157                 uint32_t max_ibs[AMDGPU_HW_IP_NUM];
1158
1159                 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
1160                         max_ibs[i] = amdgpu_ring_max_ibs(i);
1161
1162                 return copy_to_user(out, max_ibs,
1163                                     min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0;
1164         }
1165         default:
1166                 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1167                 return -EINVAL;
1168         }
1169         return 0;
1170 }
1171
1172
1173 /*
1174  * Outdated mess for old drm with Xorg being in charge (void function now).
1175  */
1176 /**
1177  * amdgpu_driver_lastclose_kms - drm callback for last close
1178  *
1179  * @dev: drm dev pointer
1180  *
1181  * Switch vga_switcheroo state after last close (all asics).
1182  */
1183 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1184 {
1185         drm_fb_helper_lastclose(dev);
1186         vga_switcheroo_process_delayed_switch();
1187 }
1188
1189 /**
1190  * amdgpu_driver_open_kms - drm callback for open
1191  *
1192  * @dev: drm dev pointer
1193  * @file_priv: drm file
1194  *
1195  * On device open, init vm on cayman+ (all asics).
1196  * Returns 0 on success, error on failure.
1197  */
1198 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1199 {
1200         struct amdgpu_device *adev = drm_to_adev(dev);
1201         struct amdgpu_fpriv *fpriv;
1202         int r, pasid;
1203
1204         /* Ensure IB tests are run on ring */
1205         flush_delayed_work(&adev->delayed_init_work);
1206
1207
1208         if (amdgpu_ras_intr_triggered()) {
1209                 DRM_ERROR("RAS Intr triggered, device disabled!!");
1210                 return -EHWPOISON;
1211         }
1212
1213         file_priv->driver_priv = NULL;
1214
1215         r = pm_runtime_get_sync(dev->dev);
1216         if (r < 0)
1217                 goto pm_put;
1218
1219         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1220         if (unlikely(!fpriv)) {
1221                 r = -ENOMEM;
1222                 goto out_suspend;
1223         }
1224
1225         pasid = amdgpu_pasid_alloc(16);
1226         if (pasid < 0) {
1227                 dev_warn(adev->dev, "No more PASIDs available!");
1228                 pasid = 0;
1229         }
1230
1231         r = amdgpu_vm_init(adev, &fpriv->vm);
1232         if (r)
1233                 goto error_pasid;
1234
1235         r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1236         if (r)
1237                 goto error_vm;
1238
1239         fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1240         if (!fpriv->prt_va) {
1241                 r = -ENOMEM;
1242                 goto error_vm;
1243         }
1244
1245         if (amdgpu_mcbp) {
1246                 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1247
1248                 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1249                                                 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1250                 if (r)
1251                         goto error_vm;
1252         }
1253
1254         mutex_init(&fpriv->bo_list_lock);
1255         idr_init_base(&fpriv->bo_list_handles, 1);
1256
1257         amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1258
1259         file_priv->driver_priv = fpriv;
1260         goto out_suspend;
1261
1262 error_vm:
1263         amdgpu_vm_fini(adev, &fpriv->vm);
1264
1265 error_pasid:
1266         if (pasid) {
1267                 amdgpu_pasid_free(pasid);
1268                 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1269         }
1270
1271         kfree(fpriv);
1272
1273 out_suspend:
1274         pm_runtime_mark_last_busy(dev->dev);
1275 pm_put:
1276         pm_runtime_put_autosuspend(dev->dev);
1277
1278         return r;
1279 }
1280
1281 /**
1282  * amdgpu_driver_postclose_kms - drm callback for post close
1283  *
1284  * @dev: drm dev pointer
1285  * @file_priv: drm file
1286  *
1287  * On device post close, tear down vm on cayman+ (all asics).
1288  */
1289 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1290                                  struct drm_file *file_priv)
1291 {
1292         struct amdgpu_device *adev = drm_to_adev(dev);
1293         struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1294         struct amdgpu_bo_list *list;
1295         struct amdgpu_bo *pd;
1296         u32 pasid;
1297         int handle;
1298
1299         if (!fpriv)
1300                 return;
1301
1302         pm_runtime_get_sync(dev->dev);
1303
1304         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1305                 amdgpu_uvd_free_handles(adev, file_priv);
1306         if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1307                 amdgpu_vce_free_handles(adev, file_priv);
1308
1309         if (amdgpu_mcbp) {
1310                 /* TODO: how to handle reserve failure */
1311                 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1312                 amdgpu_vm_bo_del(adev, fpriv->csa_va);
1313                 fpriv->csa_va = NULL;
1314                 amdgpu_bo_unreserve(adev->virt.csa_obj);
1315         }
1316
1317         pasid = fpriv->vm.pasid;
1318         pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1319         if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1320                 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1321                 amdgpu_bo_unreserve(pd);
1322         }
1323
1324         amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1325         amdgpu_vm_fini(adev, &fpriv->vm);
1326
1327         if (pasid)
1328                 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1329         amdgpu_bo_unref(&pd);
1330
1331         idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1332                 amdgpu_bo_list_put(list);
1333
1334         idr_destroy(&fpriv->bo_list_handles);
1335         mutex_destroy(&fpriv->bo_list_lock);
1336
1337         kfree(fpriv);
1338         file_priv->driver_priv = NULL;
1339
1340         pm_runtime_mark_last_busy(dev->dev);
1341         pm_runtime_put_autosuspend(dev->dev);
1342 }
1343
1344
1345 void amdgpu_driver_release_kms(struct drm_device *dev)
1346 {
1347         struct amdgpu_device *adev = drm_to_adev(dev);
1348
1349         amdgpu_device_fini_sw(adev);
1350         pci_set_drvdata(adev->pdev, NULL);
1351 }
1352
1353 /*
1354  * VBlank related functions.
1355  */
1356 /**
1357  * amdgpu_get_vblank_counter_kms - get frame count
1358  *
1359  * @crtc: crtc to get the frame count from
1360  *
1361  * Gets the frame count on the requested crtc (all asics).
1362  * Returns frame count on success, -EINVAL on failure.
1363  */
1364 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1365 {
1366         struct drm_device *dev = crtc->dev;
1367         unsigned int pipe = crtc->index;
1368         struct amdgpu_device *adev = drm_to_adev(dev);
1369         int vpos, hpos, stat;
1370         u32 count;
1371
1372         if (pipe >= adev->mode_info.num_crtc) {
1373                 DRM_ERROR("Invalid crtc %u\n", pipe);
1374                 return -EINVAL;
1375         }
1376
1377         /* The hw increments its frame counter at start of vsync, not at start
1378          * of vblank, as is required by DRM core vblank counter handling.
1379          * Cook the hw count here to make it appear to the caller as if it
1380          * incremented at start of vblank. We measure distance to start of
1381          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1382          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1383          * result by 1 to give the proper appearance to caller.
1384          */
1385         if (adev->mode_info.crtcs[pipe]) {
1386                 /* Repeat readout if needed to provide stable result if
1387                  * we cross start of vsync during the queries.
1388                  */
1389                 do {
1390                         count = amdgpu_display_vblank_get_counter(adev, pipe);
1391                         /* Ask amdgpu_display_get_crtc_scanoutpos to return
1392                          * vpos as distance to start of vblank, instead of
1393                          * regular vertical scanout pos.
1394                          */
1395                         stat = amdgpu_display_get_crtc_scanoutpos(
1396                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1397                                 &vpos, &hpos, NULL, NULL,
1398                                 &adev->mode_info.crtcs[pipe]->base.hwmode);
1399                 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1400
1401                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1402                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1403                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1404                 } else {
1405                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1406                                       pipe, vpos);
1407
1408                         /* Bump counter if we are at >= leading edge of vblank,
1409                          * but before vsync where vpos would turn negative and
1410                          * the hw counter really increments.
1411                          */
1412                         if (vpos >= 0)
1413                                 count++;
1414                 }
1415         } else {
1416                 /* Fallback to use value as is. */
1417                 count = amdgpu_display_vblank_get_counter(adev, pipe);
1418                 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1419         }
1420
1421         return count;
1422 }
1423
1424 /**
1425  * amdgpu_enable_vblank_kms - enable vblank interrupt
1426  *
1427  * @crtc: crtc to enable vblank interrupt for
1428  *
1429  * Enable the interrupt on the requested crtc (all asics).
1430  * Returns 0 on success, -EINVAL on failure.
1431  */
1432 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1433 {
1434         struct drm_device *dev = crtc->dev;
1435         unsigned int pipe = crtc->index;
1436         struct amdgpu_device *adev = drm_to_adev(dev);
1437         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1438
1439         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1440 }
1441
1442 /**
1443  * amdgpu_disable_vblank_kms - disable vblank interrupt
1444  *
1445  * @crtc: crtc to disable vblank interrupt for
1446  *
1447  * Disable the interrupt on the requested crtc (all asics).
1448  */
1449 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1450 {
1451         struct drm_device *dev = crtc->dev;
1452         unsigned int pipe = crtc->index;
1453         struct amdgpu_device *adev = drm_to_adev(dev);
1454         int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1455
1456         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1457 }
1458
1459 /*
1460  * Debugfs info
1461  */
1462 #if defined(CONFIG_DEBUG_FS)
1463
1464 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1465 {
1466         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1467         struct drm_amdgpu_info_firmware fw_info;
1468         struct drm_amdgpu_query_fw query_fw;
1469         struct atom_context *ctx = adev->mode_info.atom_context;
1470         uint8_t smu_program, smu_major, smu_minor, smu_debug;
1471         int ret, i;
1472
1473         static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1474 #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type
1475                 TA_FW_NAME(XGMI),
1476                 TA_FW_NAME(RAS),
1477                 TA_FW_NAME(HDCP),
1478                 TA_FW_NAME(DTM),
1479                 TA_FW_NAME(RAP),
1480                 TA_FW_NAME(SECUREDISPLAY),
1481 #undef TA_FW_NAME
1482         };
1483
1484         /* VCE */
1485         query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1486         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1487         if (ret)
1488                 return ret;
1489         seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1490                    fw_info.feature, fw_info.ver);
1491
1492         /* UVD */
1493         query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1494         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1495         if (ret)
1496                 return ret;
1497         seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1498                    fw_info.feature, fw_info.ver);
1499
1500         /* GMC */
1501         query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1502         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1503         if (ret)
1504                 return ret;
1505         seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1506                    fw_info.feature, fw_info.ver);
1507
1508         /* ME */
1509         query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1510         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1511         if (ret)
1512                 return ret;
1513         seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1514                    fw_info.feature, fw_info.ver);
1515
1516         /* PFP */
1517         query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1518         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1519         if (ret)
1520                 return ret;
1521         seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1522                    fw_info.feature, fw_info.ver);
1523
1524         /* CE */
1525         query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1526         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1527         if (ret)
1528                 return ret;
1529         seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1530                    fw_info.feature, fw_info.ver);
1531
1532         /* RLC */
1533         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1534         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1535         if (ret)
1536                 return ret;
1537         seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1538                    fw_info.feature, fw_info.ver);
1539
1540         /* RLC SAVE RESTORE LIST CNTL */
1541         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1542         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1543         if (ret)
1544                 return ret;
1545         seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1546                    fw_info.feature, fw_info.ver);
1547
1548         /* RLC SAVE RESTORE LIST GPM MEM */
1549         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1550         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1551         if (ret)
1552                 return ret;
1553         seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1554                    fw_info.feature, fw_info.ver);
1555
1556         /* RLC SAVE RESTORE LIST SRM MEM */
1557         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1558         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1559         if (ret)
1560                 return ret;
1561         seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1562                    fw_info.feature, fw_info.ver);
1563
1564         /* RLCP */
1565         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1566         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1567         if (ret)
1568                 return ret;
1569         seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1570                    fw_info.feature, fw_info.ver);
1571
1572         /* RLCV */
1573         query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1574         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1575         if (ret)
1576                 return ret;
1577         seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1578                    fw_info.feature, fw_info.ver);
1579
1580         /* MEC */
1581         query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1582         query_fw.index = 0;
1583         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1584         if (ret)
1585                 return ret;
1586         seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1587                    fw_info.feature, fw_info.ver);
1588
1589         /* MEC2 */
1590         if (adev->gfx.mec2_fw) {
1591                 query_fw.index = 1;
1592                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1593                 if (ret)
1594                         return ret;
1595                 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1596                            fw_info.feature, fw_info.ver);
1597         }
1598
1599         /* IMU */
1600         query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1601         query_fw.index = 0;
1602         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1603         if (ret)
1604                 return ret;
1605         seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1606                    fw_info.feature, fw_info.ver);
1607
1608         /* PSP SOS */
1609         query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1610         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1611         if (ret)
1612                 return ret;
1613         seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1614                    fw_info.feature, fw_info.ver);
1615
1616
1617         /* PSP ASD */
1618         query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1619         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1620         if (ret)
1621                 return ret;
1622         seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1623                    fw_info.feature, fw_info.ver);
1624
1625         query_fw.fw_type = AMDGPU_INFO_FW_TA;
1626         for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1627                 query_fw.index = i;
1628                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1629                 if (ret)
1630                         continue;
1631
1632                 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1633                            ta_fw_name[i], fw_info.feature, fw_info.ver);
1634         }
1635
1636         /* SMC */
1637         query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1638         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1639         if (ret)
1640                 return ret;
1641         smu_program = (fw_info.ver >> 24) & 0xff;
1642         smu_major = (fw_info.ver >> 16) & 0xff;
1643         smu_minor = (fw_info.ver >> 8) & 0xff;
1644         smu_debug = (fw_info.ver >> 0) & 0xff;
1645         seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1646                    fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1647
1648         /* SDMA */
1649         query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1650         for (i = 0; i < adev->sdma.num_instances; i++) {
1651                 query_fw.index = i;
1652                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1653                 if (ret)
1654                         return ret;
1655                 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1656                            i, fw_info.feature, fw_info.ver);
1657         }
1658
1659         /* VCN */
1660         query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1661         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1662         if (ret)
1663                 return ret;
1664         seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1665                    fw_info.feature, fw_info.ver);
1666
1667         /* DMCU */
1668         query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1669         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1670         if (ret)
1671                 return ret;
1672         seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1673                    fw_info.feature, fw_info.ver);
1674
1675         /* DMCUB */
1676         query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1677         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1678         if (ret)
1679                 return ret;
1680         seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1681                    fw_info.feature, fw_info.ver);
1682
1683         /* TOC */
1684         query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1685         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1686         if (ret)
1687                 return ret;
1688         seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1689                    fw_info.feature, fw_info.ver);
1690
1691         /* CAP */
1692         if (adev->psp.cap_fw) {
1693                 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1694                 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1695                 if (ret)
1696                         return ret;
1697                 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1698                                 fw_info.feature, fw_info.ver);
1699         }
1700
1701         /* MES_KIQ */
1702         query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1703         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1704         if (ret)
1705                 return ret;
1706         seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1707                    fw_info.feature, fw_info.ver);
1708
1709         /* MES */
1710         query_fw.fw_type = AMDGPU_INFO_FW_MES;
1711         ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1712         if (ret)
1713                 return ret;
1714         seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1715                    fw_info.feature, fw_info.ver);
1716
1717         seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1718
1719         return 0;
1720 }
1721
1722 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1723
1724 #endif
1725
1726 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1727 {
1728 #if defined(CONFIG_DEBUG_FS)
1729         struct drm_minor *minor = adev_to_drm(adev)->primary;
1730         struct dentry *root = minor->debugfs_root;
1731
1732         debugfs_create_file("amdgpu_firmware_info", 0444, root,
1733                             adev, &amdgpu_debugfs_firmware_info_fops);
1734
1735 #endif
1736 }