drivers/clk/qcom/gcc-sm6350.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2021, Konrad Dybcio <[email protected]>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/module.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/regmap.h>
  11
  12 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
  13
  14 #include "clk-alpha-pll.h"
  15 #include "clk-branch.h"
  16 #include "clk-rcg.h"
  17 #include "clk-regmap.h"
  18 #include "clk-regmap-divider.h"
  19 #include "clk-regmap-mux.h"
  20 #include "common.h"
  21 #include "gdsc.h"
  22 #include "reset.h"
  23
  24 enum {
  25         P_BI_TCXO,
  26         P_GPLL0_OUT_EVEN,
  27         P_GPLL0_OUT_MAIN,
  28         P_GPLL0_OUT_ODD,
  29         P_GPLL6_OUT_EVEN,
  30         P_GPLL7_OUT_MAIN,
  31         P_SLEEP_CLK,
  32 };
  33
  34 static struct clk_alpha_pll gpll0 = {
  35         .offset = 0x0,
  36         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  37         .clkr = {
  38                 .enable_reg = 0x52010,
  39                 .enable_mask = BIT(0),
  40                 .hw.init = &(struct clk_init_data){
  41                         .name = "gpll0",
  42                         .parent_data = &(const struct clk_parent_data){
  43                                 .fw_name = "bi_tcxo",
  44                         },
  45                         .num_parents = 1,
  46                         .ops = &clk_alpha_pll_fixed_fabia_ops,
  47                 },
  48         },
  49 };
  50
  51 static const struct clk_div_table post_div_table_gpll0_out_even[] = {
  52         { 0x1, 2 },
  53         { }
  54 };
  55
  56 static struct clk_alpha_pll_postdiv gpll0_out_even = {
  57         .offset = 0x0,
  58         .post_div_shift = 8,
  59         .post_div_table = post_div_table_gpll0_out_even,
  60         .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
  61         .width = 4,
  62         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  63         .clkr.hw.init = &(struct clk_init_data){
  64                 .name = "gpll0_out_even",
  65                 .parent_hws = (const struct clk_hw*[]){
  66                         &gpll0.clkr.hw,
  67                 },
  68                 .num_parents = 1,
  69                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
  70         },
  71 };
  72
  73 static const struct clk_div_table post_div_table_gpll0_out_odd[] = {
  74         { 0x3, 3 },
  75         { }
  76 };
  77
  78 static struct clk_alpha_pll_postdiv gpll0_out_odd = {
  79         .offset = 0x0,
  80         .post_div_shift = 12,
  81         .post_div_table = post_div_table_gpll0_out_odd,
  82         .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_odd),
  83         .width = 4,
  84         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  85         .clkr.hw.init = &(struct clk_init_data){
  86                 .name = "gpll0_out_odd",
  87                 .parent_hws = (const struct clk_hw*[]){
  88                         &gpll0.clkr.hw,
  89                 },
  90                 .num_parents = 1,
  91                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
  92         },
  93 };
  94
  95 static struct clk_alpha_pll gpll6 = {
  96         .offset = 0x6000,
  97         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  98         .clkr = {
  99                 .enable_reg = 0x52010,
 100                 .enable_mask = BIT(6),
 101                 .hw.init = &(struct clk_init_data){
 102                         .name = "gpll6",
 103                         .parent_hws = (const struct clk_hw*[]){
 104                                 &gpll0.clkr.hw,
 105                         },
 106                         .num_parents = 1,
 107                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 108                 },
 109         },
 110 };
 111
 112 static const struct clk_div_table post_div_table_gpll6_out_even[] = {
 113         { 0x1, 2 },
 114         { }
 115 };
 116
 117 static struct clk_alpha_pll_postdiv gpll6_out_even = {
 118         .offset = 0x6000,
 119         .post_div_shift = 8,
 120         .post_div_table = post_div_table_gpll6_out_even,
 121         .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even),
 122         .width = 4,
 123         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 124         .clkr.hw.init = &(struct clk_init_data){
 125                 .name = "gpll6_out_even",
 126                 .parent_hws = (const struct clk_hw*[]){
 127                         &gpll0.clkr.hw,
 128                 },
 129                 .num_parents = 1,
 130                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 131         },
 132 };
 133
 134 static struct clk_alpha_pll gpll7 = {
 135         .offset = 0x7000,
 136         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 137         .clkr = {
 138                 .enable_reg = 0x52010,
 139                 .enable_mask = BIT(7),
 140                 .hw.init = &(struct clk_init_data){
 141                         .name = "gpll7",
 142                         .parent_hws = (const struct clk_hw*[]){
 143                                 &gpll0.clkr.hw,
 144                         },
 145                         .num_parents = 1,
 146                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 147                 },
 148         },
 149 };
 150
 151 static const struct parent_map gcc_parent_map_0[] = {
 152         { P_BI_TCXO, 0 },
 153         { P_GPLL0_OUT_MAIN, 1 },
 154         { P_GPLL6_OUT_EVEN, 2 },
 155         { P_GPLL0_OUT_EVEN, 6 },
 156 };
 157
 158 static const struct clk_parent_data gcc_parent_data_0[] = {
 159         { .fw_name = "bi_tcxo" },
 160         { .hw = &gpll0.clkr.hw },
 161         { .hw = &gpll6_out_even.clkr.hw },
 162         { .hw = &gpll0_out_even.clkr.hw },
 163 };
 164
 165 static const struct parent_map gcc_parent_map_1[] = {
 166         { P_BI_TCXO, 0 },
 167         { P_GPLL0_OUT_EVEN, 6 },
 168 };
 169
 170 static const struct clk_parent_data gcc_parent_data_1[] = {
 171         { .fw_name = "bi_tcxo" },
 172         { .hw = &gpll0_out_even.clkr.hw },
 173 };
 174
 175 static const struct parent_map gcc_parent_map_2[] = {
 176         { P_BI_TCXO, 0 },
 177         { P_GPLL0_OUT_ODD, 2 },
 178 };
 179
 180 static const struct clk_parent_data gcc_parent_data_2_ao[] = {
 181         { .fw_name = "bi_tcxo_ao" },
 182         { .hw = &gpll0_out_odd.clkr.hw },
 183 };
 184
 185 static const struct parent_map gcc_parent_map_4[] = {
 186         { P_BI_TCXO, 0 },
 187         { P_GPLL0_OUT_MAIN, 1 },
 188         { P_GPLL0_OUT_ODD, 2 },
 189 };
 190
 191 static const struct clk_parent_data gcc_parent_data_4[] = {
 192         { .fw_name = "bi_tcxo" },
 193         { .hw = &gpll0.clkr.hw },
 194         { .hw = &gpll0_out_odd.clkr.hw },
 195 };
 196
 197 static const struct parent_map gcc_parent_map_5[] = {
 198         { P_BI_TCXO, 0 },
 199         { P_GPLL0_OUT_ODD, 2 },
 200         { P_SLEEP_CLK, 5 },
 201         { P_GPLL0_OUT_EVEN, 6 },
 202 };
 203
 204 static const struct clk_parent_data gcc_parent_data_5[] = {
 205         { .fw_name = "bi_tcxo" },
 206         { .hw = &gpll0_out_odd.clkr.hw },
 207         { .fw_name = "sleep_clk" },
 208         { .hw = &gpll0_out_even.clkr.hw },
 209 };
 210
 211 static const struct parent_map gcc_parent_map_6[] = {
 212         { P_BI_TCXO, 0 },
 213         { P_SLEEP_CLK, 5 },
 214 };
 215
 216 static const struct clk_parent_data gcc_parent_data_6[] = {
 217         { .fw_name = "bi_tcxo" },
 218         { .fw_name = "sleep_clk" }
 219 };
 220
 221 static const struct parent_map gcc_parent_map_7[] = {
 222         { P_BI_TCXO, 0 },
 223         { P_GPLL6_OUT_EVEN, 2 },
 224         { P_GPLL0_OUT_EVEN, 6 },
 225 };
 226
 227 static const struct clk_parent_data gcc_parent_data_7[] = {
 228         { .fw_name = "bi_tcxo" },
 229         { .hw = &gpll6_out_even.clkr.hw },
 230         { .hw = &gpll0_out_even.clkr.hw },
 231 };
 232
 233 static const struct parent_map gcc_parent_map_8[] = {
 234         { P_BI_TCXO, 0 },
 235         { P_GPLL0_OUT_ODD, 2 },
 236         { P_GPLL7_OUT_MAIN, 3 },
 237 };
 238
 239 static const struct clk_parent_data gcc_parent_data_8[] = {
 240         { .fw_name = "bi_tcxo" },
 241         { .hw = &gpll0_out_odd.clkr.hw },
 242         { .hw = &gpll7.clkr.hw },
 243 };
 244
 245 static struct clk_regmap_div gcc_gpu_gpll0_main_div_clk_src = {
 246         .reg = 0x4514C,
 247         .shift = 0,
 248         .width = 2,
 249         .clkr.hw.init = &(struct clk_init_data) {
 250                 .name = "gcc_gpu_gpll0_main_div_clk_src",
 251                 .parent_hws = (const struct clk_hw*[]){
 252                         &gpll0.clkr.hw,
 253                 },
 254                 .num_parents = 1,
 255                 .ops = &clk_regmap_div_ro_ops,
 256         },
 257 };
 258
 259 static struct clk_regmap_div gcc_npu_pll0_main_div_clk_src = {
 260         .reg = 0x4ce00,
 261         .shift = 0,
 262         .width = 2,
 263         .clkr.hw.init = &(struct clk_init_data) {
 264                 .name = "gcc_npu_pll0_main_div_clk_src",
 265                 .parent_hws = (const struct clk_hw*[]){
 266                         &gpll0.clkr.hw,
 267                 },
 268                 .num_parents = 1,
 269                 .ops = &clk_regmap_div_ro_ops,
 270         },
 271 };
 272
 273 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
 274         F(19200000, P_BI_TCXO, 1, 0, 0),
 275         { }
 276 };
 277
 278 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
 279         .cmd_rcgr = 0x30014,
 280         .mnd_width = 0,
 281         .hid_width = 5,
 282         .parent_map = gcc_parent_map_2,
 283         .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
 284         .clkr.hw.init = &(struct clk_init_data){
 285                 .name = "gcc_cpuss_ahb_clk_src",
 286                 .parent_data = gcc_parent_data_2_ao,
 287                 .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao),
 288                 .ops = &clk_rcg2_ops,
 289         },
 290 };
 291
 292 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 293         F(19200000, P_BI_TCXO, 1, 0, 0),
 294         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 295         F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
 296         F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
 297         F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
 298         { }
 299 };
 300
 301 static struct clk_rcg2 gcc_gp1_clk_src = {
 302         .cmd_rcgr = 0x37004,
 303         .mnd_width = 8,
 304         .hid_width = 5,
 305         .parent_map = gcc_parent_map_5,
 306         .freq_tbl = ftbl_gcc_gp1_clk_src,
 307         .clkr.hw.init = &(struct clk_init_data){
 308                 .name = "gcc_gp1_clk_src",
 309                 .parent_data = gcc_parent_data_5,
 310                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
 311                 .ops = &clk_rcg2_ops,
 312         },
 313 };
 314
 315 static struct clk_rcg2 gcc_gp2_clk_src = {
 316         .cmd_rcgr = 0x38004,
 317         .mnd_width = 8,
 318         .hid_width = 5,
 319         .parent_map = gcc_parent_map_5,
 320         .freq_tbl = ftbl_gcc_gp1_clk_src,
 321         .clkr.hw.init = &(struct clk_init_data){
 322                 .name = "gcc_gp2_clk_src",
 323                 .parent_data = gcc_parent_data_5,
 324                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
 325                 .ops = &clk_rcg2_ops,
 326         },
 327 };
 328
 329 static struct clk_rcg2 gcc_gp3_clk_src = {
 330         .cmd_rcgr = 0x39004,
 331         .mnd_width = 8,
 332         .hid_width = 5,
 333         .parent_map = gcc_parent_map_5,
 334         .freq_tbl = ftbl_gcc_gp1_clk_src,
 335         .clkr.hw.init = &(struct clk_init_data){
 336                 .name = "gcc_gp3_clk_src",
 337                 .parent_data = gcc_parent_data_5,
 338                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
 339                 .ops = &clk_rcg2_ops,
 340         },
 341 };
 342
 343 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 344         F(19200000, P_BI_TCXO, 1, 0, 0),
 345         F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
 346         { }
 347 };
 348
 349 static struct clk_rcg2 gcc_pdm2_clk_src = {
 350         .cmd_rcgr = 0x23010,
 351         .mnd_width = 0,
 352         .hid_width = 5,
 353         .parent_map = gcc_parent_map_1,
 354         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 355         .clkr.hw.init = &(struct clk_init_data){
 356                 .name = "gcc_pdm2_clk_src",
 357                 .parent_data = gcc_parent_data_1,
 358                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 359                 .ops = &clk_rcg2_ops,
 360         },
 361 };
 362
 363 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 364         F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
 365         F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
 366         F(19200000, P_BI_TCXO, 1, 0, 0),
 367         F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
 368         F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
 369         F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
 370         F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
 371         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 372         F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
 373         F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
 374         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 375         F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
 376         F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
 377         F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
 378         F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
 379         F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0),
 380         { }
 381 };
 382
 383 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 384         .name = "gcc_qupv3_wrap0_s0_clk_src",
 385         .parent_data = gcc_parent_data_0,
 386         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 387         .ops = &clk_rcg2_ops,
 388 };
 389
 390 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 391         .cmd_rcgr = 0x21148,
 392         .mnd_width = 16,
 393         .hid_width = 5,
 394         .parent_map = gcc_parent_map_0,
 395         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 396         .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 397 };
 398
 399 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 400         .name = "gcc_qupv3_wrap0_s1_clk_src",
 401         .parent_data = gcc_parent_data_0,
 402         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 403         .ops = &clk_rcg2_ops,
 404 };
 405
 406 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 407         .cmd_rcgr = 0x21278,
 408         .mnd_width = 16,
 409         .hid_width = 5,
 410         .parent_map = gcc_parent_map_0,
 411         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 412         .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 413 };
 414
 415 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 416         .name = "gcc_qupv3_wrap0_s2_clk_src",
 417         .parent_data = gcc_parent_data_0,
 418         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 419         .ops = &clk_rcg2_ops,
 420 };
 421
 422 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 423         .cmd_rcgr = 0x213a8,
 424         .mnd_width = 16,
 425         .hid_width = 5,
 426         .parent_map = gcc_parent_map_0,
 427         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 428         .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 429 };
 430
 431 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 432         .name = "gcc_qupv3_wrap0_s3_clk_src",
 433         .parent_data = gcc_parent_data_0,
 434         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 435         .ops = &clk_rcg2_ops,
 436 };
 437
 438 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 439         .cmd_rcgr = 0x214d8,
 440         .mnd_width = 16,
 441         .hid_width = 5,
 442         .parent_map = gcc_parent_map_0,
 443         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 444         .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 445 };
 446
 447 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 448         .name = "gcc_qupv3_wrap0_s4_clk_src",
 449         .parent_data = gcc_parent_data_0,
 450         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 451         .ops = &clk_rcg2_ops,
 452 };
 453
 454 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 455         .cmd_rcgr = 0x21608,
 456         .mnd_width = 16,
 457         .hid_width = 5,
 458         .parent_map = gcc_parent_map_0,
 459         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 460         .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 461 };
 462
 463 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 464         .name = "gcc_qupv3_wrap0_s5_clk_src",
 465         .parent_data = gcc_parent_data_0,
 466         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 467         .ops = &clk_rcg2_ops,
 468 };
 469
 470 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 471         .cmd_rcgr = 0x21738,
 472         .mnd_width = 16,
 473         .hid_width = 5,
 474         .parent_map = gcc_parent_map_0,
 475         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 476         .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 477 };
 478
 479 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 480         .name = "gcc_qupv3_wrap1_s0_clk_src",
 481         .parent_data = gcc_parent_data_0,
 482         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 483         .ops = &clk_rcg2_ops,
 484 };
 485
 486 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 487         .cmd_rcgr = 0x22018,
 488         .mnd_width = 16,
 489         .hid_width = 5,
 490         .parent_map = gcc_parent_map_0,
 491         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 492         .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 493 };
 494
 495 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 496         .name = "gcc_qupv3_wrap1_s1_clk_src",
 497         .parent_data = gcc_parent_data_0,
 498         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 499         .ops = &clk_rcg2_ops,
 500 };
 501
 502 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 503         .cmd_rcgr = 0x22148,
 504         .mnd_width = 16,
 505         .hid_width = 5,
 506         .parent_map = gcc_parent_map_0,
 507         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 508         .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 509 };
 510
 511 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
 512         .name = "gcc_qupv3_wrap1_s2_clk_src",
 513         .parent_data = gcc_parent_data_0,
 514         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 515         .ops = &clk_rcg2_ops,
 516 };
 517
 518 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 519         .cmd_rcgr = 0x22278,
 520         .mnd_width = 16,
 521         .hid_width = 5,
 522         .parent_map = gcc_parent_map_0,
 523         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 524         .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 525 };
 526
 527 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 528         .name = "gcc_qupv3_wrap1_s3_clk_src",
 529         .parent_data = gcc_parent_data_0,
 530         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 531         .ops = &clk_rcg2_ops,
 532 };
 533
 534 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 535         .cmd_rcgr = 0x223a8,
 536         .mnd_width = 16,
 537         .hid_width = 5,
 538         .parent_map = gcc_parent_map_0,
 539         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 540         .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 541 };
 542
 543 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 544         .name = "gcc_qupv3_wrap1_s4_clk_src",
 545         .parent_data = gcc_parent_data_0,
 546         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 547         .ops = &clk_rcg2_ops,
 548 };
 549
 550 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 551         .cmd_rcgr = 0x224d8,
 552         .mnd_width = 16,
 553         .hid_width = 5,
 554         .parent_map = gcc_parent_map_0,
 555         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 556         .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 557 };
 558
 559 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 560         .name = "gcc_qupv3_wrap1_s5_clk_src",
 561         .parent_data = gcc_parent_data_0,
 562         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 563         .ops = &clk_rcg2_ops,
 564 };
 565
 566 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 567         .cmd_rcgr = 0x22608,
 568         .mnd_width = 16,
 569         .hid_width = 5,
 570         .parent_map = gcc_parent_map_0,
 571         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 572         .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 573 };
 574
 575 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
 576         F(144000, P_BI_TCXO, 16, 3, 25),
 577         F(400000, P_BI_TCXO, 12, 1, 4),
 578         F(19200000, P_BI_TCXO, 1, 0, 0),
 579         F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
 580         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 581         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 582         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 583         F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0),
 584         F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
 585         { }
 586 };
 587
 588 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
 589         .cmd_rcgr = 0x4b024,
 590         .mnd_width = 8,
 591         .hid_width = 5,
 592         .parent_map = gcc_parent_map_7,
 593         .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
 594         .clkr.hw.init = &(struct clk_init_data){
 595                 .name = "gcc_sdcc1_apps_clk_src",
 596                 .parent_data = gcc_parent_data_7,
 597                 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
 598                 .ops = &clk_rcg2_ops,
 599         },
 600 };
 601
 602 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
 603         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 604         F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
 605         F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
 606         { }
 607 };
 608
 609 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
 610         .cmd_rcgr = 0x4b00c,
 611         .mnd_width = 0,
 612         .hid_width = 5,
 613         .parent_map = gcc_parent_map_1,
 614         .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
 615         .clkr.hw.init = &(struct clk_init_data){
 616                 .name = "gcc_sdcc1_ice_core_clk_src",
 617                 .parent_data = gcc_parent_data_1,
 618                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 619                 .ops = &clk_rcg2_ops,
 620         },
 621 };
 622
 623 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 624         F(400000, P_BI_TCXO, 12, 1, 4),
 625         F(9600000, P_BI_TCXO, 2, 0, 0),
 626         F(19200000, P_BI_TCXO, 1, 0, 0),
 627         F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
 628         F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
 629         F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
 630         F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
 631         { }
 632 };
 633
 634 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
 635         .cmd_rcgr = 0x2000c,
 636         .mnd_width = 8,
 637         .hid_width = 5,
 638         .parent_map = gcc_parent_map_8,
 639         .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
 640         .clkr.hw.init = &(struct clk_init_data){
 641                 .name = "gcc_sdcc2_apps_clk_src",
 642                 .parent_data = gcc_parent_data_8,
 643                 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
 644                 .ops = &clk_rcg2_floor_ops,
 645         },
 646 };
 647
 648 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
 649         F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
 650         F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
 651         F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
 652         F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
 653         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 654         { }
 655 };
 656
 657 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
 658         .cmd_rcgr = 0x3a01c,
 659         .mnd_width = 8,
 660         .hid_width = 5,
 661         .parent_map = gcc_parent_map_4,
 662         .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
 663         .clkr.hw.init = &(struct clk_init_data){
 664                 .name = "gcc_ufs_phy_axi_clk_src",
 665                 .parent_data = gcc_parent_data_4,
 666                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 667                 .ops = &clk_rcg2_ops,
 668         },
 669 };
 670
 671 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
 672         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 673         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 674         F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
 675         F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
 676         { }
 677 };
 678
 679 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
 680         .cmd_rcgr = 0x3a048,
 681         .mnd_width = 0,
 682         .hid_width = 5,
 683         .parent_map = gcc_parent_map_1,
 684         .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
 685         .clkr.hw.init = &(struct clk_init_data){
 686                 .name = "gcc_ufs_phy_ice_core_clk_src",
 687                 .parent_data = gcc_parent_data_1,
 688                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 689                 .ops = &clk_rcg2_ops,
 690         },
 691 };
 692
 693 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
 694         F(9600000, P_BI_TCXO, 2, 0, 0),
 695         F(19200000, P_BI_TCXO, 1, 0, 0),
 696         { }
 697 };
 698
 699 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
 700         .cmd_rcgr = 0x3a0b0,
 701         .mnd_width = 0,
 702         .hid_width = 5,
 703         .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
 704         .clkr.hw.init = &(struct clk_init_data){
 705                 .name = "gcc_ufs_phy_phy_aux_clk_src",
 706                 .parent_data = &(const struct clk_parent_data){
 707                         .fw_name = "bi_tcxo",
 708                 },
 709                 .num_parents = 1,
 710                 .ops = &clk_rcg2_ops,
 711         },
 712 };
 713
 714 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
 715         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 716         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 717         F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
 718         { }
 719 };
 720
 721 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
 722         .cmd_rcgr = 0x3a060,
 723         .mnd_width = 0,
 724         .hid_width = 5,
 725         .parent_map = gcc_parent_map_1,
 726         .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
 727         .clkr.hw.init = &(struct clk_init_data){
 728                 .name = "gcc_ufs_phy_unipro_core_clk_src",
 729                 .parent_data = gcc_parent_data_1,
 730                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 731                 .ops = &clk_rcg2_ops,
 732         },
 733 };
 734
 735 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
 736         F(66666667, P_GPLL0_OUT_ODD, 3, 0, 0),
 737         F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
 738         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 739         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 740         { }
 741 };
 742
 743 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
 744         .cmd_rcgr = 0x1a01c,
 745         .mnd_width = 8,
 746         .hid_width = 5,
 747         .parent_map = gcc_parent_map_4,
 748         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
 749         .clkr.hw.init = &(struct clk_init_data){
 750                 .name = "gcc_usb30_prim_master_clk_src",
 751                 .parent_data = gcc_parent_data_4,
 752                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 753                 .ops = &clk_rcg2_ops,
 754         },
 755 };
 756
 757 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
 758         F(19200000, P_BI_TCXO, 1, 0, 0),
 759         { }
 760 };
 761
 762 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
 763         .cmd_rcgr = 0x1a034,
 764         .mnd_width = 0,
 765         .hid_width = 5,
 766         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
 767         .clkr.hw.init = &(struct clk_init_data){
 768                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
 769                 .parent_data = &(const struct clk_parent_data){
 770                         .fw_name = "bi_tcxo",
 771                 },
 772                 .num_parents = 1,
 773                 .ops = &clk_rcg2_ops,
 774         },
 775 };
 776
 777 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
 778         .cmd_rcgr = 0x1a060,
 779         .mnd_width = 0,
 780         .hid_width = 5,
 781         .parent_map = gcc_parent_map_6,
 782         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
 783         .clkr.hw.init = &(struct clk_init_data){
 784                 .name = "gcc_usb3_prim_phy_aux_clk_src",
 785                 .parent_data = gcc_parent_data_6,
 786                 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 787                 .ops = &clk_rcg2_ops,
 788         },
 789 };
 790
 791 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
 792         .halt_reg = 0x3e014,
 793         .halt_check = BRANCH_HALT_DELAY,
 794         .hwcg_reg = 0x3e014,
 795         .hwcg_bit = 1,
 796         .clkr = {
 797                 .enable_reg = 0x3e014,
 798                 .enable_mask = BIT(0),
 799                 .hw.init = &(struct clk_init_data){
 800                         .name = "gcc_aggre_ufs_phy_axi_clk",
 801                         .parent_hws = (const struct clk_hw*[]){
 802                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
 803                         },
 804                         .num_parents = 1,
 805                         .flags = CLK_SET_RATE_PARENT,
 806                         .ops = &clk_branch2_ops,
 807                 },
 808         },
 809 };
 810
 811 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
 812         .halt_reg = 0x3e014,
 813         .halt_check = BRANCH_HALT,
 814         .hwcg_reg = 0x3e014,
 815         .hwcg_bit = 1,
 816         .clkr = {
 817                 .enable_reg = 0x3e014,
 818                 .enable_mask = BIT(1),
 819                 .hw.init = &(struct clk_init_data){
 820                         .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
 821                         .parent_hws = (const struct clk_hw*[]){
 822                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
 823                         },
 824                         .num_parents = 1,
 825                         .flags = CLK_SET_RATE_PARENT,
 826                         .ops = &clk_branch2_ops,
 827                 },
 828         },
 829 };
 830
 831 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
 832         .halt_reg = 0x3e014,
 833         .halt_check = BRANCH_HALT,
 834         .hwcg_reg = 0x3e014,
 835         .hwcg_bit = 1,
 836         .clkr = {
 837                 .enable_reg = 0x3e014,
 838                 .enable_mask = BIT(1),
 839                 .hw.init = &(struct clk_init_data){
 840                         .name = "gcc_ufs_phy_axi_hw_ctl_clk",
 841                         .parent_hws = (const struct clk_hw*[]){
 842                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
 843                         },
 844                         .num_parents = 1,
 845                         .flags = CLK_SET_RATE_PARENT,
 846                         .ops = &clk_branch2_ops,
 847                 },
 848         },
 849 };
 850
 851 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
 852         .halt_reg = 0x3e010,
 853         .halt_check = BRANCH_HALT,
 854         .hwcg_reg = 0x3e010,
 855         .hwcg_bit = 1,
 856         .clkr = {
 857                 .enable_reg = 0x3e010,
 858                 .enable_mask = BIT(0),
 859                 .hw.init = &(struct clk_init_data){
 860                         .name = "gcc_aggre_usb3_prim_axi_clk",
 861                         .parent_hws = (const struct clk_hw*[]){
 862                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
 863                         },
 864                         .num_parents = 1,
 865                         .flags = CLK_SET_RATE_PARENT,
 866                         .ops = &clk_branch2_ops,
 867                 },
 868         },
 869 };
 870
 871 static struct clk_branch gcc_boot_rom_ahb_clk = {
 872         .halt_reg = 0x26004,
 873         .halt_check = BRANCH_HALT_VOTED,
 874         .hwcg_reg = 0x26004,
 875         .hwcg_bit = 1,
 876         .clkr = {
 877                 .enable_reg = 0x52000,
 878                 .enable_mask = BIT(28),
 879                 .hw.init = &(struct clk_init_data){
 880                         .name = "gcc_boot_rom_ahb_clk",
 881                         .ops = &clk_branch2_ops,
 882                 },
 883         },
 884 };
 885
 886 static struct clk_branch gcc_camera_ahb_clk = {
 887         .halt_reg = 0x17008,
 888         .halt_check = BRANCH_HALT,
 889         .hwcg_reg = 0x17008,
 890         .hwcg_bit = 1,
 891         .clkr = {
 892                 .enable_reg = 0x17008,
 893                 .enable_mask = BIT(0),
 894                 .hw.init = &(struct clk_init_data){
 895                         .name = "gcc_camera_ahb_clk",
 896                         .flags = CLK_IS_CRITICAL,
 897                         .ops = &clk_branch2_ops,
 898                 },
 899         },
 900 };
 901
 902 static struct clk_branch gcc_camera_axi_clk = {
 903         .halt_reg = 0x17018,
 904         .halt_check = BRANCH_HALT,
 905         .hwcg_reg = 0x17018,
 906         .hwcg_bit = 1,
 907         .clkr = {
 908                 .enable_reg = 0x17018,
 909                 .enable_mask = BIT(0),
 910                 .hw.init = &(struct clk_init_data){
 911                         .name = "gcc_camera_axi_clk",
 912                         .ops = &clk_branch2_ops,
 913                 },
 914         },
 915 };
 916
 917 static struct clk_branch gcc_camera_throttle_nrt_axi_clk = {
 918         .halt_reg = 0x17078,
 919         .halt_check = BRANCH_VOTED,
 920         .hwcg_reg = 0x17078,
 921         .hwcg_bit = 1,
 922         .clkr = {
 923                 .enable_reg = 0x17078,
 924                 .enable_mask = BIT(0),
 925                 .hw.init = &(struct clk_init_data){
 926                         .name = "gcc_camera_throttle_nrt_axi_clk",
 927                         .ops = &clk_branch2_ops,
 928                 },
 929         },
 930 };
 931
 932 static struct clk_branch gcc_camera_throttle_rt_axi_clk = {
 933         .halt_reg = 0x17024,
 934         .halt_check = BRANCH_VOTED,
 935         .hwcg_reg = 0x17024,
 936         .hwcg_bit = 1,
 937         .clkr = {
 938                 .enable_reg = 0x17024,
 939                 .enable_mask = BIT(0),
 940                 .hw.init = &(struct clk_init_data){
 941                         .name = "gcc_camera_throttle_rt_axi_clk",
 942                         .ops = &clk_branch2_ops,
 943                 },
 944         },
 945 };
 946
 947 static struct clk_branch gcc_camera_xo_clk = {
 948         .halt_reg = 0x17030,
 949         .halt_check = BRANCH_HALT,
 950         .clkr = {
 951                 .enable_reg = 0x17030,
 952                 .enable_mask = BIT(0),
 953                 .hw.init = &(struct clk_init_data){
 954                         .name = "gcc_camera_xo_clk",
 955                         .flags = CLK_IS_CRITICAL,
 956                         .ops = &clk_branch2_ops,
 957                 },
 958         },
 959 };
 960
 961 static struct clk_branch gcc_ce1_ahb_clk = {
 962         .halt_reg = 0x2b00c,
 963         .halt_check = BRANCH_HALT_VOTED,
 964         .hwcg_reg = 0x2b00c,
 965         .hwcg_bit = 1,
 966         .clkr = {
 967                 .enable_reg = 0x52008,
 968                 .enable_mask = BIT(3),
 969                 .hw.init = &(struct clk_init_data){
 970                         .name = "gcc_ce1_ahb_clk",
 971                         .ops = &clk_branch2_ops,
 972                 },
 973         },
 974 };
 975
 976 static struct clk_branch gcc_ce1_axi_clk = {
 977         .halt_reg = 0x2b008,
 978         .halt_check = BRANCH_HALT_VOTED,
 979         .clkr = {
 980                 .enable_reg = 0x52008,
 981                 .enable_mask = BIT(2),
 982                 .hw.init = &(struct clk_init_data){
 983                         .name = "gcc_ce1_axi_clk",
 984                         .ops = &clk_branch2_ops,
 985                 },
 986         },
 987 };
 988
 989 static struct clk_branch gcc_ce1_clk = {
 990         .halt_reg = 0x2b004,
 991         .halt_check = BRANCH_HALT_VOTED,
 992         .clkr = {
 993                 .enable_reg = 0x52008,
 994                 .enable_mask = BIT(1),
 995                 .hw.init = &(struct clk_init_data){
 996                         .name = "gcc_ce1_clk",
 997                         .ops = &clk_branch2_ops,
 998                 },
 999         },
1000 };
1001
1002 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1003         .halt_reg = 0x1101c,
1004         .halt_check = BRANCH_HALT,
1005         .hwcg_reg = 0x1101c,
1006         .hwcg_bit = 1,
1007         .clkr = {
1008                 .enable_reg = 0x1101c,
1009                 .enable_mask = BIT(0),
1010                 .hw.init = &(struct clk_init_data){
1011                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1012                         .parent_hws = (const struct clk_hw*[]){
1013                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1014                         },
1015                         .num_parents = 1,
1016                         .flags = CLK_SET_RATE_PARENT,
1017                         .ops = &clk_branch2_ops,
1018                 },
1019         },
1020 };
1021
1022 static struct clk_branch gcc_cpuss_ahb_clk = {
1023         .halt_reg = 0x30000,
1024         .halt_check = BRANCH_HALT_VOTED,
1025         .hwcg_reg = 0x30000,
1026         .hwcg_bit = 1,
1027         .clkr = {
1028                 .enable_reg = 0x52008,
1029                 .enable_mask = BIT(4),
1030                 .hw.init = &(struct clk_init_data){
1031                         .name = "gcc_cpuss_ahb_clk",
1032                         .parent_hws = (const struct clk_hw*[]){
1033                                 &gcc_cpuss_ahb_clk_src.clkr.hw,
1034                         },
1035                         .num_parents = 1,
1036                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1037                         .ops = &clk_branch2_ops,
1038                 },
1039         },
1040 };
1041
1042 static struct clk_branch gcc_cpuss_gnoc_clk = {
1043         .halt_reg = 0x30004,
1044         .halt_check = BRANCH_HALT_VOTED,
1045         .hwcg_reg = 0x30004,
1046         .hwcg_bit = 1,
1047         .clkr = {
1048                 .enable_reg = 0x52008,
1049                 .enable_mask = BIT(5),
1050                 .hw.init = &(struct clk_init_data){
1051                         .name = "gcc_cpuss_gnoc_clk",
1052                         .flags = CLK_IS_CRITICAL,
1053                         .ops = &clk_branch2_ops,
1054                 },
1055         },
1056 };
1057
1058 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1059         .halt_reg = 0x30008,
1060         .halt_check = BRANCH_HALT,
1061         .clkr = {
1062                 .enable_reg = 0x30008,
1063                 .enable_mask = BIT(0),
1064                 .hw.init = &(struct clk_init_data){
1065                         .name = "gcc_cpuss_rbcpr_clk",
1066                         .ops = &clk_branch2_ops,
1067                 },
1068         },
1069 };
1070
1071 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1072         .halt_reg = 0x2d038,
1073         .halt_check = BRANCH_VOTED,
1074         .hwcg_reg = 0x2d038,
1075         .hwcg_bit = 1,
1076         .clkr = {
1077                 .enable_reg = 0x2d038,
1078                 .enable_mask = BIT(0),
1079                 .hw.init = &(struct clk_init_data){
1080                         .name = "gcc_ddrss_gpu_axi_clk",
1081                         .ops = &clk_branch2_ops,
1082                 },
1083         },
1084 };
1085
1086 static struct clk_branch gcc_disp_ahb_clk = {
1087         .halt_reg = 0x1700c,
1088         .halt_check = BRANCH_HALT,
1089         .hwcg_reg = 0x1700c,
1090         .hwcg_bit = 1,
1091         .clkr = {
1092                 .enable_reg = 0x1700c,
1093                 .enable_mask = BIT(0),
1094                 .hw.init = &(struct clk_init_data){
1095                         .name = "gcc_disp_ahb_clk",
1096                         .flags = CLK_IS_CRITICAL,
1097                         .ops = &clk_branch2_ops,
1098                 },
1099         },
1100 };
1101
1102 static struct clk_branch gcc_disp_axi_clk = {
1103         .halt_reg = 0x1701c,
1104         .halt_check = BRANCH_HALT,
1105         .hwcg_reg = 0x1701c,
1106         .hwcg_bit = 1,
1107         .clkr = {
1108                 .enable_reg = 0x1701c,
1109                 .enable_mask = BIT(0),
1110                 .hw.init = &(struct clk_init_data){
1111                         .name = "gcc_disp_axi_clk",
1112                         .ops = &clk_branch2_ops,
1113                 },
1114         },
1115 };
1116
1117 static struct clk_branch gcc_disp_cc_sleep_clk = {
1118         .halt_reg = 0x17074,
1119         .halt_check = BRANCH_HALT_DELAY,
1120         .hwcg_reg = 0x17074,
1121         .hwcg_bit = 1,
1122         .clkr = {
1123                 .enable_reg = 0x17074,
1124                 .enable_mask = BIT(0),
1125                 .hw.init = &(struct clk_init_data){
1126                         .name = "gcc_disp_cc_sleep_clk",
1127                         .ops = &clk_branch2_ops,
1128                 },
1129         },
1130 };
1131
1132 static struct clk_branch gcc_disp_cc_xo_clk = {
1133         .halt_reg = 0x17070,
1134         .halt_check = BRANCH_HALT,
1135         .hwcg_reg = 0x17070,
1136         .hwcg_bit = 1,
1137         .clkr = {
1138                 .enable_reg = 0x17070,
1139                 .enable_mask = BIT(0),
1140                 .hw.init = &(struct clk_init_data){
1141                         .name = "gcc_disp_cc_xo_clk",
1142                         .flags = CLK_IS_CRITICAL,
1143                         .ops = &clk_branch2_ops,
1144                 },
1145         },
1146 };
1147
1148 static struct clk_branch gcc_disp_gpll0_clk = {
1149         .halt_check = BRANCH_HALT_DELAY,
1150         .clkr = {
1151                 .enable_reg = 0x52000,
1152                 .enable_mask = BIT(2),
1153                 .hw.init = &(struct clk_init_data){
1154                         .name = "gcc_disp_gpll0_clk",
1155                         .parent_hws = (const struct clk_hw*[]){
1156                                 &gpll0.clkr.hw,
1157                         },
1158                         .num_parents = 1,
1159                         .ops = &clk_branch2_ops,
1160                 },
1161         },
1162 };
1163
1164 static struct clk_branch gcc_disp_throttle_axi_clk = {
1165         .halt_reg = 0x17028,
1166         .halt_check = BRANCH_HALT,
1167         .hwcg_reg = 0x17028,
1168         .hwcg_bit = 1,
1169         .clkr = {
1170                 .enable_reg = 0x17028,
1171                 .enable_mask = BIT(0),
1172                 .hw.init = &(struct clk_init_data){
1173                         .name = "gcc_disp_throttle_axi_clk",
1174                         .ops = &clk_branch2_ops,
1175                 },
1176         },
1177 };
1178
1179 static struct clk_branch gcc_disp_xo_clk = {
1180         .halt_reg = 0x17034,
1181         .halt_check = BRANCH_HALT,
1182         .clkr = {
1183                 .enable_reg = 0x17034,
1184                 .enable_mask = BIT(0),
1185                 .hw.init = &(struct clk_init_data){
1186                         .name = "gcc_disp_xo_clk",
1187                         .ops = &clk_branch2_ops,
1188                 },
1189         },
1190 };
1191
1192 static struct clk_branch gcc_gp1_clk = {
1193         .halt_reg = 0x37000,
1194         .halt_check = BRANCH_HALT,
1195         .clkr = {
1196                 .enable_reg = 0x37000,
1197                 .enable_mask = BIT(0),
1198                 .hw.init = &(struct clk_init_data){
1199                         .name = "gcc_gp1_clk",
1200                         .parent_hws = (const struct clk_hw*[]){
1201                                 &gcc_gp1_clk_src.clkr.hw,
1202                         },
1203                         .num_parents = 1,
1204                         .flags = CLK_SET_RATE_PARENT,
1205                         .ops = &clk_branch2_ops,
1206                 },
1207         },
1208 };
1209
1210 static struct clk_branch gcc_gp2_clk = {
1211         .halt_reg = 0x38000,
1212         .halt_check = BRANCH_HALT,
1213         .clkr = {
1214                 .enable_reg = 0x38000,
1215                 .enable_mask = BIT(0),
1216                 .hw.init = &(struct clk_init_data){
1217                         .name = "gcc_gp2_clk",
1218                         .parent_hws = (const struct clk_hw*[]){
1219                                 &gcc_gp2_clk_src.clkr.hw,
1220                         },
1221                         .num_parents = 1,
1222                         .flags = CLK_SET_RATE_PARENT,
1223                         .ops = &clk_branch2_ops,
1224                 },
1225         },
1226 };
1227
1228 static struct clk_branch gcc_gp3_clk = {
1229         .halt_reg = 0x39000,
1230         .halt_check = BRANCH_HALT,
1231         .clkr = {
1232                 .enable_reg = 0x39000,
1233                 .enable_mask = BIT(0),
1234                 .hw.init = &(struct clk_init_data){
1235                         .name = "gcc_gp3_clk",
1236                         .parent_hws = (const struct clk_hw*[]){
1237                                 &gcc_gp3_clk_src.clkr.hw,
1238                         },
1239                         .num_parents = 1,
1240                         .flags = CLK_SET_RATE_PARENT,
1241                         .ops = &clk_branch2_ops,
1242                 },
1243         },
1244 };
1245
1246 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1247         .halt_reg = 0x45004,
1248         .halt_check = BRANCH_HALT,
1249         .hwcg_reg = 0x45004,
1250         .hwcg_bit = 1,
1251         .clkr = {
1252                 .enable_reg = 0x45004,
1253                 .enable_mask = BIT(0),
1254                 .hw.init = &(struct clk_init_data){
1255                         .name = "gcc_gpu_cfg_ahb_clk",
1256                         .flags = CLK_IS_CRITICAL,
1257                         .ops = &clk_branch2_ops,
1258                 },
1259         },
1260 };
1261
1262 static struct clk_branch gcc_gpu_gpll0_clk = {
1263         .halt_check = BRANCH_HALT_DELAY,
1264         .clkr = {
1265                 .enable_reg = 0x52008,
1266                 .enable_mask = BIT(7),
1267                 .hw.init = &(struct clk_init_data){
1268                         .name = "gcc_gpu_gpll0_clk",
1269                         .parent_hws = (const struct clk_hw*[]){
1270                                 &gpll0.clkr.hw,
1271                         },
1272                         .num_parents = 1,
1273                         .ops = &clk_branch2_ops,
1274                 },
1275         },
1276 };
1277
1278 static struct clk_branch gcc_gpu_gpll0_div_clk = {
1279         .halt_check = BRANCH_HALT_DELAY,
1280         .clkr = {
1281                 .enable_reg = 0x52008,
1282                 .enable_mask = BIT(8),
1283                 .hw.init = &(struct clk_init_data){
1284                         .name = "gcc_gpu_gpll0_div_clk",
1285                         .parent_hws = (const struct clk_hw*[]){
1286                                 &gcc_gpu_gpll0_main_div_clk_src.clkr.hw,
1287                         },
1288                         .num_parents = 1,
1289                         .ops = &clk_branch2_ops,
1290                 },
1291         },
1292 };
1293
1294 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1295         .halt_reg = 0x4500c,
1296         .halt_check = BRANCH_VOTED,
1297         .hwcg_reg = 0x4500c,
1298         .hwcg_bit = 1,
1299         .clkr = {
1300                 .enable_reg = 0x4500c,
1301                 .enable_mask = BIT(0),
1302                 .hw.init = &(struct clk_init_data){
1303                         .name = "gcc_gpu_memnoc_gfx_clk",
1304                         .ops = &clk_branch2_ops,
1305                 },
1306         },
1307 };
1308
1309 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1310         .halt_reg = 0x45014,
1311         .halt_check = BRANCH_HALT,
1312         .hwcg_reg = 0x45014,
1313         .hwcg_bit = 1,
1314         .clkr = {
1315                 .enable_reg = 0x45014,
1316                 .enable_mask = BIT(0),
1317                 .hw.init = &(struct clk_init_data){
1318                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1319                         .ops = &clk_branch2_ops,
1320                 },
1321         },
1322 };
1323
1324 static struct clk_branch gcc_npu_axi_clk = {
1325         .halt_reg = 0x4c008,
1326         .halt_check = BRANCH_VOTED,
1327         .hwcg_reg = 0x4c008,
1328         .hwcg_bit = 1,
1329         .clkr = {
1330                 .enable_reg = 0x4c008,
1331                 .enable_mask = BIT(0),
1332                 .hw.init = &(struct clk_init_data){
1333                         .name = "gcc_npu_axi_clk",
1334                         .ops = &clk_branch2_ops,
1335                 },
1336         },
1337 };
1338
1339 static struct clk_branch gcc_npu_bwmon_axi_clk = {
1340         .halt_reg = 0x4d004,
1341         .halt_check = BRANCH_HALT_DELAY,
1342         .hwcg_reg = 0x4d004,
1343         .hwcg_bit = 1,
1344         .clkr = {
1345                 .enable_reg = 0x4d004,
1346                 .enable_mask = BIT(0),
1347                 .hw.init = &(struct clk_init_data){
1348                         .name = "gcc_npu_bwmon_axi_clk",
1349                         .ops = &clk_branch2_ops,
1350                 },
1351         },
1352 };
1353
1354 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
1355         .halt_reg = 0x4d008,
1356         .halt_check = BRANCH_HALT,
1357         .clkr = {
1358                 .enable_reg = 0x4d008,
1359                 .enable_mask = BIT(0),
1360                 .hw.init = &(struct clk_init_data){
1361                         .name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
1362                         .ops = &clk_branch2_ops,
1363                 },
1364         },
1365 };
1366
1367 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
1368         .halt_reg = 0x4d00c,
1369         .halt_check = BRANCH_HALT,
1370         .clkr = {
1371                 .enable_reg = 0x4d00c,
1372                 .enable_mask = BIT(0),
1373                 .hw.init = &(struct clk_init_data){
1374                         .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
1375                         .ops = &clk_branch2_ops,
1376                 },
1377         },
1378 };
1379
1380 static struct clk_branch gcc_npu_cfg_ahb_clk = {
1381         .halt_reg = 0x4c004,
1382         .halt_check = BRANCH_HALT,
1383         .hwcg_reg = 0x4c004,
1384         .hwcg_bit = 1,
1385         .clkr = {
1386                 .enable_reg = 0x4c004,
1387                 .enable_mask = BIT(0),
1388                 .hw.init = &(struct clk_init_data){
1389                         .name = "gcc_npu_cfg_ahb_clk",
1390                         .flags = CLK_IS_CRITICAL,
1391                         .ops = &clk_branch2_ops,
1392                 },
1393         },
1394 };
1395
1396 static struct clk_branch gcc_npu_dma_clk = {
1397         .halt_reg = 0x4c140,
1398         .halt_check = BRANCH_VOTED,
1399         .hwcg_reg = 0x4c140,
1400         .hwcg_bit = 1,
1401         .clkr = {
1402                 .enable_reg = 0x4c140,
1403                 .enable_mask = BIT(0),
1404                 .hw.init = &(struct clk_init_data){
1405                         .name = "gcc_npu_dma_clk",
1406                         .ops = &clk_branch2_ops,
1407                 },
1408         },
1409 };
1410
1411 static struct clk_branch gcc_npu_gpll0_clk = {
1412         .halt_check = BRANCH_HALT_DELAY,
1413         .clkr = {
1414                 .enable_reg = 0x52008,
1415                 .enable_mask = BIT(9),
1416                 .hw.init = &(struct clk_init_data){
1417                         .name = "gcc_npu_gpll0_clk",
1418                         .parent_hws = (const struct clk_hw*[]){
1419                                 &gpll0.clkr.hw,
1420                         },
1421                         .num_parents = 1,
1422                         .ops = &clk_branch2_ops,
1423                 },
1424         },
1425 };
1426
1427 static struct clk_branch gcc_npu_gpll0_div_clk = {
1428         .halt_check = BRANCH_HALT_DELAY,
1429         .clkr = {
1430                 .enable_reg = 0x52008,
1431                 .enable_mask = BIT(10),
1432                 .hw.init = &(struct clk_init_data){
1433                         .name = "gcc_npu_gpll0_div_clk",
1434                         .parent_hws = (const struct clk_hw*[]){
1435                                 &gcc_npu_pll0_main_div_clk_src.clkr.hw,
1436                         },
1437                         .num_parents = 1,
1438                         .ops = &clk_branch2_ops,
1439                 },
1440         },
1441 };
1442
1443 static struct clk_branch gcc_pdm2_clk = {
1444         .halt_reg = 0x2300c,
1445         .halt_check = BRANCH_HALT,
1446         .clkr = {
1447                 .enable_reg = 0x2300c,
1448                 .enable_mask = BIT(0),
1449                 .hw.init = &(struct clk_init_data){
1450                         .name = "gcc_pdm2_clk",
1451                         .parent_hws = (const struct clk_hw*[]){
1452                                 &gcc_pdm2_clk_src.clkr.hw,
1453                         },
1454                         .num_parents = 1,
1455                         .flags = CLK_SET_RATE_PARENT,
1456                         .ops = &clk_branch2_ops,
1457                 },
1458         },
1459 };
1460
1461 static struct clk_branch gcc_pdm_ahb_clk = {
1462         .halt_reg = 0x23004,
1463         .halt_check = BRANCH_HALT,
1464         .hwcg_reg = 0x23004,
1465         .hwcg_bit = 1,
1466         .clkr = {
1467                 .enable_reg = 0x23004,
1468                 .enable_mask = BIT(0),
1469                 .hw.init = &(struct clk_init_data){
1470                         .name = "gcc_pdm_ahb_clk",
1471                         .ops = &clk_branch2_ops,
1472                 },
1473         },
1474 };
1475
1476 static struct clk_branch gcc_pdm_xo4_clk = {
1477         .halt_reg = 0x23008,
1478         .halt_check = BRANCH_HALT,
1479         .clkr = {
1480                 .enable_reg = 0x23008,
1481                 .enable_mask = BIT(0),
1482                 .hw.init = &(struct clk_init_data){
1483                         .name = "gcc_pdm_xo4_clk",
1484                         .ops = &clk_branch2_ops,
1485                 },
1486         },
1487 };
1488
1489 static struct clk_branch gcc_prng_ahb_clk = {
1490         .halt_reg = 0x24004,
1491         .halt_check = BRANCH_HALT_VOTED,
1492         .hwcg_reg = 0x24004,
1493         .hwcg_bit = 1,
1494         .clkr = {
1495                 .enable_reg = 0x52000,
1496                 .enable_mask = BIT(26),
1497                 .hw.init = &(struct clk_init_data){
1498                         .name = "gcc_prng_ahb_clk",
1499                         .ops = &clk_branch2_ops,
1500                 },
1501         },
1502 };
1503
1504 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1505         .halt_reg = 0x21014,
1506         .halt_check = BRANCH_HALT_VOTED,
1507         .clkr = {
1508                 .enable_reg = 0x52000,
1509                 .enable_mask = BIT(9),
1510                 .hw.init = &(struct clk_init_data){
1511                         .name = "gcc_qupv3_wrap0_core_2x_clk",
1512                         .ops = &clk_branch2_ops,
1513                 },
1514         },
1515 };
1516
1517 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1518         .halt_reg = 0x2100c,
1519         .halt_check = BRANCH_HALT_VOTED,
1520         .clkr = {
1521                 .enable_reg = 0x52000,
1522                 .enable_mask = BIT(8),
1523                 .hw.init = &(struct clk_init_data){
1524                         .name = "gcc_qupv3_wrap0_core_clk",
1525                         .ops = &clk_branch2_ops,
1526                 },
1527         },
1528 };
1529
1530 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1531         .halt_reg = 0x21144,
1532         .halt_check = BRANCH_HALT_VOTED,
1533         .clkr = {
1534                 .enable_reg = 0x52000,
1535                 .enable_mask = BIT(10),
1536                 .hw.init = &(struct clk_init_data){
1537                         .name = "gcc_qupv3_wrap0_s0_clk",
1538                         .parent_hws = (const struct clk_hw*[]){
1539                                 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1540                         },
1541                         .num_parents = 1,
1542                         .flags = CLK_SET_RATE_PARENT,
1543                         .ops = &clk_branch2_ops,
1544                 },
1545         },
1546 };
1547
1548 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1549         .halt_reg = 0x21274,
1550         .halt_check = BRANCH_HALT_VOTED,
1551         .clkr = {
1552                 .enable_reg = 0x52000,
1553                 .enable_mask = BIT(11),
1554                 .hw.init = &(struct clk_init_data){
1555                         .name = "gcc_qupv3_wrap0_s1_clk",
1556                         .parent_hws = (const struct clk_hw*[]){
1557                                 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1558                         },
1559                         .num_parents = 1,
1560                         .flags = CLK_SET_RATE_PARENT,
1561                         .ops = &clk_branch2_ops,
1562                 },
1563         },
1564 };
1565
1566 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1567         .halt_reg = 0x213a4,
1568         .halt_check = BRANCH_HALT_VOTED,
1569         .clkr = {
1570                 .enable_reg = 0x52000,
1571                 .enable_mask = BIT(12),
1572                 .hw.init = &(struct clk_init_data){
1573                         .name = "gcc_qupv3_wrap0_s2_clk",
1574                         .parent_hws = (const struct clk_hw*[]){
1575                                 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1576                         },
1577                         .num_parents = 1,
1578                         .flags = CLK_SET_RATE_PARENT,
1579                         .ops = &clk_branch2_ops,
1580                 },
1581         },
1582 };
1583
1584 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1585         .halt_reg = 0x214d4,
1586         .halt_check = BRANCH_HALT_VOTED,
1587         .clkr = {
1588                 .enable_reg = 0x52000,
1589                 .enable_mask = BIT(13),
1590                 .hw.init = &(struct clk_init_data){
1591                         .name = "gcc_qupv3_wrap0_s3_clk",
1592                         .parent_hws = (const struct clk_hw*[]){
1593                                 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1594                         },
1595                         .num_parents = 1,
1596                         .flags = CLK_SET_RATE_PARENT,
1597                         .ops = &clk_branch2_ops,
1598                 },
1599         },
1600 };
1601
1602 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1603         .halt_reg = 0x21604,
1604         .halt_check = BRANCH_HALT_VOTED,
1605         .clkr = {
1606                 .enable_reg = 0x52000,
1607                 .enable_mask = BIT(14),
1608                 .hw.init = &(struct clk_init_data){
1609                         .name = "gcc_qupv3_wrap0_s4_clk",
1610                         .parent_hws = (const struct clk_hw*[]){
1611                                 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1612                         },
1613                         .num_parents = 1,
1614                         .flags = CLK_SET_RATE_PARENT,
1615                         .ops = &clk_branch2_ops,
1616                 },
1617         },
1618 };
1619
1620 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1621         .halt_reg = 0x21734,
1622         .halt_check = BRANCH_HALT_VOTED,
1623         .clkr = {
1624                 .enable_reg = 0x52000,
1625                 .enable_mask = BIT(15),
1626                 .hw.init = &(struct clk_init_data){
1627                         .name = "gcc_qupv3_wrap0_s5_clk",
1628                         .parent_hws = (const struct clk_hw*[]){
1629                                 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1630                         },
1631                         .num_parents = 1,
1632                         .flags = CLK_SET_RATE_PARENT,
1633                         .ops = &clk_branch2_ops,
1634                 },
1635         },
1636 };
1637
1638 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1639         .halt_reg = 0x22004,
1640         .halt_check = BRANCH_HALT_VOTED,
1641         .clkr = {
1642                 .enable_reg = 0x52000,
1643                 .enable_mask = BIT(16),
1644                 .hw.init = &(struct clk_init_data){
1645                         .name = "gcc_qupv3_wrap1_core_2x_clk",
1646                         .ops = &clk_branch2_ops,
1647                 },
1648         },
1649 };
1650
1651 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1652         .halt_reg = 0x22008,
1653         .halt_check = BRANCH_HALT_VOTED,
1654         .clkr = {
1655                 .enable_reg = 0x52000,
1656                 .enable_mask = BIT(17),
1657                 .hw.init = &(struct clk_init_data){
1658                         .name = "gcc_qupv3_wrap1_core_clk",
1659                         .ops = &clk_branch2_ops,
1660                 },
1661         },
1662 };
1663
1664 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1665         .halt_reg = 0x22014,
1666         .halt_check = BRANCH_HALT_VOTED,
1667         .clkr = {
1668                 .enable_reg = 0x52000,
1669                 .enable_mask = BIT(20),
1670                 .hw.init = &(struct clk_init_data){
1671                         .name = "gcc_qupv3_wrap1_s0_clk",
1672                         .parent_hws = (const struct clk_hw*[]){
1673                                 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1674                         },
1675                         .num_parents = 1,
1676                         .flags = CLK_SET_RATE_PARENT,
1677                         .ops = &clk_branch2_ops,
1678                 },
1679         },
1680 };
1681
1682 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1683         .halt_reg = 0x22144,
1684         .halt_check = BRANCH_HALT_VOTED,
1685         .clkr = {
1686                 .enable_reg = 0x52000,
1687                 .enable_mask = BIT(21),
1688                 .hw.init = &(struct clk_init_data){
1689                         .name = "gcc_qupv3_wrap1_s1_clk",
1690                         .parent_hws = (const struct clk_hw*[]){
1691                                 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1692                         },
1693                         .num_parents = 1,
1694                         .flags = CLK_SET_RATE_PARENT,
1695                         .ops = &clk_branch2_ops,
1696                 },
1697         },
1698 };
1699
1700 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1701         .halt_reg = 0x22274,
1702         .halt_check = BRANCH_HALT_VOTED,
1703         .clkr = {
1704                 .enable_reg = 0x52000,
1705                 .enable_mask = BIT(22),
1706                 .hw.init = &(struct clk_init_data){
1707                         .name = "gcc_qupv3_wrap1_s2_clk",
1708                         .parent_hws = (const struct clk_hw*[]){
1709                                 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1710                         },
1711                         .num_parents = 1,
1712                         .flags = CLK_SET_RATE_PARENT,
1713                         .ops = &clk_branch2_ops,
1714                 },
1715         },
1716 };
1717
1718 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1719         .halt_reg = 0x223a4,
1720         .halt_check = BRANCH_HALT_VOTED,
1721         .clkr = {
1722                 .enable_reg = 0x52000,
1723                 .enable_mask = BIT(23),
1724                 .hw.init = &(struct clk_init_data){
1725                         .name = "gcc_qupv3_wrap1_s3_clk",
1726                         .parent_hws = (const struct clk_hw*[]){
1727                                 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1728                         },
1729                         .num_parents = 1,
1730                         .flags = CLK_SET_RATE_PARENT,
1731                         .ops = &clk_branch2_ops,
1732                 },
1733         },
1734 };
1735
1736 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1737         .halt_reg = 0x224d4,
1738         .halt_check = BRANCH_HALT_VOTED,
1739         .clkr = {
1740                 .enable_reg = 0x52000,
1741                 .enable_mask = BIT(24),
1742                 .hw.init = &(struct clk_init_data){
1743                         .name = "gcc_qupv3_wrap1_s4_clk",
1744                         .parent_hws = (const struct clk_hw*[]){
1745                                 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1746                         },
1747                         .num_parents = 1,
1748                         .flags = CLK_SET_RATE_PARENT,
1749                         .ops = &clk_branch2_ops,
1750                 },
1751         },
1752 };
1753
1754 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
1755         .halt_reg = 0x22604,
1756         .halt_check = BRANCH_HALT_VOTED,
1757         .clkr = {
1758                 .enable_reg = 0x52000,
1759                 .enable_mask = BIT(25),
1760                 .hw.init = &(struct clk_init_data){
1761                         .name = "gcc_qupv3_wrap1_s5_clk",
1762                         .parent_hws = (const struct clk_hw*[]){
1763                                 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1764                         },
1765                         .num_parents = 1,
1766                         .flags = CLK_SET_RATE_PARENT,
1767                         .ops = &clk_branch2_ops,
1768                 },
1769         },
1770 };
1771
1772 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
1773         .halt_reg = 0x21004,
1774         .halt_check = BRANCH_HALT_VOTED,
1775         .hwcg_reg = 0x21004,
1776         .hwcg_bit = 1,
1777         .clkr = {
1778                 .enable_reg = 0x52000,
1779                 .enable_mask = BIT(6),
1780                 .hw.init = &(struct clk_init_data){
1781                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
1782                         .ops = &clk_branch2_ops,
1783                 },
1784         },
1785 };
1786
1787 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
1788         .halt_reg = 0x21008,
1789         .halt_check = BRANCH_HALT_VOTED,
1790         .hwcg_reg = 0x21008,
1791         .hwcg_bit = 1,
1792         .clkr = {
1793                 .enable_reg = 0x52000,
1794                 .enable_mask = BIT(7),
1795                 .hw.init = &(struct clk_init_data){
1796                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
1797                         .ops = &clk_branch2_ops,
1798                 },
1799         },
1800 };
1801
1802 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
1803         .halt_reg = 0x2200c,
1804         .halt_check = BRANCH_HALT_VOTED,
1805         .hwcg_reg = 0x2200c,
1806         .hwcg_bit = 1,
1807         .clkr = {
1808                 .enable_reg = 0x52000,
1809                 .enable_mask = BIT(18),
1810                 .hw.init = &(struct clk_init_data){
1811                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
1812                         .ops = &clk_branch2_ops,
1813                 },
1814         },
1815 };
1816
1817 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
1818         .halt_reg = 0x22010,
1819         .halt_check = BRANCH_HALT_VOTED,
1820         .hwcg_reg = 0x22010,
1821         .hwcg_bit = 1,
1822         .clkr = {
1823                 .enable_reg = 0x52000,
1824                 .enable_mask = BIT(19),
1825                 .hw.init = &(struct clk_init_data){
1826                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
1827                         .ops = &clk_branch2_ops,
1828                 },
1829         },
1830 };
1831
1832 static struct clk_branch gcc_sdcc1_ahb_clk = {
1833         .halt_reg = 0x4b004,
1834         .halt_check = BRANCH_HALT,
1835         .clkr = {
1836                 .enable_reg = 0x4b004,
1837                 .enable_mask = BIT(0),
1838                 .hw.init = &(struct clk_init_data){
1839                         .name = "gcc_sdcc1_ahb_clk",
1840                         .ops = &clk_branch2_ops,
1841                 },
1842         },
1843 };
1844
1845 static struct clk_branch gcc_sdcc1_apps_clk = {
1846         .halt_reg = 0x4b008,
1847         .halt_check = BRANCH_HALT,
1848         .clkr = {
1849                 .enable_reg = 0x4b008,
1850                 .enable_mask = BIT(0),
1851                 .hw.init = &(struct clk_init_data){
1852                         .name = "gcc_sdcc1_apps_clk",
1853                         .parent_hws = (const struct clk_hw*[]){
1854                                 &gcc_sdcc1_apps_clk_src.clkr.hw,
1855                         },
1856                         .num_parents = 1,
1857                         .flags = CLK_SET_RATE_PARENT,
1858                         .ops = &clk_branch2_ops,
1859                 },
1860         },
1861 };
1862
1863 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1864         .halt_reg = 0x4b03c,
1865         .halt_check = BRANCH_HALT,
1866         .hwcg_reg = 0x4b03c,
1867         .hwcg_bit = 1,
1868         .clkr = {
1869                 .enable_reg = 0x4b03c,
1870                 .enable_mask = BIT(0),
1871                 .hw.init = &(struct clk_init_data){
1872                         .name = "gcc_sdcc1_ice_core_clk",
1873                         .parent_hws = (const struct clk_hw*[]){
1874                                 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
1875                         },
1876                         .num_parents = 1,
1877                         .flags = CLK_SET_RATE_PARENT,
1878                         .ops = &clk_branch2_ops,
1879                 },
1880         },
1881 };
1882
1883 static struct clk_branch gcc_sdcc2_ahb_clk = {
1884         .halt_reg = 0x20008,
1885         .halt_check = BRANCH_HALT,
1886         .clkr = {
1887                 .enable_reg = 0x20008,
1888                 .enable_mask = BIT(0),
1889                 .hw.init = &(struct clk_init_data){
1890                         .name = "gcc_sdcc2_ahb_clk",
1891                         .ops = &clk_branch2_ops,
1892                 },
1893         },
1894 };
1895
1896 static struct clk_branch gcc_sdcc2_apps_clk = {
1897         .halt_reg = 0x20004,
1898         .halt_check = BRANCH_HALT,
1899         .clkr = {
1900                 .enable_reg = 0x20004,
1901                 .enable_mask = BIT(0),
1902                 .hw.init = &(struct clk_init_data){
1903                         .name = "gcc_sdcc2_apps_clk",
1904                         .parent_hws = (const struct clk_hw*[]){
1905                                 &gcc_sdcc2_apps_clk_src.clkr.hw,
1906                         },
1907                         .num_parents = 1,
1908                         .flags = CLK_SET_RATE_PARENT,
1909                         .ops = &clk_branch2_ops,
1910                 },
1911         },
1912 };
1913
1914 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
1915         .halt_reg = 0x10140,
1916         .halt_check = BRANCH_HALT_VOTED,
1917         .hwcg_reg = 0x10140,
1918         .hwcg_bit = 1,
1919         .clkr = {
1920                 .enable_reg = 0x52000,
1921                 .enable_mask = BIT(0),
1922                 .hw.init = &(struct clk_init_data){
1923                         .name = "gcc_sys_noc_cpuss_ahb_clk",
1924                         .parent_hws = (const struct clk_hw*[]){
1925                                 &gcc_cpuss_ahb_clk_src.clkr.hw,
1926                         },
1927                         .num_parents = 1,
1928                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1929                         .ops = &clk_branch2_ops,
1930                 },
1931         },
1932 };
1933
1934 static struct clk_branch gcc_ufs_mem_clkref_clk = {
1935         .halt_reg = 0x8c000,
1936         .halt_check = BRANCH_HALT,
1937         .clkr = {
1938                 .enable_reg = 0x8c000,
1939                 .enable_mask = BIT(0),
1940                 .hw.init = &(struct clk_init_data){
1941                         .name = "gcc_ufs_mem_clkref_clk",
1942                         .ops = &clk_branch2_ops,
1943                 },
1944         },
1945 };
1946
1947 static struct clk_branch gcc_ufs_phy_ahb_clk = {
1948         .halt_reg = 0x3a00c,
1949         .halt_check = BRANCH_HALT,
1950         .hwcg_reg = 0x3a00c,
1951         .hwcg_bit = 1,
1952         .clkr = {
1953                 .enable_reg = 0x3a00c,
1954                 .enable_mask = BIT(0),
1955                 .hw.init = &(struct clk_init_data){
1956                         .name = "gcc_ufs_phy_ahb_clk",
1957                         .ops = &clk_branch2_ops,
1958                 },
1959         },
1960 };
1961
1962 static struct clk_branch gcc_ufs_phy_axi_clk = {
1963         .halt_reg = 0x3a034,
1964         .halt_check = BRANCH_HALT,
1965         .hwcg_reg = 0x3a034,
1966         .hwcg_bit = 1,
1967         .clkr = {
1968                 .enable_reg = 0x3a034,
1969                 .enable_mask = BIT(0),
1970                 .hw.init = &(struct clk_init_data){
1971                         .name = "gcc_ufs_phy_axi_clk",
1972                         .parent_hws = (const struct clk_hw*[]){
1973                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1974                         },
1975                         .num_parents = 1,
1976                         .flags = CLK_SET_RATE_PARENT,
1977                         .ops = &clk_branch2_ops,
1978                 },
1979         },
1980 };
1981
1982 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
1983         .halt_reg = 0x3a0a4,
1984         .halt_check = BRANCH_HALT,
1985         .hwcg_reg = 0x3a0a4,
1986         .hwcg_bit = 1,
1987         .clkr = {
1988                 .enable_reg = 0x3a0a4,
1989                 .enable_mask = BIT(0),
1990                 .hw.init = &(struct clk_init_data){
1991                         .name = "gcc_ufs_phy_ice_core_clk",
1992                         .parent_hws = (const struct clk_hw*[]){
1993                                 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
1994                         },
1995                         .num_parents = 1,
1996                         .flags = CLK_SET_RATE_PARENT,
1997                         .ops = &clk_branch2_ops,
1998                 },
1999         },
2000 };
2001
2002 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2003         .halt_reg = 0x3a0a4,
2004         .halt_check = BRANCH_HALT,
2005         .hwcg_reg = 0x3a0a4,
2006         .hwcg_bit = 1,
2007         .clkr = {
2008                 .enable_reg = 0x3a0a4,
2009                 .enable_mask = BIT(1),
2010                 .hw.init = &(struct clk_init_data){
2011                         .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2012                         .parent_hws = (const struct clk_hw*[]){
2013                                 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2014                         },
2015                         .num_parents = 1,
2016                         .flags = CLK_SET_RATE_PARENT,
2017                         .ops = &clk_branch2_ops,
2018                 },
2019         },
2020 };
2021
2022 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2023         .halt_reg = 0x3a0ac,
2024         .halt_check = BRANCH_HALT,
2025         .hwcg_reg = 0x3a0ac,
2026         .hwcg_bit = 1,
2027         .clkr = {
2028                 .enable_reg = 0x3a0ac,
2029                 .enable_mask = BIT(0),
2030                 .hw.init = &(struct clk_init_data){
2031                         .name = "gcc_ufs_phy_phy_aux_clk",
2032                         .parent_hws = (const struct clk_hw*[]){
2033                                 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2034                         },
2035                         .num_parents = 1,
2036                         .flags = CLK_SET_RATE_PARENT,
2037                         .ops = &clk_branch2_ops,
2038                 },
2039         },
2040 };
2041
2042 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2043         .halt_reg = 0x3a0ac,
2044         .halt_check = BRANCH_HALT,
2045         .hwcg_reg = 0x3a0ac,
2046         .hwcg_bit = 1,
2047         .clkr = {
2048                 .enable_reg = 0x3a0ac,
2049                 .enable_mask = BIT(1),
2050                 .hw.init = &(struct clk_init_data){
2051                         .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2052                         .parent_hws = (const struct clk_hw*[]){
2053                                 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2054                         },
2055                         .num_parents = 1,
2056                         .flags = CLK_SET_RATE_PARENT,
2057                         .ops = &clk_branch2_ops,
2058                 },
2059         },
2060 };
2061
2062 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2063         .halt_reg = 0x3a014,
2064         .halt_check = BRANCH_HALT_SKIP,
2065         .clkr = {
2066                 .enable_reg = 0x3a014,
2067                 .enable_mask = BIT(0),
2068                 .hw.init = &(struct clk_init_data){
2069                         .name = "gcc_ufs_phy_rx_symbol_0_clk",
2070                         .ops = &clk_branch2_ops,
2071                 },
2072         },
2073 };
2074
2075 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2076         .halt_reg = 0x3a018,
2077         .halt_check = BRANCH_HALT_SKIP,
2078         .clkr = {
2079                 .enable_reg = 0x3a018,
2080                 .enable_mask = BIT(0),
2081                 .hw.init = &(struct clk_init_data){
2082                         .name = "gcc_ufs_phy_rx_symbol_1_clk",
2083                         .ops = &clk_branch2_ops,
2084                 },
2085         },
2086 };
2087
2088 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2089         .halt_reg = 0x3a010,
2090         .halt_check = BRANCH_HALT_SKIP,
2091         .clkr = {
2092                 .enable_reg = 0x3a010,
2093                 .enable_mask = BIT(0),
2094                 .hw.init = &(struct clk_init_data){
2095                         .name = "gcc_ufs_phy_tx_symbol_0_clk",
2096                         .ops = &clk_branch2_ops,
2097                 },
2098         },
2099 };
2100
2101 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2102         .halt_reg = 0x3a09c,
2103         .halt_check = BRANCH_HALT,
2104         .hwcg_reg = 0x3a09c,
2105         .hwcg_bit = 1,
2106         .clkr = {
2107                 .enable_reg = 0x3a09c,
2108                 .enable_mask = BIT(0),
2109                 .hw.init = &(struct clk_init_data){
2110                         .name = "gcc_ufs_phy_unipro_core_clk",
2111                         .parent_hws = (const struct clk_hw*[]){
2112                                 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2113                         },
2114                         .num_parents = 1,
2115                         .flags = CLK_SET_RATE_PARENT,
2116                         .ops = &clk_branch2_ops,
2117                 },
2118         },
2119 };
2120
2121 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
2122         .halt_reg = 0x3a09c,
2123         .halt_check = BRANCH_HALT,
2124         .hwcg_reg = 0x3a09c,
2125         .hwcg_bit = 1,
2126         .clkr = {
2127                 .enable_reg = 0x3a09c,
2128                 .enable_mask = BIT(1),
2129                 .hw.init = &(struct clk_init_data){
2130                         .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
2131                         .parent_hws = (const struct clk_hw*[]){
2132                                 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2133                         },
2134                         .num_parents = 1,
2135                         .flags = CLK_SET_RATE_PARENT,
2136                         .ops = &clk_branch2_ops,
2137                 },
2138         },
2139 };
2140
2141 static struct clk_branch gcc_usb30_prim_master_clk = {
2142         .halt_reg = 0x1a00c,
2143         .halt_check = BRANCH_HALT,
2144         .clkr = {
2145                 .enable_reg = 0x1a00c,
2146                 .enable_mask = BIT(0),
2147                 .hw.init = &(struct clk_init_data){
2148                         .name = "gcc_usb30_prim_master_clk",
2149                         .parent_hws = (const struct clk_hw*[]){
2150                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
2151                         },
2152                         .num_parents = 1,
2153                         .flags = CLK_SET_RATE_PARENT,
2154                         .ops = &clk_branch2_ops,
2155                 },
2156         },
2157 };
2158
2159 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2160         .halt_reg = 0x1a018,
2161         .halt_check = BRANCH_HALT,
2162         .clkr = {
2163                 .enable_reg = 0x1a018,
2164                 .enable_mask = BIT(0),
2165                 .hw.init = &(struct clk_init_data){
2166                         .name = "gcc_usb30_prim_mock_utmi_clk",
2167                         .parent_hws = (const struct clk_hw*[]){
2168                                 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
2169                         },
2170                         .num_parents = 1,
2171                         .flags = CLK_SET_RATE_PARENT,
2172                         .ops = &clk_branch2_ops,
2173                 },
2174         },
2175 };
2176
2177 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2178         .halt_reg = 0x1a014,
2179         .halt_check = BRANCH_HALT,
2180         .clkr = {
2181                 .enable_reg = 0x1a014,
2182                 .enable_mask = BIT(0),
2183                 .hw.init = &(struct clk_init_data){
2184                         .name = "gcc_usb30_prim_sleep_clk",
2185                         .ops = &clk_branch2_ops,
2186                 },
2187         },
2188 };
2189
2190 static struct clk_branch gcc_usb3_prim_clkref_clk = {
2191         .halt_reg = 0x8c010,
2192         .halt_check = BRANCH_HALT,
2193         .clkr = {
2194                 .enable_reg = 0x8c010,
2195                 .enable_mask = BIT(0),
2196                 .hw.init = &(struct clk_init_data){
2197                         .name = "gcc_usb3_prim_clkref_clk",
2198                         .ops = &clk_branch2_ops,
2199                 },
2200         },
2201 };
2202
2203 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2204         .halt_reg = 0x1a050,
2205         .halt_check = BRANCH_HALT,
2206         .clkr = {
2207                 .enable_reg = 0x1a050,
2208                 .enable_mask = BIT(0),
2209                 .hw.init = &(struct clk_init_data){
2210                         .name = "gcc_usb3_prim_phy_aux_clk",
2211                         .parent_hws = (const struct clk_hw*[]){
2212                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2213                         },
2214                         .num_parents = 1,
2215                         .flags = CLK_SET_RATE_PARENT,
2216                         .ops = &clk_branch2_ops,
2217                 },
2218         },
2219 };
2220
2221 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2222         .halt_reg = 0x1a054,
2223         .halt_check = BRANCH_HALT,
2224         .clkr = {
2225                 .enable_reg = 0x1a054,
2226                 .enable_mask = BIT(0),
2227                 .hw.init = &(struct clk_init_data){
2228                         .name = "gcc_usb3_prim_phy_com_aux_clk",
2229                         .parent_hws = (const struct clk_hw*[]){
2230                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2231                         },
2232                         .num_parents = 1,
2233                         .flags = CLK_SET_RATE_PARENT,
2234                         .ops = &clk_branch2_ops,
2235                 },
2236         },
2237 };
2238
2239 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2240         .halt_reg = 0x1a058,
2241         .halt_check = BRANCH_HALT_SKIP,
2242         .hwcg_reg = 0x1a058,
2243         .hwcg_bit = 1,
2244         .clkr = {
2245                 .enable_reg = 0x1a058,
2246                 .enable_mask = BIT(0),
2247                 .hw.init = &(struct clk_init_data){
2248                         .name = "gcc_usb3_prim_phy_pipe_clk",
2249                         .ops = &clk_branch2_ops,
2250                 },
2251         },
2252 };
2253
2254 static struct clk_branch gcc_video_ahb_clk = {
2255         .halt_reg = 0x17004,
2256         .halt_check = BRANCH_HALT,
2257         .hwcg_reg = 0x17004,
2258         .hwcg_bit = 1,
2259         .clkr = {
2260                 .enable_reg = 0x17004,
2261                 .enable_mask = BIT(0),
2262                 .hw.init = &(struct clk_init_data){
2263                         .name = "gcc_video_ahb_clk",
2264                         .flags = CLK_IS_CRITICAL,
2265                         .ops = &clk_branch2_ops,
2266                 },
2267         },
2268 };
2269
2270 static struct clk_branch gcc_video_axi_clk = {
2271         .halt_reg = 0x17014,
2272         .halt_check = BRANCH_HALT,
2273         .hwcg_reg = 0x17014,
2274         .hwcg_bit = 1,
2275         .clkr = {
2276                 .enable_reg = 0x17014,
2277                 .enable_mask = BIT(0),
2278                 .hw.init = &(struct clk_init_data){
2279                         .name = "gcc_video_axi_clk",
2280                         .ops = &clk_branch2_ops,
2281                 },
2282         },
2283 };
2284
2285 static struct clk_branch gcc_video_throttle_axi_clk = {
2286         .halt_reg = 0x17020,
2287         .halt_check = BRANCH_HALT,
2288         .hwcg_reg = 0x17020,
2289         .hwcg_bit = 1,
2290         .clkr = {
2291                 .enable_reg = 0x17020,
2292                 .enable_mask = BIT(0),
2293                 .hw.init = &(struct clk_init_data){
2294                         .name = "gcc_video_throttle_axi_clk",
2295                         .ops = &clk_branch2_ops,
2296                 },
2297         },
2298 };
2299
2300 static struct clk_branch gcc_video_xo_clk = {
2301         .halt_reg = 0x1702c,
2302         .halt_check = BRANCH_HALT,
2303         .clkr = {
2304                 .enable_reg = 0x1702c,
2305                 .enable_mask = BIT(0),
2306                 .hw.init = &(struct clk_init_data){
2307                         .name = "gcc_video_xo_clk",
2308                         .flags = CLK_IS_CRITICAL,
2309                         .ops = &clk_branch2_ops,
2310                 },
2311         },
2312 };
2313
2314 static struct gdsc usb30_prim_gdsc = {
2315         .gdscr = 0x1a004,
2316         .pd = {
2317                 .name = "usb30_prim_gdsc",
2318         },
2319         .pwrsts = PWRSTS_OFF_ON,
2320 };
2321
2322 static struct gdsc ufs_phy_gdsc = {
2323         .gdscr = 0x3a004,
2324         .pd = {
2325                 .name = "ufs_phy_gdsc",
2326         },
2327         .pwrsts = PWRSTS_OFF_ON,
2328 };
2329
2330 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
2331         .gdscr = 0xb7040,
2332         .pd = {
2333                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
2334         },
2335         .pwrsts = PWRSTS_OFF_ON,
2336         .flags = VOTABLE,
2337 };
2338
2339 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
2340         .gdscr = 0xb7044,
2341         .pd = {
2342                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
2343         },
2344         .pwrsts = PWRSTS_OFF_ON,
2345         .flags = VOTABLE,
2346 };
2347
2348 static struct clk_regmap *gcc_sm6350_clocks[] = {
2349         [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2350         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2351         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2352         [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
2353         [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
2354         [GCC_CAMERA_THROTTLE_NRT_AXI_CLK] =
2355                 &gcc_camera_throttle_nrt_axi_clk.clkr,
2356         [GCC_CAMERA_THROTTLE_RT_AXI_CLK] = &gcc_camera_throttle_rt_axi_clk.clkr,
2357         [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
2358         [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2359         [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2360         [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2361         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2362         [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
2363         [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
2364         [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
2365         [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
2366         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2367         [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
2368         [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
2369         [GCC_DISP_CC_SLEEP_CLK] = &gcc_disp_cc_sleep_clk.clkr,
2370         [GCC_DISP_CC_XO_CLK] = &gcc_disp_cc_xo_clk.clkr,
2371         [GCC_DISP_GPLL0_CLK] = &gcc_disp_gpll0_clk.clkr,
2372         [GCC_DISP_THROTTLE_AXI_CLK] = &gcc_disp_throttle_axi_clk.clkr,
2373         [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
2374         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2375         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2376         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2377         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2378         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2379         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2380         [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2381         [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
2382         [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
2383         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2384         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2385         [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
2386         [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
2387         [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
2388         [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
2389         [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
2390         [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
2391         [GCC_NPU_GPLL0_CLK] = &gcc_npu_gpll0_clk.clkr,
2392         [GCC_NPU_GPLL0_DIV_CLK] = &gcc_npu_gpll0_div_clk.clkr,
2393         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2394         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2395         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2396         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2397         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2398         [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2399         [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2400         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2401         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2402         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2403         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2404         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2405         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2406         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2407         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2408         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2409         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2410         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2411         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2412         [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2413         [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2414         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2415         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2416         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2417         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2418         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2419         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2420         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2421         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2422         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2423         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2424         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2425         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2426         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2427         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2428         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2429         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2430         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2431         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2432         [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2433         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2434         [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2435         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2436         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2437         [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2438         [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2439         [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
2440         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
2441         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
2442         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
2443         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
2444         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
2445         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
2446         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
2447         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
2448         [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
2449         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
2450         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
2451         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
2452                 &gcc_ufs_phy_unipro_core_clk_src.clkr,
2453         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2454         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2455         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2456         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
2457                 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2458         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2459         [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2460         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2461         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2462         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2463         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2464         [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
2465         [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
2466         [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
2467         [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
2468         [GPLL0] = &gpll0.clkr,
2469         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2470         [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
2471         [GPLL6] = &gpll6.clkr,
2472         [GPLL6_OUT_EVEN] = &gpll6_out_even.clkr,
2473         [GPLL7] = &gpll7.clkr,
2474         [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
2475         [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
2476         [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
2477                                 &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
2478         [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
2479                                 &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
2480         [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
2481                                 &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
2482         [GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_gpu_gpll0_main_div_clk_src.clkr,
2483         [GCC_NPU_PLL0_MAIN_DIV_CLK_SRC] = &gcc_npu_pll0_main_div_clk_src.clkr,
2484 };
2485
2486 static struct gdsc *gcc_sm6350_gdscs[] = {
2487         [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2488         [UFS_PHY_GDSC] = &ufs_phy_gdsc,
2489         [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
2490         [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
2491 };
2492
2493 static const struct qcom_reset_map gcc_sm6350_resets[] = {
2494         [GCC_QUSB2PHY_PRIM_BCR] = { 0x1d000 },
2495         [GCC_QUSB2PHY_SEC_BCR] = { 0x1e000 },
2496         [GCC_SDCC1_BCR] = { 0x4b000 },
2497         [GCC_SDCC2_BCR] = { 0x20000 },
2498         [GCC_UFS_PHY_BCR] = { 0x3a000 },
2499         [GCC_USB30_PRIM_BCR] = { 0x1a000 },
2500         [GCC_USB3_PHY_PRIM_BCR] = { 0x1c000 },
2501         [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1c008 },
2502 };
2503
2504 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2505         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2506         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2507         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2508         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2509         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2510         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2511         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2512         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2513         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2514         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2515         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2516         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2517 };
2518
2519 static const struct regmap_config gcc_sm6350_regmap_config = {
2520         .reg_bits = 32,
2521         .reg_stride = 4,
2522         .val_bits = 32,
2523         .max_register = 0xbf030,
2524         .fast_io = true,
2525 };
2526
2527 static const struct qcom_cc_desc gcc_sm6350_desc = {
2528         .config = &gcc_sm6350_regmap_config,
2529         .clks = gcc_sm6350_clocks,
2530         .num_clks = ARRAY_SIZE(gcc_sm6350_clocks),
2531         .resets = gcc_sm6350_resets,
2532         .num_resets = ARRAY_SIZE(gcc_sm6350_resets),
2533         .gdscs = gcc_sm6350_gdscs,
2534         .num_gdscs = ARRAY_SIZE(gcc_sm6350_gdscs),
2535 };
2536
2537 static const struct of_device_id gcc_sm6350_match_table[] = {
2538         { .compatible = "qcom,gcc-sm6350" },
2539         { }
2540 };
2541 MODULE_DEVICE_TABLE(of, gcc_sm6350_match_table);
2542
2543 static int gcc_sm6350_probe(struct platform_device *pdev)
2544 {
2545         struct regmap *regmap;
2546         int ret;
2547
2548         regmap = qcom_cc_map(pdev, &gcc_sm6350_desc);
2549         if (IS_ERR(regmap))
2550                 return PTR_ERR(regmap);
2551
2552         /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
2553         regmap_update_bits(regmap, 0x4cf00, 0x3, 0x3);
2554         regmap_update_bits(regmap, 0x45f00, 0x3, 0x3);
2555
2556         ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2557                         ARRAY_SIZE(gcc_dfs_clocks));
2558         if (ret)
2559                 return ret;
2560
2561         return qcom_cc_really_probe(pdev, &gcc_sm6350_desc, regmap);;
2562 }
2563
2564 static struct platform_driver gcc_sm6350_driver = {
2565         .probe = gcc_sm6350_probe,
2566         .driver = {
2567                 .name = "gcc-sm6350",
2568                 .of_match_table = gcc_sm6350_match_table,
2569         },
2570 };
2571
2572 static int __init gcc_sm6350_init(void)
2573 {
2574         return platform_driver_register(&gcc_sm6350_driver);
2575 }
2576 core_initcall(gcc_sm6350_init);
2577
2578 static void __exit gcc_sm6350_exit(void)
2579 {
2580         platform_driver_unregister(&gcc_sm6350_driver);
2581 }
2582 module_exit(gcc_sm6350_exit);
2583
2584 MODULE_DESCRIPTION("QTI GCC SM6350 Driver");
2585 MODULE_LICENSE("GPL v2");