drivers/clk/qcom/gcc-sm6350.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2021, Konrad Dybcio <[email protected]>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/module.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/regmap.h>
  11
  12 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
  13
  14 #include "clk-alpha-pll.h"
  15 #include "clk-branch.h"
  16 #include "clk-rcg.h"
  17 #include "clk-regmap.h"
  18 #include "clk-regmap-divider.h"
  19 #include "clk-regmap-mux.h"
  20 #include "common.h"
  21 #include "gdsc.h"
  22 #include "reset.h"
  23
  24 enum {
  25         P_BI_TCXO,
  26         P_GPLL0_OUT_EVEN,
  27         P_GPLL0_OUT_MAIN,
  28         P_GPLL0_OUT_ODD,
  29         P_GPLL6_OUT_EVEN,
  30         P_GPLL7_OUT_MAIN,
  31         P_SLEEP_CLK,
  32 };
  33
  34 static struct clk_alpha_pll gpll0 = {
  35         .offset = 0x0,
  36         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  37         .clkr = {
  38                 .enable_reg = 0x52010,
  39                 .enable_mask = BIT(0),
  40                 .hw.init = &(struct clk_init_data){
  41                         .name = "gpll0",
  42                         .parent_data = &(const struct clk_parent_data){
  43                                 .fw_name = "bi_tcxo",
  44                         },
  45                         .num_parents = 1,
  46                         .ops = &clk_alpha_pll_fixed_fabia_ops,
  47                 },
  48         },
  49 };
  50
  51 static const struct clk_div_table post_div_table_gpll0_out_even[] = {
  52         { 0x1, 2 },
  53         { }
  54 };
  55
  56 static struct clk_alpha_pll_postdiv gpll0_out_even = {
  57         .offset = 0x0,
  58         .post_div_shift = 8,
  59         .post_div_table = post_div_table_gpll0_out_even,
  60         .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
  61         .width = 4,
  62         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  63         .clkr.hw.init = &(struct clk_init_data){
  64                 .name = "gpll0_out_even",
  65                 .parent_hws = (const struct clk_hw*[]){
  66                         &gpll0.clkr.hw,
  67                 },
  68                 .num_parents = 1,
  69                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
  70         },
  71 };
  72
  73 static const struct clk_div_table post_div_table_gpll0_out_odd[] = {
  74         { 0x3, 3 },
  75         { }
  76 };
  77
  78 static struct clk_alpha_pll_postdiv gpll0_out_odd = {
  79         .offset = 0x0,
  80         .post_div_shift = 12,
  81         .post_div_table = post_div_table_gpll0_out_odd,
  82         .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_odd),
  83         .width = 4,
  84         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  85         .clkr.hw.init = &(struct clk_init_data){
  86                 .name = "gpll0_out_odd",
  87                 .parent_hws = (const struct clk_hw*[]){
  88                         &gpll0.clkr.hw,
  89                 },
  90                 .num_parents = 1,
  91                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
  92         },
  93 };
  94
  95 static struct clk_alpha_pll gpll6 = {
  96         .offset = 0x6000,
  97         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  98         .clkr = {
  99                 .enable_reg = 0x52010,
 100                 .enable_mask = BIT(6),
 101                 .hw.init = &(struct clk_init_data){
 102                         .name = "gpll6",
 103                         .parent_data = &(const struct clk_parent_data){
 104                                 .fw_name = "bi_tcxo",
 105                         },
 106                         .num_parents = 1,
 107                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 108                 },
 109         },
 110 };
 111
 112 static const struct clk_div_table post_div_table_gpll6_out_even[] = {
 113         { 0x1, 2 },
 114         { }
 115 };
 116
 117 static struct clk_alpha_pll_postdiv gpll6_out_even = {
 118         .offset = 0x6000,
 119         .post_div_shift = 8,
 120         .post_div_table = post_div_table_gpll6_out_even,
 121         .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even),
 122         .width = 4,
 123         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 124         .clkr.hw.init = &(struct clk_init_data){
 125                 .name = "gpll6_out_even",
 126                 .parent_hws = (const struct clk_hw*[]){
 127                         &gpll6.clkr.hw,
 128                 },
 129                 .num_parents = 1,
 130                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 131         },
 132 };
 133
 134 static struct clk_alpha_pll gpll7 = {
 135         .offset = 0x7000,
 136         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 137         .clkr = {
 138                 .enable_reg = 0x52010,
 139                 .enable_mask = BIT(7),
 140                 .hw.init = &(struct clk_init_data){
 141                         .name = "gpll7",
 142                         .parent_data = &(const struct clk_parent_data){
 143                                 .fw_name = "bi_tcxo",
 144                         },
 145                         .num_parents = 1,
 146                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 147                 },
 148         },
 149 };
 150
 151 static const struct parent_map gcc_parent_map_0[] = {
 152         { P_BI_TCXO, 0 },
 153         { P_GPLL0_OUT_MAIN, 1 },
 154         { P_GPLL6_OUT_EVEN, 2 },
 155         { P_GPLL0_OUT_EVEN, 6 },
 156 };
 157
 158 static const struct clk_parent_data gcc_parent_data_0[] = {
 159         { .fw_name = "bi_tcxo" },
 160         { .hw = &gpll0.clkr.hw },
 161         { .hw = &gpll6_out_even.clkr.hw },
 162         { .hw = &gpll0_out_even.clkr.hw },
 163 };
 164
 165 static const struct parent_map gcc_parent_map_1[] = {
 166         { P_BI_TCXO, 0 },
 167         { P_GPLL0_OUT_EVEN, 6 },
 168 };
 169
 170 static const struct clk_parent_data gcc_parent_data_1[] = {
 171         { .fw_name = "bi_tcxo" },
 172         { .hw = &gpll0_out_even.clkr.hw },
 173 };
 174
 175 static const struct parent_map gcc_parent_map_2[] = {
 176         { P_BI_TCXO, 0 },
 177         { P_GPLL0_OUT_ODD, 2 },
 178 };
 179
 180 static const struct clk_parent_data gcc_parent_data_2_ao[] = {
 181         { .fw_name = "bi_tcxo_ao" },
 182         { .hw = &gpll0_out_odd.clkr.hw },
 183 };
 184
 185 static const struct parent_map gcc_parent_map_3[] = {
 186         { P_BI_TCXO, 0 },
 187 };
 188
 189 static const struct clk_parent_data gcc_parent_data_3[] = {
 190         { .fw_name = "bi_tcxo" },
 191 };
 192
 193 static const struct parent_map gcc_parent_map_4[] = {
 194         { P_BI_TCXO, 0 },
 195         { P_GPLL0_OUT_MAIN, 1 },
 196         { P_GPLL0_OUT_ODD, 2 },
 197 };
 198
 199 static const struct clk_parent_data gcc_parent_data_4[] = {
 200         { .fw_name = "bi_tcxo" },
 201         { .hw = &gpll0.clkr.hw },
 202         { .hw = &gpll0_out_odd.clkr.hw },
 203 };
 204
 205 static const struct parent_map gcc_parent_map_5[] = {
 206         { P_BI_TCXO, 0 },
 207         { P_GPLL0_OUT_ODD, 2 },
 208         { P_SLEEP_CLK, 5 },
 209         { P_GPLL0_OUT_EVEN, 6 },
 210 };
 211
 212 static const struct clk_parent_data gcc_parent_data_5[] = {
 213         { .fw_name = "bi_tcxo" },
 214         { .hw = &gpll0_out_odd.clkr.hw },
 215         { .fw_name = "sleep_clk" },
 216         { .hw = &gpll0_out_even.clkr.hw },
 217 };
 218
 219 static const struct parent_map gcc_parent_map_6[] = {
 220         { P_BI_TCXO, 0 },
 221         { P_SLEEP_CLK, 5 },
 222 };
 223
 224 static const struct clk_parent_data gcc_parent_data_6[] = {
 225         { .fw_name = "bi_tcxo" },
 226         { .fw_name = "sleep_clk" }
 227 };
 228
 229 static const struct parent_map gcc_parent_map_7[] = {
 230         { P_BI_TCXO, 0 },
 231         { P_GPLL6_OUT_EVEN, 2 },
 232         { P_GPLL0_OUT_EVEN, 6 },
 233 };
 234
 235 static const struct clk_parent_data gcc_parent_data_7[] = {
 236         { .fw_name = "bi_tcxo" },
 237         { .hw = &gpll6_out_even.clkr.hw },
 238         { .hw = &gpll0_out_even.clkr.hw },
 239 };
 240
 241 static const struct parent_map gcc_parent_map_8[] = {
 242         { P_BI_TCXO, 0 },
 243         { P_GPLL0_OUT_ODD, 2 },
 244         { P_GPLL7_OUT_MAIN, 3 },
 245 };
 246
 247 static const struct clk_parent_data gcc_parent_data_8[] = {
 248         { .fw_name = "bi_tcxo" },
 249         { .hw = &gpll0_out_odd.clkr.hw },
 250         { .hw = &gpll7.clkr.hw },
 251 };
 252
 253 static struct clk_regmap_div gcc_gpu_gpll0_main_div_clk_src = {
 254         .reg = 0x4514C,
 255         .shift = 0,
 256         .width = 2,
 257         .clkr.hw.init = &(struct clk_init_data) {
 258                 .name = "gcc_gpu_gpll0_main_div_clk_src",
 259                 .parent_hws = (const struct clk_hw*[]){
 260                         &gpll0.clkr.hw,
 261                 },
 262                 .num_parents = 1,
 263                 .ops = &clk_regmap_div_ro_ops,
 264         },
 265 };
 266
 267 static struct clk_regmap_div gcc_npu_pll0_main_div_clk_src = {
 268         .reg = 0x4ce00,
 269         .shift = 0,
 270         .width = 2,
 271         .clkr.hw.init = &(struct clk_init_data) {
 272                 .name = "gcc_npu_pll0_main_div_clk_src",
 273                 .parent_hws = (const struct clk_hw*[]){
 274                         &gpll0.clkr.hw,
 275                 },
 276                 .num_parents = 1,
 277                 .ops = &clk_regmap_div_ro_ops,
 278         },
 279 };
 280
 281 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
 282         F(19200000, P_BI_TCXO, 1, 0, 0),
 283         { }
 284 };
 285
 286 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
 287         .cmd_rcgr = 0x30014,
 288         .mnd_width = 0,
 289         .hid_width = 5,
 290         .parent_map = gcc_parent_map_2,
 291         .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
 292         .clkr.hw.init = &(struct clk_init_data){
 293                 .name = "gcc_cpuss_ahb_clk_src",
 294                 .parent_data = gcc_parent_data_2_ao,
 295                 .num_parents = ARRAY_SIZE(gcc_parent_data_2_ao),
 296                 .ops = &clk_rcg2_ops,
 297         },
 298 };
 299
 300 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 301         F(19200000, P_BI_TCXO, 1, 0, 0),
 302         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 303         F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
 304         F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
 305         F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
 306         { }
 307 };
 308
 309 static struct clk_rcg2 gcc_gp1_clk_src = {
 310         .cmd_rcgr = 0x37004,
 311         .mnd_width = 8,
 312         .hid_width = 5,
 313         .parent_map = gcc_parent_map_5,
 314         .freq_tbl = ftbl_gcc_gp1_clk_src,
 315         .clkr.hw.init = &(struct clk_init_data){
 316                 .name = "gcc_gp1_clk_src",
 317                 .parent_data = gcc_parent_data_5,
 318                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
 319                 .ops = &clk_rcg2_ops,
 320         },
 321 };
 322
 323 static struct clk_rcg2 gcc_gp2_clk_src = {
 324         .cmd_rcgr = 0x38004,
 325         .mnd_width = 8,
 326         .hid_width = 5,
 327         .parent_map = gcc_parent_map_5,
 328         .freq_tbl = ftbl_gcc_gp1_clk_src,
 329         .clkr.hw.init = &(struct clk_init_data){
 330                 .name = "gcc_gp2_clk_src",
 331                 .parent_data = gcc_parent_data_5,
 332                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
 333                 .ops = &clk_rcg2_ops,
 334         },
 335 };
 336
 337 static struct clk_rcg2 gcc_gp3_clk_src = {
 338         .cmd_rcgr = 0x39004,
 339         .mnd_width = 8,
 340         .hid_width = 5,
 341         .parent_map = gcc_parent_map_5,
 342         .freq_tbl = ftbl_gcc_gp1_clk_src,
 343         .clkr.hw.init = &(struct clk_init_data){
 344                 .name = "gcc_gp3_clk_src",
 345                 .parent_data = gcc_parent_data_5,
 346                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
 347                 .ops = &clk_rcg2_ops,
 348         },
 349 };
 350
 351 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 352         F(19200000, P_BI_TCXO, 1, 0, 0),
 353         F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
 354         { }
 355 };
 356
 357 static struct clk_rcg2 gcc_pdm2_clk_src = {
 358         .cmd_rcgr = 0x23010,
 359         .mnd_width = 0,
 360         .hid_width = 5,
 361         .parent_map = gcc_parent_map_1,
 362         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 363         .clkr.hw.init = &(struct clk_init_data){
 364                 .name = "gcc_pdm2_clk_src",
 365                 .parent_data = gcc_parent_data_1,
 366                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 367                 .ops = &clk_rcg2_ops,
 368         },
 369 };
 370
 371 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 372         F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
 373         F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
 374         F(19200000, P_BI_TCXO, 1, 0, 0),
 375         F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
 376         F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
 377         F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
 378         F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
 379         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 380         F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
 381         F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
 382         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 383         F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
 384         F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
 385         F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
 386         F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
 387         F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0),
 388         { }
 389 };
 390
 391 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 392         .name = "gcc_qupv3_wrap0_s0_clk_src",
 393         .parent_data = gcc_parent_data_0,
 394         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 395         .ops = &clk_rcg2_ops,
 396 };
 397
 398 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 399         .cmd_rcgr = 0x21148,
 400         .mnd_width = 16,
 401         .hid_width = 5,
 402         .parent_map = gcc_parent_map_0,
 403         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 404         .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 405 };
 406
 407 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 408         .name = "gcc_qupv3_wrap0_s1_clk_src",
 409         .parent_data = gcc_parent_data_0,
 410         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 411         .ops = &clk_rcg2_ops,
 412 };
 413
 414 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 415         .cmd_rcgr = 0x21278,
 416         .mnd_width = 16,
 417         .hid_width = 5,
 418         .parent_map = gcc_parent_map_0,
 419         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 420         .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 421 };
 422
 423 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 424         .name = "gcc_qupv3_wrap0_s2_clk_src",
 425         .parent_data = gcc_parent_data_0,
 426         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 427         .ops = &clk_rcg2_ops,
 428 };
 429
 430 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 431         .cmd_rcgr = 0x213a8,
 432         .mnd_width = 16,
 433         .hid_width = 5,
 434         .parent_map = gcc_parent_map_0,
 435         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 436         .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 437 };
 438
 439 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 440         .name = "gcc_qupv3_wrap0_s3_clk_src",
 441         .parent_data = gcc_parent_data_0,
 442         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 443         .ops = &clk_rcg2_ops,
 444 };
 445
 446 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 447         .cmd_rcgr = 0x214d8,
 448         .mnd_width = 16,
 449         .hid_width = 5,
 450         .parent_map = gcc_parent_map_0,
 451         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 452         .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 453 };
 454
 455 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 456         .name = "gcc_qupv3_wrap0_s4_clk_src",
 457         .parent_data = gcc_parent_data_0,
 458         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 459         .ops = &clk_rcg2_ops,
 460 };
 461
 462 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 463         .cmd_rcgr = 0x21608,
 464         .mnd_width = 16,
 465         .hid_width = 5,
 466         .parent_map = gcc_parent_map_0,
 467         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 468         .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 469 };
 470
 471 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 472         .name = "gcc_qupv3_wrap0_s5_clk_src",
 473         .parent_data = gcc_parent_data_0,
 474         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 475         .ops = &clk_rcg2_ops,
 476 };
 477
 478 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 479         .cmd_rcgr = 0x21738,
 480         .mnd_width = 16,
 481         .hid_width = 5,
 482         .parent_map = gcc_parent_map_0,
 483         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 484         .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 485 };
 486
 487 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 488         .name = "gcc_qupv3_wrap1_s0_clk_src",
 489         .parent_data = gcc_parent_data_0,
 490         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 491         .ops = &clk_rcg2_ops,
 492 };
 493
 494 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 495         .cmd_rcgr = 0x22018,
 496         .mnd_width = 16,
 497         .hid_width = 5,
 498         .parent_map = gcc_parent_map_0,
 499         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 500         .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 501 };
 502
 503 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 504         .name = "gcc_qupv3_wrap1_s1_clk_src",
 505         .parent_data = gcc_parent_data_0,
 506         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 507         .ops = &clk_rcg2_ops,
 508 };
 509
 510 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 511         .cmd_rcgr = 0x22148,
 512         .mnd_width = 16,
 513         .hid_width = 5,
 514         .parent_map = gcc_parent_map_0,
 515         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 516         .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 517 };
 518
 519 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
 520         .name = "gcc_qupv3_wrap1_s2_clk_src",
 521         .parent_data = gcc_parent_data_0,
 522         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 523         .ops = &clk_rcg2_ops,
 524 };
 525
 526 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 527         .cmd_rcgr = 0x22278,
 528         .mnd_width = 16,
 529         .hid_width = 5,
 530         .parent_map = gcc_parent_map_0,
 531         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 532         .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 533 };
 534
 535 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 536         .name = "gcc_qupv3_wrap1_s3_clk_src",
 537         .parent_data = gcc_parent_data_0,
 538         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 539         .ops = &clk_rcg2_ops,
 540 };
 541
 542 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 543         .cmd_rcgr = 0x223a8,
 544         .mnd_width = 16,
 545         .hid_width = 5,
 546         .parent_map = gcc_parent_map_0,
 547         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 548         .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 549 };
 550
 551 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 552         .name = "gcc_qupv3_wrap1_s4_clk_src",
 553         .parent_data = gcc_parent_data_0,
 554         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 555         .ops = &clk_rcg2_ops,
 556 };
 557
 558 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 559         .cmd_rcgr = 0x224d8,
 560         .mnd_width = 16,
 561         .hid_width = 5,
 562         .parent_map = gcc_parent_map_0,
 563         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 564         .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 565 };
 566
 567 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 568         .name = "gcc_qupv3_wrap1_s5_clk_src",
 569         .parent_data = gcc_parent_data_0,
 570         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 571         .ops = &clk_rcg2_ops,
 572 };
 573
 574 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 575         .cmd_rcgr = 0x22608,
 576         .mnd_width = 16,
 577         .hid_width = 5,
 578         .parent_map = gcc_parent_map_0,
 579         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 580         .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 581 };
 582
 583 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
 584         F(144000, P_BI_TCXO, 16, 3, 25),
 585         F(400000, P_BI_TCXO, 12, 1, 4),
 586         F(19200000, P_BI_TCXO, 1, 0, 0),
 587         F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
 588         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 589         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 590         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 591         F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0),
 592         F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0),
 593         { }
 594 };
 595
 596 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
 597         .cmd_rcgr = 0x4b024,
 598         .mnd_width = 8,
 599         .hid_width = 5,
 600         .parent_map = gcc_parent_map_7,
 601         .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
 602         .clkr.hw.init = &(struct clk_init_data){
 603                 .name = "gcc_sdcc1_apps_clk_src",
 604                 .parent_data = gcc_parent_data_7,
 605                 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
 606                 .ops = &clk_rcg2_ops,
 607         },
 608 };
 609
 610 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
 611         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 612         F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
 613         F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
 614         { }
 615 };
 616
 617 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
 618         .cmd_rcgr = 0x4b00c,
 619         .mnd_width = 0,
 620         .hid_width = 5,
 621         .parent_map = gcc_parent_map_1,
 622         .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
 623         .clkr.hw.init = &(struct clk_init_data){
 624                 .name = "gcc_sdcc1_ice_core_clk_src",
 625                 .parent_data = gcc_parent_data_1,
 626                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 627                 .ops = &clk_rcg2_ops,
 628         },
 629 };
 630
 631 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 632         F(400000, P_BI_TCXO, 12, 1, 4),
 633         F(9600000, P_BI_TCXO, 2, 0, 0),
 634         F(19200000, P_BI_TCXO, 1, 0, 0),
 635         F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
 636         F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
 637         F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
 638         F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
 639         { }
 640 };
 641
 642 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
 643         .cmd_rcgr = 0x2000c,
 644         .mnd_width = 8,
 645         .hid_width = 5,
 646         .parent_map = gcc_parent_map_8,
 647         .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
 648         .clkr.hw.init = &(struct clk_init_data){
 649                 .name = "gcc_sdcc2_apps_clk_src",
 650                 .parent_data = gcc_parent_data_8,
 651                 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
 652                 .flags = CLK_OPS_PARENT_ENABLE,
 653                 .ops = &clk_rcg2_floor_ops,
 654         },
 655 };
 656
 657 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
 658         F(25000000, P_GPLL0_OUT_ODD, 8, 0, 0),
 659         F(50000000, P_GPLL0_OUT_ODD, 4, 0, 0),
 660         F(100000000, P_GPLL0_OUT_ODD, 2, 0, 0),
 661         F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
 662         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 663         { }
 664 };
 665
 666 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
 667         .cmd_rcgr = 0x3a01c,
 668         .mnd_width = 8,
 669         .hid_width = 5,
 670         .parent_map = gcc_parent_map_4,
 671         .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
 672         .clkr.hw.init = &(struct clk_init_data){
 673                 .name = "gcc_ufs_phy_axi_clk_src",
 674                 .parent_data = gcc_parent_data_4,
 675                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 676                 .ops = &clk_rcg2_ops,
 677         },
 678 };
 679
 680 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
 681         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 682         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 683         F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
 684         F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
 685         { }
 686 };
 687
 688 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
 689         .cmd_rcgr = 0x3a048,
 690         .mnd_width = 0,
 691         .hid_width = 5,
 692         .parent_map = gcc_parent_map_1,
 693         .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
 694         .clkr.hw.init = &(struct clk_init_data){
 695                 .name = "gcc_ufs_phy_ice_core_clk_src",
 696                 .parent_data = gcc_parent_data_1,
 697                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 698                 .ops = &clk_rcg2_ops,
 699         },
 700 };
 701
 702 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
 703         F(9600000, P_BI_TCXO, 2, 0, 0),
 704         F(19200000, P_BI_TCXO, 1, 0, 0),
 705         { }
 706 };
 707
 708 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
 709         .cmd_rcgr = 0x3a0b0,
 710         .mnd_width = 0,
 711         .hid_width = 5,
 712         .parent_map = gcc_parent_map_3,
 713         .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
 714         .clkr.hw.init = &(struct clk_init_data){
 715                 .name = "gcc_ufs_phy_phy_aux_clk_src",
 716                 .parent_data = gcc_parent_data_3,
 717                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 718                 .ops = &clk_rcg2_ops,
 719         },
 720 };
 721
 722 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
 723         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 724         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 725         F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
 726         { }
 727 };
 728
 729 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
 730         .cmd_rcgr = 0x3a060,
 731         .mnd_width = 0,
 732         .hid_width = 5,
 733         .parent_map = gcc_parent_map_1,
 734         .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
 735         .clkr.hw.init = &(struct clk_init_data){
 736                 .name = "gcc_ufs_phy_unipro_core_clk_src",
 737                 .parent_data = gcc_parent_data_1,
 738                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 739                 .ops = &clk_rcg2_ops,
 740         },
 741 };
 742
 743 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
 744         F(66666667, P_GPLL0_OUT_ODD, 3, 0, 0),
 745         F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
 746         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 747         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 748         { }
 749 };
 750
 751 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
 752         .cmd_rcgr = 0x1a01c,
 753         .mnd_width = 8,
 754         .hid_width = 5,
 755         .parent_map = gcc_parent_map_4,
 756         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
 757         .clkr.hw.init = &(struct clk_init_data){
 758                 .name = "gcc_usb30_prim_master_clk_src",
 759                 .parent_data = gcc_parent_data_4,
 760                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 761                 .ops = &clk_rcg2_ops,
 762         },
 763 };
 764
 765 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
 766         F(19200000, P_BI_TCXO, 1, 0, 0),
 767         { }
 768 };
 769
 770 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
 771         .cmd_rcgr = 0x1a034,
 772         .mnd_width = 0,
 773         .hid_width = 5,
 774         .parent_map = gcc_parent_map_3,
 775         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
 776         .clkr.hw.init = &(struct clk_init_data){
 777                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
 778                 .parent_data = gcc_parent_data_3,
 779                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 780                 .ops = &clk_rcg2_ops,
 781         },
 782 };
 783
 784 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
 785         .cmd_rcgr = 0x1a060,
 786         .mnd_width = 0,
 787         .hid_width = 5,
 788         .parent_map = gcc_parent_map_6,
 789         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
 790         .clkr.hw.init = &(struct clk_init_data){
 791                 .name = "gcc_usb3_prim_phy_aux_clk_src",
 792                 .parent_data = gcc_parent_data_6,
 793                 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 794                 .ops = &clk_rcg2_ops,
 795         },
 796 };
 797
 798 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
 799         .halt_reg = 0x3e014,
 800         .halt_check = BRANCH_HALT_DELAY,
 801         .hwcg_reg = 0x3e014,
 802         .hwcg_bit = 1,
 803         .clkr = {
 804                 .enable_reg = 0x3e014,
 805                 .enable_mask = BIT(0),
 806                 .hw.init = &(struct clk_init_data){
 807                         .name = "gcc_aggre_ufs_phy_axi_clk",
 808                         .parent_hws = (const struct clk_hw*[]){
 809                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
 810                         },
 811                         .num_parents = 1,
 812                         .flags = CLK_SET_RATE_PARENT,
 813                         .ops = &clk_branch2_ops,
 814                 },
 815         },
 816 };
 817
 818 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
 819         .halt_reg = 0x3e014,
 820         .halt_check = BRANCH_HALT,
 821         .hwcg_reg = 0x3e014,
 822         .hwcg_bit = 1,
 823         .clkr = {
 824                 .enable_reg = 0x3e014,
 825                 .enable_mask = BIT(1),
 826                 .hw.init = &(struct clk_init_data){
 827                         .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
 828                         .parent_hws = (const struct clk_hw*[]){
 829                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
 830                         },
 831                         .num_parents = 1,
 832                         .flags = CLK_SET_RATE_PARENT,
 833                         .ops = &clk_branch2_ops,
 834                 },
 835         },
 836 };
 837
 838 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
 839         .halt_reg = 0x3e014,
 840         .halt_check = BRANCH_HALT,
 841         .hwcg_reg = 0x3e014,
 842         .hwcg_bit = 1,
 843         .clkr = {
 844                 .enable_reg = 0x3e014,
 845                 .enable_mask = BIT(1),
 846                 .hw.init = &(struct clk_init_data){
 847                         .name = "gcc_ufs_phy_axi_hw_ctl_clk",
 848                         .parent_hws = (const struct clk_hw*[]){
 849                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
 850                         },
 851                         .num_parents = 1,
 852                         .flags = CLK_SET_RATE_PARENT,
 853                         .ops = &clk_branch2_ops,
 854                 },
 855         },
 856 };
 857
 858 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
 859         .halt_reg = 0x3e010,
 860         .halt_check = BRANCH_HALT,
 861         .hwcg_reg = 0x3e010,
 862         .hwcg_bit = 1,
 863         .clkr = {
 864                 .enable_reg = 0x3e010,
 865                 .enable_mask = BIT(0),
 866                 .hw.init = &(struct clk_init_data){
 867                         .name = "gcc_aggre_usb3_prim_axi_clk",
 868                         .parent_hws = (const struct clk_hw*[]){
 869                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
 870                         },
 871                         .num_parents = 1,
 872                         .flags = CLK_SET_RATE_PARENT,
 873                         .ops = &clk_branch2_ops,
 874                 },
 875         },
 876 };
 877
 878 static struct clk_branch gcc_boot_rom_ahb_clk = {
 879         .halt_reg = 0x26004,
 880         .halt_check = BRANCH_HALT_VOTED,
 881         .hwcg_reg = 0x26004,
 882         .hwcg_bit = 1,
 883         .clkr = {
 884                 .enable_reg = 0x52000,
 885                 .enable_mask = BIT(28),
 886                 .hw.init = &(struct clk_init_data){
 887                         .name = "gcc_boot_rom_ahb_clk",
 888                         .ops = &clk_branch2_ops,
 889                 },
 890         },
 891 };
 892
 893 static struct clk_branch gcc_camera_ahb_clk = {
 894         .halt_reg = 0x17008,
 895         .halt_check = BRANCH_HALT,
 896         .hwcg_reg = 0x17008,
 897         .hwcg_bit = 1,
 898         .clkr = {
 899                 .enable_reg = 0x17008,
 900                 .enable_mask = BIT(0),
 901                 .hw.init = &(struct clk_init_data){
 902                         .name = "gcc_camera_ahb_clk",
 903                         .flags = CLK_IS_CRITICAL,
 904                         .ops = &clk_branch2_ops,
 905                 },
 906         },
 907 };
 908
 909 static struct clk_branch gcc_camera_axi_clk = {
 910         .halt_reg = 0x17018,
 911         .halt_check = BRANCH_HALT,
 912         .hwcg_reg = 0x17018,
 913         .hwcg_bit = 1,
 914         .clkr = {
 915                 .enable_reg = 0x17018,
 916                 .enable_mask = BIT(0),
 917                 .hw.init = &(struct clk_init_data){
 918                         .name = "gcc_camera_axi_clk",
 919                         .ops = &clk_branch2_ops,
 920                 },
 921         },
 922 };
 923
 924 static struct clk_branch gcc_camera_throttle_nrt_axi_clk = {
 925         .halt_reg = 0x17078,
 926         .halt_check = BRANCH_VOTED,
 927         .hwcg_reg = 0x17078,
 928         .hwcg_bit = 1,
 929         .clkr = {
 930                 .enable_reg = 0x17078,
 931                 .enable_mask = BIT(0),
 932                 .hw.init = &(struct clk_init_data){
 933                         .name = "gcc_camera_throttle_nrt_axi_clk",
 934                         .ops = &clk_branch2_ops,
 935                 },
 936         },
 937 };
 938
 939 static struct clk_branch gcc_camera_throttle_rt_axi_clk = {
 940         .halt_reg = 0x17024,
 941         .halt_check = BRANCH_VOTED,
 942         .hwcg_reg = 0x17024,
 943         .hwcg_bit = 1,
 944         .clkr = {
 945                 .enable_reg = 0x17024,
 946                 .enable_mask = BIT(0),
 947                 .hw.init = &(struct clk_init_data){
 948                         .name = "gcc_camera_throttle_rt_axi_clk",
 949                         .ops = &clk_branch2_ops,
 950                 },
 951         },
 952 };
 953
 954 static struct clk_branch gcc_camera_xo_clk = {
 955         .halt_reg = 0x17030,
 956         .halt_check = BRANCH_HALT,
 957         .clkr = {
 958                 .enable_reg = 0x17030,
 959                 .enable_mask = BIT(0),
 960                 .hw.init = &(struct clk_init_data){
 961                         .name = "gcc_camera_xo_clk",
 962                         .flags = CLK_IS_CRITICAL,
 963                         .ops = &clk_branch2_ops,
 964                 },
 965         },
 966 };
 967
 968 static struct clk_branch gcc_ce1_ahb_clk = {
 969         .halt_reg = 0x2b00c,
 970         .halt_check = BRANCH_HALT_VOTED,
 971         .hwcg_reg = 0x2b00c,
 972         .hwcg_bit = 1,
 973         .clkr = {
 974                 .enable_reg = 0x52008,
 975                 .enable_mask = BIT(3),
 976                 .hw.init = &(struct clk_init_data){
 977                         .name = "gcc_ce1_ahb_clk",
 978                         .ops = &clk_branch2_ops,
 979                 },
 980         },
 981 };
 982
 983 static struct clk_branch gcc_ce1_axi_clk = {
 984         .halt_reg = 0x2b008,
 985         .halt_check = BRANCH_HALT_VOTED,
 986         .clkr = {
 987                 .enable_reg = 0x52008,
 988                 .enable_mask = BIT(2),
 989                 .hw.init = &(struct clk_init_data){
 990                         .name = "gcc_ce1_axi_clk",
 991                         .ops = &clk_branch2_ops,
 992                 },
 993         },
 994 };
 995
 996 static struct clk_branch gcc_ce1_clk = {
 997         .halt_reg = 0x2b004,
 998         .halt_check = BRANCH_HALT_VOTED,
 999         .clkr = {
1000                 .enable_reg = 0x52008,
1001                 .enable_mask = BIT(1),
1002                 .hw.init = &(struct clk_init_data){
1003                         .name = "gcc_ce1_clk",
1004                         .ops = &clk_branch2_ops,
1005                 },
1006         },
1007 };
1008
1009 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1010         .halt_reg = 0x1101c,
1011         .halt_check = BRANCH_HALT,
1012         .hwcg_reg = 0x1101c,
1013         .hwcg_bit = 1,
1014         .clkr = {
1015                 .enable_reg = 0x1101c,
1016                 .enable_mask = BIT(0),
1017                 .hw.init = &(struct clk_init_data){
1018                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1019                         .parent_hws = (const struct clk_hw*[]){
1020                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1021                         },
1022                         .num_parents = 1,
1023                         .flags = CLK_SET_RATE_PARENT,
1024                         .ops = &clk_branch2_ops,
1025                 },
1026         },
1027 };
1028
1029 static struct clk_branch gcc_cpuss_ahb_clk = {
1030         .halt_reg = 0x30000,
1031         .halt_check = BRANCH_HALT_VOTED,
1032         .hwcg_reg = 0x30000,
1033         .hwcg_bit = 1,
1034         .clkr = {
1035                 .enable_reg = 0x52008,
1036                 .enable_mask = BIT(4),
1037                 .hw.init = &(struct clk_init_data){
1038                         .name = "gcc_cpuss_ahb_clk",
1039                         .parent_hws = (const struct clk_hw*[]){
1040                                 &gcc_cpuss_ahb_clk_src.clkr.hw,
1041                         },
1042                         .num_parents = 1,
1043                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1044                         .ops = &clk_branch2_ops,
1045                 },
1046         },
1047 };
1048
1049 static struct clk_branch gcc_cpuss_gnoc_clk = {
1050         .halt_reg = 0x30004,
1051         .halt_check = BRANCH_HALT_VOTED,
1052         .hwcg_reg = 0x30004,
1053         .hwcg_bit = 1,
1054         .clkr = {
1055                 .enable_reg = 0x52008,
1056                 .enable_mask = BIT(5),
1057                 .hw.init = &(struct clk_init_data){
1058                         .name = "gcc_cpuss_gnoc_clk",
1059                         .flags = CLK_IS_CRITICAL,
1060                         .ops = &clk_branch2_ops,
1061                 },
1062         },
1063 };
1064
1065 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1066         .halt_reg = 0x30008,
1067         .halt_check = BRANCH_HALT,
1068         .clkr = {
1069                 .enable_reg = 0x30008,
1070                 .enable_mask = BIT(0),
1071                 .hw.init = &(struct clk_init_data){
1072                         .name = "gcc_cpuss_rbcpr_clk",
1073                         .ops = &clk_branch2_ops,
1074                 },
1075         },
1076 };
1077
1078 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1079         .halt_reg = 0x2d038,
1080         .halt_check = BRANCH_VOTED,
1081         .hwcg_reg = 0x2d038,
1082         .hwcg_bit = 1,
1083         .clkr = {
1084                 .enable_reg = 0x2d038,
1085                 .enable_mask = BIT(0),
1086                 .hw.init = &(struct clk_init_data){
1087                         .name = "gcc_ddrss_gpu_axi_clk",
1088                         .ops = &clk_branch2_ops,
1089                 },
1090         },
1091 };
1092
1093 static struct clk_branch gcc_disp_ahb_clk = {
1094         .halt_reg = 0x1700c,
1095         .halt_check = BRANCH_HALT,
1096         .hwcg_reg = 0x1700c,
1097         .hwcg_bit = 1,
1098         .clkr = {
1099                 .enable_reg = 0x1700c,
1100                 .enable_mask = BIT(0),
1101                 .hw.init = &(struct clk_init_data){
1102                         .name = "gcc_disp_ahb_clk",
1103                         .flags = CLK_IS_CRITICAL,
1104                         .ops = &clk_branch2_ops,
1105                 },
1106         },
1107 };
1108
1109 static struct clk_branch gcc_disp_axi_clk = {
1110         .halt_reg = 0x1701c,
1111         .halt_check = BRANCH_HALT,
1112         .hwcg_reg = 0x1701c,
1113         .hwcg_bit = 1,
1114         .clkr = {
1115                 .enable_reg = 0x1701c,
1116                 .enable_mask = BIT(0),
1117                 .hw.init = &(struct clk_init_data){
1118                         .name = "gcc_disp_axi_clk",
1119                         .ops = &clk_branch2_ops,
1120                 },
1121         },
1122 };
1123
1124 static struct clk_branch gcc_disp_cc_sleep_clk = {
1125         .halt_reg = 0x17074,
1126         .halt_check = BRANCH_HALT_DELAY,
1127         .hwcg_reg = 0x17074,
1128         .hwcg_bit = 1,
1129         .clkr = {
1130                 .enable_reg = 0x17074,
1131                 .enable_mask = BIT(0),
1132                 .hw.init = &(struct clk_init_data){
1133                         .name = "gcc_disp_cc_sleep_clk",
1134                         .ops = &clk_branch2_ops,
1135                 },
1136         },
1137 };
1138
1139 static struct clk_branch gcc_disp_cc_xo_clk = {
1140         .halt_reg = 0x17070,
1141         .halt_check = BRANCH_HALT,
1142         .hwcg_reg = 0x17070,
1143         .hwcg_bit = 1,
1144         .clkr = {
1145                 .enable_reg = 0x17070,
1146                 .enable_mask = BIT(0),
1147                 .hw.init = &(struct clk_init_data){
1148                         .name = "gcc_disp_cc_xo_clk",
1149                         .flags = CLK_IS_CRITICAL,
1150                         .ops = &clk_branch2_ops,
1151                 },
1152         },
1153 };
1154
1155 static struct clk_branch gcc_disp_gpll0_clk = {
1156         .halt_check = BRANCH_HALT_DELAY,
1157         .clkr = {
1158                 .enable_reg = 0x52000,
1159                 .enable_mask = BIT(2),
1160                 .hw.init = &(struct clk_init_data){
1161                         .name = "gcc_disp_gpll0_clk",
1162                         .parent_hws = (const struct clk_hw*[]){
1163                                 &gpll0.clkr.hw,
1164                         },
1165                         .num_parents = 1,
1166                         .ops = &clk_branch2_ops,
1167                 },
1168         },
1169 };
1170
1171 static struct clk_branch gcc_disp_throttle_axi_clk = {
1172         .halt_reg = 0x17028,
1173         .halt_check = BRANCH_HALT,
1174         .hwcg_reg = 0x17028,
1175         .hwcg_bit = 1,
1176         .clkr = {
1177                 .enable_reg = 0x17028,
1178                 .enable_mask = BIT(0),
1179                 .hw.init = &(struct clk_init_data){
1180                         .name = "gcc_disp_throttle_axi_clk",
1181                         .ops = &clk_branch2_ops,
1182                 },
1183         },
1184 };
1185
1186 static struct clk_branch gcc_disp_xo_clk = {
1187         .halt_reg = 0x17034,
1188         .halt_check = BRANCH_HALT,
1189         .clkr = {
1190                 .enable_reg = 0x17034,
1191                 .enable_mask = BIT(0),
1192                 .hw.init = &(struct clk_init_data){
1193                         .name = "gcc_disp_xo_clk",
1194                         .ops = &clk_branch2_ops,
1195                 },
1196         },
1197 };
1198
1199 static struct clk_branch gcc_gp1_clk = {
1200         .halt_reg = 0x37000,
1201         .halt_check = BRANCH_HALT,
1202         .clkr = {
1203                 .enable_reg = 0x37000,
1204                 .enable_mask = BIT(0),
1205                 .hw.init = &(struct clk_init_data){
1206                         .name = "gcc_gp1_clk",
1207                         .parent_hws = (const struct clk_hw*[]){
1208                                 &gcc_gp1_clk_src.clkr.hw,
1209                         },
1210                         .num_parents = 1,
1211                         .flags = CLK_SET_RATE_PARENT,
1212                         .ops = &clk_branch2_ops,
1213                 },
1214         },
1215 };
1216
1217 static struct clk_branch gcc_gp2_clk = {
1218         .halt_reg = 0x38000,
1219         .halt_check = BRANCH_HALT,
1220         .clkr = {
1221                 .enable_reg = 0x38000,
1222                 .enable_mask = BIT(0),
1223                 .hw.init = &(struct clk_init_data){
1224                         .name = "gcc_gp2_clk",
1225                         .parent_hws = (const struct clk_hw*[]){
1226                                 &gcc_gp2_clk_src.clkr.hw,
1227                         },
1228                         .num_parents = 1,
1229                         .flags = CLK_SET_RATE_PARENT,
1230                         .ops = &clk_branch2_ops,
1231                 },
1232         },
1233 };
1234
1235 static struct clk_branch gcc_gp3_clk = {
1236         .halt_reg = 0x39000,
1237         .halt_check = BRANCH_HALT,
1238         .clkr = {
1239                 .enable_reg = 0x39000,
1240                 .enable_mask = BIT(0),
1241                 .hw.init = &(struct clk_init_data){
1242                         .name = "gcc_gp3_clk",
1243                         .parent_hws = (const struct clk_hw*[]){
1244                                 &gcc_gp3_clk_src.clkr.hw,
1245                         },
1246                         .num_parents = 1,
1247                         .flags = CLK_SET_RATE_PARENT,
1248                         .ops = &clk_branch2_ops,
1249                 },
1250         },
1251 };
1252
1253 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1254         .halt_reg = 0x45004,
1255         .halt_check = BRANCH_HALT,
1256         .hwcg_reg = 0x45004,
1257         .hwcg_bit = 1,
1258         .clkr = {
1259                 .enable_reg = 0x45004,
1260                 .enable_mask = BIT(0),
1261                 .hw.init = &(struct clk_init_data){
1262                         .name = "gcc_gpu_cfg_ahb_clk",
1263                         .flags = CLK_IS_CRITICAL,
1264                         .ops = &clk_branch2_ops,
1265                 },
1266         },
1267 };
1268
1269 static struct clk_branch gcc_gpu_gpll0_clk = {
1270         .halt_check = BRANCH_HALT_DELAY,
1271         .clkr = {
1272                 .enable_reg = 0x52008,
1273                 .enable_mask = BIT(7),
1274                 .hw.init = &(struct clk_init_data){
1275                         .name = "gcc_gpu_gpll0_clk",
1276                         .parent_hws = (const struct clk_hw*[]){
1277                                 &gpll0.clkr.hw,
1278                         },
1279                         .num_parents = 1,
1280                         .ops = &clk_branch2_ops,
1281                 },
1282         },
1283 };
1284
1285 static struct clk_branch gcc_gpu_gpll0_div_clk = {
1286         .halt_check = BRANCH_HALT_DELAY,
1287         .clkr = {
1288                 .enable_reg = 0x52008,
1289                 .enable_mask = BIT(8),
1290                 .hw.init = &(struct clk_init_data){
1291                         .name = "gcc_gpu_gpll0_div_clk",
1292                         .parent_hws = (const struct clk_hw*[]){
1293                                 &gcc_gpu_gpll0_main_div_clk_src.clkr.hw,
1294                         },
1295                         .num_parents = 1,
1296                         .ops = &clk_branch2_ops,
1297                 },
1298         },
1299 };
1300
1301 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1302         .halt_reg = 0x4500c,
1303         .halt_check = BRANCH_VOTED,
1304         .hwcg_reg = 0x4500c,
1305         .hwcg_bit = 1,
1306         .clkr = {
1307                 .enable_reg = 0x4500c,
1308                 .enable_mask = BIT(0),
1309                 .hw.init = &(struct clk_init_data){
1310                         .name = "gcc_gpu_memnoc_gfx_clk",
1311                         .ops = &clk_branch2_ops,
1312                 },
1313         },
1314 };
1315
1316 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1317         .halt_reg = 0x45014,
1318         .halt_check = BRANCH_HALT,
1319         .hwcg_reg = 0x45014,
1320         .hwcg_bit = 1,
1321         .clkr = {
1322                 .enable_reg = 0x45014,
1323                 .enable_mask = BIT(0),
1324                 .hw.init = &(struct clk_init_data){
1325                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1326                         .ops = &clk_branch2_ops,
1327                 },
1328         },
1329 };
1330
1331 static struct clk_branch gcc_npu_axi_clk = {
1332         .halt_reg = 0x4c008,
1333         .halt_check = BRANCH_VOTED,
1334         .hwcg_reg = 0x4c008,
1335         .hwcg_bit = 1,
1336         .clkr = {
1337                 .enable_reg = 0x4c008,
1338                 .enable_mask = BIT(0),
1339                 .hw.init = &(struct clk_init_data){
1340                         .name = "gcc_npu_axi_clk",
1341                         .ops = &clk_branch2_ops,
1342                 },
1343         },
1344 };
1345
1346 static struct clk_branch gcc_npu_bwmon_axi_clk = {
1347         .halt_reg = 0x4d004,
1348         .halt_check = BRANCH_HALT_DELAY,
1349         .hwcg_reg = 0x4d004,
1350         .hwcg_bit = 1,
1351         .clkr = {
1352                 .enable_reg = 0x4d004,
1353                 .enable_mask = BIT(0),
1354                 .hw.init = &(struct clk_init_data){
1355                         .name = "gcc_npu_bwmon_axi_clk",
1356                         .ops = &clk_branch2_ops,
1357                 },
1358         },
1359 };
1360
1361 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
1362         .halt_reg = 0x4d008,
1363         .halt_check = BRANCH_HALT,
1364         .clkr = {
1365                 .enable_reg = 0x4d008,
1366                 .enable_mask = BIT(0),
1367                 .hw.init = &(struct clk_init_data){
1368                         .name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
1369                         .ops = &clk_branch2_ops,
1370                 },
1371         },
1372 };
1373
1374 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
1375         .halt_reg = 0x4d00c,
1376         .halt_check = BRANCH_HALT,
1377         .clkr = {
1378                 .enable_reg = 0x4d00c,
1379                 .enable_mask = BIT(0),
1380                 .hw.init = &(struct clk_init_data){
1381                         .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
1382                         .ops = &clk_branch2_ops,
1383                 },
1384         },
1385 };
1386
1387 static struct clk_branch gcc_npu_cfg_ahb_clk = {
1388         .halt_reg = 0x4c004,
1389         .halt_check = BRANCH_HALT,
1390         .hwcg_reg = 0x4c004,
1391         .hwcg_bit = 1,
1392         .clkr = {
1393                 .enable_reg = 0x4c004,
1394                 .enable_mask = BIT(0),
1395                 .hw.init = &(struct clk_init_data){
1396                         .name = "gcc_npu_cfg_ahb_clk",
1397                         .flags = CLK_IS_CRITICAL,
1398                         .ops = &clk_branch2_ops,
1399                 },
1400         },
1401 };
1402
1403 static struct clk_branch gcc_npu_dma_clk = {
1404         .halt_reg = 0x4c140,
1405         .halt_check = BRANCH_VOTED,
1406         .hwcg_reg = 0x4c140,
1407         .hwcg_bit = 1,
1408         .clkr = {
1409                 .enable_reg = 0x4c140,
1410                 .enable_mask = BIT(0),
1411                 .hw.init = &(struct clk_init_data){
1412                         .name = "gcc_npu_dma_clk",
1413                         .ops = &clk_branch2_ops,
1414                 },
1415         },
1416 };
1417
1418 static struct clk_branch gcc_npu_gpll0_clk = {
1419         .halt_check = BRANCH_HALT_DELAY,
1420         .clkr = {
1421                 .enable_reg = 0x52008,
1422                 .enable_mask = BIT(9),
1423                 .hw.init = &(struct clk_init_data){
1424                         .name = "gcc_npu_gpll0_clk",
1425                         .parent_hws = (const struct clk_hw*[]){
1426                                 &gpll0.clkr.hw,
1427                         },
1428                         .num_parents = 1,
1429                         .ops = &clk_branch2_ops,
1430                 },
1431         },
1432 };
1433
1434 static struct clk_branch gcc_npu_gpll0_div_clk = {
1435         .halt_check = BRANCH_HALT_DELAY,
1436         .clkr = {
1437                 .enable_reg = 0x52008,
1438                 .enable_mask = BIT(10),
1439                 .hw.init = &(struct clk_init_data){
1440                         .name = "gcc_npu_gpll0_div_clk",
1441                         .parent_hws = (const struct clk_hw*[]){
1442                                 &gcc_npu_pll0_main_div_clk_src.clkr.hw,
1443                         },
1444                         .num_parents = 1,
1445                         .ops = &clk_branch2_ops,
1446                 },
1447         },
1448 };
1449
1450 static struct clk_branch gcc_pdm2_clk = {
1451         .halt_reg = 0x2300c,
1452         .halt_check = BRANCH_HALT,
1453         .clkr = {
1454                 .enable_reg = 0x2300c,
1455                 .enable_mask = BIT(0),
1456                 .hw.init = &(struct clk_init_data){
1457                         .name = "gcc_pdm2_clk",
1458                         .parent_hws = (const struct clk_hw*[]){
1459                                 &gcc_pdm2_clk_src.clkr.hw,
1460                         },
1461                         .num_parents = 1,
1462                         .flags = CLK_SET_RATE_PARENT,
1463                         .ops = &clk_branch2_ops,
1464                 },
1465         },
1466 };
1467
1468 static struct clk_branch gcc_pdm_ahb_clk = {
1469         .halt_reg = 0x23004,
1470         .halt_check = BRANCH_HALT,
1471         .hwcg_reg = 0x23004,
1472         .hwcg_bit = 1,
1473         .clkr = {
1474                 .enable_reg = 0x23004,
1475                 .enable_mask = BIT(0),
1476                 .hw.init = &(struct clk_init_data){
1477                         .name = "gcc_pdm_ahb_clk",
1478                         .ops = &clk_branch2_ops,
1479                 },
1480         },
1481 };
1482
1483 static struct clk_branch gcc_pdm_xo4_clk = {
1484         .halt_reg = 0x23008,
1485         .halt_check = BRANCH_HALT,
1486         .clkr = {
1487                 .enable_reg = 0x23008,
1488                 .enable_mask = BIT(0),
1489                 .hw.init = &(struct clk_init_data){
1490                         .name = "gcc_pdm_xo4_clk",
1491                         .ops = &clk_branch2_ops,
1492                 },
1493         },
1494 };
1495
1496 static struct clk_branch gcc_prng_ahb_clk = {
1497         .halt_reg = 0x24004,
1498         .halt_check = BRANCH_HALT_VOTED,
1499         .hwcg_reg = 0x24004,
1500         .hwcg_bit = 1,
1501         .clkr = {
1502                 .enable_reg = 0x52000,
1503                 .enable_mask = BIT(26),
1504                 .hw.init = &(struct clk_init_data){
1505                         .name = "gcc_prng_ahb_clk",
1506                         .ops = &clk_branch2_ops,
1507                 },
1508         },
1509 };
1510
1511 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1512         .halt_reg = 0x21014,
1513         .halt_check = BRANCH_HALT_VOTED,
1514         .clkr = {
1515                 .enable_reg = 0x52000,
1516                 .enable_mask = BIT(9),
1517                 .hw.init = &(struct clk_init_data){
1518                         .name = "gcc_qupv3_wrap0_core_2x_clk",
1519                         .ops = &clk_branch2_ops,
1520                 },
1521         },
1522 };
1523
1524 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1525         .halt_reg = 0x2100c,
1526         .halt_check = BRANCH_HALT_VOTED,
1527         .clkr = {
1528                 .enable_reg = 0x52000,
1529                 .enable_mask = BIT(8),
1530                 .hw.init = &(struct clk_init_data){
1531                         .name = "gcc_qupv3_wrap0_core_clk",
1532                         .ops = &clk_branch2_ops,
1533                 },
1534         },
1535 };
1536
1537 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1538         .halt_reg = 0x21144,
1539         .halt_check = BRANCH_HALT_VOTED,
1540         .clkr = {
1541                 .enable_reg = 0x52000,
1542                 .enable_mask = BIT(10),
1543                 .hw.init = &(struct clk_init_data){
1544                         .name = "gcc_qupv3_wrap0_s0_clk",
1545                         .parent_hws = (const struct clk_hw*[]){
1546                                 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1547                         },
1548                         .num_parents = 1,
1549                         .flags = CLK_SET_RATE_PARENT,
1550                         .ops = &clk_branch2_ops,
1551                 },
1552         },
1553 };
1554
1555 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1556         .halt_reg = 0x21274,
1557         .halt_check = BRANCH_HALT_VOTED,
1558         .clkr = {
1559                 .enable_reg = 0x52000,
1560                 .enable_mask = BIT(11),
1561                 .hw.init = &(struct clk_init_data){
1562                         .name = "gcc_qupv3_wrap0_s1_clk",
1563                         .parent_hws = (const struct clk_hw*[]){
1564                                 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1565                         },
1566                         .num_parents = 1,
1567                         .flags = CLK_SET_RATE_PARENT,
1568                         .ops = &clk_branch2_ops,
1569                 },
1570         },
1571 };
1572
1573 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1574         .halt_reg = 0x213a4,
1575         .halt_check = BRANCH_HALT_VOTED,
1576         .clkr = {
1577                 .enable_reg = 0x52000,
1578                 .enable_mask = BIT(12),
1579                 .hw.init = &(struct clk_init_data){
1580                         .name = "gcc_qupv3_wrap0_s2_clk",
1581                         .parent_hws = (const struct clk_hw*[]){
1582                                 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1583                         },
1584                         .num_parents = 1,
1585                         .flags = CLK_SET_RATE_PARENT,
1586                         .ops = &clk_branch2_ops,
1587                 },
1588         },
1589 };
1590
1591 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1592         .halt_reg = 0x214d4,
1593         .halt_check = BRANCH_HALT_VOTED,
1594         .clkr = {
1595                 .enable_reg = 0x52000,
1596                 .enable_mask = BIT(13),
1597                 .hw.init = &(struct clk_init_data){
1598                         .name = "gcc_qupv3_wrap0_s3_clk",
1599                         .parent_hws = (const struct clk_hw*[]){
1600                                 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1601                         },
1602                         .num_parents = 1,
1603                         .flags = CLK_SET_RATE_PARENT,
1604                         .ops = &clk_branch2_ops,
1605                 },
1606         },
1607 };
1608
1609 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1610         .halt_reg = 0x21604,
1611         .halt_check = BRANCH_HALT_VOTED,
1612         .clkr = {
1613                 .enable_reg = 0x52000,
1614                 .enable_mask = BIT(14),
1615                 .hw.init = &(struct clk_init_data){
1616                         .name = "gcc_qupv3_wrap0_s4_clk",
1617                         .parent_hws = (const struct clk_hw*[]){
1618                                 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1619                         },
1620                         .num_parents = 1,
1621                         .flags = CLK_SET_RATE_PARENT,
1622                         .ops = &clk_branch2_ops,
1623                 },
1624         },
1625 };
1626
1627 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1628         .halt_reg = 0x21734,
1629         .halt_check = BRANCH_HALT_VOTED,
1630         .clkr = {
1631                 .enable_reg = 0x52000,
1632                 .enable_mask = BIT(15),
1633                 .hw.init = &(struct clk_init_data){
1634                         .name = "gcc_qupv3_wrap0_s5_clk",
1635                         .parent_hws = (const struct clk_hw*[]){
1636                                 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1637                         },
1638                         .num_parents = 1,
1639                         .flags = CLK_SET_RATE_PARENT,
1640                         .ops = &clk_branch2_ops,
1641                 },
1642         },
1643 };
1644
1645 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1646         .halt_reg = 0x22004,
1647         .halt_check = BRANCH_HALT_VOTED,
1648         .clkr = {
1649                 .enable_reg = 0x52000,
1650                 .enable_mask = BIT(16),
1651                 .hw.init = &(struct clk_init_data){
1652                         .name = "gcc_qupv3_wrap1_core_2x_clk",
1653                         .ops = &clk_branch2_ops,
1654                 },
1655         },
1656 };
1657
1658 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1659         .halt_reg = 0x22008,
1660         .halt_check = BRANCH_HALT_VOTED,
1661         .clkr = {
1662                 .enable_reg = 0x52000,
1663                 .enable_mask = BIT(17),
1664                 .hw.init = &(struct clk_init_data){
1665                         .name = "gcc_qupv3_wrap1_core_clk",
1666                         .ops = &clk_branch2_ops,
1667                 },
1668         },
1669 };
1670
1671 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1672         .halt_reg = 0x22014,
1673         .halt_check = BRANCH_HALT_VOTED,
1674         .clkr = {
1675                 .enable_reg = 0x52000,
1676                 .enable_mask = BIT(20),
1677                 .hw.init = &(struct clk_init_data){
1678                         .name = "gcc_qupv3_wrap1_s0_clk",
1679                         .parent_hws = (const struct clk_hw*[]){
1680                                 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1681                         },
1682                         .num_parents = 1,
1683                         .flags = CLK_SET_RATE_PARENT,
1684                         .ops = &clk_branch2_ops,
1685                 },
1686         },
1687 };
1688
1689 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1690         .halt_reg = 0x22144,
1691         .halt_check = BRANCH_HALT_VOTED,
1692         .clkr = {
1693                 .enable_reg = 0x52000,
1694                 .enable_mask = BIT(21),
1695                 .hw.init = &(struct clk_init_data){
1696                         .name = "gcc_qupv3_wrap1_s1_clk",
1697                         .parent_hws = (const struct clk_hw*[]){
1698                                 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1699                         },
1700                         .num_parents = 1,
1701                         .flags = CLK_SET_RATE_PARENT,
1702                         .ops = &clk_branch2_ops,
1703                 },
1704         },
1705 };
1706
1707 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1708         .halt_reg = 0x22274,
1709         .halt_check = BRANCH_HALT_VOTED,
1710         .clkr = {
1711                 .enable_reg = 0x52000,
1712                 .enable_mask = BIT(22),
1713                 .hw.init = &(struct clk_init_data){
1714                         .name = "gcc_qupv3_wrap1_s2_clk",
1715                         .parent_hws = (const struct clk_hw*[]){
1716                                 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1717                         },
1718                         .num_parents = 1,
1719                         .flags = CLK_SET_RATE_PARENT,
1720                         .ops = &clk_branch2_ops,
1721                 },
1722         },
1723 };
1724
1725 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1726         .halt_reg = 0x223a4,
1727         .halt_check = BRANCH_HALT_VOTED,
1728         .clkr = {
1729                 .enable_reg = 0x52000,
1730                 .enable_mask = BIT(23),
1731                 .hw.init = &(struct clk_init_data){
1732                         .name = "gcc_qupv3_wrap1_s3_clk",
1733                         .parent_hws = (const struct clk_hw*[]){
1734                                 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1735                         },
1736                         .num_parents = 1,
1737                         .flags = CLK_SET_RATE_PARENT,
1738                         .ops = &clk_branch2_ops,
1739                 },
1740         },
1741 };
1742
1743 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1744         .halt_reg = 0x224d4,
1745         .halt_check = BRANCH_HALT_VOTED,
1746         .clkr = {
1747                 .enable_reg = 0x52000,
1748                 .enable_mask = BIT(24),
1749                 .hw.init = &(struct clk_init_data){
1750                         .name = "gcc_qupv3_wrap1_s4_clk",
1751                         .parent_hws = (const struct clk_hw*[]){
1752                                 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1753                         },
1754                         .num_parents = 1,
1755                         .flags = CLK_SET_RATE_PARENT,
1756                         .ops = &clk_branch2_ops,
1757                 },
1758         },
1759 };
1760
1761 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
1762         .halt_reg = 0x22604,
1763         .halt_check = BRANCH_HALT_VOTED,
1764         .clkr = {
1765                 .enable_reg = 0x52000,
1766                 .enable_mask = BIT(25),
1767                 .hw.init = &(struct clk_init_data){
1768                         .name = "gcc_qupv3_wrap1_s5_clk",
1769                         .parent_hws = (const struct clk_hw*[]){
1770                                 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1771                         },
1772                         .num_parents = 1,
1773                         .flags = CLK_SET_RATE_PARENT,
1774                         .ops = &clk_branch2_ops,
1775                 },
1776         },
1777 };
1778
1779 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
1780         .halt_reg = 0x21004,
1781         .halt_check = BRANCH_HALT_VOTED,
1782         .hwcg_reg = 0x21004,
1783         .hwcg_bit = 1,
1784         .clkr = {
1785                 .enable_reg = 0x52000,
1786                 .enable_mask = BIT(6),
1787                 .hw.init = &(struct clk_init_data){
1788                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
1789                         .ops = &clk_branch2_ops,
1790                 },
1791         },
1792 };
1793
1794 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
1795         .halt_reg = 0x21008,
1796         .halt_check = BRANCH_HALT_VOTED,
1797         .hwcg_reg = 0x21008,
1798         .hwcg_bit = 1,
1799         .clkr = {
1800                 .enable_reg = 0x52000,
1801                 .enable_mask = BIT(7),
1802                 .hw.init = &(struct clk_init_data){
1803                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
1804                         .ops = &clk_branch2_ops,
1805                 },
1806         },
1807 };
1808
1809 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
1810         .halt_reg = 0x2200c,
1811         .halt_check = BRANCH_HALT_VOTED,
1812         .hwcg_reg = 0x2200c,
1813         .hwcg_bit = 1,
1814         .clkr = {
1815                 .enable_reg = 0x52000,
1816                 .enable_mask = BIT(18),
1817                 .hw.init = &(struct clk_init_data){
1818                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
1819                         .ops = &clk_branch2_ops,
1820                 },
1821         },
1822 };
1823
1824 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
1825         .halt_reg = 0x22010,
1826         .halt_check = BRANCH_HALT_VOTED,
1827         .hwcg_reg = 0x22010,
1828         .hwcg_bit = 1,
1829         .clkr = {
1830                 .enable_reg = 0x52000,
1831                 .enable_mask = BIT(19),
1832                 .hw.init = &(struct clk_init_data){
1833                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
1834                         .ops = &clk_branch2_ops,
1835                 },
1836         },
1837 };
1838
1839 static struct clk_branch gcc_sdcc1_ahb_clk = {
1840         .halt_reg = 0x4b004,
1841         .halt_check = BRANCH_HALT,
1842         .clkr = {
1843                 .enable_reg = 0x4b004,
1844                 .enable_mask = BIT(0),
1845                 .hw.init = &(struct clk_init_data){
1846                         .name = "gcc_sdcc1_ahb_clk",
1847                         .ops = &clk_branch2_ops,
1848                 },
1849         },
1850 };
1851
1852 static struct clk_branch gcc_sdcc1_apps_clk = {
1853         .halt_reg = 0x4b008,
1854         .halt_check = BRANCH_HALT,
1855         .clkr = {
1856                 .enable_reg = 0x4b008,
1857                 .enable_mask = BIT(0),
1858                 .hw.init = &(struct clk_init_data){
1859                         .name = "gcc_sdcc1_apps_clk",
1860                         .parent_hws = (const struct clk_hw*[]){
1861                                 &gcc_sdcc1_apps_clk_src.clkr.hw,
1862                         },
1863                         .num_parents = 1,
1864                         .flags = CLK_SET_RATE_PARENT,
1865                         .ops = &clk_branch2_ops,
1866                 },
1867         },
1868 };
1869
1870 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1871         .halt_reg = 0x4b03c,
1872         .halt_check = BRANCH_HALT,
1873         .hwcg_reg = 0x4b03c,
1874         .hwcg_bit = 1,
1875         .clkr = {
1876                 .enable_reg = 0x4b03c,
1877                 .enable_mask = BIT(0),
1878                 .hw.init = &(struct clk_init_data){
1879                         .name = "gcc_sdcc1_ice_core_clk",
1880                         .parent_hws = (const struct clk_hw*[]){
1881                                 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
1882                         },
1883                         .num_parents = 1,
1884                         .flags = CLK_SET_RATE_PARENT,
1885                         .ops = &clk_branch2_ops,
1886                 },
1887         },
1888 };
1889
1890 static struct clk_branch gcc_sdcc2_ahb_clk = {
1891         .halt_reg = 0x20008,
1892         .halt_check = BRANCH_HALT,
1893         .clkr = {
1894                 .enable_reg = 0x20008,
1895                 .enable_mask = BIT(0),
1896                 .hw.init = &(struct clk_init_data){
1897                         .name = "gcc_sdcc2_ahb_clk",
1898                         .ops = &clk_branch2_ops,
1899                 },
1900         },
1901 };
1902
1903 static struct clk_branch gcc_sdcc2_apps_clk = {
1904         .halt_reg = 0x20004,
1905         .halt_check = BRANCH_HALT,
1906         .clkr = {
1907                 .enable_reg = 0x20004,
1908                 .enable_mask = BIT(0),
1909                 .hw.init = &(struct clk_init_data){
1910                         .name = "gcc_sdcc2_apps_clk",
1911                         .parent_hws = (const struct clk_hw*[]){
1912                                 &gcc_sdcc2_apps_clk_src.clkr.hw,
1913                         },
1914                         .num_parents = 1,
1915                         .flags = CLK_SET_RATE_PARENT,
1916                         .ops = &clk_branch2_ops,
1917                 },
1918         },
1919 };
1920
1921 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
1922         .halt_reg = 0x10140,
1923         .halt_check = BRANCH_HALT_VOTED,
1924         .hwcg_reg = 0x10140,
1925         .hwcg_bit = 1,
1926         .clkr = {
1927                 .enable_reg = 0x52000,
1928                 .enable_mask = BIT(0),
1929                 .hw.init = &(struct clk_init_data){
1930                         .name = "gcc_sys_noc_cpuss_ahb_clk",
1931                         .parent_hws = (const struct clk_hw*[]){
1932                                 &gcc_cpuss_ahb_clk_src.clkr.hw,
1933                         },
1934                         .num_parents = 1,
1935                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1936                         .ops = &clk_branch2_ops,
1937                 },
1938         },
1939 };
1940
1941 static struct clk_branch gcc_ufs_mem_clkref_clk = {
1942         .halt_reg = 0x8c000,
1943         .halt_check = BRANCH_HALT,
1944         .clkr = {
1945                 .enable_reg = 0x8c000,
1946                 .enable_mask = BIT(0),
1947                 .hw.init = &(struct clk_init_data){
1948                         .name = "gcc_ufs_mem_clkref_clk",
1949                         .ops = &clk_branch2_ops,
1950                 },
1951         },
1952 };
1953
1954 static struct clk_branch gcc_ufs_phy_ahb_clk = {
1955         .halt_reg = 0x3a00c,
1956         .halt_check = BRANCH_HALT,
1957         .hwcg_reg = 0x3a00c,
1958         .hwcg_bit = 1,
1959         .clkr = {
1960                 .enable_reg = 0x3a00c,
1961                 .enable_mask = BIT(0),
1962                 .hw.init = &(struct clk_init_data){
1963                         .name = "gcc_ufs_phy_ahb_clk",
1964                         .ops = &clk_branch2_ops,
1965                 },
1966         },
1967 };
1968
1969 static struct clk_branch gcc_ufs_phy_axi_clk = {
1970         .halt_reg = 0x3a034,
1971         .halt_check = BRANCH_HALT,
1972         .hwcg_reg = 0x3a034,
1973         .hwcg_bit = 1,
1974         .clkr = {
1975                 .enable_reg = 0x3a034,
1976                 .enable_mask = BIT(0),
1977                 .hw.init = &(struct clk_init_data){
1978                         .name = "gcc_ufs_phy_axi_clk",
1979                         .parent_hws = (const struct clk_hw*[]){
1980                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1981                         },
1982                         .num_parents = 1,
1983                         .flags = CLK_SET_RATE_PARENT,
1984                         .ops = &clk_branch2_ops,
1985                 },
1986         },
1987 };
1988
1989 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
1990         .halt_reg = 0x3a0a4,
1991         .halt_check = BRANCH_HALT,
1992         .hwcg_reg = 0x3a0a4,
1993         .hwcg_bit = 1,
1994         .clkr = {
1995                 .enable_reg = 0x3a0a4,
1996                 .enable_mask = BIT(0),
1997                 .hw.init = &(struct clk_init_data){
1998                         .name = "gcc_ufs_phy_ice_core_clk",
1999                         .parent_hws = (const struct clk_hw*[]){
2000                                 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2001                         },
2002                         .num_parents = 1,
2003                         .flags = CLK_SET_RATE_PARENT,
2004                         .ops = &clk_branch2_ops,
2005                 },
2006         },
2007 };
2008
2009 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2010         .halt_reg = 0x3a0a4,
2011         .halt_check = BRANCH_HALT,
2012         .hwcg_reg = 0x3a0a4,
2013         .hwcg_bit = 1,
2014         .clkr = {
2015                 .enable_reg = 0x3a0a4,
2016                 .enable_mask = BIT(1),
2017                 .hw.init = &(struct clk_init_data){
2018                         .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2019                         .parent_hws = (const struct clk_hw*[]){
2020                                 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2021                         },
2022                         .num_parents = 1,
2023                         .flags = CLK_SET_RATE_PARENT,
2024                         .ops = &clk_branch2_ops,
2025                 },
2026         },
2027 };
2028
2029 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2030         .halt_reg = 0x3a0ac,
2031         .halt_check = BRANCH_HALT,
2032         .hwcg_reg = 0x3a0ac,
2033         .hwcg_bit = 1,
2034         .clkr = {
2035                 .enable_reg = 0x3a0ac,
2036                 .enable_mask = BIT(0),
2037                 .hw.init = &(struct clk_init_data){
2038                         .name = "gcc_ufs_phy_phy_aux_clk",
2039                         .parent_hws = (const struct clk_hw*[]){
2040                                 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2041                         },
2042                         .num_parents = 1,
2043                         .flags = CLK_SET_RATE_PARENT,
2044                         .ops = &clk_branch2_ops,
2045                 },
2046         },
2047 };
2048
2049 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2050         .halt_reg = 0x3a0ac,
2051         .halt_check = BRANCH_HALT,
2052         .hwcg_reg = 0x3a0ac,
2053         .hwcg_bit = 1,
2054         .clkr = {
2055                 .enable_reg = 0x3a0ac,
2056                 .enable_mask = BIT(1),
2057                 .hw.init = &(struct clk_init_data){
2058                         .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2059                         .parent_hws = (const struct clk_hw*[]){
2060                                 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2061                         },
2062                         .num_parents = 1,
2063                         .flags = CLK_SET_RATE_PARENT,
2064                         .ops = &clk_branch2_ops,
2065                 },
2066         },
2067 };
2068
2069 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2070         .halt_reg = 0x3a014,
2071         .halt_check = BRANCH_HALT_SKIP,
2072         .clkr = {
2073                 .enable_reg = 0x3a014,
2074                 .enable_mask = BIT(0),
2075                 .hw.init = &(struct clk_init_data){
2076                         .name = "gcc_ufs_phy_rx_symbol_0_clk",
2077                         .ops = &clk_branch2_ops,
2078                 },
2079         },
2080 };
2081
2082 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2083         .halt_reg = 0x3a018,
2084         .halt_check = BRANCH_HALT_SKIP,
2085         .clkr = {
2086                 .enable_reg = 0x3a018,
2087                 .enable_mask = BIT(0),
2088                 .hw.init = &(struct clk_init_data){
2089                         .name = "gcc_ufs_phy_rx_symbol_1_clk",
2090                         .ops = &clk_branch2_ops,
2091                 },
2092         },
2093 };
2094
2095 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2096         .halt_reg = 0x3a010,
2097         .halt_check = BRANCH_HALT_SKIP,
2098         .clkr = {
2099                 .enable_reg = 0x3a010,
2100                 .enable_mask = BIT(0),
2101                 .hw.init = &(struct clk_init_data){
2102                         .name = "gcc_ufs_phy_tx_symbol_0_clk",
2103                         .ops = &clk_branch2_ops,
2104                 },
2105         },
2106 };
2107
2108 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2109         .halt_reg = 0x3a09c,
2110         .halt_check = BRANCH_HALT,
2111         .hwcg_reg = 0x3a09c,
2112         .hwcg_bit = 1,
2113         .clkr = {
2114                 .enable_reg = 0x3a09c,
2115                 .enable_mask = BIT(0),
2116                 .hw.init = &(struct clk_init_data){
2117                         .name = "gcc_ufs_phy_unipro_core_clk",
2118                         .parent_hws = (const struct clk_hw*[]){
2119                                 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2120                         },
2121                         .num_parents = 1,
2122                         .flags = CLK_SET_RATE_PARENT,
2123                         .ops = &clk_branch2_ops,
2124                 },
2125         },
2126 };
2127
2128 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
2129         .halt_reg = 0x3a09c,
2130         .halt_check = BRANCH_HALT,
2131         .hwcg_reg = 0x3a09c,
2132         .hwcg_bit = 1,
2133         .clkr = {
2134                 .enable_reg = 0x3a09c,
2135                 .enable_mask = BIT(1),
2136                 .hw.init = &(struct clk_init_data){
2137                         .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
2138                         .parent_hws = (const struct clk_hw*[]){
2139                                 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2140                         },
2141                         .num_parents = 1,
2142                         .flags = CLK_SET_RATE_PARENT,
2143                         .ops = &clk_branch2_ops,
2144                 },
2145         },
2146 };
2147
2148 static struct clk_branch gcc_usb30_prim_master_clk = {
2149         .halt_reg = 0x1a00c,
2150         .halt_check = BRANCH_HALT,
2151         .clkr = {
2152                 .enable_reg = 0x1a00c,
2153                 .enable_mask = BIT(0),
2154                 .hw.init = &(struct clk_init_data){
2155                         .name = "gcc_usb30_prim_master_clk",
2156                         .parent_hws = (const struct clk_hw*[]){
2157                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
2158                         },
2159                         .num_parents = 1,
2160                         .flags = CLK_SET_RATE_PARENT,
2161                         .ops = &clk_branch2_ops,
2162                 },
2163         },
2164 };
2165
2166 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2167         .halt_reg = 0x1a018,
2168         .halt_check = BRANCH_HALT,
2169         .clkr = {
2170                 .enable_reg = 0x1a018,
2171                 .enable_mask = BIT(0),
2172                 .hw.init = &(struct clk_init_data){
2173                         .name = "gcc_usb30_prim_mock_utmi_clk",
2174                         .parent_hws = (const struct clk_hw*[]){
2175                                 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
2176                         },
2177                         .num_parents = 1,
2178                         .flags = CLK_SET_RATE_PARENT,
2179                         .ops = &clk_branch2_ops,
2180                 },
2181         },
2182 };
2183
2184 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2185         .halt_reg = 0x1a014,
2186         .halt_check = BRANCH_HALT,
2187         .clkr = {
2188                 .enable_reg = 0x1a014,
2189                 .enable_mask = BIT(0),
2190                 .hw.init = &(struct clk_init_data){
2191                         .name = "gcc_usb30_prim_sleep_clk",
2192                         .ops = &clk_branch2_ops,
2193                 },
2194         },
2195 };
2196
2197 static struct clk_branch gcc_usb3_prim_clkref_clk = {
2198         .halt_reg = 0x8c010,
2199         .halt_check = BRANCH_HALT,
2200         .clkr = {
2201                 .enable_reg = 0x8c010,
2202                 .enable_mask = BIT(0),
2203                 .hw.init = &(struct clk_init_data){
2204                         .name = "gcc_usb3_prim_clkref_clk",
2205                         .ops = &clk_branch2_ops,
2206                 },
2207         },
2208 };
2209
2210 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2211         .halt_reg = 0x1a050,
2212         .halt_check = BRANCH_HALT,
2213         .clkr = {
2214                 .enable_reg = 0x1a050,
2215                 .enable_mask = BIT(0),
2216                 .hw.init = &(struct clk_init_data){
2217                         .name = "gcc_usb3_prim_phy_aux_clk",
2218                         .parent_hws = (const struct clk_hw*[]){
2219                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2220                         },
2221                         .num_parents = 1,
2222                         .flags = CLK_SET_RATE_PARENT,
2223                         .ops = &clk_branch2_ops,
2224                 },
2225         },
2226 };
2227
2228 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2229         .halt_reg = 0x1a054,
2230         .halt_check = BRANCH_HALT,
2231         .clkr = {
2232                 .enable_reg = 0x1a054,
2233                 .enable_mask = BIT(0),
2234                 .hw.init = &(struct clk_init_data){
2235                         .name = "gcc_usb3_prim_phy_com_aux_clk",
2236                         .parent_hws = (const struct clk_hw*[]){
2237                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2238                         },
2239                         .num_parents = 1,
2240                         .flags = CLK_SET_RATE_PARENT,
2241                         .ops = &clk_branch2_ops,
2242                 },
2243         },
2244 };
2245
2246 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2247         .halt_reg = 0x1a058,
2248         .halt_check = BRANCH_HALT_SKIP,
2249         .hwcg_reg = 0x1a058,
2250         .hwcg_bit = 1,
2251         .clkr = {
2252                 .enable_reg = 0x1a058,
2253                 .enable_mask = BIT(0),
2254                 .hw.init = &(struct clk_init_data){
2255                         .name = "gcc_usb3_prim_phy_pipe_clk",
2256                         .ops = &clk_branch2_ops,
2257                 },
2258         },
2259 };
2260
2261 static struct clk_branch gcc_video_ahb_clk = {
2262         .halt_reg = 0x17004,
2263         .halt_check = BRANCH_HALT,
2264         .hwcg_reg = 0x17004,
2265         .hwcg_bit = 1,
2266         .clkr = {
2267                 .enable_reg = 0x17004,
2268                 .enable_mask = BIT(0),
2269                 .hw.init = &(struct clk_init_data){
2270                         .name = "gcc_video_ahb_clk",
2271                         .flags = CLK_IS_CRITICAL,
2272                         .ops = &clk_branch2_ops,
2273                 },
2274         },
2275 };
2276
2277 static struct clk_branch gcc_video_axi_clk = {
2278         .halt_reg = 0x17014,
2279         .halt_check = BRANCH_HALT,
2280         .hwcg_reg = 0x17014,
2281         .hwcg_bit = 1,
2282         .clkr = {
2283                 .enable_reg = 0x17014,
2284                 .enable_mask = BIT(0),
2285                 .hw.init = &(struct clk_init_data){
2286                         .name = "gcc_video_axi_clk",
2287                         .ops = &clk_branch2_ops,
2288                 },
2289         },
2290 };
2291
2292 static struct clk_branch gcc_video_throttle_axi_clk = {
2293         .halt_reg = 0x17020,
2294         .halt_check = BRANCH_HALT,
2295         .hwcg_reg = 0x17020,
2296         .hwcg_bit = 1,
2297         .clkr = {
2298                 .enable_reg = 0x17020,
2299                 .enable_mask = BIT(0),
2300                 .hw.init = &(struct clk_init_data){
2301                         .name = "gcc_video_throttle_axi_clk",
2302                         .ops = &clk_branch2_ops,
2303                 },
2304         },
2305 };
2306
2307 static struct clk_branch gcc_video_xo_clk = {
2308         .halt_reg = 0x1702c,
2309         .halt_check = BRANCH_HALT,
2310         .clkr = {
2311                 .enable_reg = 0x1702c,
2312                 .enable_mask = BIT(0),
2313                 .hw.init = &(struct clk_init_data){
2314                         .name = "gcc_video_xo_clk",
2315                         .flags = CLK_IS_CRITICAL,
2316                         .ops = &clk_branch2_ops,
2317                 },
2318         },
2319 };
2320
2321 static struct gdsc usb30_prim_gdsc = {
2322         .gdscr = 0x1a004,
2323         .pd = {
2324                 .name = "usb30_prim_gdsc",
2325         },
2326         .pwrsts = PWRSTS_RET_ON,
2327 };
2328
2329 static struct gdsc ufs_phy_gdsc = {
2330         .gdscr = 0x3a004,
2331         .pd = {
2332                 .name = "ufs_phy_gdsc",
2333         },
2334         .pwrsts = PWRSTS_OFF_ON,
2335 };
2336
2337 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
2338         .gdscr = 0xb7040,
2339         .pd = {
2340                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
2341         },
2342         .pwrsts = PWRSTS_OFF_ON,
2343         .flags = VOTABLE,
2344 };
2345
2346 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
2347         .gdscr = 0xb7044,
2348         .pd = {
2349                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
2350         },
2351         .pwrsts = PWRSTS_OFF_ON,
2352         .flags = VOTABLE,
2353 };
2354
2355 static struct clk_regmap *gcc_sm6350_clocks[] = {
2356         [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2357         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2358         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2359         [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
2360         [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
2361         [GCC_CAMERA_THROTTLE_NRT_AXI_CLK] =
2362                 &gcc_camera_throttle_nrt_axi_clk.clkr,
2363         [GCC_CAMERA_THROTTLE_RT_AXI_CLK] = &gcc_camera_throttle_rt_axi_clk.clkr,
2364         [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
2365         [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2366         [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2367         [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2368         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2369         [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
2370         [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
2371         [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
2372         [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
2373         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2374         [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
2375         [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
2376         [GCC_DISP_CC_SLEEP_CLK] = &gcc_disp_cc_sleep_clk.clkr,
2377         [GCC_DISP_CC_XO_CLK] = &gcc_disp_cc_xo_clk.clkr,
2378         [GCC_DISP_GPLL0_CLK] = &gcc_disp_gpll0_clk.clkr,
2379         [GCC_DISP_THROTTLE_AXI_CLK] = &gcc_disp_throttle_axi_clk.clkr,
2380         [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
2381         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2382         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2383         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2384         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2385         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2386         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2387         [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2388         [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
2389         [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
2390         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2391         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2392         [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
2393         [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
2394         [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
2395         [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
2396         [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
2397         [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
2398         [GCC_NPU_GPLL0_CLK] = &gcc_npu_gpll0_clk.clkr,
2399         [GCC_NPU_GPLL0_DIV_CLK] = &gcc_npu_gpll0_div_clk.clkr,
2400         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2401         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2402         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2403         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2404         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2405         [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2406         [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2407         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2408         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2409         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2410         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2411         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2412         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2413         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2414         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2415         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2416         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2417         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2418         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2419         [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2420         [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2421         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2422         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2423         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2424         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2425         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2426         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2427         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2428         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2429         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2430         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2431         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2432         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2433         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2434         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2435         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2436         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2437         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2438         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2439         [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2440         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2441         [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2442         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2443         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2444         [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2445         [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2446         [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
2447         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
2448         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
2449         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
2450         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
2451         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
2452         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
2453         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
2454         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
2455         [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
2456         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
2457         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
2458         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
2459                 &gcc_ufs_phy_unipro_core_clk_src.clkr,
2460         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2461         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2462         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2463         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
2464                 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2465         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2466         [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2467         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2468         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2469         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2470         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2471         [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
2472         [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
2473         [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
2474         [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
2475         [GPLL0] = &gpll0.clkr,
2476         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2477         [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
2478         [GPLL6] = &gpll6.clkr,
2479         [GPLL6_OUT_EVEN] = &gpll6_out_even.clkr,
2480         [GPLL7] = &gpll7.clkr,
2481         [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
2482         [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
2483         [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
2484                                 &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
2485         [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
2486                                 &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
2487         [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
2488                                 &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
2489         [GCC_GPU_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_gpu_gpll0_main_div_clk_src.clkr,
2490         [GCC_NPU_PLL0_MAIN_DIV_CLK_SRC] = &gcc_npu_pll0_main_div_clk_src.clkr,
2491 };
2492
2493 static struct gdsc *gcc_sm6350_gdscs[] = {
2494         [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2495         [UFS_PHY_GDSC] = &ufs_phy_gdsc,
2496         [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
2497         [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
2498 };
2499
2500 static const struct qcom_reset_map gcc_sm6350_resets[] = {
2501         [GCC_QUSB2PHY_PRIM_BCR] = { 0x1d000 },
2502         [GCC_QUSB2PHY_SEC_BCR] = { 0x1e000 },
2503         [GCC_SDCC1_BCR] = { 0x4b000 },
2504         [GCC_SDCC2_BCR] = { 0x20000 },
2505         [GCC_UFS_PHY_BCR] = { 0x3a000 },
2506         [GCC_USB30_PRIM_BCR] = { 0x1a000 },
2507         [GCC_USB3_PHY_PRIM_BCR] = { 0x1c000 },
2508         [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1c008 },
2509 };
2510
2511 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2512         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2513         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2514         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2515         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2516         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2517         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2518         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2519         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2520         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2521         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2522         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2523         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2524 };
2525
2526 static const struct regmap_config gcc_sm6350_regmap_config = {
2527         .reg_bits = 32,
2528         .reg_stride = 4,
2529         .val_bits = 32,
2530         .max_register = 0xbf030,
2531         .fast_io = true,
2532 };
2533
2534 static const struct qcom_cc_desc gcc_sm6350_desc = {
2535         .config = &gcc_sm6350_regmap_config,
2536         .clks = gcc_sm6350_clocks,
2537         .num_clks = ARRAY_SIZE(gcc_sm6350_clocks),
2538         .resets = gcc_sm6350_resets,
2539         .num_resets = ARRAY_SIZE(gcc_sm6350_resets),
2540         .gdscs = gcc_sm6350_gdscs,
2541         .num_gdscs = ARRAY_SIZE(gcc_sm6350_gdscs),
2542 };
2543
2544 static const struct of_device_id gcc_sm6350_match_table[] = {
2545         { .compatible = "qcom,gcc-sm6350" },
2546         { }
2547 };
2548 MODULE_DEVICE_TABLE(of, gcc_sm6350_match_table);
2549
2550 static int gcc_sm6350_probe(struct platform_device *pdev)
2551 {
2552         struct regmap *regmap;
2553         int ret;
2554
2555         regmap = qcom_cc_map(pdev, &gcc_sm6350_desc);
2556         if (IS_ERR(regmap))
2557                 return PTR_ERR(regmap);
2558
2559         /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
2560         regmap_update_bits(regmap, 0x4cf00, 0x3, 0x3);
2561         regmap_update_bits(regmap, 0x45f00, 0x3, 0x3);
2562
2563         ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2564                         ARRAY_SIZE(gcc_dfs_clocks));
2565         if (ret)
2566                 return ret;
2567
2568         return qcom_cc_really_probe(&pdev->dev, &gcc_sm6350_desc, regmap);
2569 }
2570
2571 static struct platform_driver gcc_sm6350_driver = {
2572         .probe = gcc_sm6350_probe,
2573         .driver = {
2574                 .name = "gcc-sm6350",
2575                 .of_match_table = gcc_sm6350_match_table,
2576         },
2577 };
2578
2579 static int __init gcc_sm6350_init(void)
2580 {
2581         return platform_driver_register(&gcc_sm6350_driver);
2582 }
2583 core_initcall(gcc_sm6350_init);
2584
2585 static void __exit gcc_sm6350_exit(void)
2586 {
2587         platform_driver_unregister(&gcc_sm6350_driver);
2588 }
2589 module_exit(gcc_sm6350_exit);
2590
2591 MODULE_DESCRIPTION("QTI GCC SM6350 Driver");
2592 MODULE_LICENSE("GPL v2");