drivers/net/ethernet/intel/igb/igb_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
   3
   4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   5
   6 #include <linux/module.h>
   7 #include <linux/types.h>
   8 #include <linux/init.h>
   9 #include <linux/bitops.h>
  10 #include <linux/vmalloc.h>
  11 #include <linux/pagemap.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/ipv6.h>
  14 #include <linux/slab.h>
  15 #include <net/checksum.h>
  16 #include <net/ip6_checksum.h>
  17 #include <net/pkt_sched.h>
  18 #include <net/pkt_cls.h>
  19 #include <linux/net_tstamp.h>
  20 #include <linux/mii.h>
  21 #include <linux/ethtool.h>
  22 #include <linux/if.h>
  23 #include <linux/if_vlan.h>
  24 #include <linux/pci.h>
  25 #include <linux/delay.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/ip.h>
  28 #include <linux/tcp.h>
  29 #include <linux/sctp.h>
  30 #include <linux/if_ether.h>
  31 #include <linux/aer.h>
  32 #include <linux/prefetch.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/etherdevice.h>
  35 #ifdef CONFIG_IGB_DCA
  36 #include <linux/dca.h>
  37 #endif
  38 #include <linux/i2c.h>
  39 #include "igb.h"
  40
  41 #define MAJ 5
  42 #define MIN 6
  43 #define BUILD 0
  44 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  45 __stringify(BUILD) "-k"
  46
  47 enum queue_mode {
  48         QUEUE_MODE_STRICT_PRIORITY,
  49         QUEUE_MODE_STREAM_RESERVATION,
  50 };
  51
  52 enum tx_queue_prio {
  53         TX_QUEUE_PRIO_HIGH,
  54         TX_QUEUE_PRIO_LOW,
  55 };
  56
  57 char igb_driver_name[] = "igb";
  58 char igb_driver_version[] = DRV_VERSION;
  59 static const char igb_driver_string[] =
  60                                 "Intel(R) Gigabit Ethernet Network Driver";
  61 static const char igb_copyright[] =
  62                                 "Copyright (c) 2007-2014 Intel Corporation.";
  63
  64 static const struct e1000_info *igb_info_tbl[] = {
  65         [board_82575] = &e1000_82575_info,
  66 };
  67
  68 static const struct pci_device_id igb_pci_tbl[] = {
  69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
  70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
  71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
  72         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
  73         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
  74         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
  75         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
  76         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
  77         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
  78         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
  79         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
  80         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
  81         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
  82         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
  83         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
  84         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
  85         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
  86         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
  87         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
  88         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
  89         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
  90         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
  91         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
  92         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
  93         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  94         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  95         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
  96         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  97         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  98         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
  99         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
 100         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
 101         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
 102         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
 103         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
 104         /* required last entry */
 105         {0, }
 106 };
 107
 108 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
 109
 110 static int igb_setup_all_tx_resources(struct igb_adapter *);
 111 static int igb_setup_all_rx_resources(struct igb_adapter *);
 112 static void igb_free_all_tx_resources(struct igb_adapter *);
 113 static void igb_free_all_rx_resources(struct igb_adapter *);
 114 static void igb_setup_mrqc(struct igb_adapter *);
 115 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
 116 static void igb_remove(struct pci_dev *pdev);
 117 static int igb_sw_init(struct igb_adapter *);
 118 int igb_open(struct net_device *);
 119 int igb_close(struct net_device *);
 120 static void igb_configure(struct igb_adapter *);
 121 static void igb_configure_tx(struct igb_adapter *);
 122 static void igb_configure_rx(struct igb_adapter *);
 123 static void igb_clean_all_tx_rings(struct igb_adapter *);
 124 static void igb_clean_all_rx_rings(struct igb_adapter *);
 125 static void igb_clean_tx_ring(struct igb_ring *);
 126 static void igb_clean_rx_ring(struct igb_ring *);
 127 static void igb_set_rx_mode(struct net_device *);
 128 static void igb_update_phy_info(struct timer_list *);
 129 static void igb_watchdog(struct timer_list *);
 130 static void igb_watchdog_task(struct work_struct *);
 131 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
 132 static void igb_get_stats64(struct net_device *dev,
 133                             struct rtnl_link_stats64 *stats);
 134 static int igb_change_mtu(struct net_device *, int);
 135 static int igb_set_mac(struct net_device *, void *);
 136 static void igb_set_uta(struct igb_adapter *adapter, bool set);
 137 static irqreturn_t igb_intr(int irq, void *);
 138 static irqreturn_t igb_intr_msi(int irq, void *);
 139 static irqreturn_t igb_msix_other(int irq, void *);
 140 static irqreturn_t igb_msix_ring(int irq, void *);
 141 #ifdef CONFIG_IGB_DCA
 142 static void igb_update_dca(struct igb_q_vector *);
 143 static void igb_setup_dca(struct igb_adapter *);
 144 #endif /* CONFIG_IGB_DCA */
 145 static int igb_poll(struct napi_struct *, int);
 146 static bool igb_clean_tx_irq(struct igb_q_vector *, int);
 147 static int igb_clean_rx_irq(struct igb_q_vector *, int);
 148 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 149 static void igb_tx_timeout(struct net_device *);
 150 static void igb_reset_task(struct work_struct *);
 151 static void igb_vlan_mode(struct net_device *netdev,
 152                           netdev_features_t features);
 153 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
 154 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
 155 static void igb_restore_vlan(struct igb_adapter *);
 156 static void igb_rar_set_index(struct igb_adapter *, u32);
 157 static void igb_ping_all_vfs(struct igb_adapter *);
 158 static void igb_msg_task(struct igb_adapter *);
 159 static void igb_vmm_control(struct igb_adapter *);
 160 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
 161 static void igb_flush_mac_table(struct igb_adapter *);
 162 static int igb_available_rars(struct igb_adapter *, u8);
 163 static void igb_set_default_mac_filter(struct igb_adapter *);
 164 static int igb_uc_sync(struct net_device *, const unsigned char *);
 165 static int igb_uc_unsync(struct net_device *, const unsigned char *);
 166 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 167 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
 168 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
 169                                int vf, u16 vlan, u8 qos, __be16 vlan_proto);
 170 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
 171 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
 172                                    bool setting);
 173 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf,
 174                                 bool setting);
 175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
 176                                  struct ifla_vf_info *ivi);
 177 static void igb_check_vf_rate_limit(struct igb_adapter *);
 178 static void igb_nfc_filter_exit(struct igb_adapter *adapter);
 179 static void igb_nfc_filter_restore(struct igb_adapter *adapter);
 180
 181 #ifdef CONFIG_PCI_IOV
 182 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
 183 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
 184 static int igb_disable_sriov(struct pci_dev *dev);
 185 static int igb_pci_disable_sriov(struct pci_dev *dev);
 186 #endif
 187
 188 static int igb_suspend(struct device *);
 189 static int igb_resume(struct device *);
 190 static int igb_runtime_suspend(struct device *dev);
 191 static int igb_runtime_resume(struct device *dev);
 192 static int igb_runtime_idle(struct device *dev);
 193 static const struct dev_pm_ops igb_pm_ops = {
 194         SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
 195         SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
 196                         igb_runtime_idle)
 197 };
 198 static void igb_shutdown(struct pci_dev *);
 199 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
 200 #ifdef CONFIG_IGB_DCA
 201 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 202 static struct notifier_block dca_notifier = {
 203         .notifier_call  = igb_notify_dca,
 204         .next           = NULL,
 205         .priority       = 0
 206 };
 207 #endif
 208 #ifdef CONFIG_PCI_IOV
 209 static unsigned int max_vfs;
 210 module_param(max_vfs, uint, 0);
 211 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
 212 #endif /* CONFIG_PCI_IOV */
 213
 214 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 215                      pci_channel_state_t);
 216 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 217 static void igb_io_resume(struct pci_dev *);
 218
 219 static const struct pci_error_handlers igb_err_handler = {
 220         .error_detected = igb_io_error_detected,
 221         .slot_reset = igb_io_slot_reset,
 222         .resume = igb_io_resume,
 223 };
 224
 225 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
 226
 227 static struct pci_driver igb_driver = {
 228         .name     = igb_driver_name,
 229         .id_table = igb_pci_tbl,
 230         .probe    = igb_probe,
 231         .remove   = igb_remove,
 232 #ifdef CONFIG_PM
 233         .driver.pm = &igb_pm_ops,
 234 #endif
 235         .shutdown = igb_shutdown,
 236         .sriov_configure = igb_pci_sriov_configure,
 237         .err_handler = &igb_err_handler
 238 };
 239
 240 MODULE_AUTHOR("Intel Corporation, <[email protected]>");
 241 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 242 MODULE_LICENSE("GPL v2");
 243 MODULE_VERSION(DRV_VERSION);
 244
 245 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
 246 static int debug = -1;
 247 module_param(debug, int, 0);
 248 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 249
 250 struct igb_reg_info {
 251         u32 ofs;
 252         char *name;
 253 };
 254
 255 static const struct igb_reg_info igb_reg_info_tbl[] = {
 256
 257         /* General Registers */
 258         {E1000_CTRL, "CTRL"},
 259         {E1000_STATUS, "STATUS"},
 260         {E1000_CTRL_EXT, "CTRL_EXT"},
 261
 262         /* Interrupt Registers */
 263         {E1000_ICR, "ICR"},
 264
 265         /* RX Registers */
 266         {E1000_RCTL, "RCTL"},
 267         {E1000_RDLEN(0), "RDLEN"},
 268         {E1000_RDH(0), "RDH"},
 269         {E1000_RDT(0), "RDT"},
 270         {E1000_RXDCTL(0), "RXDCTL"},
 271         {E1000_RDBAL(0), "RDBAL"},
 272         {E1000_RDBAH(0), "RDBAH"},
 273
 274         /* TX Registers */
 275         {E1000_TCTL, "TCTL"},
 276         {E1000_TDBAL(0), "TDBAL"},
 277         {E1000_TDBAH(0), "TDBAH"},
 278         {E1000_TDLEN(0), "TDLEN"},
 279         {E1000_TDH(0), "TDH"},
 280         {E1000_TDT(0), "TDT"},
 281         {E1000_TXDCTL(0), "TXDCTL"},
 282         {E1000_TDFH, "TDFH"},
 283         {E1000_TDFT, "TDFT"},
 284         {E1000_TDFHS, "TDFHS"},
 285         {E1000_TDFPC, "TDFPC"},
 286
 287         /* List Terminator */
 288         {}
 289 };
 290
 291 /* igb_regdump - register printout routine */
 292 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
 293 {
 294         int n = 0;
 295         char rname[16];
 296         u32 regs[8];
 297
 298         switch (reginfo->ofs) {
 299         case E1000_RDLEN(0):
 300                 for (n = 0; n < 4; n++)
 301                         regs[n] = rd32(E1000_RDLEN(n));
 302                 break;
 303         case E1000_RDH(0):
 304                 for (n = 0; n < 4; n++)
 305                         regs[n] = rd32(E1000_RDH(n));
 306                 break;
 307         case E1000_RDT(0):
 308                 for (n = 0; n < 4; n++)
 309                         regs[n] = rd32(E1000_RDT(n));
 310                 break;
 311         case E1000_RXDCTL(0):
 312                 for (n = 0; n < 4; n++)
 313                         regs[n] = rd32(E1000_RXDCTL(n));
 314                 break;
 315         case E1000_RDBAL(0):
 316                 for (n = 0; n < 4; n++)
 317                         regs[n] = rd32(E1000_RDBAL(n));
 318                 break;
 319         case E1000_RDBAH(0):
 320                 for (n = 0; n < 4; n++)
 321                         regs[n] = rd32(E1000_RDBAH(n));
 322                 break;
 323         case E1000_TDBAL(0):
 324                 for (n = 0; n < 4; n++)
 325                         regs[n] = rd32(E1000_RDBAL(n));
 326                 break;
 327         case E1000_TDBAH(0):
 328                 for (n = 0; n < 4; n++)
 329                         regs[n] = rd32(E1000_TDBAH(n));
 330                 break;
 331         case E1000_TDLEN(0):
 332                 for (n = 0; n < 4; n++)
 333                         regs[n] = rd32(E1000_TDLEN(n));
 334                 break;
 335         case E1000_TDH(0):
 336                 for (n = 0; n < 4; n++)
 337                         regs[n] = rd32(E1000_TDH(n));
 338                 break;
 339         case E1000_TDT(0):
 340                 for (n = 0; n < 4; n++)
 341                         regs[n] = rd32(E1000_TDT(n));
 342                 break;
 343         case E1000_TXDCTL(0):
 344                 for (n = 0; n < 4; n++)
 345                         regs[n] = rd32(E1000_TXDCTL(n));
 346                 break;
 347         default:
 348                 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
 349                 return;
 350         }
 351
 352         snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
 353         pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
 354                 regs[2], regs[3]);
 355 }
 356
 357 /* igb_dump - Print registers, Tx-rings and Rx-rings */
 358 static void igb_dump(struct igb_adapter *adapter)
 359 {
 360         struct net_device *netdev = adapter->netdev;
 361         struct e1000_hw *hw = &adapter->hw;
 362         struct igb_reg_info *reginfo;
 363         struct igb_ring *tx_ring;
 364         union e1000_adv_tx_desc *tx_desc;
 365         struct my_u0 { u64 a; u64 b; } *u0;
 366         struct igb_ring *rx_ring;
 367         union e1000_adv_rx_desc *rx_desc;
 368         u32 staterr;
 369         u16 i, n;
 370
 371         if (!netif_msg_hw(adapter))
 372                 return;
 373
 374         /* Print netdevice Info */
 375         if (netdev) {
 376                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 377                 pr_info("Device Name     state            trans_start\n");
 378                 pr_info("%-15s %016lX %016lX\n", netdev->name,
 379                         netdev->state, dev_trans_start(netdev));
 380         }
 381
 382         /* Print Registers */
 383         dev_info(&adapter->pdev->dev, "Register Dump\n");
 384         pr_info(" Register Name   Value\n");
 385         for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
 386              reginfo->name; reginfo++) {
 387                 igb_regdump(hw, reginfo);
 388         }
 389
 390         /* Print TX Ring Summary */
 391         if (!netdev || !netif_running(netdev))
 392                 goto exit;
 393
 394         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 395         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 396         for (n = 0; n < adapter->num_tx_queues; n++) {
 397                 struct igb_tx_buffer *buffer_info;
 398                 tx_ring = adapter->tx_ring[n];
 399                 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 400                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 401                         n, tx_ring->next_to_use, tx_ring->next_to_clean,
 402                         (u64)dma_unmap_addr(buffer_info, dma),
 403                         dma_unmap_len(buffer_info, len),
 404                         buffer_info->next_to_watch,
 405                         (u64)buffer_info->time_stamp);
 406         }
 407
 408         /* Print TX Rings */
 409         if (!netif_msg_tx_done(adapter))
 410                 goto rx_ring_summary;
 411
 412         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 413
 414         /* Transmit Descriptor Formats
 415          *
 416          * Advanced Transmit Descriptor
 417          *   +--------------------------------------------------------------+
 418          * 0 |         Buffer Address [63:0]                                |
 419          *   +--------------------------------------------------------------+
 420          * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
 421          *   +--------------------------------------------------------------+
 422          *   63      46 45    40 39 38 36 35 32 31   24             15       0
 423          */
 424
 425         for (n = 0; n < adapter->num_tx_queues; n++) {
 426                 tx_ring = adapter->tx_ring[n];
 427                 pr_info("------------------------------------\n");
 428                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 429                 pr_info("------------------------------------\n");
 430                 pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] [bi->dma       ] leng  ntw timestamp        bi->skb\n");
 431
 432                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 433                         const char *next_desc;
 434                         struct igb_tx_buffer *buffer_info;
 435                         tx_desc = IGB_TX_DESC(tx_ring, i);
 436                         buffer_info = &tx_ring->tx_buffer_info[i];
 437                         u0 = (struct my_u0 *)tx_desc;
 438                         if (i == tx_ring->next_to_use &&
 439                             i == tx_ring->next_to_clean)
 440                                 next_desc = " NTC/U";
 441                         else if (i == tx_ring->next_to_use)
 442                                 next_desc = " NTU";
 443                         else if (i == tx_ring->next_to_clean)
 444                                 next_desc = " NTC";
 445                         else
 446                                 next_desc = "";
 447
 448                         pr_info("T [0x%03X]    %016llX %016llX %016llX %04X  %p %016llX %p%s\n",
 449                                 i, le64_to_cpu(u0->a),
 450                                 le64_to_cpu(u0->b),
 451                                 (u64)dma_unmap_addr(buffer_info, dma),
 452                                 dma_unmap_len(buffer_info, len),
 453                                 buffer_info->next_to_watch,
 454                                 (u64)buffer_info->time_stamp,
 455                                 buffer_info->skb, next_desc);
 456
 457                         if (netif_msg_pktdata(adapter) && buffer_info->skb)
 458                                 print_hex_dump(KERN_INFO, "",
 459                                         DUMP_PREFIX_ADDRESS,
 460                                         16, 1, buffer_info->skb->data,
 461                                         dma_unmap_len(buffer_info, len),
 462                                         true);
 463                 }
 464         }
 465
 466         /* Print RX Rings Summary */
 467 rx_ring_summary:
 468         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 469         pr_info("Queue [NTU] [NTC]\n");
 470         for (n = 0; n < adapter->num_rx_queues; n++) {
 471                 rx_ring = adapter->rx_ring[n];
 472                 pr_info(" %5d %5X %5X\n",
 473                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 474         }
 475
 476         /* Print RX Rings */
 477         if (!netif_msg_rx_status(adapter))
 478                 goto exit;
 479
 480         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 481
 482         /* Advanced Receive Descriptor (Read) Format
 483          *    63                                           1        0
 484          *    +-----------------------------------------------------+
 485          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 486          *    +----------------------------------------------+------+
 487          *  8 |       Header Buffer Address [63:1]           |  DD  |
 488          *    +-----------------------------------------------------+
 489          *
 490          *
 491          * Advanced Receive Descriptor (Write-Back) Format
 492          *
 493          *   63       48 47    32 31  30      21 20 17 16   4 3     0
 494          *   +------------------------------------------------------+
 495          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 496          *   | Checksum   Ident  |   |           |    | Type | Type |
 497          *   +------------------------------------------------------+
 498          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 499          *   +------------------------------------------------------+
 500          *   63       48 47    32 31            20 19               0
 501          */
 502
 503         for (n = 0; n < adapter->num_rx_queues; n++) {
 504                 rx_ring = adapter->rx_ring[n];
 505                 pr_info("------------------------------------\n");
 506                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 507                 pr_info("------------------------------------\n");
 508                 pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] [bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
 509                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
 510
 511                 for (i = 0; i < rx_ring->count; i++) {
 512                         const char *next_desc;
 513                         struct igb_rx_buffer *buffer_info;
 514                         buffer_info = &rx_ring->rx_buffer_info[i];
 515                         rx_desc = IGB_RX_DESC(rx_ring, i);
 516                         u0 = (struct my_u0 *)rx_desc;
 517                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 518
 519                         if (i == rx_ring->next_to_use)
 520                                 next_desc = " NTU";
 521                         else if (i == rx_ring->next_to_clean)
 522                                 next_desc = " NTC";
 523                         else
 524                                 next_desc = "";
 525
 526                         if (staterr & E1000_RXD_STAT_DD) {
 527                                 /* Descriptor Done */
 528                                 pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
 529                                         "RWB", i,
 530                                         le64_to_cpu(u0->a),
 531                                         le64_to_cpu(u0->b),
 532                                         next_desc);
 533                         } else {
 534                                 pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
 535                                         "R  ", i,
 536                                         le64_to_cpu(u0->a),
 537                                         le64_to_cpu(u0->b),
 538                                         (u64)buffer_info->dma,
 539                                         next_desc);
 540
 541                                 if (netif_msg_pktdata(adapter) &&
 542                                     buffer_info->dma && buffer_info->page) {
 543                                         print_hex_dump(KERN_INFO, "",
 544                                           DUMP_PREFIX_ADDRESS,
 545                                           16, 1,
 546                                           page_address(buffer_info->page) +
 547                                                       buffer_info->page_offset,
 548                                           igb_rx_bufsz(rx_ring), true);
 549                                 }
 550                         }
 551                 }
 552         }
 553
 554 exit:
 555         return;
 556 }
 557
 558 /**
 559  *  igb_get_i2c_data - Reads the I2C SDA data bit
 560  *  @hw: pointer to hardware structure
 561  *  @i2cctl: Current value of I2CCTL register
 562  *
 563  *  Returns the I2C data bit value
 564  **/
 565 static int igb_get_i2c_data(void *data)
 566 {
 567         struct igb_adapter *adapter = (struct igb_adapter *)data;
 568         struct e1000_hw *hw = &adapter->hw;
 569         s32 i2cctl = rd32(E1000_I2CPARAMS);
 570
 571         return !!(i2cctl & E1000_I2C_DATA_IN);
 572 }
 573
 574 /**
 575  *  igb_set_i2c_data - Sets the I2C data bit
 576  *  @data: pointer to hardware structure
 577  *  @state: I2C data value (0 or 1) to set
 578  *
 579  *  Sets the I2C data bit
 580  **/
 581 static void igb_set_i2c_data(void *data, int state)
 582 {
 583         struct igb_adapter *adapter = (struct igb_adapter *)data;
 584         struct e1000_hw *hw = &adapter->hw;
 585         s32 i2cctl = rd32(E1000_I2CPARAMS);
 586
 587         if (state)
 588                 i2cctl |= E1000_I2C_DATA_OUT;
 589         else
 590                 i2cctl &= ~E1000_I2C_DATA_OUT;
 591
 592         i2cctl &= ~E1000_I2C_DATA_OE_N;
 593         i2cctl |= E1000_I2C_CLK_OE_N;
 594         wr32(E1000_I2CPARAMS, i2cctl);
 595         wrfl();
 596
 597 }
 598
 599 /**
 600  *  igb_set_i2c_clk - Sets the I2C SCL clock
 601  *  @data: pointer to hardware structure
 602  *  @state: state to set clock
 603  *
 604  *  Sets the I2C clock line to state
 605  **/
 606 static void igb_set_i2c_clk(void *data, int state)
 607 {
 608         struct igb_adapter *adapter = (struct igb_adapter *)data;
 609         struct e1000_hw *hw = &adapter->hw;
 610         s32 i2cctl = rd32(E1000_I2CPARAMS);
 611
 612         if (state) {
 613                 i2cctl |= E1000_I2C_CLK_OUT;
 614                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 615         } else {
 616                 i2cctl &= ~E1000_I2C_CLK_OUT;
 617                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 618         }
 619         wr32(E1000_I2CPARAMS, i2cctl);
 620         wrfl();
 621 }
 622
 623 /**
 624  *  igb_get_i2c_clk - Gets the I2C SCL clock state
 625  *  @data: pointer to hardware structure
 626  *
 627  *  Gets the I2C clock state
 628  **/
 629 static int igb_get_i2c_clk(void *data)
 630 {
 631         struct igb_adapter *adapter = (struct igb_adapter *)data;
 632         struct e1000_hw *hw = &adapter->hw;
 633         s32 i2cctl = rd32(E1000_I2CPARAMS);
 634
 635         return !!(i2cctl & E1000_I2C_CLK_IN);
 636 }
 637
 638 static const struct i2c_algo_bit_data igb_i2c_algo = {
 639         .setsda         = igb_set_i2c_data,
 640         .setscl         = igb_set_i2c_clk,
 641         .getsda         = igb_get_i2c_data,
 642         .getscl         = igb_get_i2c_clk,
 643         .udelay         = 5,
 644         .timeout        = 20,
 645 };
 646
 647 /**
 648  *  igb_get_hw_dev - return device
 649  *  @hw: pointer to hardware structure
 650  *
 651  *  used by hardware layer to print debugging information
 652  **/
 653 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
 654 {
 655         struct igb_adapter *adapter = hw->back;
 656         return adapter->netdev;
 657 }
 658
 659 /**
 660  *  igb_init_module - Driver Registration Routine
 661  *
 662  *  igb_init_module is the first routine called when the driver is
 663  *  loaded. All it does is register with the PCI subsystem.
 664  **/
 665 static int __init igb_init_module(void)
 666 {
 667         int ret;
 668
 669         pr_info("%s - version %s\n",
 670                igb_driver_string, igb_driver_version);
 671         pr_info("%s\n", igb_copyright);
 672
 673 #ifdef CONFIG_IGB_DCA
 674         dca_register_notify(&dca_notifier);
 675 #endif
 676         ret = pci_register_driver(&igb_driver);
 677         return ret;
 678 }
 679
 680 module_init(igb_init_module);
 681
 682 /**
 683  *  igb_exit_module - Driver Exit Cleanup Routine
 684  *
 685  *  igb_exit_module is called just before the driver is removed
 686  *  from memory.
 687  **/
 688 static void __exit igb_exit_module(void)
 689 {
 690 #ifdef CONFIG_IGB_DCA
 691         dca_unregister_notify(&dca_notifier);
 692 #endif
 693         pci_unregister_driver(&igb_driver);
 694 }
 695
 696 module_exit(igb_exit_module);
 697
 698 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 699 /**
 700  *  igb_cache_ring_register - Descriptor ring to register mapping
 701  *  @adapter: board private structure to initialize
 702  *
 703  *  Once we know the feature-set enabled for the device, we'll cache
 704  *  the register offset the descriptor ring is assigned to.
 705  **/
 706 static void igb_cache_ring_register(struct igb_adapter *adapter)
 707 {
 708         int i = 0, j = 0;
 709         u32 rbase_offset = adapter->vfs_allocated_count;
 710
 711         switch (adapter->hw.mac.type) {
 712         case e1000_82576:
 713                 /* The queues are allocated for virtualization such that VF 0
 714                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 715                  * In order to avoid collision we start at the first free queue
 716                  * and continue consuming queues in the same sequence
 717                  */
 718                 if (adapter->vfs_allocated_count) {
 719                         for (; i < adapter->rss_queues; i++)
 720                                 adapter->rx_ring[i]->reg_idx = rbase_offset +
 721                                                                Q_IDX_82576(i);
 722                 }
 723                 /* Fall through */
 724         case e1000_82575:
 725         case e1000_82580:
 726         case e1000_i350:
 727         case e1000_i354:
 728         case e1000_i210:
 729         case e1000_i211:
 730                 /* Fall through */
 731         default:
 732                 for (; i < adapter->num_rx_queues; i++)
 733                         adapter->rx_ring[i]->reg_idx = rbase_offset + i;
 734                 for (; j < adapter->num_tx_queues; j++)
 735                         adapter->tx_ring[j]->reg_idx = rbase_offset + j;
 736                 break;
 737         }
 738 }
 739
 740 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
 741 {
 742         struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
 743         u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
 744         u32 value = 0;
 745
 746         if (E1000_REMOVED(hw_addr))
 747                 return ~value;
 748
 749         value = readl(&hw_addr[reg]);
 750
 751         /* reads should not return all F's */
 752         if (!(~value) && (!reg || !(~readl(hw_addr)))) {
 753                 struct net_device *netdev = igb->netdev;
 754                 hw->hw_addr = NULL;
 755                 netdev_err(netdev, "PCIe link lost\n");
 756         }
 757
 758         return value;
 759 }
 760
 761 /**
 762  *  igb_write_ivar - configure ivar for given MSI-X vector
 763  *  @hw: pointer to the HW structure
 764  *  @msix_vector: vector number we are allocating to a given ring
 765  *  @index: row index of IVAR register to write within IVAR table
 766  *  @offset: column offset of in IVAR, should be multiple of 8
 767  *
 768  *  This function is intended to handle the writing of the IVAR register
 769  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
 770  *  each containing an cause allocation for an Rx and Tx ring, and a
 771  *  variable number of rows depending on the number of queues supported.
 772  **/
 773 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
 774                            int index, int offset)
 775 {
 776         u32 ivar = array_rd32(E1000_IVAR0, index);
 777
 778         /* clear any bits that are currently set */
 779         ivar &= ~((u32)0xFF << offset);
 780
 781         /* write vector and valid bit */
 782         ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
 783
 784         array_wr32(E1000_IVAR0, index, ivar);
 785 }
 786
 787 #define IGB_N0_QUEUE -1
 788 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
 789 {
 790         struct igb_adapter *adapter = q_vector->adapter;
 791         struct e1000_hw *hw = &adapter->hw;
 792         int rx_queue = IGB_N0_QUEUE;
 793         int tx_queue = IGB_N0_QUEUE;
 794         u32 msixbm = 0;
 795
 796         if (q_vector->rx.ring)
 797                 rx_queue = q_vector->rx.ring->reg_idx;
 798         if (q_vector->tx.ring)
 799                 tx_queue = q_vector->tx.ring->reg_idx;
 800
 801         switch (hw->mac.type) {
 802         case e1000_82575:
 803                 /* The 82575 assigns vectors using a bitmask, which matches the
 804                  * bitmask for the EICR/EIMS/EIMC registers.  To assign one
 805                  * or more queues to a vector, we write the appropriate bits
 806                  * into the MSIXBM register for that vector.
 807                  */
 808                 if (rx_queue > IGB_N0_QUEUE)
 809                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 810                 if (tx_queue > IGB_N0_QUEUE)
 811                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 812                 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
 813                         msixbm |= E1000_EIMS_OTHER;
 814                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 815                 q_vector->eims_value = msixbm;
 816                 break;
 817         case e1000_82576:
 818                 /* 82576 uses a table that essentially consists of 2 columns
 819                  * with 8 rows.  The ordering is column-major so we use the
 820                  * lower 3 bits as the row index, and the 4th bit as the
 821                  * column offset.
 822                  */
 823                 if (rx_queue > IGB_N0_QUEUE)
 824                         igb_write_ivar(hw, msix_vector,
 825                                        rx_queue & 0x7,
 826                                        (rx_queue & 0x8) << 1);
 827                 if (tx_queue > IGB_N0_QUEUE)
 828                         igb_write_ivar(hw, msix_vector,
 829                                        tx_queue & 0x7,
 830                                        ((tx_queue & 0x8) << 1) + 8);
 831                 q_vector->eims_value = BIT(msix_vector);
 832                 break;
 833         case e1000_82580:
 834         case e1000_i350:
 835         case e1000_i354:
 836         case e1000_i210:
 837         case e1000_i211:
 838                 /* On 82580 and newer adapters the scheme is similar to 82576
 839                  * however instead of ordering column-major we have things
 840                  * ordered row-major.  So we traverse the table by using
 841                  * bit 0 as the column offset, and the remaining bits as the
 842                  * row index.
 843                  */
 844                 if (rx_queue > IGB_N0_QUEUE)
 845                         igb_write_ivar(hw, msix_vector,
 846                                        rx_queue >> 1,
 847                                        (rx_queue & 0x1) << 4);
 848                 if (tx_queue > IGB_N0_QUEUE)
 849                         igb_write_ivar(hw, msix_vector,
 850                                        tx_queue >> 1,
 851                                        ((tx_queue & 0x1) << 4) + 8);
 852                 q_vector->eims_value = BIT(msix_vector);
 853                 break;
 854         default:
 855                 BUG();
 856                 break;
 857         }
 858
 859         /* add q_vector eims value to global eims_enable_mask */
 860         adapter->eims_enable_mask |= q_vector->eims_value;
 861
 862         /* configure q_vector to set itr on first interrupt */
 863         q_vector->set_itr = 1;
 864 }
 865
 866 /**
 867  *  igb_configure_msix - Configure MSI-X hardware
 868  *  @adapter: board private structure to initialize
 869  *
 870  *  igb_configure_msix sets up the hardware to properly
 871  *  generate MSI-X interrupts.
 872  **/
 873 static void igb_configure_msix(struct igb_adapter *adapter)
 874 {
 875         u32 tmp;
 876         int i, vector = 0;
 877         struct e1000_hw *hw = &adapter->hw;
 878
 879         adapter->eims_enable_mask = 0;
 880
 881         /* set vector for other causes, i.e. link changes */
 882         switch (hw->mac.type) {
 883         case e1000_82575:
 884                 tmp = rd32(E1000_CTRL_EXT);
 885                 /* enable MSI-X PBA support*/
 886                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 887
 888                 /* Auto-Mask interrupts upon ICR read. */
 889                 tmp |= E1000_CTRL_EXT_EIAME;
 890                 tmp |= E1000_CTRL_EXT_IRCA;
 891
 892                 wr32(E1000_CTRL_EXT, tmp);
 893
 894                 /* enable msix_other interrupt */
 895                 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
 896                 adapter->eims_other = E1000_EIMS_OTHER;
 897
 898                 break;
 899
 900         case e1000_82576:
 901         case e1000_82580:
 902         case e1000_i350:
 903         case e1000_i354:
 904         case e1000_i210:
 905         case e1000_i211:
 906                 /* Turn on MSI-X capability first, or our settings
 907                  * won't stick.  And it will take days to debug.
 908                  */
 909                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 910                      E1000_GPIE_PBA | E1000_GPIE_EIAME |
 911                      E1000_GPIE_NSICR);
 912
 913                 /* enable msix_other interrupt */
 914                 adapter->eims_other = BIT(vector);
 915                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 916
 917                 wr32(E1000_IVAR_MISC, tmp);
 918                 break;
 919         default:
 920                 /* do nothing, since nothing else supports MSI-X */
 921                 break;
 922         } /* switch (hw->mac.type) */
 923
 924         adapter->eims_enable_mask |= adapter->eims_other;
 925
 926         for (i = 0; i < adapter->num_q_vectors; i++)
 927                 igb_assign_vector(adapter->q_vector[i], vector++);
 928
 929         wrfl();
 930 }
 931
 932 /**
 933  *  igb_request_msix - Initialize MSI-X interrupts
 934  *  @adapter: board private structure to initialize
 935  *
 936  *  igb_request_msix allocates MSI-X vectors and requests interrupts from the
 937  *  kernel.
 938  **/
 939 static int igb_request_msix(struct igb_adapter *adapter)
 940 {
 941         struct net_device *netdev = adapter->netdev;
 942         int i, err = 0, vector = 0, free_vector = 0;
 943
 944         err = request_irq(adapter->msix_entries[vector].vector,
 945                           igb_msix_other, 0, netdev->name, adapter);
 946         if (err)
 947                 goto err_out;
 948
 949         for (i = 0; i < adapter->num_q_vectors; i++) {
 950                 struct igb_q_vector *q_vector = adapter->q_vector[i];
 951
 952                 vector++;
 953
 954                 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
 955
 956                 if (q_vector->rx.ring && q_vector->tx.ring)
 957                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
 958                                 q_vector->rx.ring->queue_index);
 959                 else if (q_vector->tx.ring)
 960                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
 961                                 q_vector->tx.ring->queue_index);
 962                 else if (q_vector->rx.ring)
 963                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
 964                                 q_vector->rx.ring->queue_index);
 965                 else
 966                         sprintf(q_vector->name, "%s-unused", netdev->name);
 967
 968                 err = request_irq(adapter->msix_entries[vector].vector,
 969                                   igb_msix_ring, 0, q_vector->name,
 970                                   q_vector);
 971                 if (err)
 972                         goto err_free;
 973         }
 974
 975         igb_configure_msix(adapter);
 976         return 0;
 977
 978 err_free:
 979         /* free already assigned IRQs */
 980         free_irq(adapter->msix_entries[free_vector++].vector, adapter);
 981
 982         vector--;
 983         for (i = 0; i < vector; i++) {
 984                 free_irq(adapter->msix_entries[free_vector++].vector,
 985                          adapter->q_vector[i]);
 986         }
 987 err_out:
 988         return err;
 989 }
 990
 991 /**
 992  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
 993  *  @adapter: board private structure to initialize
 994  *  @v_idx: Index of vector to be freed
 995  *
 996  *  This function frees the memory allocated to the q_vector.
 997  **/
 998 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
 999 {
1000         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1001
1002         adapter->q_vector[v_idx] = NULL;
1003
1004         /* igb_get_stats64() might access the rings on this vector,
1005          * we must wait a grace period before freeing it.
1006          */
1007         if (q_vector)
1008                 kfree_rcu(q_vector, rcu);
1009 }
1010
1011 /**
1012  *  igb_reset_q_vector - Reset config for interrupt vector
1013  *  @adapter: board private structure to initialize
1014  *  @v_idx: Index of vector to be reset
1015  *
1016  *  If NAPI is enabled it will delete any references to the
1017  *  NAPI struct. This is preparation for igb_free_q_vector.
1018  **/
1019 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1020 {
1021         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1022
1023         /* Coming from igb_set_interrupt_capability, the vectors are not yet
1024          * allocated. So, q_vector is NULL so we should stop here.
1025          */
1026         if (!q_vector)
1027                 return;
1028
1029         if (q_vector->tx.ring)
1030                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1031
1032         if (q_vector->rx.ring)
1033                 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1034
1035         netif_napi_del(&q_vector->napi);
1036
1037 }
1038
1039 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1040 {
1041         int v_idx = adapter->num_q_vectors;
1042
1043         if (adapter->flags & IGB_FLAG_HAS_MSIX)
1044                 pci_disable_msix(adapter->pdev);
1045         else if (adapter->flags & IGB_FLAG_HAS_MSI)
1046                 pci_disable_msi(adapter->pdev);
1047
1048         while (v_idx--)
1049                 igb_reset_q_vector(adapter, v_idx);
1050 }
1051
1052 /**
1053  *  igb_free_q_vectors - Free memory allocated for interrupt vectors
1054  *  @adapter: board private structure to initialize
1055  *
1056  *  This function frees the memory allocated to the q_vectors.  In addition if
1057  *  NAPI is enabled it will delete any references to the NAPI struct prior
1058  *  to freeing the q_vector.
1059  **/
1060 static void igb_free_q_vectors(struct igb_adapter *adapter)
1061 {
1062         int v_idx = adapter->num_q_vectors;
1063
1064         adapter->num_tx_queues = 0;
1065         adapter->num_rx_queues = 0;
1066         adapter->num_q_vectors = 0;
1067
1068         while (v_idx--) {
1069                 igb_reset_q_vector(adapter, v_idx);
1070                 igb_free_q_vector(adapter, v_idx);
1071         }
1072 }
1073
1074 /**
1075  *  igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1076  *  @adapter: board private structure to initialize
1077  *
1078  *  This function resets the device so that it has 0 Rx queues, Tx queues, and
1079  *  MSI-X interrupts allocated.
1080  */
1081 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1082 {
1083         igb_free_q_vectors(adapter);
1084         igb_reset_interrupt_capability(adapter);
1085 }
1086
1087 /**
1088  *  igb_set_interrupt_capability - set MSI or MSI-X if supported
1089  *  @adapter: board private structure to initialize
1090  *  @msix: boolean value of MSIX capability
1091  *
1092  *  Attempt to configure interrupts using the best available
1093  *  capabilities of the hardware and kernel.
1094  **/
1095 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1096 {
1097         int err;
1098         int numvecs, i;
1099
1100         if (!msix)
1101                 goto msi_only;
1102         adapter->flags |= IGB_FLAG_HAS_MSIX;
1103
1104         /* Number of supported queues. */
1105         adapter->num_rx_queues = adapter->rss_queues;
1106         if (adapter->vfs_allocated_count)
1107                 adapter->num_tx_queues = 1;
1108         else
1109                 adapter->num_tx_queues = adapter->rss_queues;
1110
1111         /* start with one vector for every Rx queue */
1112         numvecs = adapter->num_rx_queues;
1113
1114         /* if Tx handler is separate add 1 for every Tx queue */
1115         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1116                 numvecs += adapter->num_tx_queues;
1117
1118         /* store the number of vectors reserved for queues */
1119         adapter->num_q_vectors = numvecs;
1120
1121         /* add 1 vector for link status interrupts */
1122         numvecs++;
1123         for (i = 0; i < numvecs; i++)
1124                 adapter->msix_entries[i].entry = i;
1125
1126         err = pci_enable_msix_range(adapter->pdev,
1127                                     adapter->msix_entries,
1128                                     numvecs,
1129                                     numvecs);
1130         if (err > 0)
1131                 return;
1132
1133         igb_reset_interrupt_capability(adapter);
1134
1135         /* If we can't do MSI-X, try MSI */
1136 msi_only:
1137         adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1138 #ifdef CONFIG_PCI_IOV
1139         /* disable SR-IOV for non MSI-X configurations */
1140         if (adapter->vf_data) {
1141                 struct e1000_hw *hw = &adapter->hw;
1142                 /* disable iov and allow time for transactions to clear */
1143                 pci_disable_sriov(adapter->pdev);
1144                 msleep(500);
1145
1146                 kfree(adapter->vf_mac_list);
1147                 adapter->vf_mac_list = NULL;
1148                 kfree(adapter->vf_data);
1149                 adapter->vf_data = NULL;
1150                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1151                 wrfl();
1152                 msleep(100);
1153                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1154         }
1155 #endif
1156         adapter->vfs_allocated_count = 0;
1157         adapter->rss_queues = 1;
1158         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1159         adapter->num_rx_queues = 1;
1160         adapter->num_tx_queues = 1;
1161         adapter->num_q_vectors = 1;
1162         if (!pci_enable_msi(adapter->pdev))
1163                 adapter->flags |= IGB_FLAG_HAS_MSI;
1164 }
1165
1166 static void igb_add_ring(struct igb_ring *ring,
1167                          struct igb_ring_container *head)
1168 {
1169         head->ring = ring;
1170         head->count++;
1171 }
1172
1173 /**
1174  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1175  *  @adapter: board private structure to initialize
1176  *  @v_count: q_vectors allocated on adapter, used for ring interleaving
1177  *  @v_idx: index of vector in adapter struct
1178  *  @txr_count: total number of Tx rings to allocate
1179  *  @txr_idx: index of first Tx ring to allocate
1180  *  @rxr_count: total number of Rx rings to allocate
1181  *  @rxr_idx: index of first Rx ring to allocate
1182  *
1183  *  We allocate one q_vector.  If allocation fails we return -ENOMEM.
1184  **/
1185 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1186                               int v_count, int v_idx,
1187                               int txr_count, int txr_idx,
1188                               int rxr_count, int rxr_idx)
1189 {
1190         struct igb_q_vector *q_vector;
1191         struct igb_ring *ring;
1192         int ring_count;
1193         size_t size;
1194
1195         /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1196         if (txr_count > 1 || rxr_count > 1)
1197                 return -ENOMEM;
1198
1199         ring_count = txr_count + rxr_count;
1200         size = struct_size(q_vector, ring, ring_count);
1201
1202         /* allocate q_vector and rings */
1203         q_vector = adapter->q_vector[v_idx];
1204         if (!q_vector) {
1205                 q_vector = kzalloc(size, GFP_KERNEL);
1206         } else if (size > ksize(q_vector)) {
1207                 kfree_rcu(q_vector, rcu);
1208                 q_vector = kzalloc(size, GFP_KERNEL);
1209         } else {
1210                 memset(q_vector, 0, size);
1211         }
1212         if (!q_vector)
1213                 return -ENOMEM;
1214
1215         /* initialize NAPI */
1216         netif_napi_add(adapter->netdev, &q_vector->napi,
1217                        igb_poll, 64);
1218
1219         /* tie q_vector and adapter together */
1220         adapter->q_vector[v_idx] = q_vector;
1221         q_vector->adapter = adapter;
1222
1223         /* initialize work limits */
1224         q_vector->tx.work_limit = adapter->tx_work_limit;
1225
1226         /* initialize ITR configuration */
1227         q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1228         q_vector->itr_val = IGB_START_ITR;
1229
1230         /* initialize pointer to rings */
1231         ring = q_vector->ring;
1232
1233         /* intialize ITR */
1234         if (rxr_count) {
1235                 /* rx or rx/tx vector */
1236                 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1237                         q_vector->itr_val = adapter->rx_itr_setting;
1238         } else {
1239                 /* tx only vector */
1240                 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1241                         q_vector->itr_val = adapter->tx_itr_setting;
1242         }
1243
1244         if (txr_count) {
1245                 /* assign generic ring traits */
1246                 ring->dev = &adapter->pdev->dev;
1247                 ring->netdev = adapter->netdev;
1248
1249                 /* configure backlink on ring */
1250                 ring->q_vector = q_vector;
1251
1252                 /* update q_vector Tx values */
1253                 igb_add_ring(ring, &q_vector->tx);
1254
1255                 /* For 82575, context index must be unique per ring. */
1256                 if (adapter->hw.mac.type == e1000_82575)
1257                         set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1258
1259                 /* apply Tx specific ring traits */
1260                 ring->count = adapter->tx_ring_count;
1261                 ring->queue_index = txr_idx;
1262
1263                 ring->cbs_enable = false;
1264                 ring->idleslope = 0;
1265                 ring->sendslope = 0;
1266                 ring->hicredit = 0;
1267                 ring->locredit = 0;
1268
1269                 u64_stats_init(&ring->tx_syncp);
1270                 u64_stats_init(&ring->tx_syncp2);
1271
1272                 /* assign ring to adapter */
1273                 adapter->tx_ring[txr_idx] = ring;
1274
1275                 /* push pointer to next ring */
1276                 ring++;
1277         }
1278
1279         if (rxr_count) {
1280                 /* assign generic ring traits */
1281                 ring->dev = &adapter->pdev->dev;
1282                 ring->netdev = adapter->netdev;
1283
1284                 /* configure backlink on ring */
1285                 ring->q_vector = q_vector;
1286
1287                 /* update q_vector Rx values */
1288                 igb_add_ring(ring, &q_vector->rx);
1289
1290                 /* set flag indicating ring supports SCTP checksum offload */
1291                 if (adapter->hw.mac.type >= e1000_82576)
1292                         set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1293
1294                 /* On i350, i354, i210, and i211, loopback VLAN packets
1295                  * have the tag byte-swapped.
1296                  */
1297                 if (adapter->hw.mac.type >= e1000_i350)
1298                         set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1299
1300                 /* apply Rx specific ring traits */
1301                 ring->count = adapter->rx_ring_count;
1302                 ring->queue_index = rxr_idx;
1303
1304                 u64_stats_init(&ring->rx_syncp);
1305
1306                 /* assign ring to adapter */
1307                 adapter->rx_ring[rxr_idx] = ring;
1308         }
1309
1310         return 0;
1311 }
1312
1313
1314 /**
1315  *  igb_alloc_q_vectors - Allocate memory for interrupt vectors
1316  *  @adapter: board private structure to initialize
1317  *
1318  *  We allocate one q_vector per queue interrupt.  If allocation fails we
1319  *  return -ENOMEM.
1320  **/
1321 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1322 {
1323         int q_vectors = adapter->num_q_vectors;
1324         int rxr_remaining = adapter->num_rx_queues;
1325         int txr_remaining = adapter->num_tx_queues;
1326         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1327         int err;
1328
1329         if (q_vectors >= (rxr_remaining + txr_remaining)) {
1330                 for (; rxr_remaining; v_idx++) {
1331                         err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1332                                                  0, 0, 1, rxr_idx);
1333
1334                         if (err)
1335                                 goto err_out;
1336
1337                         /* update counts and index */
1338                         rxr_remaining--;
1339                         rxr_idx++;
1340                 }
1341         }
1342
1343         for (; v_idx < q_vectors; v_idx++) {
1344                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1345                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1346
1347                 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348                                          tqpv, txr_idx, rqpv, rxr_idx);
1349
1350                 if (err)
1351                         goto err_out;
1352
1353                 /* update counts and index */
1354                 rxr_remaining -= rqpv;
1355                 txr_remaining -= tqpv;
1356                 rxr_idx++;
1357                 txr_idx++;
1358         }
1359
1360         return 0;
1361
1362 err_out:
1363         adapter->num_tx_queues = 0;
1364         adapter->num_rx_queues = 0;
1365         adapter->num_q_vectors = 0;
1366
1367         while (v_idx--)
1368                 igb_free_q_vector(adapter, v_idx);
1369
1370         return -ENOMEM;
1371 }
1372
1373 /**
1374  *  igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1375  *  @adapter: board private structure to initialize
1376  *  @msix: boolean value of MSIX capability
1377  *
1378  *  This function initializes the interrupts and allocates all of the queues.
1379  **/
1380 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1381 {
1382         struct pci_dev *pdev = adapter->pdev;
1383         int err;
1384
1385         igb_set_interrupt_capability(adapter, msix);
1386
1387         err = igb_alloc_q_vectors(adapter);
1388         if (err) {
1389                 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390                 goto err_alloc_q_vectors;
1391         }
1392
1393         igb_cache_ring_register(adapter);
1394
1395         return 0;
1396
1397 err_alloc_q_vectors:
1398         igb_reset_interrupt_capability(adapter);
1399         return err;
1400 }
1401
1402 /**
1403  *  igb_request_irq - initialize interrupts
1404  *  @adapter: board private structure to initialize
1405  *
1406  *  Attempts to configure interrupts using the best available
1407  *  capabilities of the hardware and kernel.
1408  **/
1409 static int igb_request_irq(struct igb_adapter *adapter)
1410 {
1411         struct net_device *netdev = adapter->netdev;
1412         struct pci_dev *pdev = adapter->pdev;
1413         int err = 0;
1414
1415         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1416                 err = igb_request_msix(adapter);
1417                 if (!err)
1418                         goto request_done;
1419                 /* fall back to MSI */
1420                 igb_free_all_tx_resources(adapter);
1421                 igb_free_all_rx_resources(adapter);
1422
1423                 igb_clear_interrupt_scheme(adapter);
1424                 err = igb_init_interrupt_scheme(adapter, false);
1425                 if (err)
1426                         goto request_done;
1427
1428                 igb_setup_all_tx_resources(adapter);
1429                 igb_setup_all_rx_resources(adapter);
1430                 igb_configure(adapter);
1431         }
1432
1433         igb_assign_vector(adapter->q_vector[0], 0);
1434
1435         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1436                 err = request_irq(pdev->irq, igb_intr_msi, 0,
1437                                   netdev->name, adapter);
1438                 if (!err)
1439                         goto request_done;
1440
1441                 /* fall back to legacy interrupts */
1442                 igb_reset_interrupt_capability(adapter);
1443                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1444         }
1445
1446         err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1447                           netdev->name, adapter);
1448
1449         if (err)
1450                 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1451                         err);
1452
1453 request_done:
1454         return err;
1455 }
1456
1457 static void igb_free_irq(struct igb_adapter *adapter)
1458 {
1459         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1460                 int vector = 0, i;
1461
1462                 free_irq(adapter->msix_entries[vector++].vector, adapter);
1463
1464                 for (i = 0; i < adapter->num_q_vectors; i++)
1465                         free_irq(adapter->msix_entries[vector++].vector,
1466                                  adapter->q_vector[i]);
1467         } else {
1468                 free_irq(adapter->pdev->irq, adapter);
1469         }
1470 }
1471
1472 /**
1473  *  igb_irq_disable - Mask off interrupt generation on the NIC
1474  *  @adapter: board private structure
1475  **/
1476 static void igb_irq_disable(struct igb_adapter *adapter)
1477 {
1478         struct e1000_hw *hw = &adapter->hw;
1479
1480         /* we need to be careful when disabling interrupts.  The VFs are also
1481          * mapped into these registers and so clearing the bits can cause
1482          * issues on the VF drivers so we only need to clear what we set
1483          */
1484         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1485                 u32 regval = rd32(E1000_EIAM);
1486
1487                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1488                 wr32(E1000_EIMC, adapter->eims_enable_mask);
1489                 regval = rd32(E1000_EIAC);
1490                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1491         }
1492
1493         wr32(E1000_IAM, 0);
1494         wr32(E1000_IMC, ~0);
1495         wrfl();
1496         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1497                 int i;
1498
1499                 for (i = 0; i < adapter->num_q_vectors; i++)
1500                         synchronize_irq(adapter->msix_entries[i].vector);
1501         } else {
1502                 synchronize_irq(adapter->pdev->irq);
1503         }
1504 }
1505
1506 /**
1507  *  igb_irq_enable - Enable default interrupt generation settings
1508  *  @adapter: board private structure
1509  **/
1510 static void igb_irq_enable(struct igb_adapter *adapter)
1511 {
1512         struct e1000_hw *hw = &adapter->hw;
1513
1514         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1515                 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1516                 u32 regval = rd32(E1000_EIAC);
1517
1518                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1519                 regval = rd32(E1000_EIAM);
1520                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1521                 wr32(E1000_EIMS, adapter->eims_enable_mask);
1522                 if (adapter->vfs_allocated_count) {
1523                         wr32(E1000_MBVFIMR, 0xFF);
1524                         ims |= E1000_IMS_VMMB;
1525                 }
1526                 wr32(E1000_IMS, ims);
1527         } else {
1528                 wr32(E1000_IMS, IMS_ENABLE_MASK |
1529                                 E1000_IMS_DRSTA);
1530                 wr32(E1000_IAM, IMS_ENABLE_MASK |
1531                                 E1000_IMS_DRSTA);
1532         }
1533 }
1534
1535 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1536 {
1537         struct e1000_hw *hw = &adapter->hw;
1538         u16 pf_id = adapter->vfs_allocated_count;
1539         u16 vid = adapter->hw.mng_cookie.vlan_id;
1540         u16 old_vid = adapter->mng_vlan_id;
1541
1542         if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1543                 /* add VID to filter table */
1544                 igb_vfta_set(hw, vid, pf_id, true, true);
1545                 adapter->mng_vlan_id = vid;
1546         } else {
1547                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1548         }
1549
1550         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1551             (vid != old_vid) &&
1552             !test_bit(old_vid, adapter->active_vlans)) {
1553                 /* remove VID from filter table */
1554                 igb_vfta_set(hw, vid, pf_id, false, true);
1555         }
1556 }
1557
1558 /**
1559  *  igb_release_hw_control - release control of the h/w to f/w
1560  *  @adapter: address of board private structure
1561  *
1562  *  igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1563  *  For ASF and Pass Through versions of f/w this means that the
1564  *  driver is no longer loaded.
1565  **/
1566 static void igb_release_hw_control(struct igb_adapter *adapter)
1567 {
1568         struct e1000_hw *hw = &adapter->hw;
1569         u32 ctrl_ext;
1570
1571         /* Let firmware take over control of h/w */
1572         ctrl_ext = rd32(E1000_CTRL_EXT);
1573         wr32(E1000_CTRL_EXT,
1574                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1575 }
1576
1577 /**
1578  *  igb_get_hw_control - get control of the h/w from f/w
1579  *  @adapter: address of board private structure
1580  *
1581  *  igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1582  *  For ASF and Pass Through versions of f/w this means that
1583  *  the driver is loaded.
1584  **/
1585 static void igb_get_hw_control(struct igb_adapter *adapter)
1586 {
1587         struct e1000_hw *hw = &adapter->hw;
1588         u32 ctrl_ext;
1589
1590         /* Let firmware know the driver has taken over */
1591         ctrl_ext = rd32(E1000_CTRL_EXT);
1592         wr32(E1000_CTRL_EXT,
1593                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1594 }
1595
1596 static void enable_fqtss(struct igb_adapter *adapter, bool enable)
1597 {
1598         struct net_device *netdev = adapter->netdev;
1599         struct e1000_hw *hw = &adapter->hw;
1600
1601         WARN_ON(hw->mac.type != e1000_i210);
1602
1603         if (enable)
1604                 adapter->flags |= IGB_FLAG_FQTSS;
1605         else
1606                 adapter->flags &= ~IGB_FLAG_FQTSS;
1607
1608         if (netif_running(netdev))
1609                 schedule_work(&adapter->reset_task);
1610 }
1611
1612 static bool is_fqtss_enabled(struct igb_adapter *adapter)
1613 {
1614         return (adapter->flags & IGB_FLAG_FQTSS) ? true : false;
1615 }
1616
1617 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue,
1618                                    enum tx_queue_prio prio)
1619 {
1620         u32 val;
1621
1622         WARN_ON(hw->mac.type != e1000_i210);
1623         WARN_ON(queue < 0 || queue > 4);
1624
1625         val = rd32(E1000_I210_TXDCTL(queue));
1626
1627         if (prio == TX_QUEUE_PRIO_HIGH)
1628                 val |= E1000_TXDCTL_PRIORITY;
1629         else
1630                 val &= ~E1000_TXDCTL_PRIORITY;
1631
1632         wr32(E1000_I210_TXDCTL(queue), val);
1633 }
1634
1635 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode)
1636 {
1637         u32 val;
1638
1639         WARN_ON(hw->mac.type != e1000_i210);
1640         WARN_ON(queue < 0 || queue > 1);
1641
1642         val = rd32(E1000_I210_TQAVCC(queue));
1643
1644         if (mode == QUEUE_MODE_STREAM_RESERVATION)
1645                 val |= E1000_TQAVCC_QUEUEMODE;
1646         else
1647                 val &= ~E1000_TQAVCC_QUEUEMODE;
1648
1649         wr32(E1000_I210_TQAVCC(queue), val);
1650 }
1651
1652 static bool is_any_cbs_enabled(struct igb_adapter *adapter)
1653 {
1654         int i;
1655
1656         for (i = 0; i < adapter->num_tx_queues; i++) {
1657                 if (adapter->tx_ring[i]->cbs_enable)
1658                         return true;
1659         }
1660
1661         return false;
1662 }
1663
1664 static bool is_any_txtime_enabled(struct igb_adapter *adapter)
1665 {
1666         int i;
1667
1668         for (i = 0; i < adapter->num_tx_queues; i++) {
1669                 if (adapter->tx_ring[i]->launchtime_enable)
1670                         return true;
1671         }
1672
1673         return false;
1674 }
1675
1676 /**
1677  *  igb_config_tx_modes - Configure "Qav Tx mode" features on igb
1678  *  @adapter: pointer to adapter struct
1679  *  @queue: queue number
1680  *
1681  *  Configure CBS and Launchtime for a given hardware queue.
1682  *  Parameters are retrieved from the correct Tx ring, so
1683  *  igb_save_cbs_params() and igb_save_txtime_params() should be used
1684  *  for setting those correctly prior to this function being called.
1685  **/
1686 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1687 {
1688         struct igb_ring *ring = adapter->tx_ring[queue];
1689         struct net_device *netdev = adapter->netdev;
1690         struct e1000_hw *hw = &adapter->hw;
1691         u32 tqavcc, tqavctrl;
1692         u16 value;
1693
1694         WARN_ON(hw->mac.type != e1000_i210);
1695         WARN_ON(queue < 0 || queue > 1);
1696
1697         /* If any of the Qav features is enabled, configure queues as SR and
1698          * with HIGH PRIO. If none is, then configure them with LOW PRIO and
1699          * as SP.
1700          */
1701         if (ring->cbs_enable || ring->launchtime_enable) {
1702                 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1703                 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1704         } else {
1705                 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1706                 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1707         }
1708
1709         /* If CBS is enabled, set DataTranARB and config its parameters. */
1710         if (ring->cbs_enable || queue == 0) {
1711                 /* i210 does not allow the queue 0 to be in the Strict
1712                  * Priority mode while the Qav mode is enabled, so,
1713                  * instead of disabling strict priority mode, we give
1714                  * queue 0 the maximum of credits possible.
1715                  *
1716                  * See section 8.12.19 of the i210 datasheet, "Note:
1717                  * Queue0 QueueMode must be set to 1b when
1718                  * TransmitMode is set to Qav."
1719                  */
1720                 if (queue == 0 && !ring->cbs_enable) {
1721                         /* max "linkspeed" idleslope in kbps */
1722                         ring->idleslope = 1000000;
1723                         ring->hicredit = ETH_FRAME_LEN;
1724                 }
1725
1726                 /* Always set data transfer arbitration to credit-based
1727                  * shaper algorithm on TQAVCTRL if CBS is enabled for any of
1728                  * the queues.
1729                  */
1730                 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1731                 tqavctrl |= E1000_TQAVCTRL_DATATRANARB;
1732                 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1733
1734                 /* According to i210 datasheet section 7.2.7.7, we should set
1735                  * the 'idleSlope' field from TQAVCC register following the
1736                  * equation:
1737                  *
1738                  * For 100 Mbps link speed:
1739                  *
1740                  *     value = BW * 0x7735 * 0.2                          (E1)
1741                  *
1742                  * For 1000Mbps link speed:
1743                  *
1744                  *     value = BW * 0x7735 * 2                            (E2)
1745                  *
1746                  * E1 and E2 can be merged into one equation as shown below.
1747                  * Note that 'link-speed' is in Mbps.
1748                  *
1749                  *     value = BW * 0x7735 * 2 * link-speed
1750                  *                           --------------               (E3)
1751                  *                                1000
1752                  *
1753                  * 'BW' is the percentage bandwidth out of full link speed
1754                  * which can be found with the following equation. Note that
1755                  * idleSlope here is the parameter from this function which
1756                  * is in kbps.
1757                  *
1758                  *     BW =     idleSlope
1759                  *          -----------------                             (E4)
1760                  *          link-speed * 1000
1761                  *
1762                  * That said, we can come up with a generic equation to
1763                  * calculate the value we should set it TQAVCC register by
1764                  * replacing 'BW' in E3 by E4. The resulting equation is:
1765                  *
1766                  * value =     idleSlope     * 0x7735 * 2 * link-speed
1767                  *         -----------------            --------------    (E5)
1768                  *         link-speed * 1000                 1000
1769                  *
1770                  * 'link-speed' is present in both sides of the fraction so
1771                  * it is canceled out. The final equation is the following:
1772                  *
1773                  *     value = idleSlope * 61034
1774                  *             -----------------                          (E6)
1775                  *                  1000000
1776                  *
1777                  * NOTE: For i210, given the above, we can see that idleslope
1778                  *       is represented in 16.38431 kbps units by the value at
1779                  *       the TQAVCC register (1Gbps / 61034), which reduces
1780                  *       the granularity for idleslope increments.
1781                  *       For instance, if you want to configure a 2576kbps
1782                  *       idleslope, the value to be written on the register
1783                  *       would have to be 157.23. If rounded down, you end
1784                  *       up with less bandwidth available than originally
1785                  *       required (~2572 kbps). If rounded up, you end up
1786                  *       with a higher bandwidth (~2589 kbps). Below the
1787                  *       approach we take is to always round up the
1788                  *       calculated value, so the resulting bandwidth might
1789                  *       be slightly higher for some configurations.
1790                  */
1791                 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000);
1792
1793                 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1794                 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1795                 tqavcc |= value;
1796                 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1797
1798                 wr32(E1000_I210_TQAVHC(queue),
1799                      0x80000000 + ring->hicredit * 0x7735);
1800         } else {
1801
1802                 /* Set idleSlope to zero. */
1803                 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1804                 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1805                 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1806
1807                 /* Set hiCredit to zero. */
1808                 wr32(E1000_I210_TQAVHC(queue), 0);
1809
1810                 /* If CBS is not enabled for any queues anymore, then return to
1811                  * the default state of Data Transmission Arbitration on
1812                  * TQAVCTRL.
1813                  */
1814                 if (!is_any_cbs_enabled(adapter)) {
1815                         tqavctrl = rd32(E1000_I210_TQAVCTRL);
1816                         tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB;
1817                         wr32(E1000_I210_TQAVCTRL, tqavctrl);
1818                 }
1819         }
1820
1821         /* If LaunchTime is enabled, set DataTranTIM. */
1822         if (ring->launchtime_enable) {
1823                 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled
1824                  * for any of the SR queues, and configure fetchtime delta.
1825                  * XXX NOTE:
1826                  *     - LaunchTime will be enabled for all SR queues.
1827                  *     - A fixed offset can be added relative to the launch
1828                  *       time of all packets if configured at reg LAUNCH_OS0.
1829                  *       We are keeping it as 0 for now (default value).
1830                  */
1831                 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1832                 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM |
1833                        E1000_TQAVCTRL_FETCHTIME_DELTA;
1834                 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1835         } else {
1836                 /* If Launchtime is not enabled for any SR queues anymore,
1837                  * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta,
1838                  * effectively disabling Launchtime.
1839                  */
1840                 if (!is_any_txtime_enabled(adapter)) {
1841                         tqavctrl = rd32(E1000_I210_TQAVCTRL);
1842                         tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM;
1843                         tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA;
1844                         wr32(E1000_I210_TQAVCTRL, tqavctrl);
1845                 }
1846         }
1847
1848         /* XXX: In i210 controller the sendSlope and loCredit parameters from
1849          * CBS are not configurable by software so we don't do any 'controller
1850          * configuration' in respect to these parameters.
1851          */
1852
1853         netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n",
1854                    ring->cbs_enable ? "enabled" : "disabled",
1855                    ring->launchtime_enable ? "enabled" : "disabled",
1856                    queue,
1857                    ring->idleslope, ring->sendslope,
1858                    ring->hicredit, ring->locredit);
1859 }
1860
1861 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue,
1862                                   bool enable)
1863 {
1864         struct igb_ring *ring;
1865
1866         if (queue < 0 || queue > adapter->num_tx_queues)
1867                 return -EINVAL;
1868
1869         ring = adapter->tx_ring[queue];
1870         ring->launchtime_enable = enable;
1871
1872         return 0;
1873 }
1874
1875 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue,
1876                                bool enable, int idleslope, int sendslope,
1877                                int hicredit, int locredit)
1878 {
1879         struct igb_ring *ring;
1880
1881         if (queue < 0 || queue > adapter->num_tx_queues)
1882                 return -EINVAL;
1883
1884         ring = adapter->tx_ring[queue];
1885
1886         ring->cbs_enable = enable;
1887         ring->idleslope = idleslope;
1888         ring->sendslope = sendslope;
1889         ring->hicredit = hicredit;
1890         ring->locredit = locredit;
1891
1892         return 0;
1893 }
1894
1895 /**
1896  *  igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable
1897  *  @adapter: pointer to adapter struct
1898  *
1899  *  Configure TQAVCTRL register switching the controller's Tx mode
1900  *  if FQTSS mode is enabled or disabled. Additionally, will issue
1901  *  a call to igb_config_tx_modes() per queue so any previously saved
1902  *  Tx parameters are applied.
1903  **/
1904 static void igb_setup_tx_mode(struct igb_adapter *adapter)
1905 {
1906         struct net_device *netdev = adapter->netdev;
1907         struct e1000_hw *hw = &adapter->hw;
1908         u32 val;
1909
1910         /* Only i210 controller supports changing the transmission mode. */
1911         if (hw->mac.type != e1000_i210)
1912                 return;
1913
1914         if (is_fqtss_enabled(adapter)) {
1915                 int i, max_queue;
1916
1917                 /* Configure TQAVCTRL register: set transmit mode to 'Qav',
1918                  * set data fetch arbitration to 'round robin', set SP_WAIT_SR
1919                  * so SP queues wait for SR ones.
1920                  */
1921                 val = rd32(E1000_I210_TQAVCTRL);
1922                 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR;
1923                 val &= ~E1000_TQAVCTRL_DATAFETCHARB;
1924                 wr32(E1000_I210_TQAVCTRL, val);
1925
1926                 /* Configure Tx and Rx packet buffers sizes as described in
1927                  * i210 datasheet section 7.2.7.7.
1928                  */
1929                 val = rd32(E1000_TXPBS);
1930                 val &= ~I210_TXPBSIZE_MASK;
1931                 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB |
1932                         I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB;
1933                 wr32(E1000_TXPBS, val);
1934
1935                 val = rd32(E1000_RXPBS);
1936                 val &= ~I210_RXPBSIZE_MASK;
1937                 val |= I210_RXPBSIZE_PB_30KB;
1938                 wr32(E1000_RXPBS, val);
1939
1940                 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ
1941                  * register should not exceed the buffer size programmed in
1942                  * TXPBS. The smallest buffer size programmed in TXPBS is 4kB
1943                  * so according to the datasheet we should set MAX_TPKT_SIZE to
1944                  * 4kB / 64.
1945                  *
1946                  * However, when we do so, no frame from queue 2 and 3 are
1947                  * transmitted.  It seems the MAX_TPKT_SIZE should not be great
1948                  * or _equal_ to the buffer size programmed in TXPBS. For this
1949                  * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64.
1950                  */
1951                 val = (4096 - 1) / 64;
1952                 wr32(E1000_I210_DTXMXPKTSZ, val);
1953
1954                 /* Since FQTSS mode is enabled, apply any CBS configuration
1955                  * previously set. If no previous CBS configuration has been
1956                  * done, then the initial configuration is applied, which means
1957                  * CBS is disabled.
1958                  */
1959                 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ?
1960                             adapter->num_tx_queues : I210_SR_QUEUES_NUM;
1961
1962                 for (i = 0; i < max_queue; i++) {
1963                         igb_config_tx_modes(adapter, i);
1964                 }
1965         } else {
1966                 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
1967                 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
1968                 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT);
1969
1970                 val = rd32(E1000_I210_TQAVCTRL);
1971                 /* According to Section 8.12.21, the other flags we've set when
1972                  * enabling FQTSS are not relevant when disabling FQTSS so we
1973                  * don't set they here.
1974                  */
1975                 val &= ~E1000_TQAVCTRL_XMIT_MODE;
1976                 wr32(E1000_I210_TQAVCTRL, val);
1977         }
1978
1979         netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ?
1980                    "enabled" : "disabled");
1981 }
1982
1983 /**
1984  *  igb_configure - configure the hardware for RX and TX
1985  *  @adapter: private board structure
1986  **/
1987 static void igb_configure(struct igb_adapter *adapter)
1988 {
1989         struct net_device *netdev = adapter->netdev;
1990         int i;
1991
1992         igb_get_hw_control(adapter);
1993         igb_set_rx_mode(netdev);
1994         igb_setup_tx_mode(adapter);
1995
1996         igb_restore_vlan(adapter);
1997
1998         igb_setup_tctl(adapter);
1999         igb_setup_mrqc(adapter);
2000         igb_setup_rctl(adapter);
2001
2002         igb_nfc_filter_restore(adapter);
2003         igb_configure_tx(adapter);
2004         igb_configure_rx(adapter);
2005
2006         igb_rx_fifo_flush_82575(&adapter->hw);
2007
2008         /* call igb_desc_unused which always leaves
2009          * at least 1 descriptor unused to make sure
2010          * next_to_use != next_to_clean
2011          */
2012         for (i = 0; i < adapter->num_rx_queues; i++) {
2013                 struct igb_ring *ring = adapter->rx_ring[i];
2014                 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
2015         }
2016 }
2017
2018 /**
2019  *  igb_power_up_link - Power up the phy/serdes link
2020  *  @adapter: address of board private structure
2021  **/
2022 void igb_power_up_link(struct igb_adapter *adapter)
2023 {
2024         igb_reset_phy(&adapter->hw);
2025
2026         if (adapter->hw.phy.media_type == e1000_media_type_copper)
2027                 igb_power_up_phy_copper(&adapter->hw);
2028         else
2029                 igb_power_up_serdes_link_82575(&adapter->hw);
2030
2031         igb_setup_link(&adapter->hw);
2032 }
2033
2034 /**
2035  *  igb_power_down_link - Power down the phy/serdes link
2036  *  @adapter: address of board private structure
2037  */
2038 static void igb_power_down_link(struct igb_adapter *adapter)
2039 {
2040         if (adapter->hw.phy.media_type == e1000_media_type_copper)
2041                 igb_power_down_phy_copper_82575(&adapter->hw);
2042         else
2043                 igb_shutdown_serdes_link_82575(&adapter->hw);
2044 }
2045
2046 /**
2047  * Detect and switch function for Media Auto Sense
2048  * @adapter: address of the board private structure
2049  **/
2050 static void igb_check_swap_media(struct igb_adapter *adapter)
2051 {
2052         struct e1000_hw *hw = &adapter->hw;
2053         u32 ctrl_ext, connsw;
2054         bool swap_now = false;
2055
2056         ctrl_ext = rd32(E1000_CTRL_EXT);
2057         connsw = rd32(E1000_CONNSW);
2058
2059         /* need to live swap if current media is copper and we have fiber/serdes
2060          * to go to.
2061          */
2062
2063         if ((hw->phy.media_type == e1000_media_type_copper) &&
2064             (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
2065                 swap_now = true;
2066         } else if (!(connsw & E1000_CONNSW_SERDESD)) {
2067                 /* copper signal takes time to appear */
2068                 if (adapter->copper_tries < 4) {
2069                         adapter->copper_tries++;
2070                         connsw |= E1000_CONNSW_AUTOSENSE_CONF;
2071                         wr32(E1000_CONNSW, connsw);
2072                         return;
2073                 } else {
2074                         adapter->copper_tries = 0;
2075                         if ((connsw & E1000_CONNSW_PHYSD) &&
2076                             (!(connsw & E1000_CONNSW_PHY_PDN))) {
2077                                 swap_now = true;
2078                                 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
2079                                 wr32(E1000_CONNSW, connsw);
2080                         }
2081                 }
2082         }
2083
2084         if (!swap_now)
2085                 return;
2086
2087         switch (hw->phy.media_type) {
2088         case e1000_media_type_copper:
2089                 netdev_info(adapter->netdev,
2090                         "MAS: changing media to fiber/serdes\n");
2091                 ctrl_ext |=
2092                         E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2093                 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2094                 adapter->copper_tries = 0;
2095                 break;
2096         case e1000_media_type_internal_serdes:
2097         case e1000_media_type_fiber:
2098                 netdev_info(adapter->netdev,
2099                         "MAS: changing media to copper\n");
2100                 ctrl_ext &=
2101                         ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2102                 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2103                 break;
2104         default:
2105                 /* shouldn't get here during regular operation */
2106                 netdev_err(adapter->netdev,
2107                         "AMS: Invalid media type found, returning\n");
2108                 break;
2109         }
2110         wr32(E1000_CTRL_EXT, ctrl_ext);
2111 }
2112
2113 /**
2114  *  igb_up - Open the interface and prepare it to handle traffic
2115  *  @adapter: board private structure
2116  **/
2117 int igb_up(struct igb_adapter *adapter)
2118 {
2119         struct e1000_hw *hw = &adapter->hw;
2120         int i;
2121
2122         /* hardware has been reset, we need to reload some things */
2123         igb_configure(adapter);
2124
2125         clear_bit(__IGB_DOWN, &adapter->state);
2126
2127         for (i = 0; i < adapter->num_q_vectors; i++)
2128                 napi_enable(&(adapter->q_vector[i]->napi));
2129
2130         if (adapter->flags & IGB_FLAG_HAS_MSIX)
2131                 igb_configure_msix(adapter);
2132         else
2133                 igb_assign_vector(adapter->q_vector[0], 0);
2134
2135         /* Clear any pending interrupts. */
2136         rd32(E1000_TSICR);
2137         rd32(E1000_ICR);
2138         igb_irq_enable(adapter);
2139
2140         /* notify VFs that reset has been completed */
2141         if (adapter->vfs_allocated_count) {
2142                 u32 reg_data = rd32(E1000_CTRL_EXT);
2143
2144                 reg_data |= E1000_CTRL_EXT_PFRSTD;
2145                 wr32(E1000_CTRL_EXT, reg_data);
2146         }
2147
2148         netif_tx_start_all_queues(adapter->netdev);
2149
2150         /* start the watchdog. */
2151         hw->mac.get_link_status = 1;
2152         schedule_work(&adapter->watchdog_task);
2153
2154         if ((adapter->flags & IGB_FLAG_EEE) &&
2155             (!hw->dev_spec._82575.eee_disable))
2156                 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
2157
2158         return 0;
2159 }
2160
2161 void igb_down(struct igb_adapter *adapter)
2162 {
2163         struct net_device *netdev = adapter->netdev;
2164         struct e1000_hw *hw = &adapter->hw;
2165         u32 tctl, rctl;
2166         int i;
2167
2168         /* signal that we're down so the interrupt handler does not
2169          * reschedule our watchdog timer
2170          */
2171         set_bit(__IGB_DOWN, &adapter->state);
2172
2173         /* disable receives in the hardware */
2174         rctl = rd32(E1000_RCTL);
2175         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2176         /* flush and sleep below */
2177
2178         igb_nfc_filter_exit(adapter);
2179
2180         netif_carrier_off(netdev);
2181         netif_tx_stop_all_queues(netdev);
2182
2183         /* disable transmits in the hardware */
2184         tctl = rd32(E1000_TCTL);
2185         tctl &= ~E1000_TCTL_EN;
2186         wr32(E1000_TCTL, tctl);
2187         /* flush both disables and wait for them to finish */
2188         wrfl();
2189         usleep_range(10000, 11000);
2190
2191         igb_irq_disable(adapter);
2192
2193         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
2194
2195         for (i = 0; i < adapter->num_q_vectors; i++) {
2196                 if (adapter->q_vector[i]) {
2197                         napi_synchronize(&adapter->q_vector[i]->napi);
2198                         napi_disable(&adapter->q_vector[i]->napi);
2199                 }
2200         }
2201
2202         del_timer_sync(&adapter->watchdog_timer);
2203         del_timer_sync(&adapter->phy_info_timer);
2204
2205         /* record the stats before reset*/
2206         spin_lock(&adapter->stats64_lock);
2207         igb_update_stats(adapter);
2208         spin_unlock(&adapter->stats64_lock);
2209
2210         adapter->link_speed = 0;
2211         adapter->link_duplex = 0;
2212
2213         if (!pci_channel_offline(adapter->pdev))
2214                 igb_reset(adapter);
2215
2216         /* clear VLAN promisc flag so VFTA will be updated if necessary */
2217         adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
2218
2219         igb_clean_all_tx_rings(adapter);
2220         igb_clean_all_rx_rings(adapter);
2221 #ifdef CONFIG_IGB_DCA
2222
2223         /* since we reset the hardware DCA settings were cleared */
2224         igb_setup_dca(adapter);
2225 #endif
2226 }
2227
2228 void igb_reinit_locked(struct igb_adapter *adapter)
2229 {
2230         WARN_ON(in_interrupt());
2231         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2232                 usleep_range(1000, 2000);
2233         igb_down(adapter);
2234         igb_up(adapter);
2235         clear_bit(__IGB_RESETTING, &adapter->state);
2236 }
2237
2238 /** igb_enable_mas - Media Autosense re-enable after swap
2239  *
2240  * @adapter: adapter struct
2241  **/
2242 static void igb_enable_mas(struct igb_adapter *adapter)
2243 {
2244         struct e1000_hw *hw = &adapter->hw;
2245         u32 connsw = rd32(E1000_CONNSW);
2246
2247         /* configure for SerDes media detect */
2248         if ((hw->phy.media_type == e1000_media_type_copper) &&
2249             (!(connsw & E1000_CONNSW_SERDESD))) {
2250                 connsw |= E1000_CONNSW_ENRGSRC;
2251                 connsw |= E1000_CONNSW_AUTOSENSE_EN;
2252                 wr32(E1000_CONNSW, connsw);
2253                 wrfl();
2254         }
2255 }
2256
2257 void igb_reset(struct igb_adapter *adapter)
2258 {
2259         struct pci_dev *pdev = adapter->pdev;
2260         struct e1000_hw *hw = &adapter->hw;
2261         struct e1000_mac_info *mac = &hw->mac;
2262         struct e1000_fc_info *fc = &hw->fc;
2263         u32 pba, hwm;
2264
2265         /* Repartition Pba for greater than 9k mtu
2266          * To take effect CTRL.RST is required.
2267          */
2268         switch (mac->type) {
2269         case e1000_i350:
2270         case e1000_i354:
2271         case e1000_82580:
2272                 pba = rd32(E1000_RXPBS);
2273                 pba = igb_rxpbs_adjust_82580(pba);
2274                 break;
2275         case e1000_82576:
2276                 pba = rd32(E1000_RXPBS);
2277                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2278                 break;
2279         case e1000_82575:
2280         case e1000_i210:
2281         case e1000_i211:
2282         default:
2283                 pba = E1000_PBA_34K;
2284                 break;
2285         }
2286
2287         if (mac->type == e1000_82575) {
2288                 u32 min_rx_space, min_tx_space, needed_tx_space;
2289
2290                 /* write Rx PBA so that hardware can report correct Tx PBA */
2291                 wr32(E1000_PBA, pba);
2292
2293                 /* To maintain wire speed transmits, the Tx FIFO should be
2294                  * large enough to accommodate two full transmit packets,
2295                  * rounded up to the next 1KB and expressed in KB.  Likewise,
2296                  * the Rx FIFO should be large enough to accommodate at least
2297                  * one full receive packet and is similarly rounded up and
2298                  * expressed in KB.
2299                  */
2300                 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
2301
2302                 /* The Tx FIFO also stores 16 bytes of information about the Tx
2303                  * but don't include Ethernet FCS because hardware appends it.
2304                  * We only need to round down to the nearest 512 byte block
2305                  * count since the value we care about is 2 frames, not 1.
2306                  */
2307                 min_tx_space = adapter->max_frame_size;
2308                 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
2309                 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
2310
2311                 /* upper 16 bits has Tx packet buffer allocation size in KB */
2312                 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
2313
2314                 /* If current Tx allocation is less than the min Tx FIFO size,
2315                  * and the min Tx FIFO size is less than the current Rx FIFO
2316                  * allocation, take space away from current Rx allocation.
2317                  */
2318                 if (needed_tx_space < pba) {
2319                         pba -= needed_tx_space;
2320
2321                         /* if short on Rx space, Rx wins and must trump Tx
2322                          * adjustment
2323                          */
2324                         if (pba < min_rx_space)
2325                                 pba = min_rx_space;
2326                 }
2327
2328                 /* adjust PBA for jumbo frames */
2329                 wr32(E1000_PBA, pba);
2330         }
2331
2332         /* flow control settings
2333          * The high water mark must be low enough to fit one full frame
2334          * after transmitting the pause frame.  As such we must have enough
2335          * space to allow for us to complete our current transmit and then
2336          * receive the frame that is in progress from the link partner.
2337          * Set it to:
2338          * - the full Rx FIFO size minus one full Tx plus one full Rx frame
2339          */
2340         hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
2341
2342         fc->high_water = hwm & 0xFFFFFFF0;      /* 16-byte granularity */
2343         fc->low_water = fc->high_water - 16;
2344         fc->pause_time = 0xFFFF;
2345         fc->send_xon = 1;
2346         fc->current_mode = fc->requested_mode;
2347
2348         /* disable receive for all VFs and wait one second */
2349         if (adapter->vfs_allocated_count) {
2350                 int i;
2351
2352                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
2353                         adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
2354
2355                 /* ping all the active vfs to let them know we are going down */
2356                 igb_ping_all_vfs(adapter);
2357
2358                 /* disable transmits and receives */
2359                 wr32(E1000_VFRE, 0);
2360                 wr32(E1000_VFTE, 0);
2361         }
2362
2363         /* Allow time for pending master requests to run */
2364         hw->mac.ops.reset_hw(hw);
2365         wr32(E1000_WUC, 0);
2366
2367         if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
2368                 /* need to resetup here after media swap */
2369                 adapter->ei.get_invariants(hw);
2370                 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
2371         }
2372         if ((mac->type == e1000_82575) &&
2373             (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
2374                 igb_enable_mas(adapter);
2375         }
2376         if (hw->mac.ops.init_hw(hw))
2377                 dev_err(&pdev->dev, "Hardware Error\n");
2378
2379         /* RAR registers were cleared during init_hw, clear mac table */
2380         igb_flush_mac_table(adapter);
2381         __dev_uc_unsync(adapter->netdev, NULL);
2382
2383         /* Recover default RAR entry */
2384         igb_set_default_mac_filter(adapter);
2385
2386         /* Flow control settings reset on hardware reset, so guarantee flow
2387          * control is off when forcing speed.
2388          */
2389         if (!hw->mac.autoneg)
2390                 igb_force_mac_fc(hw);
2391
2392         igb_init_dmac(adapter, pba);
2393 #ifdef CONFIG_IGB_HWMON
2394         /* Re-initialize the thermal sensor on i350 devices. */
2395         if (!test_bit(__IGB_DOWN, &adapter->state)) {
2396                 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2397                         /* If present, re-initialize the external thermal sensor
2398                          * interface.
2399                          */
2400                         if (adapter->ets)
2401                                 mac->ops.init_thermal_sensor_thresh(hw);
2402                 }
2403         }
2404 #endif
2405         /* Re-establish EEE setting */
2406         if (hw->phy.media_type == e1000_media_type_copper) {
2407                 switch (mac->type) {
2408                 case e1000_i350:
2409                 case e1000_i210:
2410                 case e1000_i211:
2411                         igb_set_eee_i350(hw, true, true);
2412                         break;
2413                 case e1000_i354:
2414                         igb_set_eee_i354(hw, true, true);
2415                         break;
2416                 default:
2417                         break;
2418                 }
2419         }
2420         if (!netif_running(adapter->netdev))
2421                 igb_power_down_link(adapter);
2422
2423         igb_update_mng_vlan(adapter);
2424
2425         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2426         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2427
2428         /* Re-enable PTP, where applicable. */
2429         if (adapter->ptp_flags & IGB_PTP_ENABLED)
2430                 igb_ptp_reset(adapter);
2431
2432         igb_get_phy_info(hw);
2433 }
2434
2435 static netdev_features_t igb_fix_features(struct net_device *netdev,
2436         netdev_features_t features)
2437 {
2438         /* Since there is no support for separate Rx/Tx vlan accel
2439          * enable/disable make sure Tx flag is always in same state as Rx.
2440          */
2441         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2442                 features |= NETIF_F_HW_VLAN_CTAG_TX;
2443         else
2444                 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2445
2446         return features;
2447 }
2448
2449 static int igb_set_features(struct net_device *netdev,
2450         netdev_features_t features)
2451 {
2452         netdev_features_t changed = netdev->features ^ features;
2453         struct igb_adapter *adapter = netdev_priv(netdev);
2454
2455         if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2456                 igb_vlan_mode(netdev, features);
2457
2458         if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2459                 return 0;
2460
2461         if (!(features & NETIF_F_NTUPLE)) {
2462                 struct hlist_node *node2;
2463                 struct igb_nfc_filter *rule;
2464
2465                 spin_lock(&adapter->nfc_lock);
2466                 hlist_for_each_entry_safe(rule, node2,
2467                                           &adapter->nfc_filter_list, nfc_node) {
2468                         igb_erase_filter(adapter, rule);
2469                         hlist_del(&rule->nfc_node);
2470                         kfree(rule);
2471                 }
2472                 spin_unlock(&adapter->nfc_lock);
2473                 adapter->nfc_filter_count = 0;
2474         }
2475
2476         netdev->features = features;
2477
2478         if (netif_running(netdev))
2479                 igb_reinit_locked(adapter);
2480         else
2481                 igb_reset(adapter);
2482
2483         return 0;
2484 }
2485
2486 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2487                            struct net_device *dev,
2488                            const unsigned char *addr, u16 vid,
2489                            u16 flags,
2490                            struct netlink_ext_ack *extack)
2491 {
2492         /* guarantee we can provide a unique filter for the unicast address */
2493         if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2494                 struct igb_adapter *adapter = netdev_priv(dev);
2495                 int vfn = adapter->vfs_allocated_count;
2496
2497                 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn))
2498                         return -ENOMEM;
2499         }
2500
2501         return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2502 }
2503
2504 #define IGB_MAX_MAC_HDR_LEN     127
2505 #define IGB_MAX_NETWORK_HDR_LEN 511
2506
2507 static netdev_features_t
2508 igb_features_check(struct sk_buff *skb, struct net_device *dev,
2509                    netdev_features_t features)
2510 {
2511         unsigned int network_hdr_len, mac_hdr_len;
2512
2513         /* Make certain the headers can be described by a context descriptor */
2514         mac_hdr_len = skb_network_header(skb) - skb->data;
2515         if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2516                 return features & ~(NETIF_F_HW_CSUM |
2517                                     NETIF_F_SCTP_CRC |
2518                                     NETIF_F_HW_VLAN_CTAG_TX |
2519                                     NETIF_F_TSO |
2520                                     NETIF_F_TSO6);
2521
2522         network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2523         if (unlikely(network_hdr_len >  IGB_MAX_NETWORK_HDR_LEN))
2524                 return features & ~(NETIF_F_HW_CSUM |
2525                                     NETIF_F_SCTP_CRC |
2526                                     NETIF_F_TSO |
2527                                     NETIF_F_TSO6);
2528
2529         /* We can only support IPV4 TSO in tunnels if we can mangle the
2530          * inner IP ID field, so strip TSO if MANGLEID is not supported.
2531          */
2532         if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2533                 features &= ~NETIF_F_TSO;
2534
2535         return features;
2536 }
2537
2538 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue)
2539 {
2540         if (!is_fqtss_enabled(adapter)) {
2541                 enable_fqtss(adapter, true);
2542                 return;
2543         }
2544
2545         igb_config_tx_modes(adapter, queue);
2546
2547         if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter))
2548                 enable_fqtss(adapter, false);
2549 }
2550
2551 static int igb_offload_cbs(struct igb_adapter *adapter,
2552                            struct tc_cbs_qopt_offload *qopt)
2553 {
2554         struct e1000_hw *hw = &adapter->hw;
2555         int err;
2556
2557         /* CBS offloading is only supported by i210 controller. */
2558         if (hw->mac.type != e1000_i210)
2559                 return -EOPNOTSUPP;
2560
2561         /* CBS offloading is only supported by queue 0 and queue 1. */
2562         if (qopt->queue < 0 || qopt->queue > 1)
2563                 return -EINVAL;
2564
2565         err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable,
2566                                   qopt->idleslope, qopt->sendslope,
2567                                   qopt->hicredit, qopt->locredit);
2568         if (err)
2569                 return err;
2570
2571         igb_offload_apply(adapter, qopt->queue);
2572
2573         return 0;
2574 }
2575
2576 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2577 #define VLAN_PRIO_FULL_MASK (0x07)
2578
2579 static int igb_parse_cls_flower(struct igb_adapter *adapter,
2580                                 struct tc_cls_flower_offload *f,
2581                                 int traffic_class,
2582                                 struct igb_nfc_filter *input)
2583 {
2584         struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
2585         struct flow_dissector *dissector = rule->match.dissector;
2586         struct netlink_ext_ack *extack = f->common.extack;
2587
2588         if (dissector->used_keys &
2589             ~(BIT(FLOW_DISSECTOR_KEY_BASIC) |
2590               BIT(FLOW_DISSECTOR_KEY_CONTROL) |
2591               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2592               BIT(FLOW_DISSECTOR_KEY_VLAN))) {
2593                 NL_SET_ERR_MSG_MOD(extack,
2594                                    "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported");
2595                 return -EOPNOTSUPP;
2596         }
2597
2598         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2599                 struct flow_match_eth_addrs match;
2600
2601                 flow_rule_match_eth_addrs(rule, &match);
2602                 if (!is_zero_ether_addr(match.mask->dst)) {
2603                         if (!is_broadcast_ether_addr(match.mask->dst)) {
2604                                 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address");
2605                                 return -EINVAL;
2606                         }
2607
2608                         input->filter.match_flags |=
2609                                 IGB_FILTER_FLAG_DST_MAC_ADDR;
2610                         ether_addr_copy(input->filter.dst_addr, match.key->dst);
2611                 }
2612
2613                 if (!is_zero_ether_addr(match.mask->src)) {
2614                         if (!is_broadcast_ether_addr(match.mask->src)) {
2615                                 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address");
2616                                 return -EINVAL;
2617                         }
2618
2619                         input->filter.match_flags |=
2620                                 IGB_FILTER_FLAG_SRC_MAC_ADDR;
2621                         ether_addr_copy(input->filter.src_addr, match.key->src);
2622                 }
2623         }
2624
2625         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2626                 struct flow_match_basic match;
2627
2628                 flow_rule_match_basic(rule, &match);
2629                 if (match.mask->n_proto) {
2630                         if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) {
2631                                 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter");
2632                                 return -EINVAL;
2633                         }
2634
2635                         input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE;
2636                         input->filter.etype = match.key->n_proto;
2637                 }
2638         }
2639
2640         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
2641                 struct flow_match_vlan match;
2642
2643                 flow_rule_match_vlan(rule, &match);
2644                 if (match.mask->vlan_priority) {
2645                         if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) {
2646                                 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority");
2647                                 return -EINVAL;
2648                         }
2649
2650                         input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2651                         input->filter.vlan_tci = match.key->vlan_priority;
2652                 }
2653         }
2654
2655         input->action = traffic_class;
2656         input->cookie = f->cookie;
2657
2658         return 0;
2659 }
2660
2661 static int igb_configure_clsflower(struct igb_adapter *adapter,
2662                                    struct tc_cls_flower_offload *cls_flower)
2663 {
2664         struct netlink_ext_ack *extack = cls_flower->common.extack;
2665         struct igb_nfc_filter *filter, *f;
2666         int err, tc;
2667
2668         tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid);
2669         if (tc < 0) {
2670                 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class");
2671                 return -EINVAL;
2672         }
2673
2674         filter = kzalloc(sizeof(*filter), GFP_KERNEL);
2675         if (!filter)
2676                 return -ENOMEM;
2677
2678         err = igb_parse_cls_flower(adapter, cls_flower, tc, filter);
2679         if (err < 0)
2680                 goto err_parse;
2681
2682         spin_lock(&adapter->nfc_lock);
2683
2684         hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) {
2685                 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2686                         err = -EEXIST;
2687                         NL_SET_ERR_MSG_MOD(extack,
2688                                            "This filter is already set in ethtool");
2689                         goto err_locked;
2690                 }
2691         }
2692
2693         hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) {
2694                 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2695                         err = -EEXIST;
2696                         NL_SET_ERR_MSG_MOD(extack,
2697                                            "This filter is already set in cls_flower");
2698                         goto err_locked;
2699                 }
2700         }
2701
2702         err = igb_add_filter(adapter, filter);
2703         if (err < 0) {
2704                 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter");
2705                 goto err_locked;
2706         }
2707
2708         hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list);
2709
2710         spin_unlock(&adapter->nfc_lock);
2711
2712         return 0;
2713
2714 err_locked:
2715         spin_unlock(&adapter->nfc_lock);
2716
2717 err_parse:
2718         kfree(filter);
2719
2720         return err;
2721 }
2722
2723 static int igb_delete_clsflower(struct igb_adapter *adapter,
2724                                 struct tc_cls_flower_offload *cls_flower)
2725 {
2726         struct igb_nfc_filter *filter;
2727         int err;
2728
2729         spin_lock(&adapter->nfc_lock);
2730
2731         hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node)
2732                 if (filter->cookie == cls_flower->cookie)
2733                         break;
2734
2735         if (!filter) {
2736                 err = -ENOENT;
2737                 goto out;
2738         }
2739
2740         err = igb_erase_filter(adapter, filter);
2741         if (err < 0)
2742                 goto out;
2743
2744         hlist_del(&filter->nfc_node);
2745         kfree(filter);
2746
2747 out:
2748         spin_unlock(&adapter->nfc_lock);
2749
2750         return err;
2751 }
2752
2753 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter,
2754                                    struct tc_cls_flower_offload *cls_flower)
2755 {
2756         switch (cls_flower->command) {
2757         case TC_CLSFLOWER_REPLACE:
2758                 return igb_configure_clsflower(adapter, cls_flower);
2759         case TC_CLSFLOWER_DESTROY:
2760                 return igb_delete_clsflower(adapter, cls_flower);
2761         case TC_CLSFLOWER_STATS:
2762                 return -EOPNOTSUPP;
2763         default:
2764                 return -EOPNOTSUPP;
2765         }
2766 }
2767
2768 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2769                                  void *cb_priv)
2770 {
2771         struct igb_adapter *adapter = cb_priv;
2772
2773         if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
2774                 return -EOPNOTSUPP;
2775
2776         switch (type) {
2777         case TC_SETUP_CLSFLOWER:
2778                 return igb_setup_tc_cls_flower(adapter, type_data);
2779
2780         default:
2781                 return -EOPNOTSUPP;
2782         }
2783 }
2784
2785 static int igb_setup_tc_block(struct igb_adapter *adapter,
2786                               struct tc_block_offload *f)
2787 {
2788         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
2789                 return -EOPNOTSUPP;
2790
2791         switch (f->command) {
2792         case TC_BLOCK_BIND:
2793                 return tcf_block_cb_register(f->block, igb_setup_tc_block_cb,
2794                                              adapter, adapter, f->extack);
2795         case TC_BLOCK_UNBIND:
2796                 tcf_block_cb_unregister(f->block, igb_setup_tc_block_cb,
2797                                         adapter);
2798                 return 0;
2799         default:
2800                 return -EOPNOTSUPP;
2801         }
2802 }
2803
2804 static int igb_offload_txtime(struct igb_adapter *adapter,
2805                               struct tc_etf_qopt_offload *qopt)
2806 {
2807         struct e1000_hw *hw = &adapter->hw;
2808         int err;
2809
2810         /* Launchtime offloading is only supported by i210 controller. */
2811         if (hw->mac.type != e1000_i210)
2812                 return -EOPNOTSUPP;
2813
2814         /* Launchtime offloading is only supported by queues 0 and 1. */
2815         if (qopt->queue < 0 || qopt->queue > 1)
2816                 return -EINVAL;
2817
2818         err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable);
2819         if (err)
2820                 return err;
2821
2822         igb_offload_apply(adapter, qopt->queue);
2823
2824         return 0;
2825 }
2826
2827 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2828                         void *type_data)
2829 {
2830         struct igb_adapter *adapter = netdev_priv(dev);
2831
2832         switch (type) {
2833         case TC_SETUP_QDISC_CBS:
2834                 return igb_offload_cbs(adapter, type_data);
2835         case TC_SETUP_BLOCK:
2836                 return igb_setup_tc_block(adapter, type_data);
2837         case TC_SETUP_QDISC_ETF:
2838                 return igb_offload_txtime(adapter, type_data);
2839
2840         default:
2841                 return -EOPNOTSUPP;
2842         }
2843 }
2844
2845 static const struct net_device_ops igb_netdev_ops = {
2846         .ndo_open               = igb_open,
2847         .ndo_stop               = igb_close,
2848         .ndo_start_xmit         = igb_xmit_frame,
2849         .ndo_get_stats64        = igb_get_stats64,
2850         .ndo_set_rx_mode        = igb_set_rx_mode,
2851         .ndo_set_mac_address    = igb_set_mac,
2852         .ndo_change_mtu         = igb_change_mtu,
2853         .ndo_do_ioctl           = igb_ioctl,
2854         .ndo_tx_timeout         = igb_tx_timeout,
2855         .ndo_validate_addr      = eth_validate_addr,
2856         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
2857         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
2858         .ndo_set_vf_mac         = igb_ndo_set_vf_mac,
2859         .ndo_set_vf_vlan        = igb_ndo_set_vf_vlan,
2860         .ndo_set_vf_rate        = igb_ndo_set_vf_bw,
2861         .ndo_set_vf_spoofchk    = igb_ndo_set_vf_spoofchk,
2862         .ndo_set_vf_trust       = igb_ndo_set_vf_trust,
2863         .ndo_get_vf_config      = igb_ndo_get_vf_config,
2864         .ndo_fix_features       = igb_fix_features,
2865         .ndo_set_features       = igb_set_features,
2866         .ndo_fdb_add            = igb_ndo_fdb_add,
2867         .ndo_features_check     = igb_features_check,
2868         .ndo_setup_tc           = igb_setup_tc,
2869 };
2870
2871 /**
2872  * igb_set_fw_version - Configure version string for ethtool
2873  * @adapter: adapter struct
2874  **/
2875 void igb_set_fw_version(struct igb_adapter *adapter)
2876 {
2877         struct e1000_hw *hw = &adapter->hw;
2878         struct e1000_fw_version fw;
2879
2880         igb_get_fw_version(hw, &fw);
2881
2882         switch (hw->mac.type) {
2883         case e1000_i210:
2884         case e1000_i211:
2885                 if (!(igb_get_flash_presence_i210(hw))) {
2886                         snprintf(adapter->fw_version,
2887                                  sizeof(adapter->fw_version),
2888                                  "%2d.%2d-%d",
2889                                  fw.invm_major, fw.invm_minor,
2890                                  fw.invm_img_type);
2891                         break;
2892                 }
2893                 /* fall through */
2894         default:
2895                 /* if option is rom valid, display its version too */
2896                 if (fw.or_valid) {
2897                         snprintf(adapter->fw_version,
2898                                  sizeof(adapter->fw_version),
2899                                  "%d.%d, 0x%08x, %d.%d.%d",
2900                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2901                                  fw.or_major, fw.or_build, fw.or_patch);
2902                 /* no option rom */
2903                 } else if (fw.etrack_id != 0X0000) {
2904                         snprintf(adapter->fw_version,
2905                             sizeof(adapter->fw_version),
2906                             "%d.%d, 0x%08x",
2907                             fw.eep_major, fw.eep_minor, fw.etrack_id);
2908                 } else {
2909                 snprintf(adapter->fw_version,
2910                     sizeof(adapter->fw_version),
2911                     "%d.%d.%d",
2912                     fw.eep_major, fw.eep_minor, fw.eep_build);
2913                 }
2914                 break;
2915         }
2916 }
2917
2918 /**
2919  * igb_init_mas - init Media Autosense feature if enabled in the NVM
2920  *
2921  * @adapter: adapter struct
2922  **/
2923 static void igb_init_mas(struct igb_adapter *adapter)
2924 {
2925         struct e1000_hw *hw = &adapter->hw;
2926         u16 eeprom_data;
2927
2928         hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2929         switch (hw->bus.func) {
2930         case E1000_FUNC_0:
2931                 if (eeprom_data & IGB_MAS_ENABLE_0) {
2932                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2933                         netdev_info(adapter->netdev,
2934                                 "MAS: Enabling Media Autosense for port %d\n",
2935                                 hw->bus.func);
2936                 }
2937                 break;
2938         case E1000_FUNC_1:
2939                 if (eeprom_data & IGB_MAS_ENABLE_1) {
2940                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2941                         netdev_info(adapter->netdev,
2942                                 "MAS: Enabling Media Autosense for port %d\n",
2943                                 hw->bus.func);
2944                 }
2945                 break;
2946         case E1000_FUNC_2:
2947                 if (eeprom_data & IGB_MAS_ENABLE_2) {
2948                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2949                         netdev_info(adapter->netdev,
2950                                 "MAS: Enabling Media Autosense for port %d\n",
2951                                 hw->bus.func);
2952                 }
2953                 break;
2954         case E1000_FUNC_3:
2955                 if (eeprom_data & IGB_MAS_ENABLE_3) {
2956                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2957                         netdev_info(adapter->netdev,
2958                                 "MAS: Enabling Media Autosense for port %d\n",
2959                                 hw->bus.func);
2960                 }
2961                 break;
2962         default:
2963                 /* Shouldn't get here */
2964                 netdev_err(adapter->netdev,
2965                         "MAS: Invalid port configuration, returning\n");
2966                 break;
2967         }
2968 }
2969
2970 /**
2971  *  igb_init_i2c - Init I2C interface
2972  *  @adapter: pointer to adapter structure
2973  **/
2974 static s32 igb_init_i2c(struct igb_adapter *adapter)
2975 {
2976         s32 status = 0;
2977
2978         /* I2C interface supported on i350 devices */
2979         if (adapter->hw.mac.type != e1000_i350)
2980                 return 0;
2981
2982         /* Initialize the i2c bus which is controlled by the registers.
2983          * This bus will use the i2c_algo_bit structue that implements
2984          * the protocol through toggling of the 4 bits in the register.
2985          */
2986         adapter->i2c_adap.owner = THIS_MODULE;
2987         adapter->i2c_algo = igb_i2c_algo;
2988         adapter->i2c_algo.data = adapter;
2989         adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2990         adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2991         strlcpy(adapter->i2c_adap.name, "igb BB",
2992                 sizeof(adapter->i2c_adap.name));
2993         status = i2c_bit_add_bus(&adapter->i2c_adap);
2994         return status;
2995 }
2996
2997 /**
2998  *  igb_probe - Device Initialization Routine
2999  *  @pdev: PCI device information struct
3000  *  @ent: entry in igb_pci_tbl
3001  *
3002  *  Returns 0 on success, negative on failure
3003  *
3004  *  igb_probe initializes an adapter identified by a pci_dev structure.
3005  *  The OS initialization, configuring of the adapter private structure,
3006  *  and a hardware reset occur.
3007  **/
3008 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3009 {
3010         struct net_device *netdev;
3011         struct igb_adapter *adapter;
3012         struct e1000_hw *hw;
3013         u16 eeprom_data = 0;
3014         s32 ret_val;
3015         static int global_quad_port_a; /* global quad port a indication */
3016         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
3017         int err, pci_using_dac;
3018         u8 part_str[E1000_PBANUM_LENGTH];
3019
3020         /* Catch broken hardware that put the wrong VF device ID in
3021          * the PCIe SR-IOV capability.
3022          */
3023         if (pdev->is_virtfn) {
3024                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
3025                         pci_name(pdev), pdev->vendor, pdev->device);
3026                 return -EINVAL;
3027         }
3028
3029         err = pci_enable_device_mem(pdev);
3030         if (err)
3031                 return err;
3032
3033         pci_using_dac = 0;
3034         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3035         if (!err) {
3036                 pci_using_dac = 1;
3037         } else {
3038                 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3039                 if (err) {
3040                         dev_err(&pdev->dev,
3041                                 "No usable DMA configuration, aborting\n");
3042                         goto err_dma;
3043                 }
3044         }
3045
3046         err = pci_request_mem_regions(pdev, igb_driver_name);
3047         if (err)
3048                 goto err_pci_reg;
3049
3050         pci_enable_pcie_error_reporting(pdev);
3051
3052         pci_set_master(pdev);
3053         pci_save_state(pdev);
3054
3055         err = -ENOMEM;
3056         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
3057                                    IGB_MAX_TX_QUEUES);
3058         if (!netdev)
3059                 goto err_alloc_etherdev;
3060
3061         SET_NETDEV_DEV(netdev, &pdev->dev);
3062
3063         pci_set_drvdata(pdev, netdev);
3064         adapter = netdev_priv(netdev);
3065         adapter->netdev = netdev;
3066         adapter->pdev = pdev;
3067         hw = &adapter->hw;
3068         hw->back = adapter;
3069         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3070
3071         err = -EIO;
3072         adapter->io_addr = pci_iomap(pdev, 0, 0);
3073         if (!adapter->io_addr)
3074                 goto err_ioremap;
3075         /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
3076         hw->hw_addr = adapter->io_addr;
3077
3078         netdev->netdev_ops = &igb_netdev_ops;
3079         igb_set_ethtool_ops(netdev);
3080         netdev->watchdog_timeo = 5 * HZ;
3081
3082         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
3083
3084         netdev->mem_start = pci_resource_start(pdev, 0);
3085         netdev->mem_end = pci_resource_end(pdev, 0);
3086
3087         /* PCI config space info */
3088         hw->vendor_id = pdev->vendor;
3089         hw->device_id = pdev->device;
3090         hw->revision_id = pdev->revision;
3091         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3092         hw->subsystem_device_id = pdev->subsystem_device;
3093
3094         /* Copy the default MAC, PHY and NVM function pointers */
3095         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
3096         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
3097         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
3098         /* Initialize skew-specific constants */
3099         err = ei->get_invariants(hw);
3100         if (err)
3101                 goto err_sw_init;
3102
3103         /* setup the private structure */
3104         err = igb_sw_init(adapter);
3105         if (err)
3106                 goto err_sw_init;
3107
3108         igb_get_bus_info_pcie(hw);
3109
3110         hw->phy.autoneg_wait_to_complete = false;
3111
3112         /* Copper options */
3113         if (hw->phy.media_type == e1000_media_type_copper) {
3114                 hw->phy.mdix = AUTO_ALL_MODES;
3115                 hw->phy.disable_polarity_correction = false;
3116                 hw->phy.ms_type = e1000_ms_hw_default;
3117         }
3118
3119         if (igb_check_reset_block(hw))
3120                 dev_info(&pdev->dev,
3121                         "PHY reset is blocked due to SOL/IDER session.\n");
3122
3123         /* features is initialized to 0 in allocation, it might have bits
3124          * set by igb_sw_init so we should use an or instead of an
3125          * assignment.
3126          */
3127         netdev->features |= NETIF_F_SG |
3128                             NETIF_F_TSO |
3129                             NETIF_F_TSO6 |
3130                             NETIF_F_RXHASH |
3131                             NETIF_F_RXCSUM |
3132                             NETIF_F_HW_CSUM;
3133
3134         if (hw->mac.type >= e1000_82576)
3135                 netdev->features |= NETIF_F_SCTP_CRC;
3136
3137         if (hw->mac.type >= e1000_i350)
3138                 netdev->features |= NETIF_F_HW_TC;
3139
3140 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
3141                                   NETIF_F_GSO_GRE_CSUM | \
3142                                   NETIF_F_GSO_IPXIP4 | \
3143                                   NETIF_F_GSO_IPXIP6 | \
3144                                   NETIF_F_GSO_UDP_TUNNEL | \
3145                                   NETIF_F_GSO_UDP_TUNNEL_CSUM)
3146
3147         netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
3148         netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
3149
3150         /* copy netdev features into list of user selectable features */
3151         netdev->hw_features |= netdev->features |
3152                                NETIF_F_HW_VLAN_CTAG_RX |
3153                                NETIF_F_HW_VLAN_CTAG_TX |
3154                                NETIF_F_RXALL;
3155
3156         if (hw->mac.type >= e1000_i350)
3157                 netdev->hw_features |= NETIF_F_NTUPLE;
3158
3159         if (pci_using_dac)
3160                 netdev->features |= NETIF_F_HIGHDMA;
3161
3162         netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
3163         netdev->mpls_features |= NETIF_F_HW_CSUM;
3164         netdev->hw_enc_features |= netdev->vlan_features;
3165
3166         /* set this bit last since it cannot be part of vlan_features */
3167         netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3168                             NETIF_F_HW_VLAN_CTAG_RX |
3169                             NETIF_F_HW_VLAN_CTAG_TX;
3170
3171         netdev->priv_flags |= IFF_SUPP_NOFCS;
3172
3173         netdev->priv_flags |= IFF_UNICAST_FLT;
3174
3175         /* MTU range: 68 - 9216 */
3176         netdev->min_mtu = ETH_MIN_MTU;
3177         netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
3178
3179         adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
3180
3181         /* before reading the NVM, reset the controller to put the device in a
3182          * known good starting state
3183          */
3184         hw->mac.ops.reset_hw(hw);
3185
3186         /* make sure the NVM is good , i211/i210 parts can have special NVM
3187          * that doesn't contain a checksum
3188          */
3189         switch (hw->mac.type) {
3190         case e1000_i210:
3191         case e1000_i211:
3192                 if (igb_get_flash_presence_i210(hw)) {
3193                         if (hw->nvm.ops.validate(hw) < 0) {
3194                                 dev_err(&pdev->dev,
3195                                         "The NVM Checksum Is Not Valid\n");
3196                                 err = -EIO;
3197                                 goto err_eeprom;
3198                         }
3199                 }
3200                 break;
3201         default:
3202                 if (hw->nvm.ops.validate(hw) < 0) {
3203                         dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
3204                         err = -EIO;
3205                         goto err_eeprom;
3206                 }
3207                 break;
3208         }
3209
3210         if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
3211                 /* copy the MAC address out of the NVM */
3212                 if (hw->mac.ops.read_mac_addr(hw))
3213                         dev_err(&pdev->dev, "NVM Read Error\n");
3214         }
3215
3216         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
3217
3218         if (!is_valid_ether_addr(netdev->dev_addr)) {
3219                 dev_err(&pdev->dev, "Invalid MAC Address\n");
3220                 err = -EIO;
3221                 goto err_eeprom;
3222         }
3223
3224         igb_set_default_mac_filter(adapter);
3225
3226         /* get firmware version for ethtool -i */
3227         igb_set_fw_version(adapter);
3228
3229         /* configure RXPBSIZE and TXPBSIZE */
3230         if (hw->mac.type == e1000_i210) {
3231                 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
3232                 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
3233         }
3234
3235         timer_setup(&adapter->watchdog_timer, igb_watchdog, 0);
3236         timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0);
3237
3238         INIT_WORK(&adapter->reset_task, igb_reset_task);
3239         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
3240
3241         /* Initialize link properties that are user-changeable */
3242         adapter->fc_autoneg = true;
3243         hw->mac.autoneg = true;
3244         hw->phy.autoneg_advertised = 0x2f;
3245
3246         hw->fc.requested_mode = e1000_fc_default;
3247         hw->fc.current_mode = e1000_fc_default;
3248
3249         igb_validate_mdi_setting(hw);
3250
3251         /* By default, support wake on port A */
3252         if (hw->bus.func == 0)
3253                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3254
3255         /* Check the NVM for wake support on non-port A ports */
3256         if (hw->mac.type >= e1000_82580)
3257                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
3258                                  NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
3259                                  &eeprom_data);
3260         else if (hw->bus.func == 1)
3261                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3262
3263         if (eeprom_data & IGB_EEPROM_APME)
3264                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3265
3266         /* now that we have the eeprom settings, apply the special cases where
3267          * the eeprom may be wrong or the board simply won't support wake on
3268          * lan on a particular port
3269          */
3270         switch (pdev->device) {
3271         case E1000_DEV_ID_82575GB_QUAD_COPPER:
3272                 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3273                 break;
3274         case E1000_DEV_ID_82575EB_FIBER_SERDES:
3275         case E1000_DEV_ID_82576_FIBER:
3276         case E1000_DEV_ID_82576_SERDES:
3277                 /* Wake events only supported on port A for dual fiber
3278                  * regardless of eeprom setting
3279                  */
3280                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
3281                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3282                 break;
3283         case E1000_DEV_ID_82576_QUAD_COPPER:
3284         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
3285                 /* if quad port adapter, disable WoL on all but port A */
3286                 if (global_quad_port_a != 0)
3287                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3288                 else
3289                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
3290                 /* Reset for multiple quad port adapters */
3291                 if (++global_quad_port_a == 4)
3292                         global_quad_port_a = 0;
3293                 break;
3294         default:
3295                 /* If the device can't wake, don't set software support */
3296                 if (!device_can_wakeup(&adapter->pdev->dev))
3297                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3298         }
3299
3300         /* initialize the wol settings based on the eeprom settings */
3301         if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
3302                 adapter->wol |= E1000_WUFC_MAG;
3303
3304         /* Some vendors want WoL disabled by default, but still supported */
3305         if ((hw->mac.type == e1000_i350) &&
3306             (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
3307                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3308                 adapter->wol = 0;
3309         }
3310
3311         /* Some vendors want the ability to Use the EEPROM setting as
3312          * enable/disable only, and not for capability
3313          */
3314         if (((hw->mac.type == e1000_i350) ||
3315              (hw->mac.type == e1000_i354)) &&
3316             (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
3317                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3318                 adapter->wol = 0;
3319         }
3320         if (hw->mac.type == e1000_i350) {
3321                 if (((pdev->subsystem_device == 0x5001) ||
3322                      (pdev->subsystem_device == 0x5002)) &&
3323                                 (hw->bus.func == 0)) {
3324                         adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3325                         adapter->wol = 0;
3326                 }
3327                 if (pdev->subsystem_device == 0x1F52)
3328                         adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3329         }
3330
3331         device_set_wakeup_enable(&adapter->pdev->dev,
3332                                  adapter->flags & IGB_FLAG_WOL_SUPPORTED);
3333
3334         /* reset the hardware with the new settings */
3335         igb_reset(adapter);
3336
3337         /* Init the I2C interface */
3338         err = igb_init_i2c(adapter);
3339         if (err) {
3340                 dev_err(&pdev->dev, "failed to init i2c interface\n");
3341                 goto err_eeprom;
3342         }
3343
3344         /* let the f/w know that the h/w is now under the control of the
3345          * driver.
3346          */
3347         igb_get_hw_control(adapter);
3348
3349         strcpy(netdev->name, "eth%d");
3350         err = register_netdev(netdev);
3351         if (err)
3352                 goto err_register;
3353
3354         /* carrier off reporting is important to ethtool even BEFORE open */
3355         netif_carrier_off(netdev);
3356
3357 #ifdef CONFIG_IGB_DCA
3358         if (dca_add_requester(&pdev->dev) == 0) {
3359                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3360                 dev_info(&pdev->dev, "DCA enabled\n");
3361                 igb_setup_dca(adapter);
3362         }
3363
3364 #endif
3365 #ifdef CONFIG_IGB_HWMON
3366         /* Initialize the thermal sensor on i350 devices. */
3367         if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
3368                 u16 ets_word;
3369
3370                 /* Read the NVM to determine if this i350 device supports an
3371                  * external thermal sensor.
3372                  */
3373                 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
3374                 if (ets_word != 0x0000 && ets_word != 0xFFFF)
3375                         adapter->ets = true;
3376                 else
3377                         adapter->ets = false;
3378                 if (igb_sysfs_init(adapter))
3379                         dev_err(&pdev->dev,
3380                                 "failed to allocate sysfs resources\n");
3381         } else {
3382                 adapter->ets = false;
3383         }
3384 #endif
3385         /* Check if Media Autosense is enabled */
3386         adapter->ei = *ei;
3387         if (hw->dev_spec._82575.mas_capable)
3388                 igb_init_mas(adapter);
3389
3390         /* do hw tstamp init after resetting */
3391         igb_ptp_init(adapter);
3392
3393         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
3394         /* print bus type/speed/width info, not applicable to i354 */
3395         if (hw->mac.type != e1000_i354) {
3396                 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
3397                          netdev->name,
3398                          ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
3399                           (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
3400                            "unknown"),
3401                          ((hw->bus.width == e1000_bus_width_pcie_x4) ?
3402                           "Width x4" :
3403                           (hw->bus.width == e1000_bus_width_pcie_x2) ?
3404                           "Width x2" :
3405                           (hw->bus.width == e1000_bus_width_pcie_x1) ?
3406                           "Width x1" : "unknown"), netdev->dev_addr);
3407         }
3408
3409         if ((hw->mac.type >= e1000_i210 ||
3410              igb_get_flash_presence_i210(hw))) {
3411                 ret_val = igb_read_part_string(hw, part_str,
3412                                                E1000_PBANUM_LENGTH);
3413         } else {
3414                 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
3415         }
3416
3417         if (ret_val)
3418                 strcpy(part_str, "Unknown");
3419         dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
3420         dev_info(&pdev->dev,
3421                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
3422                 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
3423                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
3424                 adapter->num_rx_queues, adapter->num_tx_queues);
3425         if (hw->phy.media_type == e1000_media_type_copper) {
3426                 switch (hw->mac.type) {
3427                 case e1000_i350:
3428                 case e1000_i210:
3429                 case e1000_i211:
3430                         /* Enable EEE for internal copper PHY devices */
3431                         err = igb_set_eee_i350(hw, true, true);
3432                         if ((!err) &&
3433                             (!hw->dev_spec._82575.eee_disable)) {
3434                                 adapter->eee_advert =
3435                                         MDIO_EEE_100TX | MDIO_EEE_1000T;
3436                                 adapter->flags |= IGB_FLAG_EEE;
3437                         }
3438                         break;
3439                 case e1000_i354:
3440                         if ((rd32(E1000_CTRL_EXT) &
3441                             E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3442                                 err = igb_set_eee_i354(hw, true, true);
3443                                 if ((!err) &&
3444                                         (!hw->dev_spec._82575.eee_disable)) {
3445                                         adapter->eee_advert =
3446                                            MDIO_EEE_100TX | MDIO_EEE_1000T;
3447                                         adapter->flags |= IGB_FLAG_EEE;
3448                                 }
3449                         }
3450                         break;
3451                 default:
3452                         break;
3453                 }
3454         }
3455         pm_runtime_put_noidle(&pdev->dev);
3456         return 0;
3457
3458 err_register:
3459         igb_release_hw_control(adapter);
3460         memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
3461 err_eeprom:
3462         if (!igb_check_reset_block(hw))
3463                 igb_reset_phy(hw);
3464
3465         if (hw->flash_address)
3466                 iounmap(hw->flash_address);
3467 err_sw_init:
3468         kfree(adapter->mac_table);
3469         kfree(adapter->shadow_vfta);
3470         igb_clear_interrupt_scheme(adapter);
3471 #ifdef CONFIG_PCI_IOV
3472         igb_disable_sriov(pdev);
3473 #endif
3474         pci_iounmap(pdev, adapter->io_addr);
3475 err_ioremap:
3476         free_netdev(netdev);
3477 err_alloc_etherdev:
3478         pci_release_mem_regions(pdev);
3479 err_pci_reg:
3480 err_dma:
3481         pci_disable_device(pdev);
3482         return err;
3483 }
3484
3485 #ifdef CONFIG_PCI_IOV
3486 static int igb_disable_sriov(struct pci_dev *pdev)
3487 {
3488         struct net_device *netdev = pci_get_drvdata(pdev);
3489         struct igb_adapter *adapter = netdev_priv(netdev);
3490         struct e1000_hw *hw = &adapter->hw;
3491
3492         /* reclaim resources allocated to VFs */
3493         if (adapter->vf_data) {
3494                 /* disable iov and allow time for transactions to clear */
3495                 if (pci_vfs_assigned(pdev)) {
3496                         dev_warn(&pdev->dev,
3497                                  "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
3498                         return -EPERM;
3499                 } else {
3500                         pci_disable_sriov(pdev);
3501                         msleep(500);
3502                 }
3503
3504                 kfree(adapter->vf_mac_list);
3505                 adapter->vf_mac_list = NULL;
3506                 kfree(adapter->vf_data);
3507                 adapter->vf_data = NULL;
3508                 adapter->vfs_allocated_count = 0;
3509                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
3510                 wrfl();
3511                 msleep(100);
3512                 dev_info(&pdev->dev, "IOV Disabled\n");
3513
3514                 /* Re-enable DMA Coalescing flag since IOV is turned off */
3515                 adapter->flags |= IGB_FLAG_DMAC;
3516         }
3517
3518         return 0;
3519 }
3520
3521 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
3522 {
3523         struct net_device *netdev = pci_get_drvdata(pdev);
3524         struct igb_adapter *adapter = netdev_priv(netdev);
3525         int old_vfs = pci_num_vf(pdev);
3526         struct vf_mac_filter *mac_list;
3527         int err = 0;
3528         int num_vf_mac_filters, i;
3529
3530         if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
3531                 err = -EPERM;
3532                 goto out;
3533         }
3534         if (!num_vfs)
3535                 goto out;
3536
3537         if (old_vfs) {
3538                 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
3539                          old_vfs, max_vfs);
3540                 adapter->vfs_allocated_count = old_vfs;
3541         } else
3542                 adapter->vfs_allocated_count = num_vfs;
3543
3544         adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
3545                                 sizeof(struct vf_data_storage), GFP_KERNEL);
3546
3547         /* if allocation failed then we do not support SR-IOV */
3548         if (!adapter->vf_data) {
3549                 adapter->vfs_allocated_count = 0;
3550                 err = -ENOMEM;
3551                 goto out;
3552         }
3553
3554         /* Due to the limited number of RAR entries calculate potential
3555          * number of MAC filters available for the VFs. Reserve entries
3556          * for PF default MAC, PF MAC filters and at least one RAR entry
3557          * for each VF for VF MAC.
3558          */
3559         num_vf_mac_filters = adapter->hw.mac.rar_entry_count -
3560                              (1 + IGB_PF_MAC_FILTERS_RESERVED +
3561                               adapter->vfs_allocated_count);
3562
3563         adapter->vf_mac_list = kcalloc(num_vf_mac_filters,
3564                                        sizeof(struct vf_mac_filter),
3565                                        GFP_KERNEL);
3566
3567         mac_list = adapter->vf_mac_list;
3568         INIT_LIST_HEAD(&adapter->vf_macs.l);
3569
3570         if (adapter->vf_mac_list) {
3571                 /* Initialize list of VF MAC filters */
3572                 for (i = 0; i < num_vf_mac_filters; i++) {
3573                         mac_list->vf = -1;
3574                         mac_list->free = true;
3575                         list_add(&mac_list->l, &adapter->vf_macs.l);
3576                         mac_list++;
3577                 }
3578         } else {
3579                 /* If we could not allocate memory for the VF MAC filters
3580                  * we can continue without this feature but warn user.
3581                  */
3582                 dev_err(&pdev->dev,
3583                         "Unable to allocate memory for VF MAC filter list\n");
3584         }
3585
3586         /* only call pci_enable_sriov() if no VFs are allocated already */
3587         if (!old_vfs) {
3588                 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
3589                 if (err)
3590                         goto err_out;
3591         }
3592         dev_info(&pdev->dev, "%d VFs allocated\n",
3593                  adapter->vfs_allocated_count);
3594         for (i = 0; i < adapter->vfs_allocated_count; i++)
3595                 igb_vf_configure(adapter, i);
3596
3597         /* DMA Coalescing is not supported in IOV mode. */
3598         adapter->flags &= ~IGB_FLAG_DMAC;
3599         goto out;
3600
3601 err_out:
3602         kfree(adapter->vf_mac_list);
3603         adapter->vf_mac_list = NULL;
3604         kfree(adapter->vf_data);
3605         adapter->vf_data = NULL;
3606         adapter->vfs_allocated_count = 0;
3607 out:
3608         return err;
3609 }
3610
3611 #endif
3612 /**
3613  *  igb_remove_i2c - Cleanup  I2C interface
3614  *  @adapter: pointer to adapter structure
3615  **/
3616 static void igb_remove_i2c(struct igb_adapter *adapter)
3617 {
3618         /* free the adapter bus structure */
3619         i2c_del_adapter(&adapter->i2c_adap);
3620 }
3621
3622 /**
3623  *  igb_remove - Device Removal Routine
3624  *  @pdev: PCI device information struct
3625  *
3626  *  igb_remove is called by the PCI subsystem to alert the driver
3627  *  that it should release a PCI device.  The could be caused by a
3628  *  Hot-Plug event, or because the driver is going to be removed from
3629  *  memory.
3630  **/
3631 static void igb_remove(struct pci_dev *pdev)
3632 {
3633         struct net_device *netdev = pci_get_drvdata(pdev);
3634         struct igb_adapter *adapter = netdev_priv(netdev);
3635         struct e1000_hw *hw = &adapter->hw;
3636
3637         pm_runtime_get_noresume(&pdev->dev);
3638 #ifdef CONFIG_IGB_HWMON
3639         igb_sysfs_exit(adapter);
3640 #endif
3641         igb_remove_i2c(adapter);
3642         igb_ptp_stop(adapter);
3643         /* The watchdog timer may be rescheduled, so explicitly
3644          * disable watchdog from being rescheduled.
3645          */
3646         set_bit(__IGB_DOWN, &adapter->state);
3647         del_timer_sync(&adapter->watchdog_timer);
3648         del_timer_sync(&adapter->phy_info_timer);
3649
3650         cancel_work_sync(&adapter->reset_task);
3651         cancel_work_sync(&adapter->watchdog_task);
3652
3653 #ifdef CONFIG_IGB_DCA
3654         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3655                 dev_info(&pdev->dev, "DCA disabled\n");
3656                 dca_remove_requester(&pdev->dev);
3657                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3658                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3659         }
3660 #endif
3661
3662         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
3663          * would have already happened in close and is redundant.
3664          */
3665         igb_release_hw_control(adapter);
3666
3667 #ifdef CONFIG_PCI_IOV
3668         igb_disable_sriov(pdev);
3669 #endif
3670
3671         unregister_netdev(netdev);
3672
3673         igb_clear_interrupt_scheme(adapter);
3674
3675         pci_iounmap(pdev, adapter->io_addr);
3676         if (hw->flash_address)
3677                 iounmap(hw->flash_address);
3678         pci_release_mem_regions(pdev);
3679
3680         kfree(adapter->mac_table);
3681         kfree(adapter->shadow_vfta);
3682         free_netdev(netdev);
3683
3684         pci_disable_pcie_error_reporting(pdev);
3685
3686         pci_disable_device(pdev);
3687 }
3688
3689 /**
3690  *  igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
3691  *  @adapter: board private structure to initialize
3692  *
3693  *  This function initializes the vf specific data storage and then attempts to
3694  *  allocate the VFs.  The reason for ordering it this way is because it is much
3695  *  mor expensive time wise to disable SR-IOV than it is to allocate and free
3696  *  the memory for the VFs.
3697  **/
3698 static void igb_probe_vfs(struct igb_adapter *adapter)
3699 {
3700 #ifdef CONFIG_PCI_IOV
3701         struct pci_dev *pdev = adapter->pdev;
3702         struct e1000_hw *hw = &adapter->hw;
3703
3704         /* Virtualization features not supported on i210 family. */
3705         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
3706                 return;
3707
3708         /* Of the below we really only want the effect of getting
3709          * IGB_FLAG_HAS_MSIX set (if available), without which
3710          * igb_enable_sriov() has no effect.
3711          */
3712         igb_set_interrupt_capability(adapter, true);
3713         igb_reset_interrupt_capability(adapter);
3714
3715         pci_sriov_set_totalvfs(pdev, 7);
3716         igb_enable_sriov(pdev, max_vfs);
3717
3718 #endif /* CONFIG_PCI_IOV */
3719 }
3720
3721 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter)
3722 {
3723         struct e1000_hw *hw = &adapter->hw;
3724         unsigned int max_rss_queues;
3725
3726         /* Determine the maximum number of RSS queues supported. */
3727         switch (hw->mac.type) {
3728         case e1000_i211:
3729                 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
3730                 break;
3731         case e1000_82575:
3732         case e1000_i210:
3733                 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
3734                 break;
3735         case e1000_i350:
3736                 /* I350 cannot do RSS and SR-IOV at the same time */
3737                 if (!!adapter->vfs_allocated_count) {
3738                         max_rss_queues = 1;
3739                         break;
3740                 }
3741                 /* fall through */
3742         case e1000_82576:
3743                 if (!!adapter->vfs_allocated_count) {
3744                         max_rss_queues = 2;
3745                         break;
3746                 }
3747                 /* fall through */
3748         case e1000_82580:
3749         case e1000_i354:
3750         default:
3751                 max_rss_queues = IGB_MAX_RX_QUEUES;
3752                 break;
3753         }
3754
3755         return max_rss_queues;
3756 }
3757
3758 static void igb_init_queue_configuration(struct igb_adapter *adapter)
3759 {
3760         u32 max_rss_queues;
3761
3762         max_rss_queues = igb_get_max_rss_queues(adapter);
3763         adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
3764
3765         igb_set_flag_queue_pairs(adapter, max_rss_queues);
3766 }
3767
3768 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
3769                               const u32 max_rss_queues)
3770 {
3771         struct e1000_hw *hw = &adapter->hw;
3772
3773         /* Determine if we need to pair queues. */
3774         switch (hw->mac.type) {
3775         case e1000_82575:
3776         case e1000_i211:
3777                 /* Device supports enough interrupts without queue pairing. */
3778                 break;
3779         case e1000_82576:
3780         case e1000_82580:
3781         case e1000_i350:
3782         case e1000_i354:
3783         case e1000_i210:
3784         default:
3785                 /* If rss_queues > half of max_rss_queues, pair the queues in
3786                  * order to conserve interrupts due to limited supply.
3787                  */
3788                 if (adapter->rss_queues > (max_rss_queues / 2))
3789                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
3790                 else
3791                         adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
3792                 break;
3793         }
3794 }
3795
3796 /**
3797  *  igb_sw_init - Initialize general software structures (struct igb_adapter)
3798  *  @adapter: board private structure to initialize
3799  *
3800  *  igb_sw_init initializes the Adapter private data structure.
3801  *  Fields are initialized based on PCI device information and
3802  *  OS network device settings (MTU size).
3803  **/
3804 static int igb_sw_init(struct igb_adapter *adapter)
3805 {
3806         struct e1000_hw *hw = &adapter->hw;
3807         struct net_device *netdev = adapter->netdev;
3808         struct pci_dev *pdev = adapter->pdev;
3809
3810         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3811
3812         /* set default ring sizes */
3813         adapter->tx_ring_count = IGB_DEFAULT_TXD;
3814         adapter->rx_ring_count = IGB_DEFAULT_RXD;
3815
3816         /* set default ITR values */
3817         adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3818         adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3819
3820         /* set default work limits */
3821         adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3822
3823         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
3824                                   VLAN_HLEN;
3825         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3826
3827         spin_lock_init(&adapter->nfc_lock);
3828         spin_lock_init(&adapter->stats64_lock);
3829 #ifdef CONFIG_PCI_IOV
3830         switch (hw->mac.type) {
3831         case e1000_82576:
3832         case e1000_i350:
3833                 if (max_vfs > 7) {
3834                         dev_warn(&pdev->dev,
3835                                  "Maximum of 7 VFs per PF, using max\n");
3836                         max_vfs = adapter->vfs_allocated_count = 7;
3837                 } else
3838                         adapter->vfs_allocated_count = max_vfs;
3839                 if (adapter->vfs_allocated_count)
3840                         dev_warn(&pdev->dev,
3841                                  "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3842                 break;
3843         default:
3844                 break;
3845         }
3846 #endif /* CONFIG_PCI_IOV */
3847
3848         /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3849         adapter->flags |= IGB_FLAG_HAS_MSIX;
3850
3851         adapter->mac_table = kcalloc(hw->mac.rar_entry_count,
3852                                      sizeof(struct igb_mac_addr),
3853                                      GFP_KERNEL);
3854         if (!adapter->mac_table)
3855                 return -ENOMEM;
3856
3857         igb_probe_vfs(adapter);
3858
3859         igb_init_queue_configuration(adapter);
3860
3861         /* Setup and initialize a copy of the hw vlan table array */
3862         adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3863                                        GFP_KERNEL);
3864         if (!adapter->shadow_vfta)
3865                 return -ENOMEM;
3866
3867         /* This call may decrease the number of queues */
3868         if (igb_init_interrupt_scheme(adapter, true)) {
3869                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3870                 return -ENOMEM;
3871         }
3872
3873         /* Explicitly disable IRQ since the NIC can be in any state. */
3874         igb_irq_disable(adapter);
3875
3876         if (hw->mac.type >= e1000_i350)
3877                 adapter->flags &= ~IGB_FLAG_DMAC;
3878
3879         set_bit(__IGB_DOWN, &adapter->state);
3880         return 0;
3881 }
3882
3883 /**
3884  *  igb_open - Called when a network interface is made active
3885  *  @netdev: network interface device structure
3886  *
3887  *  Returns 0 on success, negative value on failure
3888  *
3889  *  The open entry point is called when a network interface is made
3890  *  active by the system (IFF_UP).  At this point all resources needed
3891  *  for transmit and receive operations are allocated, the interrupt
3892  *  handler is registered with the OS, the watchdog timer is started,
3893  *  and the stack is notified that the interface is ready.
3894  **/
3895 static int __igb_open(struct net_device *netdev, bool resuming)
3896 {
3897         struct igb_adapter *adapter = netdev_priv(netdev);
3898         struct e1000_hw *hw = &adapter->hw;
3899         struct pci_dev *pdev = adapter->pdev;
3900         int err;
3901         int i;
3902
3903         /* disallow open during test */
3904         if (test_bit(__IGB_TESTING, &adapter->state)) {
3905                 WARN_ON(resuming);
3906                 return -EBUSY;
3907         }
3908
3909         if (!resuming)
3910                 pm_runtime_get_sync(&pdev->dev);
3911
3912         netif_carrier_off(netdev);
3913
3914         /* allocate transmit descriptors */
3915         err = igb_setup_all_tx_resources(adapter);
3916         if (err)
3917                 goto err_setup_tx;
3918
3919         /* allocate receive descriptors */
3920         err = igb_setup_all_rx_resources(adapter);
3921         if (err)
3922                 goto err_setup_rx;
3923
3924         igb_power_up_link(adapter);
3925
3926         /* before we allocate an interrupt, we must be ready to handle it.
3927          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3928          * as soon as we call pci_request_irq, so we have to setup our
3929          * clean_rx handler before we do so.
3930          */
3931         igb_configure(adapter);
3932
3933         err = igb_request_irq(adapter);
3934         if (err)
3935                 goto err_req_irq;
3936
3937         /* Notify the stack of the actual queue counts. */
3938         err = netif_set_real_num_tx_queues(adapter->netdev,
3939                                            adapter->num_tx_queues);
3940         if (err)
3941                 goto err_set_queues;
3942
3943         err = netif_set_real_num_rx_queues(adapter->netdev,
3944                                            adapter->num_rx_queues);
3945         if (err)
3946                 goto err_set_queues;
3947
3948         /* From here on the code is the same as igb_up() */
3949         clear_bit(__IGB_DOWN, &adapter->state);
3950
3951         for (i = 0; i < adapter->num_q_vectors; i++)
3952                 napi_enable(&(adapter->q_vector[i]->napi));
3953
3954         /* Clear any pending interrupts. */
3955         rd32(E1000_TSICR);
3956         rd32(E1000_ICR);
3957
3958         igb_irq_enable(adapter);
3959
3960         /* notify VFs that reset has been completed */
3961         if (adapter->vfs_allocated_count) {
3962                 u32 reg_data = rd32(E1000_CTRL_EXT);
3963
3964                 reg_data |= E1000_CTRL_EXT_PFRSTD;
3965                 wr32(E1000_CTRL_EXT, reg_data);
3966         }
3967
3968         netif_tx_start_all_queues(netdev);
3969
3970         if (!resuming)
3971                 pm_runtime_put(&pdev->dev);
3972
3973         /* start the watchdog. */
3974         hw->mac.get_link_status = 1;
3975         schedule_work(&adapter->watchdog_task);
3976
3977         return 0;
3978
3979 err_set_queues:
3980         igb_free_irq(adapter);
3981 err_req_irq:
3982         igb_release_hw_control(adapter);
3983         igb_power_down_link(adapter);
3984         igb_free_all_rx_resources(adapter);
3985 err_setup_rx:
3986         igb_free_all_tx_resources(adapter);
3987 err_setup_tx:
3988         igb_reset(adapter);
3989         if (!resuming)
3990                 pm_runtime_put(&pdev->dev);
3991
3992         return err;
3993 }
3994
3995 int igb_open(struct net_device *netdev)
3996 {
3997         return __igb_open(netdev, false);
3998 }
3999
4000 /**
4001  *  igb_close - Disables a network interface
4002  *  @netdev: network interface device structure
4003  *
4004  *  Returns 0, this is not allowed to fail
4005  *
4006  *  The close entry point is called when an interface is de-activated
4007  *  by the OS.  The hardware is still under the driver's control, but
4008  *  needs to be disabled.  A global MAC reset is issued to stop the
4009  *  hardware, and all transmit and receive resources are freed.
4010  **/
4011 static int __igb_close(struct net_device *netdev, bool suspending)
4012 {
4013         struct igb_adapter *adapter = netdev_priv(netdev);
4014         struct pci_dev *pdev = adapter->pdev;
4015
4016         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
4017
4018         if (!suspending)
4019                 pm_runtime_get_sync(&pdev->dev);
4020
4021         igb_down(adapter);
4022         igb_free_irq(adapter);
4023
4024         igb_free_all_tx_resources(adapter);
4025         igb_free_all_rx_resources(adapter);
4026
4027         if (!suspending)
4028                 pm_runtime_put_sync(&pdev->dev);
4029         return 0;
4030 }
4031
4032 int igb_close(struct net_device *netdev)
4033 {
4034         if (netif_device_present(netdev) || netdev->dismantle)
4035                 return __igb_close(netdev, false);
4036         return 0;
4037 }
4038
4039 /**
4040  *  igb_setup_tx_resources - allocate Tx resources (Descriptors)
4041  *  @tx_ring: tx descriptor ring (for a specific queue) to setup
4042  *
4043  *  Return 0 on success, negative on failure
4044  **/
4045 int igb_setup_tx_resources(struct igb_ring *tx_ring)
4046 {
4047         struct device *dev = tx_ring->dev;
4048         int size;
4049
4050         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
4051
4052         tx_ring->tx_buffer_info = vmalloc(size);
4053         if (!tx_ring->tx_buffer_info)
4054                 goto err;
4055
4056         /* round up to nearest 4K */
4057         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
4058         tx_ring->size = ALIGN(tx_ring->size, 4096);
4059
4060         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4061                                            &tx_ring->dma, GFP_KERNEL);
4062         if (!tx_ring->desc)
4063                 goto err;
4064
4065         tx_ring->next_to_use = 0;
4066         tx_ring->next_to_clean = 0;
4067
4068         return 0;
4069
4070 err:
4071         vfree(tx_ring->tx_buffer_info);
4072         tx_ring->tx_buffer_info = NULL;
4073         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4074         return -ENOMEM;
4075 }
4076
4077 /**
4078  *  igb_setup_all_tx_resources - wrapper to allocate Tx resources
4079  *                               (Descriptors) for all queues
4080  *  @adapter: board private structure
4081  *
4082  *  Return 0 on success, negative on failure
4083  **/
4084 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
4085 {
4086         struct pci_dev *pdev = adapter->pdev;
4087         int i, err = 0;
4088
4089         for (i = 0; i < adapter->num_tx_queues; i++) {
4090                 err = igb_setup_tx_resources(adapter->tx_ring[i]);
4091                 if (err) {
4092                         dev_err(&pdev->dev,
4093                                 "Allocation for Tx Queue %u failed\n", i);
4094                         for (i--; i >= 0; i--)
4095                                 igb_free_tx_resources(adapter->tx_ring[i]);
4096                         break;
4097                 }
4098         }
4099
4100         return err;
4101 }
4102
4103 /**
4104  *  igb_setup_tctl - configure the transmit control registers
4105  *  @adapter: Board private structure
4106  **/
4107 void igb_setup_tctl(struct igb_adapter *adapter)
4108 {
4109         struct e1000_hw *hw = &adapter->hw;
4110         u32 tctl;
4111
4112         /* disable queue 0 which is enabled by default on 82575 and 82576 */
4113         wr32(E1000_TXDCTL(0), 0);
4114
4115         /* Program the Transmit Control Register */
4116         tctl = rd32(E1000_TCTL);
4117         tctl &= ~E1000_TCTL_CT;
4118         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
4119                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4120
4121         igb_config_collision_dist(hw);
4122
4123         /* Enable transmits */
4124         tctl |= E1000_TCTL_EN;
4125
4126         wr32(E1000_TCTL, tctl);
4127 }
4128
4129 /**
4130  *  igb_configure_tx_ring - Configure transmit ring after Reset
4131  *  @adapter: board private structure
4132  *  @ring: tx ring to configure
4133  *
4134  *  Configure a transmit ring after a reset.
4135  **/
4136 void igb_configure_tx_ring(struct igb_adapter *adapter,
4137                            struct igb_ring *ring)
4138 {
4139         struct e1000_hw *hw = &adapter->hw;
4140         u32 txdctl = 0;
4141         u64 tdba = ring->dma;
4142         int reg_idx = ring->reg_idx;
4143
4144         wr32(E1000_TDLEN(reg_idx),
4145              ring->count * sizeof(union e1000_adv_tx_desc));
4146         wr32(E1000_TDBAL(reg_idx),
4147              tdba & 0x00000000ffffffffULL);
4148         wr32(E1000_TDBAH(reg_idx), tdba >> 32);
4149
4150         ring->tail = adapter->io_addr + E1000_TDT(reg_idx);
4151         wr32(E1000_TDH(reg_idx), 0);
4152         writel(0, ring->tail);
4153
4154         txdctl |= IGB_TX_PTHRESH;
4155         txdctl |= IGB_TX_HTHRESH << 8;
4156         txdctl |= IGB_TX_WTHRESH << 16;
4157
4158         /* reinitialize tx_buffer_info */
4159         memset(ring->tx_buffer_info, 0,
4160                sizeof(struct igb_tx_buffer) * ring->count);
4161
4162         txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
4163         wr32(E1000_TXDCTL(reg_idx), txdctl);
4164 }
4165
4166 /**
4167  *  igb_configure_tx - Configure transmit Unit after Reset
4168  *  @adapter: board private structure
4169  *
4170  *  Configure the Tx unit of the MAC after a reset.
4171  **/
4172 static void igb_configure_tx(struct igb_adapter *adapter)
4173 {
4174         struct e1000_hw *hw = &adapter->hw;
4175         int i;
4176
4177         /* disable the queues */
4178         for (i = 0; i < adapter->num_tx_queues; i++)
4179                 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0);
4180
4181         wrfl();
4182         usleep_range(10000, 20000);
4183
4184         for (i = 0; i < adapter->num_tx_queues; i++)
4185                 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
4186 }
4187
4188 /**
4189  *  igb_setup_rx_resources - allocate Rx resources (Descriptors)
4190  *  @rx_ring: Rx descriptor ring (for a specific queue) to setup
4191  *
4192  *  Returns 0 on success, negative on failure
4193  **/
4194 int igb_setup_rx_resources(struct igb_ring *rx_ring)
4195 {
4196         struct device *dev = rx_ring->dev;
4197         int size;
4198
4199         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
4200
4201         rx_ring->rx_buffer_info = vmalloc(size);
4202         if (!rx_ring->rx_buffer_info)
4203                 goto err;
4204
4205         /* Round up to nearest 4K */
4206         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
4207         rx_ring->size = ALIGN(rx_ring->size, 4096);
4208
4209         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4210                                            &rx_ring->dma, GFP_KERNEL);
4211         if (!rx_ring->desc)
4212                 goto err;
4213
4214         rx_ring->next_to_alloc = 0;
4215         rx_ring->next_to_clean = 0;
4216         rx_ring->next_to_use = 0;
4217
4218         return 0;
4219
4220 err:
4221         vfree(rx_ring->rx_buffer_info);
4222         rx_ring->rx_buffer_info = NULL;
4223         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4224         return -ENOMEM;
4225 }
4226
4227 /**
4228  *  igb_setup_all_rx_resources - wrapper to allocate Rx resources
4229  *                               (Descriptors) for all queues
4230  *  @adapter: board private structure
4231  *
4232  *  Return 0 on success, negative on failure
4233  **/
4234 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
4235 {
4236         struct pci_dev *pdev = adapter->pdev;
4237         int i, err = 0;
4238
4239         for (i = 0; i < adapter->num_rx_queues; i++) {
4240                 err = igb_setup_rx_resources(adapter->rx_ring[i]);
4241                 if (err) {
4242                         dev_err(&pdev->dev,
4243                                 "Allocation for Rx Queue %u failed\n", i);
4244                         for (i--; i >= 0; i--)
4245                                 igb_free_rx_resources(adapter->rx_ring[i]);
4246                         break;
4247                 }
4248         }
4249
4250         return err;
4251 }
4252
4253 /**
4254  *  igb_setup_mrqc - configure the multiple receive queue control registers
4255  *  @adapter: Board private structure
4256  **/
4257 static void igb_setup_mrqc(struct igb_adapter *adapter)
4258 {
4259         struct e1000_hw *hw = &adapter->hw;
4260         u32 mrqc, rxcsum;
4261         u32 j, num_rx_queues;
4262         u32 rss_key[10];
4263
4264         netdev_rss_key_fill(rss_key, sizeof(rss_key));
4265         for (j = 0; j < 10; j++)
4266                 wr32(E1000_RSSRK(j), rss_key[j]);
4267
4268         num_rx_queues = adapter->rss_queues;
4269
4270         switch (hw->mac.type) {
4271         case e1000_82576:
4272                 /* 82576 supports 2 RSS queues for SR-IOV */
4273                 if (adapter->vfs_allocated_count)
4274                         num_rx_queues = 2;
4275                 break;
4276         default:
4277                 break;
4278         }
4279
4280         if (adapter->rss_indir_tbl_init != num_rx_queues) {
4281                 for (j = 0; j < IGB_RETA_SIZE; j++)
4282                         adapter->rss_indir_tbl[j] =
4283                         (j * num_rx_queues) / IGB_RETA_SIZE;
4284                 adapter->rss_indir_tbl_init = num_rx_queues;
4285         }
4286         igb_write_rss_indir_tbl(adapter);
4287
4288         /* Disable raw packet checksumming so that RSS hash is placed in
4289          * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
4290          * offloads as they are enabled by default
4291          */
4292         rxcsum = rd32(E1000_RXCSUM);
4293         rxcsum |= E1000_RXCSUM_PCSD;
4294
4295         if (adapter->hw.mac.type >= e1000_82576)
4296                 /* Enable Receive Checksum Offload for SCTP */
4297                 rxcsum |= E1000_RXCSUM_CRCOFL;
4298
4299         /* Don't need to set TUOFL or IPOFL, they default to 1 */
4300         wr32(E1000_RXCSUM, rxcsum);
4301
4302         /* Generate RSS hash based on packet types, TCP/UDP
4303          * port numbers and/or IPv4/v6 src and dst addresses
4304          */
4305         mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
4306                E1000_MRQC_RSS_FIELD_IPV4_TCP |
4307                E1000_MRQC_RSS_FIELD_IPV6 |
4308                E1000_MRQC_RSS_FIELD_IPV6_TCP |
4309                E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
4310
4311         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
4312                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
4313         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
4314                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
4315
4316         /* If VMDq is enabled then we set the appropriate mode for that, else
4317          * we default to RSS so that an RSS hash is calculated per packet even
4318          * if we are only using one queue
4319          */
4320         if (adapter->vfs_allocated_count) {
4321                 if (hw->mac.type > e1000_82575) {
4322                         /* Set the default pool for the PF's first queue */
4323                         u32 vtctl = rd32(E1000_VT_CTL);
4324
4325                         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
4326                                    E1000_VT_CTL_DISABLE_DEF_POOL);
4327                         vtctl |= adapter->vfs_allocated_count <<
4328                                 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
4329                         wr32(E1000_VT_CTL, vtctl);
4330                 }
4331                 if (adapter->rss_queues > 1)
4332                         mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
4333                 else
4334                         mrqc |= E1000_MRQC_ENABLE_VMDQ;
4335         } else {
4336                 if (hw->mac.type != e1000_i211)
4337                         mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
4338         }
4339         igb_vmm_control(adapter);
4340
4341         wr32(E1000_MRQC, mrqc);
4342 }
4343
4344 /**
4345  *  igb_setup_rctl - configure the receive control registers
4346  *  @adapter: Board private structure
4347  **/
4348 void igb_setup_rctl(struct igb_adapter *adapter)
4349 {
4350         struct e1000_hw *hw = &adapter->hw;
4351         u32 rctl;
4352
4353         rctl = rd32(E1000_RCTL);
4354
4355         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4356         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
4357
4358         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
4359                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
4360
4361         /* enable stripping of CRC. It's unlikely this will break BMC
4362          * redirection as it did with e1000. Newer features require
4363          * that the HW strips the CRC.
4364          */
4365         rctl |= E1000_RCTL_SECRC;
4366
4367         /* disable store bad packets and clear size bits. */
4368         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
4369
4370         /* enable LPE to allow for reception of jumbo frames */
4371         rctl |= E1000_RCTL_LPE;
4372
4373         /* disable queue 0 to prevent tail write w/o re-config */
4374         wr32(E1000_RXDCTL(0), 0);
4375
4376         /* Attention!!!  For SR-IOV PF driver operations you must enable
4377          * queue drop for all VF and PF queues to prevent head of line blocking
4378          * if an un-trusted VF does not provide descriptors to hardware.
4379          */
4380         if (adapter->vfs_allocated_count) {
4381                 /* set all queue drop enable bits */
4382                 wr32(E1000_QDE, ALL_QUEUES);
4383         }
4384
4385         /* This is useful for sniffing bad packets. */
4386         if (adapter->netdev->features & NETIF_F_RXALL) {
4387                 /* UPE and MPE will be handled by normal PROMISC logic
4388                  * in e1000e_set_rx_mode
4389                  */
4390                 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
4391                          E1000_RCTL_BAM | /* RX All Bcast Pkts */
4392                          E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
4393
4394                 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
4395                           E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
4396                 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
4397                  * and that breaks VLANs.
4398                  */
4399         }
4400
4401         wr32(E1000_RCTL, rctl);
4402 }
4403
4404 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
4405                                    int vfn)
4406 {
4407         struct e1000_hw *hw = &adapter->hw;
4408         u32 vmolr;
4409
4410         if (size > MAX_JUMBO_FRAME_SIZE)
4411                 size = MAX_JUMBO_FRAME_SIZE;
4412
4413         vmolr = rd32(E1000_VMOLR(vfn));
4414         vmolr &= ~E1000_VMOLR_RLPML_MASK;
4415         vmolr |= size | E1000_VMOLR_LPE;
4416         wr32(E1000_VMOLR(vfn), vmolr);
4417
4418         return 0;
4419 }
4420
4421 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
4422                                          int vfn, bool enable)
4423 {
4424         struct e1000_hw *hw = &adapter->hw;
4425         u32 val, reg;
4426
4427         if (hw->mac.type < e1000_82576)
4428                 return;
4429
4430         if (hw->mac.type == e1000_i350)
4431                 reg = E1000_DVMOLR(vfn);
4432         else
4433                 reg = E1000_VMOLR(vfn);
4434
4435         val = rd32(reg);
4436         if (enable)
4437                 val |= E1000_VMOLR_STRVLAN;
4438         else
4439                 val &= ~(E1000_VMOLR_STRVLAN);
4440         wr32(reg, val);
4441 }
4442
4443 static inline void igb_set_vmolr(struct igb_adapter *adapter,
4444                                  int vfn, bool aupe)
4445 {
4446         struct e1000_hw *hw = &adapter->hw;
4447         u32 vmolr;
4448
4449         /* This register exists only on 82576 and newer so if we are older then
4450          * we should exit and do nothing
4451          */
4452         if (hw->mac.type < e1000_82576)
4453                 return;
4454
4455         vmolr = rd32(E1000_VMOLR(vfn));
4456         if (aupe)
4457                 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
4458         else
4459                 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
4460
4461         /* clear all bits that might not be set */
4462         vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
4463
4464         if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
4465                 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
4466         /* for VMDq only allow the VFs and pool 0 to accept broadcast and
4467          * multicast packets
4468          */
4469         if (vfn <= adapter->vfs_allocated_count)
4470                 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
4471
4472         wr32(E1000_VMOLR(vfn), vmolr);
4473 }
4474
4475 /**
4476  *  igb_configure_rx_ring - Configure a receive ring after Reset
4477  *  @adapter: board private structure
4478  *  @ring: receive ring to be configured
4479  *
4480  *  Configure the Rx unit of the MAC after a reset.
4481  **/
4482 void igb_configure_rx_ring(struct igb_adapter *adapter,
4483                            struct igb_ring *ring)
4484 {
4485         struct e1000_hw *hw = &adapter->hw;
4486         union e1000_adv_rx_desc *rx_desc;
4487         u64 rdba = ring->dma;
4488         int reg_idx = ring->reg_idx;
4489         u32 srrctl = 0, rxdctl = 0;
4490
4491         /* disable the queue */
4492         wr32(E1000_RXDCTL(reg_idx), 0);
4493
4494         /* Set DMA base address registers */
4495         wr32(E1000_RDBAL(reg_idx),
4496              rdba & 0x00000000ffffffffULL);
4497         wr32(E1000_RDBAH(reg_idx), rdba >> 32);
4498         wr32(E1000_RDLEN(reg_idx),
4499              ring->count * sizeof(union e1000_adv_rx_desc));
4500
4501         /* initialize head and tail */
4502         ring->tail = adapter->io_addr + E1000_RDT(reg_idx);
4503         wr32(E1000_RDH(reg_idx), 0);
4504         writel(0, ring->tail);
4505
4506         /* set descriptor configuration */
4507         srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
4508         if (ring_uses_large_buffer(ring))
4509                 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4510         else
4511                 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4512         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
4513         if (hw->mac.type >= e1000_82580)
4514                 srrctl |= E1000_SRRCTL_TIMESTAMP;
4515         /* Only set Drop Enable if we are supporting multiple queues */
4516         if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
4517                 srrctl |= E1000_SRRCTL_DROP_EN;
4518
4519         wr32(E1000_SRRCTL(reg_idx), srrctl);
4520
4521         /* set filtering for VMDQ pools */
4522         igb_set_vmolr(adapter, reg_idx & 0x7, true);
4523
4524         rxdctl |= IGB_RX_PTHRESH;
4525         rxdctl |= IGB_RX_HTHRESH << 8;
4526         rxdctl |= IGB_RX_WTHRESH << 16;
4527
4528         /* initialize rx_buffer_info */
4529         memset(ring->rx_buffer_info, 0,
4530                sizeof(struct igb_rx_buffer) * ring->count);
4531
4532         /* initialize Rx descriptor 0 */
4533         rx_desc = IGB_RX_DESC(ring, 0);
4534         rx_desc->wb.upper.length = 0;
4535
4536         /* enable receive descriptor fetching */
4537         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
4538         wr32(E1000_RXDCTL(reg_idx), rxdctl);
4539 }
4540
4541 static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
4542                                   struct igb_ring *rx_ring)
4543 {
4544         /* set build_skb and buffer size flags */
4545         clear_ring_build_skb_enabled(rx_ring);
4546         clear_ring_uses_large_buffer(rx_ring);
4547
4548         if (adapter->flags & IGB_FLAG_RX_LEGACY)
4549                 return;
4550
4551         set_ring_build_skb_enabled(rx_ring);
4552
4553 #if (PAGE_SIZE < 8192)
4554         if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
4555                 return;
4556
4557         set_ring_uses_large_buffer(rx_ring);
4558 #endif
4559 }
4560
4561 /**
4562  *  igb_configure_rx - Configure receive Unit after Reset
4563  *  @adapter: board private structure
4564  *
4565  *  Configure the Rx unit of the MAC after a reset.
4566  **/
4567 static void igb_configure_rx(struct igb_adapter *adapter)
4568 {
4569         int i;
4570
4571         /* set the correct pool for the PF default MAC address in entry 0 */
4572         igb_set_default_mac_filter(adapter);
4573
4574         /* Setup the HW Rx Head and Tail Descriptor Pointers and
4575          * the Base and Length of the Rx Descriptor Ring
4576          */
4577         for (i = 0; i < adapter->num_rx_queues; i++) {
4578                 struct igb_ring *rx_ring = adapter->rx_ring[i];
4579
4580                 igb_set_rx_buffer_len(adapter, rx_ring);
4581                 igb_configure_rx_ring(adapter, rx_ring);
4582         }
4583 }
4584
4585 /**
4586  *  igb_free_tx_resources - Free Tx Resources per Queue
4587  *  @tx_ring: Tx descriptor ring for a specific queue
4588  *
4589  *  Free all transmit software resources
4590  **/
4591 void igb_free_tx_resources(struct igb_ring *tx_ring)
4592 {
4593         igb_clean_tx_ring(tx_ring);
4594
4595         vfree(tx_ring->tx_buffer_info);
4596         tx_ring->tx_buffer_info = NULL;
4597
4598         /* if not set, then don't free */
4599         if (!tx_ring->desc)
4600                 return;
4601
4602         dma_free_coherent(tx_ring->dev, tx_ring->size,
4603                           tx_ring->desc, tx_ring->dma);
4604
4605         tx_ring->desc = NULL;
4606 }
4607
4608 /**
4609  *  igb_free_all_tx_resources - Free Tx Resources for All Queues
4610  *  @adapter: board private structure
4611  *
4612  *  Free all transmit software resources
4613  **/
4614 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
4615 {
4616         int i;
4617
4618         for (i = 0; i < adapter->num_tx_queues; i++)
4619                 if (adapter->tx_ring[i])
4620                         igb_free_tx_resources(adapter->tx_ring[i]);
4621 }
4622
4623 /**
4624  *  igb_clean_tx_ring - Free Tx Buffers
4625  *  @tx_ring: ring to be cleaned
4626  **/
4627 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
4628 {
4629         u16 i = tx_ring->next_to_clean;
4630         struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
4631
4632         while (i != tx_ring->next_to_use) {
4633                 union e1000_adv_tx_desc *eop_desc, *tx_desc;
4634
4635                 /* Free all the Tx ring sk_buffs */
4636                 dev_kfree_skb_any(tx_buffer->skb);
4637
4638                 /* unmap skb header data */
4639                 dma_unmap_single(tx_ring->dev,
4640                                  dma_unmap_addr(tx_buffer, dma),
4641                                  dma_unmap_len(tx_buffer, len),
4642                                  DMA_TO_DEVICE);
4643
4644                 /* check for eop_desc to determine the end of the packet */
4645                 eop_desc = tx_buffer->next_to_watch;
4646                 tx_desc = IGB_TX_DESC(tx_ring, i);
4647
4648                 /* unmap remaining buffers */
4649                 while (tx_desc != eop_desc) {
4650                         tx_buffer++;
4651                         tx_desc++;
4652                         i++;
4653                         if (unlikely(i == tx_ring->count)) {
4654                                 i = 0;
4655                                 tx_buffer = tx_ring->tx_buffer_info;
4656                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
4657                         }
4658
4659                         /* unmap any remaining paged data */
4660                         if (dma_unmap_len(tx_buffer, len))
4661                                 dma_unmap_page(tx_ring->dev,
4662                                                dma_unmap_addr(tx_buffer, dma),
4663                                                dma_unmap_len(tx_buffer, len),
4664                                                DMA_TO_DEVICE);
4665                 }
4666
4667                 /* move us one more past the eop_desc for start of next pkt */
4668                 tx_buffer++;
4669                 i++;
4670                 if (unlikely(i == tx_ring->count)) {
4671                         i = 0;
4672                         tx_buffer = tx_ring->tx_buffer_info;
4673                 }
4674         }
4675
4676         /* reset BQL for queue */
4677         netdev_tx_reset_queue(txring_txq(tx_ring));
4678
4679         /* reset next_to_use and next_to_clean */
4680         tx_ring->next_to_use = 0;
4681         tx_ring->next_to_clean = 0;
4682 }
4683
4684 /**
4685  *  igb_clean_all_tx_rings - Free Tx Buffers for all queues
4686  *  @adapter: board private structure
4687  **/
4688 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
4689 {
4690         int i;
4691
4692         for (i = 0; i < adapter->num_tx_queues; i++)
4693                 if (adapter->tx_ring[i])
4694                         igb_clean_tx_ring(adapter->tx_ring[i]);
4695 }
4696
4697 /**
4698  *  igb_free_rx_resources - Free Rx Resources
4699  *  @rx_ring: ring to clean the resources from
4700  *
4701  *  Free all receive software resources
4702  **/
4703 void igb_free_rx_resources(struct igb_ring *rx_ring)
4704 {
4705         igb_clean_rx_ring(rx_ring);
4706
4707         vfree(rx_ring->rx_buffer_info);
4708         rx_ring->rx_buffer_info = NULL;
4709
4710         /* if not set, then don't free */
4711         if (!rx_ring->desc)
4712                 return;
4713
4714         dma_free_coherent(rx_ring->dev, rx_ring->size,
4715                           rx_ring->desc, rx_ring->dma);
4716
4717         rx_ring->desc = NULL;
4718 }
4719
4720 /**
4721  *  igb_free_all_rx_resources - Free Rx Resources for All Queues
4722  *  @adapter: board private structure
4723  *
4724  *  Free all receive software resources
4725  **/
4726 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
4727 {
4728         int i;
4729
4730         for (i = 0; i < adapter->num_rx_queues; i++)
4731                 if (adapter->rx_ring[i])
4732                         igb_free_rx_resources(adapter->rx_ring[i]);
4733 }
4734
4735 /**
4736  *  igb_clean_rx_ring - Free Rx Buffers per Queue
4737  *  @rx_ring: ring to free buffers from
4738  **/
4739 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
4740 {
4741         u16 i = rx_ring->next_to_clean;
4742
4743         if (rx_ring->skb)
4744                 dev_kfree_skb(rx_ring->skb);
4745         rx_ring->skb = NULL;
4746
4747         /* Free all the Rx ring sk_buffs */
4748         while (i != rx_ring->next_to_alloc) {
4749                 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
4750
4751                 /* Invalidate cache lines that may have been written to by
4752                  * device so that we avoid corrupting memory.
4753                  */
4754                 dma_sync_single_range_for_cpu(rx_ring->dev,
4755                                               buffer_info->dma,
4756                                               buffer_info->page_offset,
4757                                               igb_rx_bufsz(rx_ring),
4758                                               DMA_FROM_DEVICE);
4759
4760                 /* free resources associated with mapping */
4761                 dma_unmap_page_attrs(rx_ring->dev,
4762                                      buffer_info->dma,
4763                                      igb_rx_pg_size(rx_ring),
4764                                      DMA_FROM_DEVICE,
4765                                      IGB_RX_DMA_ATTR);
4766                 __page_frag_cache_drain(buffer_info->page,
4767                                         buffer_info->pagecnt_bias);
4768
4769                 i++;
4770                 if (i == rx_ring->count)
4771                         i = 0;
4772         }
4773
4774         rx_ring->next_to_alloc = 0;
4775         rx_ring->next_to_clean = 0;
4776         rx_ring->next_to_use = 0;
4777 }
4778
4779 /**
4780  *  igb_clean_all_rx_rings - Free Rx Buffers for all queues
4781  *  @adapter: board private structure
4782  **/
4783 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
4784 {
4785         int i;
4786
4787         for (i = 0; i < adapter->num_rx_queues; i++)
4788                 if (adapter->rx_ring[i])
4789                         igb_clean_rx_ring(adapter->rx_ring[i]);
4790 }
4791
4792 /**
4793  *  igb_set_mac - Change the Ethernet Address of the NIC
4794  *  @netdev: network interface device structure
4795  *  @p: pointer to an address structure
4796  *
4797  *  Returns 0 on success, negative on failure
4798  **/
4799 static int igb_set_mac(struct net_device *netdev, void *p)
4800 {
4801         struct igb_adapter *adapter = netdev_priv(netdev);
4802         struct e1000_hw *hw = &adapter->hw;
4803         struct sockaddr *addr = p;
4804
4805         if (!is_valid_ether_addr(addr->sa_data))
4806                 return -EADDRNOTAVAIL;
4807
4808         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4809         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4810
4811         /* set the correct pool for the new PF MAC address in entry 0 */
4812         igb_set_default_mac_filter(adapter);
4813
4814         return 0;
4815 }
4816
4817 /**
4818  *  igb_write_mc_addr_list - write multicast addresses to MTA
4819  *  @netdev: network interface device structure
4820  *
4821  *  Writes multicast address list to the MTA hash table.
4822  *  Returns: -ENOMEM on failure
4823  *           0 on no addresses written
4824  *           X on writing X addresses to MTA
4825  **/
4826 static int igb_write_mc_addr_list(struct net_device *netdev)
4827 {
4828         struct igb_adapter *adapter = netdev_priv(netdev);
4829         struct e1000_hw *hw = &adapter->hw;
4830         struct netdev_hw_addr *ha;
4831         u8  *mta_list;
4832         int i;
4833
4834         if (netdev_mc_empty(netdev)) {
4835                 /* nothing to program, so clear mc list */
4836                 igb_update_mc_addr_list(hw, NULL, 0);
4837                 igb_restore_vf_multicasts(adapter);
4838                 return 0;
4839         }
4840
4841         mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
4842         if (!mta_list)
4843                 return -ENOMEM;
4844
4845         /* The shared function expects a packed array of only addresses. */
4846         i = 0;
4847         netdev_for_each_mc_addr(ha, netdev)
4848                 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
4849
4850         igb_update_mc_addr_list(hw, mta_list, i);
4851         kfree(mta_list);
4852
4853         return netdev_mc_count(netdev);
4854 }
4855
4856 static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
4857 {
4858         struct e1000_hw *hw = &adapter->hw;
4859         u32 i, pf_id;
4860
4861         switch (hw->mac.type) {
4862         case e1000_i210:
4863         case e1000_i211:
4864         case e1000_i350:
4865                 /* VLAN filtering needed for VLAN prio filter */
4866                 if (adapter->netdev->features & NETIF_F_NTUPLE)
4867                         break;
4868                 /* fall through */
4869         case e1000_82576:
4870         case e1000_82580:
4871         case e1000_i354:
4872                 /* VLAN filtering needed for pool filtering */
4873                 if (adapter->vfs_allocated_count)
4874                         break;
4875                 /* fall through */
4876         default:
4877                 return 1;
4878         }
4879
4880         /* We are already in VLAN promisc, nothing to do */
4881         if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
4882                 return 0;
4883
4884         if (!adapter->vfs_allocated_count)
4885                 goto set_vfta;
4886
4887         /* Add PF to all active pools */
4888         pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4889
4890         for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4891                 u32 vlvf = rd32(E1000_VLVF(i));
4892
4893                 vlvf |= BIT(pf_id);
4894                 wr32(E1000_VLVF(i), vlvf);
4895         }
4896
4897 set_vfta:
4898         /* Set all bits in the VLAN filter table array */
4899         for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
4900                 hw->mac.ops.write_vfta(hw, i, ~0U);
4901
4902         /* Set flag so we don't redo unnecessary work */
4903         adapter->flags |= IGB_FLAG_VLAN_PROMISC;
4904
4905         return 0;
4906 }
4907
4908 #define VFTA_BLOCK_SIZE 8
4909 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4910 {
4911         struct e1000_hw *hw = &adapter->hw;
4912         u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4913         u32 vid_start = vfta_offset * 32;
4914         u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4915         u32 i, vid, word, bits, pf_id;
4916
4917         /* guarantee that we don't scrub out management VLAN */
4918         vid = adapter->mng_vlan_id;
4919         if (vid >= vid_start && vid < vid_end)
4920                 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4921
4922         if (!adapter->vfs_allocated_count)
4923                 goto set_vfta;
4924
4925         pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4926
4927         for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4928                 u32 vlvf = rd32(E1000_VLVF(i));
4929
4930                 /* pull VLAN ID from VLVF */
4931                 vid = vlvf & VLAN_VID_MASK;
4932
4933                 /* only concern ourselves with a certain range */
4934                 if (vid < vid_start || vid >= vid_end)
4935                         continue;
4936
4937                 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4938                         /* record VLAN ID in VFTA */
4939                         vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4940
4941                         /* if PF is part of this then continue */
4942                         if (test_bit(vid, adapter->active_vlans))
4943                                 continue;
4944                 }
4945
4946                 /* remove PF from the pool */
4947                 bits = ~BIT(pf_id);
4948                 bits &= rd32(E1000_VLVF(i));
4949                 wr32(E1000_VLVF(i), bits);
4950         }
4951
4952 set_vfta:
4953         /* extract values from active_vlans and write back to VFTA */
4954         for (i = VFTA_BLOCK_SIZE; i--;) {
4955                 vid = (vfta_offset + i) * 32;
4956                 word = vid / BITS_PER_LONG;
4957                 bits = vid % BITS_PER_LONG;
4958
4959                 vfta[i] |= adapter->active_vlans[word] >> bits;
4960
4961                 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
4962         }
4963 }
4964
4965 static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
4966 {
4967         u32 i;
4968
4969         /* We are not in VLAN promisc, nothing to do */
4970         if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
4971                 return;
4972
4973         /* Set flag so we don't redo unnecessary work */
4974         adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
4975
4976         for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
4977                 igb_scrub_vfta(adapter, i);
4978 }
4979
4980 /**
4981  *  igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4982  *  @netdev: network interface device structure
4983  *
4984  *  The set_rx_mode entry point is called whenever the unicast or multicast
4985  *  address lists or the network interface flags are updated.  This routine is
4986  *  responsible for configuring the hardware for proper unicast, multicast,
4987  *  promiscuous mode, and all-multi behavior.
4988  **/
4989 static void igb_set_rx_mode(struct net_device *netdev)
4990 {
4991         struct igb_adapter *adapter = netdev_priv(netdev);
4992         struct e1000_hw *hw = &adapter->hw;
4993         unsigned int vfn = adapter->vfs_allocated_count;
4994         u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
4995         int count;
4996
4997         /* Check for Promiscuous and All Multicast modes */
4998         if (netdev->flags & IFF_PROMISC) {
4999                 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
5000                 vmolr |= E1000_VMOLR_MPME;
5001
5002                 /* enable use of UTA filter to force packets to default pool */
5003                 if (hw->mac.type == e1000_82576)
5004                         vmolr |= E1000_VMOLR_ROPE;
5005         } else {
5006                 if (netdev->flags & IFF_ALLMULTI) {
5007                         rctl |= E1000_RCTL_MPE;
5008                         vmolr |= E1000_VMOLR_MPME;
5009                 } else {
5010                         /* Write addresses to the MTA, if the attempt fails
5011                          * then we should just turn on promiscuous mode so
5012                          * that we can at least receive multicast traffic
5013                          */
5014                         count = igb_write_mc_addr_list(netdev);
5015                         if (count < 0) {
5016                                 rctl |= E1000_RCTL_MPE;
5017                                 vmolr |= E1000_VMOLR_MPME;
5018                         } else if (count) {
5019                                 vmolr |= E1000_VMOLR_ROMPE;
5020                         }
5021                 }
5022         }
5023
5024         /* Write addresses to available RAR registers, if there is not
5025          * sufficient space to store all the addresses then enable
5026          * unicast promiscuous mode
5027          */
5028         if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) {
5029                 rctl |= E1000_RCTL_UPE;
5030                 vmolr |= E1000_VMOLR_ROPE;
5031         }
5032
5033         /* enable VLAN filtering by default */
5034         rctl |= E1000_RCTL_VFE;
5035
5036         /* disable VLAN filtering for modes that require it */
5037         if ((netdev->flags & IFF_PROMISC) ||
5038             (netdev->features & NETIF_F_RXALL)) {
5039                 /* if we fail to set all rules then just clear VFE */
5040                 if (igb_vlan_promisc_enable(adapter))
5041                         rctl &= ~E1000_RCTL_VFE;
5042         } else {
5043                 igb_vlan_promisc_disable(adapter);
5044         }
5045
5046         /* update state of unicast, multicast, and VLAN filtering modes */
5047         rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
5048                                      E1000_RCTL_VFE);
5049         wr32(E1000_RCTL, rctl);
5050
5051 #if (PAGE_SIZE < 8192)
5052         if (!adapter->vfs_allocated_count) {
5053                 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5054                         rlpml = IGB_MAX_FRAME_BUILD_SKB;
5055         }
5056 #endif
5057         wr32(E1000_RLPML, rlpml);
5058
5059         /* In order to support SR-IOV and eventually VMDq it is necessary to set
5060          * the VMOLR to enable the appropriate modes.  Without this workaround
5061          * we will have issues with VLAN tag stripping not being done for frames
5062          * that are only arriving because we are the default pool
5063          */
5064         if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
5065                 return;
5066
5067         /* set UTA to appropriate mode */
5068         igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
5069
5070         vmolr |= rd32(E1000_VMOLR(vfn)) &
5071                  ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
5072
5073         /* enable Rx jumbo frames, restrict as needed to support build_skb */
5074         vmolr &= ~E1000_VMOLR_RLPML_MASK;
5075 #if (PAGE_SIZE < 8192)
5076         if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5077                 vmolr |= IGB_MAX_FRAME_BUILD_SKB;
5078         else
5079 #endif
5080                 vmolr |= MAX_JUMBO_FRAME_SIZE;
5081         vmolr |= E1000_VMOLR_LPE;
5082
5083         wr32(E1000_VMOLR(vfn), vmolr);
5084
5085         igb_restore_vf_multicasts(adapter);
5086 }
5087
5088 static void igb_check_wvbr(struct igb_adapter *adapter)
5089 {
5090         struct e1000_hw *hw = &adapter->hw;
5091         u32 wvbr = 0;
5092
5093         switch (hw->mac.type) {
5094         case e1000_82576:
5095         case e1000_i350:
5096                 wvbr = rd32(E1000_WVBR);
5097                 if (!wvbr)
5098                         return;
5099                 break;
5100         default:
5101                 break;
5102         }
5103
5104         adapter->wvbr |= wvbr;
5105 }
5106
5107 #define IGB_STAGGERED_QUEUE_OFFSET 8
5108
5109 static void igb_spoof_check(struct igb_adapter *adapter)
5110 {
5111         int j;
5112
5113         if (!adapter->wvbr)
5114                 return;
5115
5116         for (j = 0; j < adapter->vfs_allocated_count; j++) {
5117                 if (adapter->wvbr & BIT(j) ||
5118                     adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
5119                         dev_warn(&adapter->pdev->dev,
5120                                 "Spoof event(s) detected on VF %d\n", j);
5121                         adapter->wvbr &=
5122                                 ~(BIT(j) |
5123                                   BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
5124                 }
5125         }
5126 }
5127
5128 /* Need to wait a few seconds after link up to get diagnostic information from
5129  * the phy
5130  */
5131 static void igb_update_phy_info(struct timer_list *t)
5132 {
5133         struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer);
5134         igb_get_phy_info(&adapter->hw);
5135 }
5136
5137 /**
5138  *  igb_has_link - check shared code for link and determine up/down
5139  *  @adapter: pointer to driver private info
5140  **/
5141 bool igb_has_link(struct igb_adapter *adapter)
5142 {
5143         struct e1000_hw *hw = &adapter->hw;
5144         bool link_active = false;
5145
5146         /* get_link_status is set on LSC (link status) interrupt or
5147          * rx sequence error interrupt.  get_link_status will stay
5148          * false until the e1000_check_for_link establishes link
5149          * for copper adapters ONLY
5150          */
5151         switch (hw->phy.media_type) {
5152         case e1000_media_type_copper:
5153                 if (!hw->mac.get_link_status)
5154                         return true;
5155                 /* fall through */
5156         case e1000_media_type_internal_serdes:
5157                 hw->mac.ops.check_for_link(hw);
5158                 link_active = !hw->mac.get_link_status;
5159                 break;
5160         default:
5161         case e1000_media_type_unknown:
5162                 break;
5163         }
5164
5165         if (((hw->mac.type == e1000_i210) ||
5166              (hw->mac.type == e1000_i211)) &&
5167              (hw->phy.id == I210_I_PHY_ID)) {
5168                 if (!netif_carrier_ok(adapter->netdev)) {
5169                         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5170                 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
5171                         adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
5172                         adapter->link_check_timeout = jiffies;
5173                 }
5174         }
5175
5176         return link_active;
5177 }
5178
5179 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
5180 {
5181         bool ret = false;
5182         u32 ctrl_ext, thstat;
5183
5184         /* check for thermal sensor event on i350 copper only */
5185         if (hw->mac.type == e1000_i350) {
5186                 thstat = rd32(E1000_THSTAT);
5187                 ctrl_ext = rd32(E1000_CTRL_EXT);
5188
5189                 if ((hw->phy.media_type == e1000_media_type_copper) &&
5190                     !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
5191                         ret = !!(thstat & event);
5192         }
5193
5194         return ret;
5195 }
5196
5197 /**
5198  *  igb_check_lvmmc - check for malformed packets received
5199  *  and indicated in LVMMC register
5200  *  @adapter: pointer to adapter
5201  **/
5202 static void igb_check_lvmmc(struct igb_adapter *adapter)
5203 {
5204         struct e1000_hw *hw = &adapter->hw;
5205         u32 lvmmc;
5206
5207         lvmmc = rd32(E1000_LVMMC);
5208         if (lvmmc) {
5209                 if (unlikely(net_ratelimit())) {
5210                         netdev_warn(adapter->netdev,
5211                                     "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
5212                                     lvmmc);
5213                 }
5214         }
5215 }
5216
5217 /**
5218  *  igb_watchdog - Timer Call-back
5219  *  @data: pointer to adapter cast into an unsigned long
5220  **/
5221 static void igb_watchdog(struct timer_list *t)
5222 {
5223         struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5224         /* Do the rest outside of interrupt context */
5225         schedule_work(&adapter->watchdog_task);
5226 }
5227
5228 static void igb_watchdog_task(struct work_struct *work)
5229 {
5230         struct igb_adapter *adapter = container_of(work,
5231                                                    struct igb_adapter,
5232                                                    watchdog_task);
5233         struct e1000_hw *hw = &adapter->hw;
5234         struct e1000_phy_info *phy = &hw->phy;
5235         struct net_device *netdev = adapter->netdev;
5236         u32 link;
5237         int i;
5238         u32 connsw;
5239         u16 phy_data, retry_count = 20;
5240
5241         link = igb_has_link(adapter);
5242
5243         if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
5244                 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
5245                         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5246                 else
5247                         link = false;
5248         }
5249
5250         /* Force link down if we have fiber to swap to */
5251         if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5252                 if (hw->phy.media_type == e1000_media_type_copper) {
5253                         connsw = rd32(E1000_CONNSW);
5254                         if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
5255                                 link = 0;
5256                 }
5257         }
5258         if (link) {
5259                 /* Perform a reset if the media type changed. */
5260                 if (hw->dev_spec._82575.media_changed) {
5261                         hw->dev_spec._82575.media_changed = false;
5262                         adapter->flags |= IGB_FLAG_MEDIA_RESET;
5263                         igb_reset(adapter);
5264                 }
5265                 /* Cancel scheduled suspend requests. */
5266                 pm_runtime_resume(netdev->dev.parent);
5267
5268                 if (!netif_carrier_ok(netdev)) {
5269                         u32 ctrl;
5270
5271                         hw->mac.ops.get_speed_and_duplex(hw,
5272                                                          &adapter->link_speed,
5273                                                          &adapter->link_duplex);
5274
5275                         ctrl = rd32(E1000_CTRL);
5276                         /* Links status message must follow this format */
5277                         netdev_info(netdev,
5278                                "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5279                                netdev->name,
5280                                adapter->link_speed,
5281                                adapter->link_duplex == FULL_DUPLEX ?
5282                                "Full" : "Half",
5283                                (ctrl & E1000_CTRL_TFCE) &&
5284                                (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
5285                                (ctrl & E1000_CTRL_RFCE) ?  "RX" :
5286                                (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
5287
5288                         /* disable EEE if enabled */
5289                         if ((adapter->flags & IGB_FLAG_EEE) &&
5290                                 (adapter->link_duplex == HALF_DUPLEX)) {
5291                                 dev_info(&adapter->pdev->dev,
5292                                 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
5293                                 adapter->hw.dev_spec._82575.eee_disable = true;
5294                                 adapter->flags &= ~IGB_FLAG_EEE;
5295                         }
5296
5297                         /* check if SmartSpeed worked */
5298                         igb_check_downshift(hw);
5299                         if (phy->speed_downgraded)
5300                                 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
5301
5302                         /* check for thermal sensor event */
5303                         if (igb_thermal_sensor_event(hw,
5304                             E1000_THSTAT_LINK_THROTTLE))
5305                                 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
5306
5307                         /* adjust timeout factor according to speed/duplex */
5308                         adapter->tx_timeout_factor = 1;
5309                         switch (adapter->link_speed) {
5310                         case SPEED_10:
5311                                 adapter->tx_timeout_factor = 14;
5312                                 break;
5313                         case SPEED_100:
5314                                 /* maybe add some timeout factor ? */
5315                                 break;
5316                         }
5317
5318                         if (adapter->link_speed != SPEED_1000)
5319                                 goto no_wait;
5320
5321                         /* wait for Remote receiver status OK */
5322 retry_read_status:
5323                         if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
5324                                               &phy_data)) {
5325                                 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
5326                                     retry_count) {
5327                                         msleep(100);
5328                                         retry_count--;
5329                                         goto retry_read_status;
5330                                 } else if (!retry_count) {
5331                                         dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
5332                                 }
5333                         } else {
5334                                 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
5335                         }
5336 no_wait:
5337                         netif_carrier_on(netdev);
5338
5339                         igb_ping_all_vfs(adapter);
5340                         igb_check_vf_rate_limit(adapter);
5341
5342                         /* link state has changed, schedule phy info update */
5343                         if (!test_bit(__IGB_DOWN, &adapter->state))
5344                                 mod_timer(&adapter->phy_info_timer,
5345                                           round_jiffies(jiffies + 2 * HZ));
5346                 }
5347         } else {
5348                 if (netif_carrier_ok(netdev)) {
5349                         adapter->link_speed = 0;
5350                         adapter->link_duplex = 0;
5351
5352                         /* check for thermal sensor event */
5353                         if (igb_thermal_sensor_event(hw,
5354                             E1000_THSTAT_PWR_DOWN)) {
5355                                 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
5356                         }
5357
5358                         /* Links status message must follow this format */
5359                         netdev_info(netdev, "igb: %s NIC Link is Down\n",
5360                                netdev->name);
5361                         netif_carrier_off(netdev);
5362
5363                         igb_ping_all_vfs(adapter);
5364
5365                         /* link state has changed, schedule phy info update */
5366                         if (!test_bit(__IGB_DOWN, &adapter->state))
5367                                 mod_timer(&adapter->phy_info_timer,
5368                                           round_jiffies(jiffies + 2 * HZ));
5369
5370                         /* link is down, time to check for alternate media */
5371                         if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5372                                 igb_check_swap_media(adapter);
5373                                 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5374                                         schedule_work(&adapter->reset_task);
5375                                         /* return immediately */
5376                                         return;
5377                                 }
5378                         }
5379                         pm_schedule_suspend(netdev->dev.parent,
5380                                             MSEC_PER_SEC * 5);
5381
5382                 /* also check for alternate media here */
5383                 } else if (!netif_carrier_ok(netdev) &&
5384                            (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
5385                         igb_check_swap_media(adapter);
5386                         if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5387                                 schedule_work(&adapter->reset_task);
5388                                 /* return immediately */
5389                                 return;
5390                         }
5391                 }
5392         }
5393
5394         spin_lock(&adapter->stats64_lock);
5395         igb_update_stats(adapter);
5396         spin_unlock(&adapter->stats64_lock);
5397
5398         for (i = 0; i < adapter->num_tx_queues; i++) {
5399                 struct igb_ring *tx_ring = adapter->tx_ring[i];
5400                 if (!netif_carrier_ok(netdev)) {
5401                         /* We've lost link, so the controller stops DMA,
5402                          * but we've got queued Tx work that's never going
5403                          * to get done, so reset controller to flush Tx.
5404                          * (Do the reset outside of interrupt context).
5405                          */
5406                         if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
5407                                 adapter->tx_timeout_count++;
5408                                 schedule_work(&adapter->reset_task);
5409                                 /* return immediately since reset is imminent */
5410                                 return;
5411                         }
5412                 }
5413
5414                 /* Force detection of hung controller every watchdog period */
5415                 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5416         }
5417
5418         /* Cause software interrupt to ensure Rx ring is cleaned */
5419         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
5420                 u32 eics = 0;
5421
5422                 for (i = 0; i < adapter->num_q_vectors; i++)
5423                         eics |= adapter->q_vector[i]->eims_value;
5424                 wr32(E1000_EICS, eics);
5425         } else {
5426                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
5427         }
5428
5429         igb_spoof_check(adapter);
5430         igb_ptp_rx_hang(adapter);
5431         igb_ptp_tx_hang(adapter);
5432
5433         /* Check LVMMC register on i350/i354 only */
5434         if ((adapter->hw.mac.type == e1000_i350) ||
5435             (adapter->hw.mac.type == e1000_i354))
5436                 igb_check_lvmmc(adapter);
5437
5438         /* Reset the timer */
5439         if (!test_bit(__IGB_DOWN, &adapter->state)) {
5440                 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
5441                         mod_timer(&adapter->watchdog_timer,
5442                                   round_jiffies(jiffies +  HZ));
5443                 else
5444                         mod_timer(&adapter->watchdog_timer,
5445                                   round_jiffies(jiffies + 2 * HZ));
5446         }
5447 }
5448
5449 enum latency_range {
5450         lowest_latency = 0,
5451         low_latency = 1,
5452         bulk_latency = 2,
5453         latency_invalid = 255
5454 };
5455
5456 /**
5457  *  igb_update_ring_itr - update the dynamic ITR value based on packet size
5458  *  @q_vector: pointer to q_vector
5459  *
5460  *  Stores a new ITR value based on strictly on packet size.  This
5461  *  algorithm is less sophisticated than that used in igb_update_itr,
5462  *  due to the difficulty of synchronizing statistics across multiple
5463  *  receive rings.  The divisors and thresholds used by this function
5464  *  were determined based on theoretical maximum wire speed and testing
5465  *  data, in order to minimize response time while increasing bulk
5466  *  throughput.
5467  *  This functionality is controlled by ethtool's coalescing settings.
5468  *  NOTE:  This function is called only when operating in a multiqueue
5469  *         receive environment.
5470  **/
5471 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
5472 {
5473         int new_val = q_vector->itr_val;
5474         int avg_wire_size = 0;
5475         struct igb_adapter *adapter = q_vector->adapter;
5476         unsigned int packets;
5477
5478         /* For non-gigabit speeds, just fix the interrupt rate at 4000
5479          * ints/sec - ITR timer value of 120 ticks.
5480          */
5481         if (adapter->link_speed != SPEED_1000) {
5482                 new_val = IGB_4K_ITR;
5483                 goto set_itr_val;
5484         }
5485
5486         packets = q_vector->rx.total_packets;
5487         if (packets)
5488                 avg_wire_size = q_vector->rx.total_bytes / packets;
5489
5490         packets = q_vector->tx.total_packets;
5491         if (packets)
5492                 avg_wire_size = max_t(u32, avg_wire_size,
5493                                       q_vector->tx.total_bytes / packets);
5494
5495         /* if avg_wire_size isn't set no work was done */
5496         if (!avg_wire_size)
5497                 goto clear_counts;
5498
5499         /* Add 24 bytes to size to account for CRC, preamble, and gap */
5500         avg_wire_size += 24;
5501
5502         /* Don't starve jumbo frames */
5503         avg_wire_size = min(avg_wire_size, 3000);
5504
5505         /* Give a little boost to mid-size frames */
5506         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
5507                 new_val = avg_wire_size / 3;
5508         else
5509                 new_val = avg_wire_size / 2;
5510
5511         /* conservative mode (itr 3) eliminates the lowest_latency setting */
5512         if (new_val < IGB_20K_ITR &&
5513             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5514              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5515                 new_val = IGB_20K_ITR;
5516
5517 set_itr_val:
5518         if (new_val != q_vector->itr_val) {
5519                 q_vector->itr_val = new_val;
5520                 q_vector->set_itr = 1;
5521         }
5522 clear_counts:
5523         q_vector->rx.total_bytes = 0;
5524         q_vector->rx.total_packets = 0;
5525         q_vector->tx.total_bytes = 0;
5526         q_vector->tx.total_packets = 0;
5527 }
5528
5529 /**
5530  *  igb_update_itr - update the dynamic ITR value based on statistics
5531  *  @q_vector: pointer to q_vector
5532  *  @ring_container: ring info to update the itr for
5533  *
5534  *  Stores a new ITR value based on packets and byte
5535  *  counts during the last interrupt.  The advantage of per interrupt
5536  *  computation is faster updates and more accurate ITR for the current
5537  *  traffic pattern.  Constants in this function were computed
5538  *  based on theoretical maximum wire speed and thresholds were set based
5539  *  on testing data as well as attempting to minimize response time
5540  *  while increasing bulk throughput.
5541  *  This functionality is controlled by ethtool's coalescing settings.
5542  *  NOTE:  These calculations are only valid when operating in a single-
5543  *         queue environment.
5544  **/
5545 static void igb_update_itr(struct igb_q_vector *q_vector,
5546                            struct igb_ring_container *ring_container)
5547 {
5548         unsigned int packets = ring_container->total_packets;
5549         unsigned int bytes = ring_container->total_bytes;
5550         u8 itrval = ring_container->itr;
5551
5552         /* no packets, exit with status unchanged */
5553         if (packets == 0)
5554                 return;
5555
5556         switch (itrval) {
5557         case lowest_latency:
5558                 /* handle TSO and jumbo frames */
5559                 if (bytes/packets > 8000)
5560                         itrval = bulk_latency;
5561                 else if ((packets < 5) && (bytes > 512))
5562                         itrval = low_latency;
5563                 break;
5564         case low_latency:  /* 50 usec aka 20000 ints/s */
5565                 if (bytes > 10000) {
5566                         /* this if handles the TSO accounting */
5567                         if (bytes/packets > 8000)
5568                                 itrval = bulk_latency;
5569                         else if ((packets < 10) || ((bytes/packets) > 1200))
5570                                 itrval = bulk_latency;
5571                         else if ((packets > 35))
5572                                 itrval = lowest_latency;
5573                 } else if (bytes/packets > 2000) {
5574                         itrval = bulk_latency;
5575                 } else if (packets <= 2 && bytes < 512) {
5576                         itrval = lowest_latency;
5577                 }
5578                 break;
5579         case bulk_latency: /* 250 usec aka 4000 ints/s */
5580                 if (bytes > 25000) {
5581                         if (packets > 35)
5582                                 itrval = low_latency;
5583                 } else if (bytes < 1500) {
5584                         itrval = low_latency;
5585                 }
5586                 break;
5587         }
5588
5589         /* clear work counters since we have the values we need */
5590         ring_container->total_bytes = 0;
5591         ring_container->total_packets = 0;
5592
5593         /* write updated itr to ring container */
5594         ring_container->itr = itrval;
5595 }
5596
5597 static void igb_set_itr(struct igb_q_vector *q_vector)
5598 {
5599         struct igb_adapter *adapter = q_vector->adapter;
5600         u32 new_itr = q_vector->itr_val;
5601         u8 current_itr = 0;
5602
5603         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
5604         if (adapter->link_speed != SPEED_1000) {
5605                 current_itr = 0;
5606                 new_itr = IGB_4K_ITR;
5607                 goto set_itr_now;
5608         }
5609
5610         igb_update_itr(q_vector, &q_vector->tx);
5611         igb_update_itr(q_vector, &q_vector->rx);
5612
5613         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
5614
5615         /* conservative mode (itr 3) eliminates the lowest_latency setting */
5616         if (current_itr == lowest_latency &&
5617             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5618              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5619                 current_itr = low_latency;
5620
5621         switch (current_itr) {
5622         /* counts and packets in update_itr are dependent on these numbers */
5623         case lowest_latency:
5624                 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
5625                 break;
5626         case low_latency:
5627                 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
5628                 break;
5629         case bulk_latency:
5630                 new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
5631                 break;
5632         default:
5633                 break;
5634         }
5635
5636 set_itr_now:
5637         if (new_itr != q_vector->itr_val) {
5638                 /* this attempts to bias the interrupt rate towards Bulk
5639                  * by adding intermediate steps when interrupt rate is
5640                  * increasing
5641                  */
5642                 new_itr = new_itr > q_vector->itr_val ?
5643                           max((new_itr * q_vector->itr_val) /
5644                           (new_itr + (q_vector->itr_val >> 2)),
5645                           new_itr) : new_itr;
5646                 /* Don't write the value here; it resets the adapter's
5647                  * internal timer, and causes us to delay far longer than
5648                  * we should between interrupts.  Instead, we write the ITR
5649                  * value at the beginning of the next interrupt so the timing
5650                  * ends up being correct.
5651                  */
5652                 q_vector->itr_val = new_itr;
5653                 q_vector->set_itr = 1;
5654         }
5655 }
5656
5657 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring,
5658                             struct igb_tx_buffer *first,
5659                             u32 vlan_macip_lens, u32 type_tucmd,
5660                             u32 mss_l4len_idx)
5661 {
5662         struct e1000_adv_tx_context_desc *context_desc;
5663         u16 i = tx_ring->next_to_use;
5664         struct timespec64 ts;
5665
5666         context_desc = IGB_TX_CTXTDESC(tx_ring, i);
5667
5668         i++;
5669         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
5670
5671         /* set bits to identify this as an advanced context descriptor */
5672         type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
5673
5674         /* For 82575, context index must be unique per ring. */
5675         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5676                 mss_l4len_idx |= tx_ring->reg_idx << 4;
5677
5678         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
5679         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
5680         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
5681
5682         /* We assume there is always a valid tx time available. Invalid times
5683          * should have been handled by the upper layers.
5684          */
5685         if (tx_ring->launchtime_enable) {
5686                 ts = ns_to_timespec64(first->skb->tstamp);
5687                 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32);
5688         } else {
5689                 context_desc->seqnum_seed = 0;
5690         }
5691 }
5692
5693 static int igb_tso(struct igb_ring *tx_ring,
5694                    struct igb_tx_buffer *first,
5695                    u8 *hdr_len)
5696 {
5697         u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
5698         struct sk_buff *skb = first->skb;
5699         union {
5700                 struct iphdr *v4;
5701                 struct ipv6hdr *v6;
5702                 unsigned char *hdr;
5703         } ip;
5704         union {
5705                 struct tcphdr *tcp;
5706                 unsigned char *hdr;
5707         } l4;
5708         u32 paylen, l4_offset;
5709         int err;
5710
5711         if (skb->ip_summed != CHECKSUM_PARTIAL)
5712                 return 0;
5713
5714         if (!skb_is_gso(skb))
5715                 return 0;
5716
5717         err = skb_cow_head(skb, 0);
5718         if (err < 0)
5719                 return err;
5720
5721         ip.hdr = skb_network_header(skb);
5722         l4.hdr = skb_checksum_start(skb);
5723
5724         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5725         type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
5726
5727         /* initialize outer IP header fields */
5728         if (ip.v4->version == 4) {
5729                 unsigned char *csum_start = skb_checksum_start(skb);
5730                 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
5731
5732                 /* IP header will have to cancel out any data that
5733                  * is not a part of the outer IP header
5734                  */
5735                 ip.v4->check = csum_fold(csum_partial(trans_start,
5736                                                       csum_start - trans_start,
5737                                                       0));
5738                 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
5739
5740                 ip.v4->tot_len = 0;
5741                 first->tx_flags |= IGB_TX_FLAGS_TSO |
5742                                    IGB_TX_FLAGS_CSUM |
5743                                    IGB_TX_FLAGS_IPV4;
5744         } else {
5745                 ip.v6->payload_len = 0;
5746                 first->tx_flags |= IGB_TX_FLAGS_TSO |
5747                                    IGB_TX_FLAGS_CSUM;
5748         }
5749
5750         /* determine offset of inner transport header */
5751         l4_offset = l4.hdr - skb->data;
5752
5753         /* compute length of segmentation header */
5754         *hdr_len = (l4.tcp->doff * 4) + l4_offset;
5755
5756         /* remove payload length from inner checksum */
5757         paylen = skb->len - l4_offset;
5758         csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
5759
5760         /* update gso size and bytecount with header size */
5761         first->gso_segs = skb_shinfo(skb)->gso_segs;
5762         first->bytecount += (first->gso_segs - 1) * *hdr_len;
5763
5764         /* MSS L4LEN IDX */
5765         mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
5766         mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
5767
5768         /* VLAN MACLEN IPLEN */
5769         vlan_macip_lens = l4.hdr - ip.hdr;
5770         vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
5771         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5772
5773         igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
5774                         type_tucmd, mss_l4len_idx);
5775
5776         return 1;
5777 }
5778
5779 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb)
5780 {
5781         unsigned int offset = 0;
5782
5783         ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
5784
5785         return offset == skb_checksum_start_offset(skb);
5786 }
5787
5788 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
5789 {
5790         struct sk_buff *skb = first->skb;
5791         u32 vlan_macip_lens = 0;
5792         u32 type_tucmd = 0;
5793
5794         if (skb->ip_summed != CHECKSUM_PARTIAL) {
5795 csum_failed:
5796                 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) &&
5797                     !tx_ring->launchtime_enable)
5798                         return;
5799                 goto no_csum;
5800         }
5801
5802         switch (skb->csum_offset) {
5803         case offsetof(struct tcphdr, check):
5804                 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
5805                 /* fall through */
5806         case offsetof(struct udphdr, check):
5807                 break;
5808         case offsetof(struct sctphdr, checksum):
5809                 /* validate that this is actually an SCTP request */
5810                 if (((first->protocol == htons(ETH_P_IP)) &&
5811                      (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
5812                     ((first->protocol == htons(ETH_P_IPV6)) &&
5813                      igb_ipv6_csum_is_sctp(skb))) {
5814                         type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
5815                         break;
5816                 }
5817                 /* fall through */
5818         default:
5819                 skb_checksum_help(skb);
5820                 goto csum_failed;
5821         }
5822
5823         /* update TX checksum flag */
5824         first->tx_flags |= IGB_TX_FLAGS_CSUM;
5825         vlan_macip_lens = skb_checksum_start_offset(skb) -
5826                           skb_network_offset(skb);
5827 no_csum:
5828         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
5829         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5830
5831         igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
5832 }
5833
5834 #define IGB_SET_FLAG(_input, _flag, _result) \
5835         ((_flag <= _result) ? \
5836          ((u32)(_input & _flag) * (_result / _flag)) : \
5837          ((u32)(_input & _flag) / (_flag / _result)))
5838
5839 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
5840 {
5841         /* set type for advanced descriptor with frame checksum insertion */
5842         u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
5843                        E1000_ADVTXD_DCMD_DEXT |
5844                        E1000_ADVTXD_DCMD_IFCS;
5845
5846         /* set HW vlan bit if vlan is present */
5847         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
5848                                  (E1000_ADVTXD_DCMD_VLE));
5849
5850         /* set segmentation bits for TSO */
5851         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
5852                                  (E1000_ADVTXD_DCMD_TSE));
5853
5854         /* set timestamp bit if present */
5855         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
5856                                  (E1000_ADVTXD_MAC_TSTAMP));
5857
5858         /* insert frame checksum */
5859         cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
5860
5861         return cmd_type;
5862 }
5863
5864 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
5865                                  union e1000_adv_tx_desc *tx_desc,
5866                                  u32 tx_flags, unsigned int paylen)
5867 {
5868         u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
5869
5870         /* 82575 requires a unique index per ring */
5871         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5872                 olinfo_status |= tx_ring->reg_idx << 4;
5873
5874         /* insert L4 checksum */
5875         olinfo_status |= IGB_SET_FLAG(tx_flags,
5876                                       IGB_TX_FLAGS_CSUM,
5877                                       (E1000_TXD_POPTS_TXSM << 8));
5878
5879         /* insert IPv4 checksum */
5880         olinfo_status |= IGB_SET_FLAG(tx_flags,
5881                                       IGB_TX_FLAGS_IPV4,
5882                                       (E1000_TXD_POPTS_IXSM << 8));
5883
5884         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5885 }
5886
5887 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5888 {
5889         struct net_device *netdev = tx_ring->netdev;
5890
5891         netif_stop_subqueue(netdev, tx_ring->queue_index);
5892
5893         /* Herbert's original patch had:
5894          *  smp_mb__after_netif_stop_queue();
5895          * but since that doesn't exist yet, just open code it.
5896          */
5897         smp_mb();
5898
5899         /* We need to check again in a case another CPU has just
5900          * made room available.
5901          */
5902         if (igb_desc_unused(tx_ring) < size)
5903                 return -EBUSY;
5904
5905         /* A reprieve! */
5906         netif_wake_subqueue(netdev, tx_ring->queue_index);
5907
5908         u64_stats_update_begin(&tx_ring->tx_syncp2);
5909         tx_ring->tx_stats.restart_queue2++;
5910         u64_stats_update_end(&tx_ring->tx_syncp2);
5911
5912         return 0;
5913 }
5914
5915 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5916 {
5917         if (igb_desc_unused(tx_ring) >= size)
5918                 return 0;
5919         return __igb_maybe_stop_tx(tx_ring, size);
5920 }
5921
5922 static int igb_tx_map(struct igb_ring *tx_ring,
5923                       struct igb_tx_buffer *first,
5924                       const u8 hdr_len)
5925 {
5926         struct sk_buff *skb = first->skb;
5927         struct igb_tx_buffer *tx_buffer;
5928         union e1000_adv_tx_desc *tx_desc;
5929         struct skb_frag_struct *frag;
5930         dma_addr_t dma;
5931         unsigned int data_len, size;
5932         u32 tx_flags = first->tx_flags;
5933         u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
5934         u16 i = tx_ring->next_to_use;
5935
5936         tx_desc = IGB_TX_DESC(tx_ring, i);
5937
5938         igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
5939
5940         size = skb_headlen(skb);
5941         data_len = skb->data_len;
5942
5943         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5944
5945         tx_buffer = first;
5946
5947         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
5948                 if (dma_mapping_error(tx_ring->dev, dma))
5949                         goto dma_error;
5950
5951                 /* record length, and DMA address */
5952                 dma_unmap_len_set(tx_buffer, len, size);
5953                 dma_unmap_addr_set(tx_buffer, dma, dma);
5954
5955                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5956
5957                 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
5958                         tx_desc->read.cmd_type_len =
5959                                 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
5960
5961                         i++;
5962                         tx_desc++;
5963                         if (i == tx_ring->count) {
5964                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
5965                                 i = 0;
5966                         }
5967                         tx_desc->read.olinfo_status = 0;
5968
5969                         dma += IGB_MAX_DATA_PER_TXD;
5970                         size -= IGB_MAX_DATA_PER_TXD;
5971
5972                         tx_desc->read.buffer_addr = cpu_to_le64(dma);
5973                 }
5974
5975                 if (likely(!data_len))
5976                         break;
5977
5978                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
5979
5980                 i++;
5981                 tx_desc++;
5982                 if (i == tx_ring->count) {
5983                         tx_desc = IGB_TX_DESC(tx_ring, 0);
5984                         i = 0;
5985                 }
5986                 tx_desc->read.olinfo_status = 0;
5987
5988                 size = skb_frag_size(frag);
5989                 data_len -= size;
5990
5991                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
5992                                        size, DMA_TO_DEVICE);
5993
5994                 tx_buffer = &tx_ring->tx_buffer_info[i];
5995         }
5996
5997         /* write last descriptor with RS and EOP bits */
5998         cmd_type |= size | IGB_TXD_DCMD;
5999         tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6000
6001         netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6002
6003         /* set the timestamp */
6004         first->time_stamp = jiffies;
6005
6006         skb_tx_timestamp(skb);
6007
6008         /* Force memory writes to complete before letting h/w know there
6009          * are new descriptors to fetch.  (Only applicable for weak-ordered
6010          * memory model archs, such as IA-64).
6011          *
6012          * We also need this memory barrier to make certain all of the
6013          * status bits have been updated before next_to_watch is written.
6014          */
6015         dma_wmb();
6016
6017         /* set next_to_watch value indicating a packet is present */
6018         first->next_to_watch = tx_desc;
6019
6020         i++;
6021         if (i == tx_ring->count)
6022                 i = 0;
6023
6024         tx_ring->next_to_use = i;
6025
6026         /* Make sure there is space in the ring for the next send. */
6027         igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6028
6029         if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
6030                 writel(i, tx_ring->tail);
6031
6032                 /* we need this if more than one processor can write to our tail
6033                  * at a time, it synchronizes IO on IA64/Altix systems
6034                  */
6035                 mmiowb();
6036         }
6037         return 0;
6038
6039 dma_error:
6040         dev_err(tx_ring->dev, "TX DMA map failed\n");
6041         tx_buffer = &tx_ring->tx_buffer_info[i];
6042
6043         /* clear dma mappings for failed tx_buffer_info map */
6044         while (tx_buffer != first) {
6045                 if (dma_unmap_len(tx_buffer, len))
6046                         dma_unmap_page(tx_ring->dev,
6047                                        dma_unmap_addr(tx_buffer, dma),
6048                                        dma_unmap_len(tx_buffer, len),
6049                                        DMA_TO_DEVICE);
6050                 dma_unmap_len_set(tx_buffer, len, 0);
6051
6052                 if (i-- == 0)
6053                         i += tx_ring->count;
6054                 tx_buffer = &tx_ring->tx_buffer_info[i];
6055         }
6056
6057         if (dma_unmap_len(tx_buffer, len))
6058                 dma_unmap_single(tx_ring->dev,
6059                                  dma_unmap_addr(tx_buffer, dma),
6060                                  dma_unmap_len(tx_buffer, len),
6061                                  DMA_TO_DEVICE);
6062         dma_unmap_len_set(tx_buffer, len, 0);
6063
6064         dev_kfree_skb_any(tx_buffer->skb);
6065         tx_buffer->skb = NULL;
6066
6067         tx_ring->next_to_use = i;
6068
6069         return -1;
6070 }
6071
6072 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
6073                                 struct igb_ring *tx_ring)
6074 {
6075         struct igb_tx_buffer *first;
6076         int tso;
6077         u32 tx_flags = 0;
6078         unsigned short f;
6079         u16 count = TXD_USE_COUNT(skb_headlen(skb));
6080         __be16 protocol = vlan_get_protocol(skb);
6081         u8 hdr_len = 0;
6082
6083         /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
6084          *       + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
6085          *       + 2 desc gap to keep tail from touching head,
6086          *       + 1 desc for context descriptor,
6087          * otherwise try next time
6088          */
6089         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6090                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6091
6092         if (igb_maybe_stop_tx(tx_ring, count + 3)) {
6093                 /* this is a hard error */
6094                 return NETDEV_TX_BUSY;
6095         }
6096
6097         /* record the location of the first descriptor for this packet */
6098         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6099         first->skb = skb;
6100         first->bytecount = skb->len;
6101         first->gso_segs = 1;
6102
6103         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6104                 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6105
6106                 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
6107                     !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
6108                                            &adapter->state)) {
6109                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6110                         tx_flags |= IGB_TX_FLAGS_TSTAMP;
6111
6112                         adapter->ptp_tx_skb = skb_get(skb);
6113                         adapter->ptp_tx_start = jiffies;
6114                         if (adapter->hw.mac.type == e1000_82576)
6115                                 schedule_work(&adapter->ptp_tx_work);
6116                 } else {
6117                         adapter->tx_hwtstamp_skipped++;
6118                 }
6119         }
6120
6121         if (skb_vlan_tag_present(skb)) {
6122                 tx_flags |= IGB_TX_FLAGS_VLAN;
6123                 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
6124         }
6125
6126         /* record initial flags and protocol */
6127         first->tx_flags = tx_flags;
6128         first->protocol = protocol;
6129
6130         tso = igb_tso(tx_ring, first, &hdr_len);
6131         if (tso < 0)
6132                 goto out_drop;
6133         else if (!tso)
6134                 igb_tx_csum(tx_ring, first);
6135
6136         if (igb_tx_map(tx_ring, first, hdr_len))
6137                 goto cleanup_tx_tstamp;
6138
6139         return NETDEV_TX_OK;
6140
6141 out_drop:
6142         dev_kfree_skb_any(first->skb);
6143         first->skb = NULL;
6144 cleanup_tx_tstamp:
6145         if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) {
6146                 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6147
6148                 dev_kfree_skb_any(adapter->ptp_tx_skb);
6149                 adapter->ptp_tx_skb = NULL;
6150                 if (adapter->hw.mac.type == e1000_82576)
6151                         cancel_work_sync(&adapter->ptp_tx_work);
6152                 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
6153         }
6154
6155         return NETDEV_TX_OK;
6156 }
6157
6158 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
6159                                                     struct sk_buff *skb)
6160 {
6161         unsigned int r_idx = skb->queue_mapping;
6162
6163         if (r_idx >= adapter->num_tx_queues)
6164                 r_idx = r_idx % adapter->num_tx_queues;
6165
6166         return adapter->tx_ring[r_idx];
6167 }
6168
6169 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
6170                                   struct net_device *netdev)
6171 {
6172         struct igb_adapter *adapter = netdev_priv(netdev);
6173
6174         /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
6175          * in order to meet this minimum size requirement.
6176          */
6177         if (skb_put_padto(skb, 17))
6178                 return NETDEV_TX_OK;
6179
6180         return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
6181 }
6182
6183 /**
6184  *  igb_tx_timeout - Respond to a Tx Hang
6185  *  @netdev: network interface device structure
6186  **/
6187 static void igb_tx_timeout(struct net_device *netdev)
6188 {
6189         struct igb_adapter *adapter = netdev_priv(netdev);
6190         struct e1000_hw *hw = &adapter->hw;
6191
6192         /* Do the reset outside of interrupt context */
6193         adapter->tx_timeout_count++;
6194
6195         if (hw->mac.type >= e1000_82580)
6196                 hw->dev_spec._82575.global_device_reset = true;
6197
6198         schedule_work(&adapter->reset_task);
6199         wr32(E1000_EICS,
6200              (adapter->eims_enable_mask & ~adapter->eims_other));
6201 }
6202
6203 static void igb_reset_task(struct work_struct *work)
6204 {
6205         struct igb_adapter *adapter;
6206         adapter = container_of(work, struct igb_adapter, reset_task);
6207
6208         igb_dump(adapter);
6209         netdev_err(adapter->netdev, "Reset adapter\n");
6210         igb_reinit_locked(adapter);
6211 }
6212
6213 /**
6214  *  igb_get_stats64 - Get System Network Statistics
6215  *  @netdev: network interface device structure
6216  *  @stats: rtnl_link_stats64 pointer
6217  **/
6218 static void igb_get_stats64(struct net_device *netdev,
6219                             struct rtnl_link_stats64 *stats)
6220 {
6221         struct igb_adapter *adapter = netdev_priv(netdev);
6222
6223         spin_lock(&adapter->stats64_lock);
6224         igb_update_stats(adapter);
6225         memcpy(stats, &adapter->stats64, sizeof(*stats));
6226         spin_unlock(&adapter->stats64_lock);
6227 }
6228
6229 /**
6230  *  igb_change_mtu - Change the Maximum Transfer Unit
6231  *  @netdev: network interface device structure
6232  *  @new_mtu: new value for maximum frame size
6233  *
6234  *  Returns 0 on success, negative on failure
6235  **/
6236 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
6237 {
6238         struct igb_adapter *adapter = netdev_priv(netdev);
6239         struct pci_dev *pdev = adapter->pdev;
6240         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
6241
6242         /* adjust max frame to be at least the size of a standard frame */
6243         if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
6244                 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
6245
6246         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
6247                 usleep_range(1000, 2000);
6248
6249         /* igb_down has a dependency on max_frame_size */
6250         adapter->max_frame_size = max_frame;
6251
6252         if (netif_running(netdev))
6253                 igb_down(adapter);
6254
6255         dev_info(&pdev->dev, "changing MTU from %d to %d\n",
6256                  netdev->mtu, new_mtu);
6257         netdev->mtu = new_mtu;
6258
6259         if (netif_running(netdev))
6260                 igb_up(adapter);
6261         else
6262                 igb_reset(adapter);
6263
6264         clear_bit(__IGB_RESETTING, &adapter->state);
6265
6266         return 0;
6267 }
6268
6269 /**
6270  *  igb_update_stats - Update the board statistics counters
6271  *  @adapter: board private structure
6272  **/
6273 void igb_update_stats(struct igb_adapter *adapter)
6274 {
6275         struct rtnl_link_stats64 *net_stats = &adapter->stats64;
6276         struct e1000_hw *hw = &adapter->hw;
6277         struct pci_dev *pdev = adapter->pdev;
6278         u32 reg, mpc;
6279         int i;
6280         u64 bytes, packets;
6281         unsigned int start;
6282         u64 _bytes, _packets;
6283
6284         /* Prevent stats update while adapter is being reset, or if the pci
6285          * connection is down.
6286          */
6287         if (adapter->link_speed == 0)
6288                 return;
6289         if (pci_channel_offline(pdev))
6290                 return;
6291
6292         bytes = 0;
6293         packets = 0;
6294
6295         rcu_read_lock();
6296         for (i = 0; i < adapter->num_rx_queues; i++) {
6297                 struct igb_ring *ring = adapter->rx_ring[i];
6298                 u32 rqdpc = rd32(E1000_RQDPC(i));
6299                 if (hw->mac.type >= e1000_i210)
6300                         wr32(E1000_RQDPC(i), 0);
6301
6302                 if (rqdpc) {
6303                         ring->rx_stats.drops += rqdpc;
6304                         net_stats->rx_fifo_errors += rqdpc;
6305                 }
6306
6307                 do {
6308                         start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
6309                         _bytes = ring->rx_stats.bytes;
6310                         _packets = ring->rx_stats.packets;
6311                 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
6312                 bytes += _bytes;
6313                 packets += _packets;
6314         }
6315
6316         net_stats->rx_bytes = bytes;
6317         net_stats->rx_packets = packets;
6318
6319         bytes = 0;
6320         packets = 0;
6321         for (i = 0; i < adapter->num_tx_queues; i++) {
6322                 struct igb_ring *ring = adapter->tx_ring[i];
6323                 do {
6324                         start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
6325                         _bytes = ring->tx_stats.bytes;
6326                         _packets = ring->tx_stats.packets;
6327                 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
6328                 bytes += _bytes;
6329                 packets += _packets;
6330         }
6331         net_stats->tx_bytes = bytes;
6332         net_stats->tx_packets = packets;
6333         rcu_read_unlock();
6334
6335         /* read stats registers */
6336         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
6337         adapter->stats.gprc += rd32(E1000_GPRC);
6338         adapter->stats.gorc += rd32(E1000_GORCL);
6339         rd32(E1000_GORCH); /* clear GORCL */
6340         adapter->stats.bprc += rd32(E1000_BPRC);
6341         adapter->stats.mprc += rd32(E1000_MPRC);
6342         adapter->stats.roc += rd32(E1000_ROC);
6343
6344         adapter->stats.prc64 += rd32(E1000_PRC64);
6345         adapter->stats.prc127 += rd32(E1000_PRC127);
6346         adapter->stats.prc255 += rd32(E1000_PRC255);
6347         adapter->stats.prc511 += rd32(E1000_PRC511);
6348         adapter->stats.prc1023 += rd32(E1000_PRC1023);
6349         adapter->stats.prc1522 += rd32(E1000_PRC1522);
6350         adapter->stats.symerrs += rd32(E1000_SYMERRS);
6351         adapter->stats.sec += rd32(E1000_SEC);
6352
6353         mpc = rd32(E1000_MPC);
6354         adapter->stats.mpc += mpc;
6355         net_stats->rx_fifo_errors += mpc;
6356         adapter->stats.scc += rd32(E1000_SCC);
6357         adapter->stats.ecol += rd32(E1000_ECOL);
6358         adapter->stats.mcc += rd32(E1000_MCC);
6359         adapter->stats.latecol += rd32(E1000_LATECOL);
6360         adapter->stats.dc += rd32(E1000_DC);
6361         adapter->stats.rlec += rd32(E1000_RLEC);
6362         adapter->stats.xonrxc += rd32(E1000_XONRXC);
6363         adapter->stats.xontxc += rd32(E1000_XONTXC);
6364         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
6365         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
6366         adapter->stats.fcruc += rd32(E1000_FCRUC);
6367         adapter->stats.gptc += rd32(E1000_GPTC);
6368         adapter->stats.gotc += rd32(E1000_GOTCL);
6369         rd32(E1000_GOTCH); /* clear GOTCL */
6370         adapter->stats.rnbc += rd32(E1000_RNBC);
6371         adapter->stats.ruc += rd32(E1000_RUC);
6372         adapter->stats.rfc += rd32(E1000_RFC);
6373         adapter->stats.rjc += rd32(E1000_RJC);
6374         adapter->stats.tor += rd32(E1000_TORH);
6375         adapter->stats.tot += rd32(E1000_TOTH);
6376         adapter->stats.tpr += rd32(E1000_TPR);
6377
6378         adapter->stats.ptc64 += rd32(E1000_PTC64);
6379         adapter->stats.ptc127 += rd32(E1000_PTC127);
6380         adapter->stats.ptc255 += rd32(E1000_PTC255);
6381         adapter->stats.ptc511 += rd32(E1000_PTC511);
6382         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
6383         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
6384
6385         adapter->stats.mptc += rd32(E1000_MPTC);
6386         adapter->stats.bptc += rd32(E1000_BPTC);
6387
6388         adapter->stats.tpt += rd32(E1000_TPT);
6389         adapter->stats.colc += rd32(E1000_COLC);
6390
6391         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
6392         /* read internal phy specific stats */
6393         reg = rd32(E1000_CTRL_EXT);
6394         if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
6395                 adapter->stats.rxerrc += rd32(E1000_RXERRC);
6396
6397                 /* this stat has invalid values on i210/i211 */
6398                 if ((hw->mac.type != e1000_i210) &&
6399                     (hw->mac.type != e1000_i211))
6400                         adapter->stats.tncrs += rd32(E1000_TNCRS);
6401         }
6402
6403         adapter->stats.tsctc += rd32(E1000_TSCTC);
6404         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
6405
6406         adapter->stats.iac += rd32(E1000_IAC);
6407         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
6408         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
6409         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
6410         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
6411         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
6412         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
6413         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
6414         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
6415
6416         /* Fill out the OS statistics structure */
6417         net_stats->multicast = adapter->stats.mprc;
6418         net_stats->collisions = adapter->stats.colc;
6419
6420         /* Rx Errors */
6421
6422         /* RLEC on some newer hardware can be incorrect so build
6423          * our own version based on RUC and ROC
6424          */
6425         net_stats->rx_errors = adapter->stats.rxerrc +
6426                 adapter->stats.crcerrs + adapter->stats.algnerrc +
6427                 adapter->stats.ruc + adapter->stats.roc +
6428                 adapter->stats.cexterr;
6429         net_stats->rx_length_errors = adapter->stats.ruc +
6430                                       adapter->stats.roc;
6431         net_stats->rx_crc_errors = adapter->stats.crcerrs;
6432         net_stats->rx_frame_errors = adapter->stats.algnerrc;
6433         net_stats->rx_missed_errors = adapter->stats.mpc;
6434
6435         /* Tx Errors */
6436         net_stats->tx_errors = adapter->stats.ecol +
6437                                adapter->stats.latecol;
6438         net_stats->tx_aborted_errors = adapter->stats.ecol;
6439         net_stats->tx_window_errors = adapter->stats.latecol;
6440         net_stats->tx_carrier_errors = adapter->stats.tncrs;
6441
6442         /* Tx Dropped needs to be maintained elsewhere */
6443
6444         /* Management Stats */
6445         adapter->stats.mgptc += rd32(E1000_MGTPTC);
6446         adapter->stats.mgprc += rd32(E1000_MGTPRC);
6447         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
6448
6449         /* OS2BMC Stats */
6450         reg = rd32(E1000_MANC);
6451         if (reg & E1000_MANC_EN_BMC2OS) {
6452                 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
6453                 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
6454                 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
6455                 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
6456         }
6457 }
6458
6459 static void igb_tsync_interrupt(struct igb_adapter *adapter)
6460 {
6461         struct e1000_hw *hw = &adapter->hw;
6462         struct ptp_clock_event event;
6463         struct timespec64 ts;
6464         u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
6465
6466         if (tsicr & TSINTR_SYS_WRAP) {
6467                 event.type = PTP_CLOCK_PPS;
6468                 if (adapter->ptp_caps.pps)
6469                         ptp_clock_event(adapter->ptp_clock, &event);
6470                 ack |= TSINTR_SYS_WRAP;
6471         }
6472
6473         if (tsicr & E1000_TSICR_TXTS) {
6474                 /* retrieve hardware timestamp */
6475                 schedule_work(&adapter->ptp_tx_work);
6476                 ack |= E1000_TSICR_TXTS;
6477         }
6478
6479         if (tsicr & TSINTR_TT0) {
6480                 spin_lock(&adapter->tmreg_lock);
6481                 ts = timespec64_add(adapter->perout[0].start,
6482                                     adapter->perout[0].period);
6483                 /* u32 conversion of tv_sec is safe until y2106 */
6484                 wr32(E1000_TRGTTIML0, ts.tv_nsec);
6485                 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
6486                 tsauxc = rd32(E1000_TSAUXC);
6487                 tsauxc |= TSAUXC_EN_TT0;
6488                 wr32(E1000_TSAUXC, tsauxc);
6489                 adapter->perout[0].start = ts;
6490                 spin_unlock(&adapter->tmreg_lock);
6491                 ack |= TSINTR_TT0;
6492         }
6493
6494         if (tsicr & TSINTR_TT1) {
6495                 spin_lock(&adapter->tmreg_lock);
6496                 ts = timespec64_add(adapter->perout[1].start,
6497                                     adapter->perout[1].period);
6498                 wr32(E1000_TRGTTIML1, ts.tv_nsec);
6499                 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
6500                 tsauxc = rd32(E1000_TSAUXC);
6501                 tsauxc |= TSAUXC_EN_TT1;
6502                 wr32(E1000_TSAUXC, tsauxc);
6503                 adapter->perout[1].start = ts;
6504                 spin_unlock(&adapter->tmreg_lock);
6505                 ack |= TSINTR_TT1;
6506         }
6507
6508         if (tsicr & TSINTR_AUTT0) {
6509                 nsec = rd32(E1000_AUXSTMPL0);
6510                 sec  = rd32(E1000_AUXSTMPH0);
6511                 event.type = PTP_CLOCK_EXTTS;
6512                 event.index = 0;
6513                 event.timestamp = sec * 1000000000ULL + nsec;
6514                 ptp_clock_event(adapter->ptp_clock, &event);
6515                 ack |= TSINTR_AUTT0;
6516         }
6517
6518         if (tsicr & TSINTR_AUTT1) {
6519                 nsec = rd32(E1000_AUXSTMPL1);
6520                 sec  = rd32(E1000_AUXSTMPH1);
6521                 event.type = PTP_CLOCK_EXTTS;
6522                 event.index = 1;
6523                 event.timestamp = sec * 1000000000ULL + nsec;
6524                 ptp_clock_event(adapter->ptp_clock, &event);
6525                 ack |= TSINTR_AUTT1;
6526         }
6527
6528         /* acknowledge the interrupts */
6529         wr32(E1000_TSICR, ack);
6530 }
6531
6532 static irqreturn_t igb_msix_other(int irq, void *data)
6533 {
6534         struct igb_adapter *adapter = data;
6535         struct e1000_hw *hw = &adapter->hw;
6536         u32 icr = rd32(E1000_ICR);
6537         /* reading ICR causes bit 31 of EICR to be cleared */
6538
6539         if (icr & E1000_ICR_DRSTA)
6540                 schedule_work(&adapter->reset_task);
6541
6542         if (icr & E1000_ICR_DOUTSYNC) {
6543                 /* HW is reporting DMA is out of sync */
6544                 adapter->stats.doosync++;
6545                 /* The DMA Out of Sync is also indication of a spoof event
6546                  * in IOV mode. Check the Wrong VM Behavior register to
6547                  * see if it is really a spoof event.
6548                  */
6549                 igb_check_wvbr(adapter);
6550         }
6551
6552         /* Check for a mailbox event */
6553         if (icr & E1000_ICR_VMMB)
6554                 igb_msg_task(adapter);
6555
6556         if (icr & E1000_ICR_LSC) {
6557                 hw->mac.get_link_status = 1;
6558                 /* guard against interrupt when we're going down */
6559                 if (!test_bit(__IGB_DOWN, &adapter->state))
6560                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
6561         }
6562
6563         if (icr & E1000_ICR_TS)
6564                 igb_tsync_interrupt(adapter);
6565
6566         wr32(E1000_EIMS, adapter->eims_other);
6567
6568         return IRQ_HANDLED;
6569 }
6570
6571 static void igb_write_itr(struct igb_q_vector *q_vector)
6572 {
6573         struct igb_adapter *adapter = q_vector->adapter;
6574         u32 itr_val = q_vector->itr_val & 0x7FFC;
6575
6576         if (!q_vector->set_itr)
6577                 return;
6578
6579         if (!itr_val)
6580                 itr_val = 0x4;
6581
6582         if (adapter->hw.mac.type == e1000_82575)
6583                 itr_val |= itr_val << 16;
6584         else
6585                 itr_val |= E1000_EITR_CNT_IGNR;
6586
6587         writel(itr_val, q_vector->itr_register);
6588         q_vector->set_itr = 0;
6589 }
6590
6591 static irqreturn_t igb_msix_ring(int irq, void *data)
6592 {
6593         struct igb_q_vector *q_vector = data;
6594
6595         /* Write the ITR value calculated from the previous interrupt. */
6596         igb_write_itr(q_vector);
6597
6598         napi_schedule(&q_vector->napi);
6599
6600         return IRQ_HANDLED;
6601 }
6602
6603 #ifdef CONFIG_IGB_DCA
6604 static void igb_update_tx_dca(struct igb_adapter *adapter,
6605                               struct igb_ring *tx_ring,
6606                               int cpu)
6607 {
6608         struct e1000_hw *hw = &adapter->hw;
6609         u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
6610
6611         if (hw->mac.type != e1000_82575)
6612                 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
6613
6614         /* We can enable relaxed ordering for reads, but not writes when
6615          * DCA is enabled.  This is due to a known issue in some chipsets
6616          * which will cause the DCA tag to be cleared.
6617          */
6618         txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
6619                   E1000_DCA_TXCTRL_DATA_RRO_EN |
6620                   E1000_DCA_TXCTRL_DESC_DCA_EN;
6621
6622         wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
6623 }
6624
6625 static void igb_update_rx_dca(struct igb_adapter *adapter,
6626                               struct igb_ring *rx_ring,
6627                               int cpu)
6628 {
6629         struct e1000_hw *hw = &adapter->hw;
6630         u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
6631
6632         if (hw->mac.type != e1000_82575)
6633                 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
6634
6635         /* We can enable relaxed ordering for reads, but not writes when
6636          * DCA is enabled.  This is due to a known issue in some chipsets
6637          * which will cause the DCA tag to be cleared.
6638          */
6639         rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
6640                   E1000_DCA_RXCTRL_DESC_DCA_EN;
6641
6642         wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
6643 }
6644
6645 static void igb_update_dca(struct igb_q_vector *q_vector)
6646 {
6647         struct igb_adapter *adapter = q_vector->adapter;
6648         int cpu = get_cpu();
6649
6650         if (q_vector->cpu == cpu)
6651                 goto out_no_update;
6652
6653         if (q_vector->tx.ring)
6654                 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
6655
6656         if (q_vector->rx.ring)
6657                 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
6658
6659         q_vector->cpu = cpu;
6660 out_no_update:
6661         put_cpu();
6662 }
6663
6664 static void igb_setup_dca(struct igb_adapter *adapter)
6665 {
6666         struct e1000_hw *hw = &adapter->hw;
6667         int i;
6668
6669         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
6670                 return;
6671
6672         /* Always use CB2 mode, difference is masked in the CB driver. */
6673         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
6674
6675         for (i = 0; i < adapter->num_q_vectors; i++) {
6676                 adapter->q_vector[i]->cpu = -1;
6677                 igb_update_dca(adapter->q_vector[i]);
6678         }
6679 }
6680
6681 static int __igb_notify_dca(struct device *dev, void *data)
6682 {
6683         struct net_device *netdev = dev_get_drvdata(dev);
6684         struct igb_adapter *adapter = netdev_priv(netdev);
6685         struct pci_dev *pdev = adapter->pdev;
6686         struct e1000_hw *hw = &adapter->hw;
6687         unsigned long event = *(unsigned long *)data;
6688
6689         switch (event) {
6690         case DCA_PROVIDER_ADD:
6691                 /* if already enabled, don't do it again */
6692                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
6693                         break;
6694                 if (dca_add_requester(dev) == 0) {
6695                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
6696                         dev_info(&pdev->dev, "DCA enabled\n");
6697                         igb_setup_dca(adapter);
6698                         break;
6699                 }
6700                 /* Fall Through since DCA is disabled. */
6701         case DCA_PROVIDER_REMOVE:
6702                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
6703                         /* without this a class_device is left
6704                          * hanging around in the sysfs model
6705                          */
6706                         dca_remove_requester(dev);
6707                         dev_info(&pdev->dev, "DCA disabled\n");
6708                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
6709                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
6710                 }
6711                 break;
6712         }
6713
6714         return 0;
6715 }
6716
6717 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
6718                           void *p)
6719 {
6720         int ret_val;
6721
6722         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
6723                                          __igb_notify_dca);
6724
6725         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6726 }
6727 #endif /* CONFIG_IGB_DCA */
6728
6729 #ifdef CONFIG_PCI_IOV
6730 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
6731 {
6732         unsigned char mac_addr[ETH_ALEN];
6733
6734         eth_zero_addr(mac_addr);
6735         igb_set_vf_mac(adapter, vf, mac_addr);
6736
6737         /* By default spoof check is enabled for all VFs */
6738         adapter->vf_data[vf].spoofchk_enabled = true;
6739
6740         /* By default VFs are not trusted */
6741         adapter->vf_data[vf].trusted = false;
6742
6743         return 0;
6744 }
6745
6746 #endif
6747 static void igb_ping_all_vfs(struct igb_adapter *adapter)
6748 {
6749         struct e1000_hw *hw = &adapter->hw;
6750         u32 ping;
6751         int i;
6752
6753         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
6754                 ping = E1000_PF_CONTROL_MSG;
6755                 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
6756                         ping |= E1000_VT_MSGTYPE_CTS;
6757                 igb_write_mbx(hw, &ping, 1, i);
6758         }
6759 }
6760
6761 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6762 {
6763         struct e1000_hw *hw = &adapter->hw;
6764         u32 vmolr = rd32(E1000_VMOLR(vf));
6765         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6766
6767         vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
6768                             IGB_VF_FLAG_MULTI_PROMISC);
6769         vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
6770
6771         if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
6772                 vmolr |= E1000_VMOLR_MPME;
6773                 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
6774                 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
6775         } else {
6776                 /* if we have hashes and we are clearing a multicast promisc
6777                  * flag we need to write the hashes to the MTA as this step
6778                  * was previously skipped
6779                  */
6780                 if (vf_data->num_vf_mc_hashes > 30) {
6781                         vmolr |= E1000_VMOLR_MPME;
6782                 } else if (vf_data->num_vf_mc_hashes) {
6783                         int j;
6784
6785                         vmolr |= E1000_VMOLR_ROMPE;
6786                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
6787                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
6788                 }
6789         }
6790
6791         wr32(E1000_VMOLR(vf), vmolr);
6792
6793         /* there are flags left unprocessed, likely not supported */
6794         if (*msgbuf & E1000_VT_MSGINFO_MASK)
6795                 return -EINVAL;
6796
6797         return 0;
6798 }
6799
6800 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
6801                                   u32 *msgbuf, u32 vf)
6802 {
6803         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6804         u16 *hash_list = (u16 *)&msgbuf[1];
6805         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6806         int i;
6807
6808         /* salt away the number of multicast addresses assigned
6809          * to this VF for later use to restore when the PF multi cast
6810          * list changes
6811          */
6812         vf_data->num_vf_mc_hashes = n;
6813
6814         /* only up to 30 hash values supported */
6815         if (n > 30)
6816                 n = 30;
6817
6818         /* store the hashes for later use */
6819         for (i = 0; i < n; i++)
6820                 vf_data->vf_mc_hashes[i] = hash_list[i];
6821
6822         /* Flush and reset the mta with the new values */
6823         igb_set_rx_mode(adapter->netdev);
6824
6825         return 0;
6826 }
6827
6828 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
6829 {
6830         struct e1000_hw *hw = &adapter->hw;
6831         struct vf_data_storage *vf_data;
6832         int i, j;
6833
6834         for (i = 0; i < adapter->vfs_allocated_count; i++) {
6835                 u32 vmolr = rd32(E1000_VMOLR(i));
6836
6837                 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
6838
6839                 vf_data = &adapter->vf_data[i];
6840
6841                 if ((vf_data->num_vf_mc_hashes > 30) ||
6842                     (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
6843                         vmolr |= E1000_VMOLR_MPME;
6844                 } else if (vf_data->num_vf_mc_hashes) {
6845                         vmolr |= E1000_VMOLR_ROMPE;
6846                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
6847                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
6848                 }
6849                 wr32(E1000_VMOLR(i), vmolr);
6850         }
6851 }
6852
6853 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
6854 {
6855         struct e1000_hw *hw = &adapter->hw;
6856         u32 pool_mask, vlvf_mask, i;
6857
6858         /* create mask for VF and other pools */
6859         pool_mask = E1000_VLVF_POOLSEL_MASK;
6860         vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
6861
6862         /* drop PF from pool bits */
6863         pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
6864                              adapter->vfs_allocated_count);
6865
6866         /* Find the vlan filter for this id */
6867         for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
6868                 u32 vlvf = rd32(E1000_VLVF(i));
6869                 u32 vfta_mask, vid, vfta;
6870
6871                 /* remove the vf from the pool */
6872                 if (!(vlvf & vlvf_mask))
6873                         continue;
6874
6875                 /* clear out bit from VLVF */
6876                 vlvf ^= vlvf_mask;
6877
6878                 /* if other pools are present, just remove ourselves */
6879                 if (vlvf & pool_mask)
6880                         goto update_vlvfb;
6881
6882                 /* if PF is present, leave VFTA */
6883                 if (vlvf & E1000_VLVF_POOLSEL_MASK)
6884                         goto update_vlvf;
6885
6886                 vid = vlvf & E1000_VLVF_VLANID_MASK;
6887                 vfta_mask = BIT(vid % 32);
6888
6889                 /* clear bit from VFTA */
6890                 vfta = adapter->shadow_vfta[vid / 32];
6891                 if (vfta & vfta_mask)
6892                         hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
6893 update_vlvf:
6894                 /* clear pool selection enable */
6895                 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6896                         vlvf &= E1000_VLVF_POOLSEL_MASK;
6897                 else
6898                         vlvf = 0;
6899 update_vlvfb:
6900                 /* clear pool bits */
6901                 wr32(E1000_VLVF(i), vlvf);
6902         }
6903 }
6904
6905 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
6906 {
6907         u32 vlvf;
6908         int idx;
6909
6910         /* short cut the special case */
6911         if (vlan == 0)
6912                 return 0;
6913
6914         /* Search for the VLAN id in the VLVF entries */
6915         for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
6916                 vlvf = rd32(E1000_VLVF(idx));
6917                 if ((vlvf & VLAN_VID_MASK) == vlan)
6918                         break;
6919         }
6920
6921         return idx;
6922 }
6923
6924 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
6925 {
6926         struct e1000_hw *hw = &adapter->hw;
6927         u32 bits, pf_id;
6928         int idx;
6929
6930         idx = igb_find_vlvf_entry(hw, vid);
6931         if (!idx)
6932                 return;
6933
6934         /* See if any other pools are set for this VLAN filter
6935          * entry other than the PF.
6936          */
6937         pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
6938         bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
6939         bits &= rd32(E1000_VLVF(idx));
6940
6941         /* Disable the filter so this falls into the default pool. */
6942         if (!bits) {
6943                 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6944                         wr32(E1000_VLVF(idx), BIT(pf_id));
6945                 else
6946                         wr32(E1000_VLVF(idx), 0);
6947         }
6948 }
6949
6950 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
6951                            bool add, u32 vf)
6952 {
6953         int pf_id = adapter->vfs_allocated_count;
6954         struct e1000_hw *hw = &adapter->hw;
6955         int err;
6956
6957         /* If VLAN overlaps with one the PF is currently monitoring make
6958          * sure that we are able to allocate a VLVF entry.  This may be
6959          * redundant but it guarantees PF will maintain visibility to
6960          * the VLAN.
6961          */
6962         if (add && test_bit(vid, adapter->active_vlans)) {
6963                 err = igb_vfta_set(hw, vid, pf_id, true, false);
6964                 if (err)
6965                         return err;
6966         }
6967
6968         err = igb_vfta_set(hw, vid, vf, add, false);
6969
6970         if (add && !err)
6971                 return err;
6972
6973         /* If we failed to add the VF VLAN or we are removing the VF VLAN
6974          * we may need to drop the PF pool bit in order to allow us to free
6975          * up the VLVF resources.
6976          */
6977         if (test_bit(vid, adapter->active_vlans) ||
6978             (adapter->flags & IGB_FLAG_VLAN_PROMISC))
6979                 igb_update_pf_vlvf(adapter, vid);
6980
6981         return err;
6982 }
6983
6984 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
6985 {
6986         struct e1000_hw *hw = &adapter->hw;
6987
6988         if (vid)
6989                 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
6990         else
6991                 wr32(E1000_VMVIR(vf), 0);
6992 }
6993
6994 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
6995                                 u16 vlan, u8 qos)
6996 {
6997         int err;
6998
6999         err = igb_set_vf_vlan(adapter, vlan, true, vf);
7000         if (err)
7001                 return err;
7002
7003         igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
7004         igb_set_vmolr(adapter, vf, !vlan);
7005
7006         /* revoke access to previous VLAN */
7007         if (vlan != adapter->vf_data[vf].pf_vlan)
7008                 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7009                                 false, vf);
7010
7011         adapter->vf_data[vf].pf_vlan = vlan;
7012         adapter->vf_data[vf].pf_qos = qos;
7013         igb_set_vf_vlan_strip(adapter, vf, true);
7014         dev_info(&adapter->pdev->dev,
7015                  "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
7016         if (test_bit(__IGB_DOWN, &adapter->state)) {
7017                 dev_warn(&adapter->pdev->dev,
7018                          "The VF VLAN has been set, but the PF device is not up.\n");
7019                 dev_warn(&adapter->pdev->dev,
7020                          "Bring the PF device up before attempting to use the VF device.\n");
7021         }
7022
7023         return err;
7024 }
7025
7026 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
7027 {
7028         /* Restore tagless access via VLAN 0 */
7029         igb_set_vf_vlan(adapter, 0, true, vf);
7030
7031         igb_set_vmvir(adapter, 0, vf);
7032         igb_set_vmolr(adapter, vf, true);
7033
7034         /* Remove any PF assigned VLAN */
7035         if (adapter->vf_data[vf].pf_vlan)
7036                 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7037                                 false, vf);
7038
7039         adapter->vf_data[vf].pf_vlan = 0;
7040         adapter->vf_data[vf].pf_qos = 0;
7041         igb_set_vf_vlan_strip(adapter, vf, false);
7042
7043         return 0;
7044 }
7045
7046 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf,
7047                                u16 vlan, u8 qos, __be16 vlan_proto)
7048 {
7049         struct igb_adapter *adapter = netdev_priv(netdev);
7050
7051         if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
7052                 return -EINVAL;
7053
7054         if (vlan_proto != htons(ETH_P_8021Q))
7055                 return -EPROTONOSUPPORT;
7056
7057         return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
7058                                igb_disable_port_vlan(adapter, vf);
7059 }
7060
7061 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7062 {
7063         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
7064         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
7065         int ret;
7066
7067         if (adapter->vf_data[vf].pf_vlan)
7068                 return -1;
7069
7070         /* VLAN 0 is a special case, don't allow it to be removed */
7071         if (!vid && !add)
7072                 return 0;
7073
7074         ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
7075         if (!ret)
7076                 igb_set_vf_vlan_strip(adapter, vf, !!vid);
7077         return ret;
7078 }
7079
7080 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
7081 {
7082         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7083
7084         /* clear flags - except flag that indicates PF has set the MAC */
7085         vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
7086         vf_data->last_nack = jiffies;
7087
7088         /* reset vlans for device */
7089         igb_clear_vf_vfta(adapter, vf);
7090         igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
7091         igb_set_vmvir(adapter, vf_data->pf_vlan |
7092                                (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
7093         igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
7094         igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
7095
7096         /* reset multicast table array for vf */
7097         adapter->vf_data[vf].num_vf_mc_hashes = 0;
7098
7099         /* Flush and reset the mta with the new values */
7100         igb_set_rx_mode(adapter->netdev);
7101 }
7102
7103 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
7104 {
7105         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7106
7107         /* clear mac address as we were hotplug removed/added */
7108         if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7109                 eth_zero_addr(vf_mac);
7110
7111         /* process remaining reset events */
7112         igb_vf_reset(adapter, vf);
7113 }
7114
7115 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
7116 {
7117         struct e1000_hw *hw = &adapter->hw;
7118         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7119         u32 reg, msgbuf[3];
7120         u8 *addr = (u8 *)(&msgbuf[1]);
7121
7122         /* process all the same items cleared in a function level reset */
7123         igb_vf_reset(adapter, vf);
7124
7125         /* set vf mac address */
7126         igb_set_vf_mac(adapter, vf, vf_mac);
7127
7128         /* enable transmit and receive for vf */
7129         reg = rd32(E1000_VFTE);
7130         wr32(E1000_VFTE, reg | BIT(vf));
7131         reg = rd32(E1000_VFRE);
7132         wr32(E1000_VFRE, reg | BIT(vf));
7133
7134         adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
7135
7136         /* reply to reset with ack and vf mac address */
7137         if (!is_zero_ether_addr(vf_mac)) {
7138                 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
7139                 memcpy(addr, vf_mac, ETH_ALEN);
7140         } else {
7141                 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
7142         }
7143         igb_write_mbx(hw, msgbuf, 3, vf);
7144 }
7145
7146 static void igb_flush_mac_table(struct igb_adapter *adapter)
7147 {
7148         struct e1000_hw *hw = &adapter->hw;
7149         int i;
7150
7151         for (i = 0; i < hw->mac.rar_entry_count; i++) {
7152                 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE;
7153                 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
7154                 adapter->mac_table[i].queue = 0;
7155                 igb_rar_set_index(adapter, i);
7156         }
7157 }
7158
7159 static int igb_available_rars(struct igb_adapter *adapter, u8 queue)
7160 {
7161         struct e1000_hw *hw = &adapter->hw;
7162         /* do not count rar entries reserved for VFs MAC addresses */
7163         int rar_entries = hw->mac.rar_entry_count -
7164                           adapter->vfs_allocated_count;
7165         int i, count = 0;
7166
7167         for (i = 0; i < rar_entries; i++) {
7168                 /* do not count default entries */
7169                 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT)
7170                         continue;
7171
7172                 /* do not count "in use" entries for different queues */
7173                 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) &&
7174                     (adapter->mac_table[i].queue != queue))
7175                         continue;
7176
7177                 count++;
7178         }
7179
7180         return count;
7181 }
7182
7183 /* Set default MAC address for the PF in the first RAR entry */
7184 static void igb_set_default_mac_filter(struct igb_adapter *adapter)
7185 {
7186         struct igb_mac_addr *mac_table = &adapter->mac_table[0];
7187
7188         ether_addr_copy(mac_table->addr, adapter->hw.mac.addr);
7189         mac_table->queue = adapter->vfs_allocated_count;
7190         mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7191
7192         igb_rar_set_index(adapter, 0);
7193 }
7194
7195 /* If the filter to be added and an already existing filter express
7196  * the same address and address type, it should be possible to only
7197  * override the other configurations, for example the queue to steer
7198  * traffic.
7199  */
7200 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry,
7201                                       const u8 *addr, const u8 flags)
7202 {
7203         if (!(entry->state & IGB_MAC_STATE_IN_USE))
7204                 return true;
7205
7206         if ((entry->state & IGB_MAC_STATE_SRC_ADDR) !=
7207             (flags & IGB_MAC_STATE_SRC_ADDR))
7208                 return false;
7209
7210         if (!ether_addr_equal(addr, entry->addr))
7211                 return false;
7212
7213         return true;
7214 }
7215
7216 /* Add a MAC filter for 'addr' directing matching traffic to 'queue',
7217  * 'flags' is used to indicate what kind of match is made, match is by
7218  * default for the destination address, if matching by source address
7219  * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used.
7220  */
7221 static int igb_add_mac_filter_flags(struct igb_adapter *adapter,
7222                                     const u8 *addr, const u8 queue,
7223                                     const u8 flags)
7224 {
7225         struct e1000_hw *hw = &adapter->hw;
7226         int rar_entries = hw->mac.rar_entry_count -
7227                           adapter->vfs_allocated_count;
7228         int i;
7229
7230         if (is_zero_ether_addr(addr))
7231                 return -EINVAL;
7232
7233         /* Search for the first empty entry in the MAC table.
7234          * Do not touch entries at the end of the table reserved for the VF MAC
7235          * addresses.
7236          */
7237         for (i = 0; i < rar_entries; i++) {
7238                 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i],
7239                                                addr, flags))
7240                         continue;
7241
7242                 ether_addr_copy(adapter->mac_table[i].addr, addr);
7243                 adapter->mac_table[i].queue = queue;
7244                 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags;
7245
7246                 igb_rar_set_index(adapter, i);
7247                 return i;
7248         }
7249
7250         return -ENOSPC;
7251 }
7252
7253 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7254                               const u8 queue)
7255 {
7256         return igb_add_mac_filter_flags(adapter, addr, queue, 0);
7257 }
7258
7259 /* Remove a MAC filter for 'addr' directing matching traffic to
7260  * 'queue', 'flags' is used to indicate what kind of match need to be
7261  * removed, match is by default for the destination address, if
7262  * matching by source address is to be removed the flag
7263  * IGB_MAC_STATE_SRC_ADDR can be used.
7264  */
7265 static int igb_del_mac_filter_flags(struct igb_adapter *adapter,
7266                                     const u8 *addr, const u8 queue,
7267                                     const u8 flags)
7268 {
7269         struct e1000_hw *hw = &adapter->hw;
7270         int rar_entries = hw->mac.rar_entry_count -
7271                           adapter->vfs_allocated_count;
7272         int i;
7273
7274         if (is_zero_ether_addr(addr))
7275                 return -EINVAL;
7276
7277         /* Search for matching entry in the MAC table based on given address
7278          * and queue. Do not touch entries at the end of the table reserved
7279          * for the VF MAC addresses.
7280          */
7281         for (i = 0; i < rar_entries; i++) {
7282                 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE))
7283                         continue;
7284                 if ((adapter->mac_table[i].state & flags) != flags)
7285                         continue;
7286                 if (adapter->mac_table[i].queue != queue)
7287                         continue;
7288                 if (!ether_addr_equal(adapter->mac_table[i].addr, addr))
7289                         continue;
7290
7291                 /* When a filter for the default address is "deleted",
7292                  * we return it to its initial configuration
7293                  */
7294                 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) {
7295                         adapter->mac_table[i].state =
7296                                 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7297                         adapter->mac_table[i].queue =
7298                                 adapter->vfs_allocated_count;
7299                 } else {
7300                         adapter->mac_table[i].state = 0;
7301                         adapter->mac_table[i].queue = 0;
7302                         memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
7303                 }
7304
7305                 igb_rar_set_index(adapter, i);
7306                 return 0;
7307         }
7308
7309         return -ENOENT;
7310 }
7311
7312 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7313                               const u8 queue)
7314 {
7315         return igb_del_mac_filter_flags(adapter, addr, queue, 0);
7316 }
7317
7318 int igb_add_mac_steering_filter(struct igb_adapter *adapter,
7319                                 const u8 *addr, u8 queue, u8 flags)
7320 {
7321         struct e1000_hw *hw = &adapter->hw;
7322
7323         /* In theory, this should be supported on 82575 as well, but
7324          * that part wasn't easily accessible during development.
7325          */
7326         if (hw->mac.type != e1000_i210)
7327                 return -EOPNOTSUPP;
7328
7329         return igb_add_mac_filter_flags(adapter, addr, queue,
7330                                         IGB_MAC_STATE_QUEUE_STEERING | flags);
7331 }
7332
7333 int igb_del_mac_steering_filter(struct igb_adapter *adapter,
7334                                 const u8 *addr, u8 queue, u8 flags)
7335 {
7336         return igb_del_mac_filter_flags(adapter, addr, queue,
7337                                         IGB_MAC_STATE_QUEUE_STEERING | flags);
7338 }
7339
7340 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr)
7341 {
7342         struct igb_adapter *adapter = netdev_priv(netdev);
7343         int ret;
7344
7345         ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7346
7347         return min_t(int, ret, 0);
7348 }
7349
7350 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr)
7351 {
7352         struct igb_adapter *adapter = netdev_priv(netdev);
7353
7354         igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7355
7356         return 0;
7357 }
7358
7359 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf,
7360                                  const u32 info, const u8 *addr)
7361 {
7362         struct pci_dev *pdev = adapter->pdev;
7363         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7364         struct list_head *pos;
7365         struct vf_mac_filter *entry = NULL;
7366         int ret = 0;
7367
7368         switch (info) {
7369         case E1000_VF_MAC_FILTER_CLR:
7370                 /* remove all unicast MAC filters related to the current VF */
7371                 list_for_each(pos, &adapter->vf_macs.l) {
7372                         entry = list_entry(pos, struct vf_mac_filter, l);
7373                         if (entry->vf == vf) {
7374                                 entry->vf = -1;
7375                                 entry->free = true;
7376                                 igb_del_mac_filter(adapter, entry->vf_mac, vf);
7377                         }
7378                 }
7379                 break;
7380         case E1000_VF_MAC_FILTER_ADD:
7381                 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7382                     !vf_data->trusted) {
7383                         dev_warn(&pdev->dev,
7384                                  "VF %d requested MAC filter but is administratively denied\n",
7385                                  vf);
7386                         return -EINVAL;
7387                 }
7388                 if (!is_valid_ether_addr(addr)) {
7389                         dev_warn(&pdev->dev,
7390                                  "VF %d attempted to set invalid MAC filter\n",
7391                                  vf);
7392                         return -EINVAL;
7393                 }
7394
7395                 /* try to find empty slot in the list */
7396                 list_for_each(pos, &adapter->vf_macs.l) {
7397                         entry = list_entry(pos, struct vf_mac_filter, l);
7398                         if (entry->free)
7399                                 break;
7400                 }
7401
7402                 if (entry && entry->free) {
7403                         entry->free = false;
7404                         entry->vf = vf;
7405                         ether_addr_copy(entry->vf_mac, addr);
7406
7407                         ret = igb_add_mac_filter(adapter, addr, vf);
7408                         ret = min_t(int, ret, 0);
7409                 } else {
7410                         ret = -ENOSPC;
7411                 }
7412
7413                 if (ret == -ENOSPC)
7414                         dev_warn(&pdev->dev,
7415                                  "VF %d has requested MAC filter but there is no space for it\n",
7416                                  vf);
7417                 break;
7418         default:
7419                 ret = -EINVAL;
7420                 break;
7421         }
7422
7423         return ret;
7424 }
7425
7426 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
7427 {
7428         struct pci_dev *pdev = adapter->pdev;
7429         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7430         u32 info = msg[0] & E1000_VT_MSGINFO_MASK;
7431
7432         /* The VF MAC Address is stored in a packed array of bytes
7433          * starting at the second 32 bit word of the msg array
7434          */
7435         unsigned char *addr = (unsigned char *)&msg[1];
7436         int ret = 0;
7437
7438         if (!info) {
7439                 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7440                     !vf_data->trusted) {
7441                         dev_warn(&pdev->dev,
7442                                  "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
7443                                  vf);
7444                         return -EINVAL;
7445                 }
7446
7447                 if (!is_valid_ether_addr(addr)) {
7448                         dev_warn(&pdev->dev,
7449                                  "VF %d attempted to set invalid MAC\n",
7450                                  vf);
7451                         return -EINVAL;
7452                 }
7453
7454                 ret = igb_set_vf_mac(adapter, vf, addr);
7455         } else {
7456                 ret = igb_set_vf_mac_filter(adapter, vf, info, addr);
7457         }
7458
7459         return ret;
7460 }
7461
7462 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
7463 {
7464         struct e1000_hw *hw = &adapter->hw;
7465         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7466         u32 msg = E1000_VT_MSGTYPE_NACK;
7467
7468         /* if device isn't clear to send it shouldn't be reading either */
7469         if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
7470             time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
7471                 igb_write_mbx(hw, &msg, 1, vf);
7472                 vf_data->last_nack = jiffies;
7473         }
7474 }
7475
7476 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
7477 {
7478         struct pci_dev *pdev = adapter->pdev;
7479         u32 msgbuf[E1000_VFMAILBOX_SIZE];
7480         struct e1000_hw *hw = &adapter->hw;
7481         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7482         s32 retval;
7483
7484         retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false);
7485
7486         if (retval) {
7487                 /* if receive failed revoke VF CTS stats and restart init */
7488                 dev_err(&pdev->dev, "Error receiving message from VF\n");
7489                 vf_data->flags &= ~IGB_VF_FLAG_CTS;
7490                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7491                         goto unlock;
7492                 goto out;
7493         }
7494
7495         /* this is a message we already processed, do nothing */
7496         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
7497                 goto unlock;
7498
7499         /* until the vf completes a reset it should not be
7500          * allowed to start any configuration.
7501          */
7502         if (msgbuf[0] == E1000_VF_RESET) {
7503                 /* unlocks mailbox */
7504                 igb_vf_reset_msg(adapter, vf);
7505                 return;
7506         }
7507
7508         if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
7509                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7510                         goto unlock;
7511                 retval = -1;
7512                 goto out;
7513         }
7514
7515         switch ((msgbuf[0] & 0xFFFF)) {
7516         case E1000_VF_SET_MAC_ADDR:
7517                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
7518                 break;
7519         case E1000_VF_SET_PROMISC:
7520                 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
7521                 break;
7522         case E1000_VF_SET_MULTICAST:
7523                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
7524                 break;
7525         case E1000_VF_SET_LPE:
7526                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
7527                 break;
7528         case E1000_VF_SET_VLAN:
7529                 retval = -1;
7530                 if (vf_data->pf_vlan)
7531                         dev_warn(&pdev->dev,
7532                                  "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
7533                                  vf);
7534                 else
7535                         retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
7536                 break;
7537         default:
7538                 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
7539                 retval = -1;
7540                 break;
7541         }
7542
7543         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
7544 out:
7545         /* notify the VF of the results of what it sent us */
7546         if (retval)
7547                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
7548         else
7549                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
7550
7551         /* unlocks mailbox */
7552         igb_write_mbx(hw, msgbuf, 1, vf);
7553         return;
7554
7555 unlock:
7556         igb_unlock_mbx(hw, vf);
7557 }
7558
7559 static void igb_msg_task(struct igb_adapter *adapter)
7560 {
7561         struct e1000_hw *hw = &adapter->hw;
7562         u32 vf;
7563
7564         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
7565                 /* process any reset requests */
7566                 if (!igb_check_for_rst(hw, vf))
7567                         igb_vf_reset_event(adapter, vf);
7568
7569                 /* process any messages pending */
7570                 if (!igb_check_for_msg(hw, vf))
7571                         igb_rcv_msg_from_vf(adapter, vf);
7572
7573                 /* process any acks */
7574                 if (!igb_check_for_ack(hw, vf))
7575                         igb_rcv_ack_from_vf(adapter, vf);
7576         }
7577 }
7578
7579 /**
7580  *  igb_set_uta - Set unicast filter table address
7581  *  @adapter: board private structure
7582  *  @set: boolean indicating if we are setting or clearing bits
7583  *
7584  *  The unicast table address is a register array of 32-bit registers.
7585  *  The table is meant to be used in a way similar to how the MTA is used
7586  *  however due to certain limitations in the hardware it is necessary to
7587  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
7588  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
7589  **/
7590 static void igb_set_uta(struct igb_adapter *adapter, bool set)
7591 {
7592         struct e1000_hw *hw = &adapter->hw;
7593         u32 uta = set ? ~0 : 0;
7594         int i;
7595
7596         /* we only need to do this if VMDq is enabled */
7597         if (!adapter->vfs_allocated_count)
7598                 return;
7599
7600         for (i = hw->mac.uta_reg_count; i--;)
7601                 array_wr32(E1000_UTA, i, uta);
7602 }
7603
7604 /**
7605  *  igb_intr_msi - Interrupt Handler
7606  *  @irq: interrupt number
7607  *  @data: pointer to a network interface device structure
7608  **/
7609 static irqreturn_t igb_intr_msi(int irq, void *data)
7610 {
7611         struct igb_adapter *adapter = data;
7612         struct igb_q_vector *q_vector = adapter->q_vector[0];
7613         struct e1000_hw *hw = &adapter->hw;
7614         /* read ICR disables interrupts using IAM */
7615         u32 icr = rd32(E1000_ICR);
7616
7617         igb_write_itr(q_vector);
7618
7619         if (icr & E1000_ICR_DRSTA)
7620                 schedule_work(&adapter->reset_task);
7621
7622         if (icr & E1000_ICR_DOUTSYNC) {
7623                 /* HW is reporting DMA is out of sync */
7624                 adapter->stats.doosync++;
7625         }
7626
7627         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
7628                 hw->mac.get_link_status = 1;
7629                 if (!test_bit(__IGB_DOWN, &adapter->state))
7630                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
7631         }
7632
7633         if (icr & E1000_ICR_TS)
7634                 igb_tsync_interrupt(adapter);
7635
7636         napi_schedule(&q_vector->napi);
7637
7638         return IRQ_HANDLED;
7639 }
7640
7641 /**
7642  *  igb_intr - Legacy Interrupt Handler
7643  *  @irq: interrupt number
7644  *  @data: pointer to a network interface device structure
7645  **/
7646 static irqreturn_t igb_intr(int irq, void *data)
7647 {
7648         struct igb_adapter *adapter = data;
7649         struct igb_q_vector *q_vector = adapter->q_vector[0];
7650         struct e1000_hw *hw = &adapter->hw;
7651         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
7652          * need for the IMC write
7653          */
7654         u32 icr = rd32(E1000_ICR);
7655
7656         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
7657          * not set, then the adapter didn't send an interrupt
7658          */
7659         if (!(icr & E1000_ICR_INT_ASSERTED))
7660                 return IRQ_NONE;
7661
7662         igb_write_itr(q_vector);
7663
7664         if (icr & E1000_ICR_DRSTA)
7665                 schedule_work(&adapter->reset_task);
7666
7667         if (icr & E1000_ICR_DOUTSYNC) {
7668                 /* HW is reporting DMA is out of sync */
7669                 adapter->stats.doosync++;
7670         }
7671
7672         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
7673                 hw->mac.get_link_status = 1;
7674                 /* guard against interrupt when we're going down */
7675                 if (!test_bit(__IGB_DOWN, &adapter->state))
7676                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
7677         }
7678
7679         if (icr & E1000_ICR_TS)
7680                 igb_tsync_interrupt(adapter);
7681
7682         napi_schedule(&q_vector->napi);
7683
7684         return IRQ_HANDLED;
7685 }
7686
7687 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
7688 {
7689         struct igb_adapter *adapter = q_vector->adapter;
7690         struct e1000_hw *hw = &adapter->hw;
7691
7692         if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
7693             (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
7694                 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
7695                         igb_set_itr(q_vector);
7696                 else
7697                         igb_update_ring_itr(q_vector);
7698         }
7699
7700         if (!test_bit(__IGB_DOWN, &adapter->state)) {
7701                 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7702                         wr32(E1000_EIMS, q_vector->eims_value);
7703                 else
7704                         igb_irq_enable(adapter);
7705         }
7706 }
7707
7708 /**
7709  *  igb_poll - NAPI Rx polling callback
7710  *  @napi: napi polling structure
7711  *  @budget: count of how many packets we should handle
7712  **/
7713 static int igb_poll(struct napi_struct *napi, int budget)
7714 {
7715         struct igb_q_vector *q_vector = container_of(napi,
7716                                                      struct igb_q_vector,
7717                                                      napi);
7718         bool clean_complete = true;
7719         int work_done = 0;
7720
7721 #ifdef CONFIG_IGB_DCA
7722         if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
7723                 igb_update_dca(q_vector);
7724 #endif
7725         if (q_vector->tx.ring)
7726                 clean_complete = igb_clean_tx_irq(q_vector, budget);
7727
7728         if (q_vector->rx.ring) {
7729                 int cleaned = igb_clean_rx_irq(q_vector, budget);
7730
7731                 work_done += cleaned;
7732                 if (cleaned >= budget)
7733                         clean_complete = false;
7734         }
7735
7736         /* If all work not completed, return budget and keep polling */
7737         if (!clean_complete)
7738                 return budget;
7739
7740         /* Exit the polling mode, but don't re-enable interrupts if stack might
7741          * poll us due to busy-polling
7742          */
7743         if (likely(napi_complete_done(napi, work_done)))
7744                 igb_ring_irq_enable(q_vector);
7745
7746         return min(work_done, budget - 1);
7747 }
7748
7749 /**
7750  *  igb_clean_tx_irq - Reclaim resources after transmit completes
7751  *  @q_vector: pointer to q_vector containing needed info
7752  *  @napi_budget: Used to determine if we are in netpoll
7753  *
7754  *  returns true if ring is completely cleaned
7755  **/
7756 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
7757 {
7758         struct igb_adapter *adapter = q_vector->adapter;
7759         struct igb_ring *tx_ring = q_vector->tx.ring;
7760         struct igb_tx_buffer *tx_buffer;
7761         union e1000_adv_tx_desc *tx_desc;
7762         unsigned int total_bytes = 0, total_packets = 0;
7763         unsigned int budget = q_vector->tx.work_limit;
7764         unsigned int i = tx_ring->next_to_clean;
7765
7766         if (test_bit(__IGB_DOWN, &adapter->state))
7767                 return true;
7768
7769         tx_buffer = &tx_ring->tx_buffer_info[i];
7770         tx_desc = IGB_TX_DESC(tx_ring, i);
7771         i -= tx_ring->count;
7772
7773         do {
7774                 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
7775
7776                 /* if next_to_watch is not set then there is no work pending */
7777                 if (!eop_desc)
7778                         break;
7779
7780                 /* prevent any other reads prior to eop_desc */
7781                 smp_rmb();
7782
7783                 /* if DD is not set pending work has not been completed */
7784                 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
7785                         break;
7786
7787                 /* clear next_to_watch to prevent false hangs */
7788                 tx_buffer->next_to_watch = NULL;
7789
7790                 /* update the statistics for this packet */
7791                 total_bytes += tx_buffer->bytecount;
7792                 total_packets += tx_buffer->gso_segs;
7793
7794                 /* free the skb */
7795                 napi_consume_skb(tx_buffer->skb, napi_budget);
7796
7797                 /* unmap skb header data */
7798                 dma_unmap_single(tx_ring->dev,
7799                                  dma_unmap_addr(tx_buffer, dma),
7800                                  dma_unmap_len(tx_buffer, len),
7801                                  DMA_TO_DEVICE);
7802
7803                 /* clear tx_buffer data */
7804                 dma_unmap_len_set(tx_buffer, len, 0);
7805
7806                 /* clear last DMA location and unmap remaining buffers */
7807                 while (tx_desc != eop_desc) {
7808                         tx_buffer++;
7809                         tx_desc++;
7810                         i++;
7811                         if (unlikely(!i)) {
7812                                 i -= tx_ring->count;
7813                                 tx_buffer = tx_ring->tx_buffer_info;
7814                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
7815                         }
7816
7817                         /* unmap any remaining paged data */
7818                         if (dma_unmap_len(tx_buffer, len)) {
7819                                 dma_unmap_page(tx_ring->dev,
7820                                                dma_unmap_addr(tx_buffer, dma),
7821                                                dma_unmap_len(tx_buffer, len),
7822                                                DMA_TO_DEVICE);
7823                                 dma_unmap_len_set(tx_buffer, len, 0);
7824                         }
7825                 }
7826
7827                 /* move us one more past the eop_desc for start of next pkt */
7828                 tx_buffer++;
7829                 tx_desc++;
7830                 i++;
7831                 if (unlikely(!i)) {
7832                         i -= tx_ring->count;
7833                         tx_buffer = tx_ring->tx_buffer_info;
7834                         tx_desc = IGB_TX_DESC(tx_ring, 0);
7835                 }
7836
7837                 /* issue prefetch for next Tx descriptor */
7838                 prefetch(tx_desc);
7839
7840                 /* update budget accounting */
7841                 budget--;
7842         } while (likely(budget));
7843
7844         netdev_tx_completed_queue(txring_txq(tx_ring),
7845                                   total_packets, total_bytes);
7846         i += tx_ring->count;
7847         tx_ring->next_to_clean = i;
7848         u64_stats_update_begin(&tx_ring->tx_syncp);
7849         tx_ring->tx_stats.bytes += total_bytes;
7850         tx_ring->tx_stats.packets += total_packets;
7851         u64_stats_update_end(&tx_ring->tx_syncp);
7852         q_vector->tx.total_bytes += total_bytes;
7853         q_vector->tx.total_packets += total_packets;
7854
7855         if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
7856                 struct e1000_hw *hw = &adapter->hw;
7857
7858                 /* Detect a transmit hang in hardware, this serializes the
7859                  * check with the clearing of time_stamp and movement of i
7860                  */
7861                 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
7862                 if (tx_buffer->next_to_watch &&
7863                     time_after(jiffies, tx_buffer->time_stamp +
7864                                (adapter->tx_timeout_factor * HZ)) &&
7865                     !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
7866
7867                         /* detected Tx unit hang */
7868                         dev_err(tx_ring->dev,
7869                                 "Detected Tx Unit Hang\n"
7870                                 "  Tx Queue             <%d>\n"
7871                                 "  TDH                  <%x>\n"
7872                                 "  TDT                  <%x>\n"
7873                                 "  next_to_use          <%x>\n"
7874                                 "  next_to_clean        <%x>\n"
7875                                 "buffer_info[next_to_clean]\n"
7876                                 "  time_stamp           <%lx>\n"
7877                                 "  next_to_watch        <%p>\n"
7878                                 "  jiffies              <%lx>\n"
7879                                 "  desc.status          <%x>\n",
7880                                 tx_ring->queue_index,
7881                                 rd32(E1000_TDH(tx_ring->reg_idx)),
7882                                 readl(tx_ring->tail),
7883                                 tx_ring->next_to_use,
7884                                 tx_ring->next_to_clean,
7885                                 tx_buffer->time_stamp,
7886                                 tx_buffer->next_to_watch,
7887                                 jiffies,
7888                                 tx_buffer->next_to_watch->wb.status);
7889                         netif_stop_subqueue(tx_ring->netdev,
7890                                             tx_ring->queue_index);
7891
7892                         /* we are about to reset, no point in enabling stuff */
7893                         return true;
7894                 }
7895         }
7896
7897 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
7898         if (unlikely(total_packets &&
7899             netif_carrier_ok(tx_ring->netdev) &&
7900             igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
7901                 /* Make sure that anybody stopping the queue after this
7902                  * sees the new next_to_clean.
7903                  */
7904                 smp_mb();
7905                 if (__netif_subqueue_stopped(tx_ring->netdev,
7906                                              tx_ring->queue_index) &&
7907                     !(test_bit(__IGB_DOWN, &adapter->state))) {
7908                         netif_wake_subqueue(tx_ring->netdev,
7909                                             tx_ring->queue_index);
7910
7911                         u64_stats_update_begin(&tx_ring->tx_syncp);
7912                         tx_ring->tx_stats.restart_queue++;
7913                         u64_stats_update_end(&tx_ring->tx_syncp);
7914                 }
7915         }
7916
7917         return !!budget;
7918 }
7919
7920 /**
7921  *  igb_reuse_rx_page - page flip buffer and store it back on the ring
7922  *  @rx_ring: rx descriptor ring to store buffers on
7923  *  @old_buff: donor buffer to have page reused
7924  *
7925  *  Synchronizes page for reuse by the adapter
7926  **/
7927 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
7928                               struct igb_rx_buffer *old_buff)
7929 {
7930         struct igb_rx_buffer *new_buff;
7931         u16 nta = rx_ring->next_to_alloc;
7932
7933         new_buff = &rx_ring->rx_buffer_info[nta];
7934
7935         /* update, and store next to alloc */
7936         nta++;
7937         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
7938
7939         /* Transfer page from old buffer to new buffer.
7940          * Move each member individually to avoid possible store
7941          * forwarding stalls.
7942          */
7943         new_buff->dma           = old_buff->dma;
7944         new_buff->page          = old_buff->page;
7945         new_buff->page_offset   = old_buff->page_offset;
7946         new_buff->pagecnt_bias  = old_buff->pagecnt_bias;
7947 }
7948
7949 static inline bool igb_page_is_reserved(struct page *page)
7950 {
7951         return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
7952 }
7953
7954 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer)
7955 {
7956         unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
7957         struct page *page = rx_buffer->page;
7958
7959         /* avoid re-using remote pages */
7960         if (unlikely(igb_page_is_reserved(page)))
7961                 return false;
7962
7963 #if (PAGE_SIZE < 8192)
7964         /* if we are only owner of page we can reuse it */
7965         if (unlikely((page_ref_count(page) - pagecnt_bias) > 1))
7966                 return false;
7967 #else
7968 #define IGB_LAST_OFFSET \
7969         (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048)
7970
7971         if (rx_buffer->page_offset > IGB_LAST_OFFSET)
7972                 return false;
7973 #endif
7974
7975         /* If we have drained the page fragment pool we need to update
7976          * the pagecnt_bias and page count so that we fully restock the
7977          * number of references the driver holds.
7978          */
7979         if (unlikely(!pagecnt_bias)) {
7980                 page_ref_add(page, USHRT_MAX);
7981                 rx_buffer->pagecnt_bias = USHRT_MAX;
7982         }
7983
7984         return true;
7985 }
7986
7987 /**
7988  *  igb_add_rx_frag - Add contents of Rx buffer to sk_buff
7989  *  @rx_ring: rx descriptor ring to transact packets on
7990  *  @rx_buffer: buffer containing page to add
7991  *  @skb: sk_buff to place the data into
7992  *  @size: size of buffer to be added
7993  *
7994  *  This function will add the data contained in rx_buffer->page to the skb.
7995  **/
7996 static void igb_add_rx_frag(struct igb_ring *rx_ring,
7997                             struct igb_rx_buffer *rx_buffer,
7998                             struct sk_buff *skb,
7999                             unsigned int size)
8000 {
8001 #if (PAGE_SIZE < 8192)
8002         unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8003 #else
8004         unsigned int truesize = ring_uses_build_skb(rx_ring) ?
8005                                 SKB_DATA_ALIGN(IGB_SKB_PAD + size) :
8006                                 SKB_DATA_ALIGN(size);
8007 #endif
8008         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
8009                         rx_buffer->page_offset, size, truesize);
8010 #if (PAGE_SIZE < 8192)
8011         rx_buffer->page_offset ^= truesize;
8012 #else
8013         rx_buffer->page_offset += truesize;
8014 #endif
8015 }
8016
8017 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring,
8018                                          struct igb_rx_buffer *rx_buffer,
8019                                          union e1000_adv_rx_desc *rx_desc,
8020                                          unsigned int size)
8021 {
8022         void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
8023 #if (PAGE_SIZE < 8192)
8024         unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8025 #else
8026         unsigned int truesize = SKB_DATA_ALIGN(size);
8027 #endif
8028         unsigned int headlen;
8029         struct sk_buff *skb;
8030
8031         /* prefetch first cache line of first page */
8032         prefetch(va);
8033 #if L1_CACHE_BYTES < 128
8034         prefetch(va + L1_CACHE_BYTES);
8035 #endif
8036
8037         /* allocate a skb to store the frags */
8038         skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
8039         if (unlikely(!skb))
8040                 return NULL;
8041
8042         if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
8043                 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
8044                 va += IGB_TS_HDR_LEN;
8045                 size -= IGB_TS_HDR_LEN;
8046         }
8047
8048         /* Determine available headroom for copy */
8049         headlen = size;
8050         if (headlen > IGB_RX_HDR_LEN)
8051                 headlen = eth_get_headlen(va, IGB_RX_HDR_LEN);
8052
8053         /* align pull length to size of long to optimize memcpy performance */
8054         memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long)));
8055
8056         /* update all of the pointers */
8057         size -= headlen;
8058         if (size) {
8059                 skb_add_rx_frag(skb, 0, rx_buffer->page,
8060                                 (va + headlen) - page_address(rx_buffer->page),
8061                                 size, truesize);
8062 #if (PAGE_SIZE < 8192)
8063                 rx_buffer->page_offset ^= truesize;
8064 #else
8065                 rx_buffer->page_offset += truesize;
8066 #endif
8067         } else {
8068                 rx_buffer->pagecnt_bias++;
8069         }
8070
8071         return skb;
8072 }
8073
8074 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring,
8075                                      struct igb_rx_buffer *rx_buffer,
8076                                      union e1000_adv_rx_desc *rx_desc,
8077                                      unsigned int size)
8078 {
8079         void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
8080 #if (PAGE_SIZE < 8192)
8081         unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8082 #else
8083         unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
8084                                 SKB_DATA_ALIGN(IGB_SKB_PAD + size);
8085 #endif
8086         struct sk_buff *skb;
8087
8088         /* prefetch first cache line of first page */
8089         prefetch(va);
8090 #if L1_CACHE_BYTES < 128
8091         prefetch(va + L1_CACHE_BYTES);
8092 #endif
8093
8094         /* build an skb around the page buffer */
8095         skb = build_skb(va - IGB_SKB_PAD, truesize);
8096         if (unlikely(!skb))
8097                 return NULL;
8098
8099         /* update pointers within the skb to store the data */
8100         skb_reserve(skb, IGB_SKB_PAD);
8101         __skb_put(skb, size);
8102
8103         /* pull timestamp out of packet data */
8104         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
8105                 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb);
8106                 __skb_pull(skb, IGB_TS_HDR_LEN);
8107         }
8108
8109         /* update buffer offset */
8110 #if (PAGE_SIZE < 8192)
8111         rx_buffer->page_offset ^= truesize;
8112 #else
8113         rx_buffer->page_offset += truesize;
8114 #endif
8115
8116         return skb;
8117 }
8118
8119 static inline void igb_rx_checksum(struct igb_ring *ring,
8120                                    union e1000_adv_rx_desc *rx_desc,
8121                                    struct sk_buff *skb)
8122 {
8123         skb_checksum_none_assert(skb);
8124
8125         /* Ignore Checksum bit is set */
8126         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
8127                 return;
8128
8129         /* Rx checksum disabled via ethtool */
8130         if (!(ring->netdev->features & NETIF_F_RXCSUM))
8131                 return;
8132
8133         /* TCP/UDP checksum error bit is set */
8134         if (igb_test_staterr(rx_desc,
8135                              E1000_RXDEXT_STATERR_TCPE |
8136                              E1000_RXDEXT_STATERR_IPE)) {
8137                 /* work around errata with sctp packets where the TCPE aka
8138                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
8139                  * packets, (aka let the stack check the crc32c)
8140                  */
8141                 if (!((skb->len == 60) &&
8142                       test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
8143                         u64_stats_update_begin(&ring->rx_syncp);
8144                         ring->rx_stats.csum_err++;
8145                         u64_stats_update_end(&ring->rx_syncp);
8146                 }
8147                 /* let the stack verify checksum errors */
8148                 return;
8149         }
8150         /* It must be a TCP or UDP packet with a valid checksum */
8151         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
8152                                       E1000_RXD_STAT_UDPCS))
8153                 skb->ip_summed = CHECKSUM_UNNECESSARY;
8154
8155         dev_dbg(ring->dev, "cksum success: bits %08X\n",
8156                 le32_to_cpu(rx_desc->wb.upper.status_error));
8157 }
8158
8159 static inline void igb_rx_hash(struct igb_ring *ring,
8160                                union e1000_adv_rx_desc *rx_desc,
8161                                struct sk_buff *skb)
8162 {
8163         if (ring->netdev->features & NETIF_F_RXHASH)
8164                 skb_set_hash(skb,
8165                              le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
8166                              PKT_HASH_TYPE_L3);
8167 }
8168
8169 /**
8170  *  igb_is_non_eop - process handling of non-EOP buffers
8171  *  @rx_ring: Rx ring being processed
8172  *  @rx_desc: Rx descriptor for current buffer
8173  *  @skb: current socket buffer containing buffer in progress
8174  *
8175  *  This function updates next to clean.  If the buffer is an EOP buffer
8176  *  this function exits returning false, otherwise it will place the
8177  *  sk_buff in the next buffer to be chained and return true indicating
8178  *  that this is in fact a non-EOP buffer.
8179  **/
8180 static bool igb_is_non_eop(struct igb_ring *rx_ring,
8181                            union e1000_adv_rx_desc *rx_desc)
8182 {
8183         u32 ntc = rx_ring->next_to_clean + 1;
8184
8185         /* fetch, update, and store next to clean */
8186         ntc = (ntc < rx_ring->count) ? ntc : 0;
8187         rx_ring->next_to_clean = ntc;
8188
8189         prefetch(IGB_RX_DESC(rx_ring, ntc));
8190
8191         if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
8192                 return false;
8193
8194         return true;
8195 }
8196
8197 /**
8198  *  igb_cleanup_headers - Correct corrupted or empty headers
8199  *  @rx_ring: rx descriptor ring packet is being transacted on
8200  *  @rx_desc: pointer to the EOP Rx descriptor
8201  *  @skb: pointer to current skb being fixed
8202  *
8203  *  Address the case where we are pulling data in on pages only
8204  *  and as such no data is present in the skb header.
8205  *
8206  *  In addition if skb is not at least 60 bytes we need to pad it so that
8207  *  it is large enough to qualify as a valid Ethernet frame.
8208  *
8209  *  Returns true if an error was encountered and skb was freed.
8210  **/
8211 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
8212                                 union e1000_adv_rx_desc *rx_desc,
8213                                 struct sk_buff *skb)
8214 {
8215         if (unlikely((igb_test_staterr(rx_desc,
8216                                        E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
8217                 struct net_device *netdev = rx_ring->netdev;
8218                 if (!(netdev->features & NETIF_F_RXALL)) {
8219                         dev_kfree_skb_any(skb);
8220                         return true;
8221                 }
8222         }
8223
8224         /* if eth_skb_pad returns an error the skb was freed */
8225         if (eth_skb_pad(skb))
8226                 return true;
8227
8228         return false;
8229 }
8230
8231 /**
8232  *  igb_process_skb_fields - Populate skb header fields from Rx descriptor
8233  *  @rx_ring: rx descriptor ring packet is being transacted on
8234  *  @rx_desc: pointer to the EOP Rx descriptor
8235  *  @skb: pointer to current skb being populated
8236  *
8237  *  This function checks the ring, descriptor, and packet information in
8238  *  order to populate the hash, checksum, VLAN, timestamp, protocol, and
8239  *  other fields within the skb.
8240  **/
8241 static void igb_process_skb_fields(struct igb_ring *rx_ring,
8242                                    union e1000_adv_rx_desc *rx_desc,
8243                                    struct sk_buff *skb)
8244 {
8245         struct net_device *dev = rx_ring->netdev;
8246
8247         igb_rx_hash(rx_ring, rx_desc, skb);
8248
8249         igb_rx_checksum(rx_ring, rx_desc, skb);
8250
8251         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
8252             !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
8253                 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
8254
8255         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
8256             igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
8257                 u16 vid;
8258
8259                 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
8260                     test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
8261                         vid = be16_to_cpu(rx_desc->wb.upper.vlan);
8262                 else
8263                         vid = le16_to_cpu(rx_desc->wb.upper.vlan);
8264
8265                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
8266         }
8267
8268         skb_record_rx_queue(skb, rx_ring->queue_index);
8269
8270         skb->protocol = eth_type_trans(skb, rx_ring->netdev);
8271 }
8272
8273 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring,
8274                                                const unsigned int size)
8275 {
8276         struct igb_rx_buffer *rx_buffer;
8277
8278         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
8279         prefetchw(rx_buffer->page);
8280
8281         /* we are reusing so sync this buffer for CPU use */
8282         dma_sync_single_range_for_cpu(rx_ring->dev,
8283                                       rx_buffer->dma,
8284                                       rx_buffer->page_offset,
8285                                       size,
8286                                       DMA_FROM_DEVICE);
8287
8288         rx_buffer->pagecnt_bias--;
8289
8290         return rx_buffer;
8291 }
8292
8293 static void igb_put_rx_buffer(struct igb_ring *rx_ring,
8294                               struct igb_rx_buffer *rx_buffer)
8295 {
8296         if (igb_can_reuse_rx_page(rx_buffer)) {
8297                 /* hand second half of page back to the ring */
8298                 igb_reuse_rx_page(rx_ring, rx_buffer);
8299         } else {
8300                 /* We are not reusing the buffer so unmap it and free
8301                  * any references we are holding to it
8302                  */
8303                 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
8304                                      igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
8305                                      IGB_RX_DMA_ATTR);
8306                 __page_frag_cache_drain(rx_buffer->page,
8307                                         rx_buffer->pagecnt_bias);
8308         }
8309
8310         /* clear contents of rx_buffer */
8311         rx_buffer->page = NULL;
8312 }
8313
8314 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
8315 {
8316         struct igb_ring *rx_ring = q_vector->rx.ring;
8317         struct sk_buff *skb = rx_ring->skb;
8318         unsigned int total_bytes = 0, total_packets = 0;
8319         u16 cleaned_count = igb_desc_unused(rx_ring);
8320
8321         while (likely(total_packets < budget)) {
8322                 union e1000_adv_rx_desc *rx_desc;
8323                 struct igb_rx_buffer *rx_buffer;
8324                 unsigned int size;
8325
8326                 /* return some buffers to hardware, one at a time is too slow */
8327                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
8328                         igb_alloc_rx_buffers(rx_ring, cleaned_count);
8329                         cleaned_count = 0;
8330                 }
8331
8332                 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
8333                 size = le16_to_cpu(rx_desc->wb.upper.length);
8334                 if (!size)
8335                         break;
8336
8337                 /* This memory barrier is needed to keep us from reading
8338                  * any other fields out of the rx_desc until we know the
8339                  * descriptor has been written back
8340                  */
8341                 dma_rmb();
8342
8343                 rx_buffer = igb_get_rx_buffer(rx_ring, size);
8344
8345                 /* retrieve a buffer from the ring */
8346                 if (skb)
8347                         igb_add_rx_frag(rx_ring, rx_buffer, skb, size);
8348                 else if (ring_uses_build_skb(rx_ring))
8349                         skb = igb_build_skb(rx_ring, rx_buffer, rx_desc, size);
8350                 else
8351                         skb = igb_construct_skb(rx_ring, rx_buffer,
8352                                                 rx_desc, size);
8353
8354                 /* exit if we failed to retrieve a buffer */
8355                 if (!skb) {
8356                         rx_ring->rx_stats.alloc_failed++;
8357                         rx_buffer->pagecnt_bias++;
8358                         break;
8359                 }
8360
8361                 igb_put_rx_buffer(rx_ring, rx_buffer);
8362                 cleaned_count++;
8363
8364                 /* fetch next buffer in frame if non-eop */
8365                 if (igb_is_non_eop(rx_ring, rx_desc))
8366                         continue;
8367
8368                 /* verify the packet layout is correct */
8369                 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
8370                         skb = NULL;
8371                         continue;
8372                 }
8373
8374                 /* probably a little skewed due to removing CRC */
8375                 total_bytes += skb->len;
8376
8377                 /* populate checksum, timestamp, VLAN, and protocol */
8378                 igb_process_skb_fields(rx_ring, rx_desc, skb);
8379
8380                 napi_gro_receive(&q_vector->napi, skb);
8381
8382                 /* reset skb pointer */
8383                 skb = NULL;
8384
8385                 /* update budget accounting */
8386                 total_packets++;
8387         }
8388
8389         /* place incomplete frames back on ring for completion */
8390         rx_ring->skb = skb;
8391
8392         u64_stats_update_begin(&rx_ring->rx_syncp);
8393         rx_ring->rx_stats.packets += total_packets;
8394         rx_ring->rx_stats.bytes += total_bytes;
8395         u64_stats_update_end(&rx_ring->rx_syncp);
8396         q_vector->rx.total_packets += total_packets;
8397         q_vector->rx.total_bytes += total_bytes;
8398
8399         if (cleaned_count)
8400                 igb_alloc_rx_buffers(rx_ring, cleaned_count);
8401
8402         return total_packets;
8403 }
8404
8405 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring)
8406 {
8407         return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0;
8408 }
8409
8410 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
8411                                   struct igb_rx_buffer *bi)
8412 {
8413         struct page *page = bi->page;
8414         dma_addr_t dma;
8415
8416         /* since we are recycling buffers we should seldom need to alloc */
8417         if (likely(page))
8418                 return true;
8419
8420         /* alloc new page for storage */
8421         page = dev_alloc_pages(igb_rx_pg_order(rx_ring));
8422         if (unlikely(!page)) {
8423                 rx_ring->rx_stats.alloc_failed++;
8424                 return false;
8425         }
8426
8427         /* map page for use */
8428         dma = dma_map_page_attrs(rx_ring->dev, page, 0,
8429                                  igb_rx_pg_size(rx_ring),
8430                                  DMA_FROM_DEVICE,
8431                                  IGB_RX_DMA_ATTR);
8432
8433         /* if mapping failed free memory back to system since
8434          * there isn't much point in holding memory we can't use
8435          */
8436         if (dma_mapping_error(rx_ring->dev, dma)) {
8437                 __free_pages(page, igb_rx_pg_order(rx_ring));
8438
8439                 rx_ring->rx_stats.alloc_failed++;
8440                 return false;
8441         }
8442
8443         bi->dma = dma;
8444         bi->page = page;
8445         bi->page_offset = igb_rx_offset(rx_ring);
8446         bi->pagecnt_bias = 1;
8447
8448         return true;
8449 }
8450
8451 /**
8452  *  igb_alloc_rx_buffers - Replace used receive buffers; packet split
8453  *  @adapter: address of board private structure
8454  **/
8455 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
8456 {
8457         union e1000_adv_rx_desc *rx_desc;
8458         struct igb_rx_buffer *bi;
8459         u16 i = rx_ring->next_to_use;
8460         u16 bufsz;
8461
8462         /* nothing to do */
8463         if (!cleaned_count)
8464                 return;
8465
8466         rx_desc = IGB_RX_DESC(rx_ring, i);
8467         bi = &rx_ring->rx_buffer_info[i];
8468         i -= rx_ring->count;
8469
8470         bufsz = igb_rx_bufsz(rx_ring);
8471
8472         do {
8473                 if (!igb_alloc_mapped_page(rx_ring, bi))
8474                         break;
8475
8476                 /* sync the buffer for use by the device */
8477                 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
8478                                                  bi->page_offset, bufsz,
8479                                                  DMA_FROM_DEVICE);
8480
8481                 /* Refresh the desc even if buffer_addrs didn't change
8482                  * because each write-back erases this info.
8483                  */
8484                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
8485
8486                 rx_desc++;
8487                 bi++;
8488                 i++;
8489                 if (unlikely(!i)) {
8490                         rx_desc = IGB_RX_DESC(rx_ring, 0);
8491                         bi = rx_ring->rx_buffer_info;
8492                         i -= rx_ring->count;
8493                 }
8494
8495                 /* clear the length for the next_to_use descriptor */
8496                 rx_desc->wb.upper.length = 0;
8497
8498                 cleaned_count--;
8499         } while (cleaned_count);
8500
8501         i += rx_ring->count;
8502
8503         if (rx_ring->next_to_use != i) {
8504                 /* record the next descriptor to use */
8505                 rx_ring->next_to_use = i;
8506
8507                 /* update next to alloc since we have filled the ring */
8508                 rx_ring->next_to_alloc = i;
8509
8510                 /* Force memory writes to complete before letting h/w
8511                  * know there are new descriptors to fetch.  (Only
8512                  * applicable for weak-ordered memory model archs,
8513                  * such as IA-64).
8514                  */
8515                 dma_wmb();
8516                 writel(i, rx_ring->tail);
8517         }
8518 }
8519
8520 /**
8521  * igb_mii_ioctl -
8522  * @netdev:
8523  * @ifreq:
8524  * @cmd:
8525  **/
8526 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
8527 {
8528         struct igb_adapter *adapter = netdev_priv(netdev);
8529         struct mii_ioctl_data *data = if_mii(ifr);
8530
8531         if (adapter->hw.phy.media_type != e1000_media_type_copper)
8532                 return -EOPNOTSUPP;
8533
8534         switch (cmd) {
8535         case SIOCGMIIPHY:
8536                 data->phy_id = adapter->hw.phy.addr;
8537                 break;
8538         case SIOCGMIIREG:
8539                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
8540                                      &data->val_out))
8541                         return -EIO;
8542                 break;
8543         case SIOCSMIIREG:
8544         default:
8545                 return -EOPNOTSUPP;
8546         }
8547         return 0;
8548 }
8549
8550 /**
8551  * igb_ioctl -
8552  * @netdev:
8553  * @ifreq:
8554  * @cmd:
8555  **/
8556 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
8557 {
8558         switch (cmd) {
8559         case SIOCGMIIPHY:
8560         case SIOCGMIIREG:
8561         case SIOCSMIIREG:
8562                 return igb_mii_ioctl(netdev, ifr, cmd);
8563         case SIOCGHWTSTAMP:
8564                 return igb_ptp_get_ts_config(netdev, ifr);
8565         case SIOCSHWTSTAMP:
8566                 return igb_ptp_set_ts_config(netdev, ifr);
8567         default:
8568                 return -EOPNOTSUPP;
8569         }
8570 }
8571
8572 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
8573 {
8574         struct igb_adapter *adapter = hw->back;
8575
8576         pci_read_config_word(adapter->pdev, reg, value);
8577 }
8578
8579 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
8580 {
8581         struct igb_adapter *adapter = hw->back;
8582
8583         pci_write_config_word(adapter->pdev, reg, *value);
8584 }
8585
8586 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
8587 {
8588         struct igb_adapter *adapter = hw->back;
8589
8590         if (pcie_capability_read_word(adapter->pdev, reg, value))
8591                 return -E1000_ERR_CONFIG;
8592
8593         return 0;
8594 }
8595
8596 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
8597 {
8598         struct igb_adapter *adapter = hw->back;
8599
8600         if (pcie_capability_write_word(adapter->pdev, reg, *value))
8601                 return -E1000_ERR_CONFIG;
8602
8603         return 0;
8604 }
8605
8606 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
8607 {
8608         struct igb_adapter *adapter = netdev_priv(netdev);
8609         struct e1000_hw *hw = &adapter->hw;
8610         u32 ctrl, rctl;
8611         bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
8612
8613         if (enable) {
8614                 /* enable VLAN tag insert/strip */
8615                 ctrl = rd32(E1000_CTRL);
8616                 ctrl |= E1000_CTRL_VME;
8617                 wr32(E1000_CTRL, ctrl);
8618
8619                 /* Disable CFI check */
8620                 rctl = rd32(E1000_RCTL);
8621                 rctl &= ~E1000_RCTL_CFIEN;
8622                 wr32(E1000_RCTL, rctl);
8623         } else {
8624                 /* disable VLAN tag insert/strip */
8625                 ctrl = rd32(E1000_CTRL);
8626                 ctrl &= ~E1000_CTRL_VME;
8627                 wr32(E1000_CTRL, ctrl);
8628         }
8629
8630         igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
8631 }
8632
8633 static int igb_vlan_rx_add_vid(struct net_device *netdev,
8634                                __be16 proto, u16 vid)
8635 {
8636         struct igb_adapter *adapter = netdev_priv(netdev);
8637         struct e1000_hw *hw = &adapter->hw;
8638         int pf_id = adapter->vfs_allocated_count;
8639
8640         /* add the filter since PF can receive vlans w/o entry in vlvf */
8641         if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
8642                 igb_vfta_set(hw, vid, pf_id, true, !!vid);
8643
8644         set_bit(vid, adapter->active_vlans);
8645
8646         return 0;
8647 }
8648
8649 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
8650                                 __be16 proto, u16 vid)
8651 {
8652         struct igb_adapter *adapter = netdev_priv(netdev);
8653         int pf_id = adapter->vfs_allocated_count;
8654         struct e1000_hw *hw = &adapter->hw;
8655
8656         /* remove VID from filter table */
8657         if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
8658                 igb_vfta_set(hw, vid, pf_id, false, true);
8659
8660         clear_bit(vid, adapter->active_vlans);
8661
8662         return 0;
8663 }
8664
8665 static void igb_restore_vlan(struct igb_adapter *adapter)
8666 {
8667         u16 vid = 1;
8668
8669         igb_vlan_mode(adapter->netdev, adapter->netdev->features);
8670         igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
8671
8672         for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
8673                 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
8674 }
8675
8676 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
8677 {
8678         struct pci_dev *pdev = adapter->pdev;
8679         struct e1000_mac_info *mac = &adapter->hw.mac;
8680
8681         mac->autoneg = 0;
8682
8683         /* Make sure dplx is at most 1 bit and lsb of speed is not set
8684          * for the switch() below to work
8685          */
8686         if ((spd & 1) || (dplx & ~1))
8687                 goto err_inval;
8688
8689         /* Fiber NIC's only allow 1000 gbps Full duplex
8690          * and 100Mbps Full duplex for 100baseFx sfp
8691          */
8692         if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
8693                 switch (spd + dplx) {
8694                 case SPEED_10 + DUPLEX_HALF:
8695                 case SPEED_10 + DUPLEX_FULL:
8696                 case SPEED_100 + DUPLEX_HALF:
8697                         goto err_inval;
8698                 default:
8699                         break;
8700                 }
8701         }
8702
8703         switch (spd + dplx) {
8704         case SPEED_10 + DUPLEX_HALF:
8705                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
8706                 break;
8707         case SPEED_10 + DUPLEX_FULL:
8708                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
8709                 break;
8710         case SPEED_100 + DUPLEX_HALF:
8711                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
8712                 break;
8713         case SPEED_100 + DUPLEX_FULL:
8714                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
8715                 break;
8716         case SPEED_1000 + DUPLEX_FULL:
8717                 mac->autoneg = 1;
8718                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
8719                 break;
8720         case SPEED_1000 + DUPLEX_HALF: /* not supported */
8721         default:
8722                 goto err_inval;
8723         }
8724
8725         /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
8726         adapter->hw.phy.mdix = AUTO_ALL_MODES;
8727
8728         return 0;
8729
8730 err_inval:
8731         dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
8732         return -EINVAL;
8733 }
8734
8735 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
8736                           bool runtime)
8737 {
8738         struct net_device *netdev = pci_get_drvdata(pdev);
8739         struct igb_adapter *adapter = netdev_priv(netdev);
8740         struct e1000_hw *hw = &adapter->hw;
8741         u32 ctrl, rctl, status;
8742         u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
8743         bool wake;
8744
8745         rtnl_lock();
8746         netif_device_detach(netdev);
8747
8748         if (netif_running(netdev))
8749                 __igb_close(netdev, true);
8750
8751         igb_ptp_suspend(adapter);
8752
8753         igb_clear_interrupt_scheme(adapter);
8754         rtnl_unlock();
8755
8756         status = rd32(E1000_STATUS);
8757         if (status & E1000_STATUS_LU)
8758                 wufc &= ~E1000_WUFC_LNKC;
8759
8760         if (wufc) {
8761                 igb_setup_rctl(adapter);
8762                 igb_set_rx_mode(netdev);
8763
8764                 /* turn on all-multi mode if wake on multicast is enabled */
8765                 if (wufc & E1000_WUFC_MC) {
8766                         rctl = rd32(E1000_RCTL);
8767                         rctl |= E1000_RCTL_MPE;
8768                         wr32(E1000_RCTL, rctl);
8769                 }
8770
8771                 ctrl = rd32(E1000_CTRL);
8772                 ctrl |= E1000_CTRL_ADVD3WUC;
8773                 wr32(E1000_CTRL, ctrl);
8774
8775                 /* Allow time for pending master requests to run */
8776                 igb_disable_pcie_master(hw);
8777
8778                 wr32(E1000_WUC, E1000_WUC_PME_EN);
8779                 wr32(E1000_WUFC, wufc);
8780         } else {
8781                 wr32(E1000_WUC, 0);
8782                 wr32(E1000_WUFC, 0);
8783         }
8784
8785         wake = wufc || adapter->en_mng_pt;
8786         if (!wake)
8787                 igb_power_down_link(adapter);
8788         else
8789                 igb_power_up_link(adapter);
8790
8791         if (enable_wake)
8792                 *enable_wake = wake;
8793
8794         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
8795          * would have already happened in close and is redundant.
8796          */
8797         igb_release_hw_control(adapter);
8798
8799         pci_disable_device(pdev);
8800
8801         return 0;
8802 }
8803
8804 static void igb_deliver_wake_packet(struct net_device *netdev)
8805 {
8806         struct igb_adapter *adapter = netdev_priv(netdev);
8807         struct e1000_hw *hw = &adapter->hw;
8808         struct sk_buff *skb;
8809         u32 wupl;
8810
8811         wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK;
8812
8813         /* WUPM stores only the first 128 bytes of the wake packet.
8814          * Read the packet only if we have the whole thing.
8815          */
8816         if ((wupl == 0) || (wupl > E1000_WUPM_BYTES))
8817                 return;
8818
8819         skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES);
8820         if (!skb)
8821                 return;
8822
8823         skb_put(skb, wupl);
8824
8825         /* Ensure reads are 32-bit aligned */
8826         wupl = roundup(wupl, 4);
8827
8828         memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl);
8829
8830         skb->protocol = eth_type_trans(skb, netdev);
8831         netif_rx(skb);
8832 }
8833
8834 static int __maybe_unused igb_suspend(struct device *dev)
8835 {
8836         return __igb_shutdown(to_pci_dev(dev), NULL, 0);
8837 }
8838
8839 static int __maybe_unused igb_resume(struct device *dev)
8840 {
8841         struct pci_dev *pdev = to_pci_dev(dev);
8842         struct net_device *netdev = pci_get_drvdata(pdev);
8843         struct igb_adapter *adapter = netdev_priv(netdev);
8844         struct e1000_hw *hw = &adapter->hw;
8845         u32 err, val;
8846
8847         pci_set_power_state(pdev, PCI_D0);
8848         pci_restore_state(pdev);
8849         pci_save_state(pdev);
8850
8851         if (!pci_device_is_present(pdev))
8852                 return -ENODEV;
8853         err = pci_enable_device_mem(pdev);
8854         if (err) {
8855                 dev_err(&pdev->dev,
8856                         "igb: Cannot enable PCI device from suspend\n");
8857                 return err;
8858         }
8859         pci_set_master(pdev);
8860
8861         pci_enable_wake(pdev, PCI_D3hot, 0);
8862         pci_enable_wake(pdev, PCI_D3cold, 0);
8863
8864         if (igb_init_interrupt_scheme(adapter, true)) {
8865                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8866                 return -ENOMEM;
8867         }
8868
8869         igb_reset(adapter);
8870
8871         /* let the f/w know that the h/w is now under the control of the
8872          * driver.
8873          */
8874         igb_get_hw_control(adapter);
8875
8876         val = rd32(E1000_WUS);
8877         if (val & WAKE_PKT_WUS)
8878                 igb_deliver_wake_packet(netdev);
8879
8880         wr32(E1000_WUS, ~0);
8881
8882         rtnl_lock();
8883         if (!err && netif_running(netdev))
8884                 err = __igb_open(netdev, true);
8885
8886         if (!err)
8887                 netif_device_attach(netdev);
8888         rtnl_unlock();
8889
8890         return err;
8891 }
8892
8893 static int __maybe_unused igb_runtime_idle(struct device *dev)
8894 {
8895         struct pci_dev *pdev = to_pci_dev(dev);
8896         struct net_device *netdev = pci_get_drvdata(pdev);
8897         struct igb_adapter *adapter = netdev_priv(netdev);
8898
8899         if (!igb_has_link(adapter))
8900                 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
8901
8902         return -EBUSY;
8903 }
8904
8905 static int __maybe_unused igb_runtime_suspend(struct device *dev)
8906 {
8907         return __igb_shutdown(to_pci_dev(dev), NULL, 1);
8908 }
8909
8910 static int __maybe_unused igb_runtime_resume(struct device *dev)
8911 {
8912         return igb_resume(dev);
8913 }
8914
8915 static void igb_shutdown(struct pci_dev *pdev)
8916 {
8917         bool wake;
8918
8919         __igb_shutdown(pdev, &wake, 0);
8920
8921         if (system_state == SYSTEM_POWER_OFF) {
8922                 pci_wake_from_d3(pdev, wake);
8923                 pci_set_power_state(pdev, PCI_D3hot);
8924         }
8925 }
8926
8927 #ifdef CONFIG_PCI_IOV
8928 static int igb_sriov_reinit(struct pci_dev *dev)
8929 {
8930         struct net_device *netdev = pci_get_drvdata(dev);
8931         struct igb_adapter *adapter = netdev_priv(netdev);
8932         struct pci_dev *pdev = adapter->pdev;
8933
8934         rtnl_lock();
8935
8936         if (netif_running(netdev))
8937                 igb_close(netdev);
8938         else
8939                 igb_reset(adapter);
8940
8941         igb_clear_interrupt_scheme(adapter);
8942
8943         igb_init_queue_configuration(adapter);
8944
8945         if (igb_init_interrupt_scheme(adapter, true)) {
8946                 rtnl_unlock();
8947                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8948                 return -ENOMEM;
8949         }
8950
8951         if (netif_running(netdev))
8952                 igb_open(netdev);
8953
8954         rtnl_unlock();
8955
8956         return 0;
8957 }
8958
8959 static int igb_pci_disable_sriov(struct pci_dev *dev)
8960 {
8961         int err = igb_disable_sriov(dev);
8962
8963         if (!err)
8964                 err = igb_sriov_reinit(dev);
8965
8966         return err;
8967 }
8968
8969 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
8970 {
8971         int err = igb_enable_sriov(dev, num_vfs);
8972
8973         if (err)
8974                 goto out;
8975
8976         err = igb_sriov_reinit(dev);
8977         if (!err)
8978                 return num_vfs;
8979
8980 out:
8981         return err;
8982 }
8983
8984 #endif
8985 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
8986 {
8987 #ifdef CONFIG_PCI_IOV
8988         if (num_vfs == 0)
8989                 return igb_pci_disable_sriov(dev);
8990         else
8991                 return igb_pci_enable_sriov(dev, num_vfs);
8992 #endif
8993         return 0;
8994 }
8995
8996 /**
8997  *  igb_io_error_detected - called when PCI error is detected
8998  *  @pdev: Pointer to PCI device
8999  *  @state: The current pci connection state
9000  *
9001  *  This function is called after a PCI bus error affecting
9002  *  this device has been detected.
9003  **/
9004 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
9005                                               pci_channel_state_t state)
9006 {
9007         struct net_device *netdev = pci_get_drvdata(pdev);
9008         struct igb_adapter *adapter = netdev_priv(netdev);
9009
9010         netif_device_detach(netdev);
9011
9012         if (state == pci_channel_io_perm_failure)
9013                 return PCI_ERS_RESULT_DISCONNECT;
9014
9015         if (netif_running(netdev))
9016                 igb_down(adapter);
9017         pci_disable_device(pdev);
9018
9019         /* Request a slot slot reset. */
9020         return PCI_ERS_RESULT_NEED_RESET;
9021 }
9022
9023 /**
9024  *  igb_io_slot_reset - called after the pci bus has been reset.
9025  *  @pdev: Pointer to PCI device
9026  *
9027  *  Restart the card from scratch, as if from a cold-boot. Implementation
9028  *  resembles the first-half of the igb_resume routine.
9029  **/
9030 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
9031 {
9032         struct net_device *netdev = pci_get_drvdata(pdev);
9033         struct igb_adapter *adapter = netdev_priv(netdev);
9034         struct e1000_hw *hw = &adapter->hw;
9035         pci_ers_result_t result;
9036
9037         if (pci_enable_device_mem(pdev)) {
9038                 dev_err(&pdev->dev,
9039                         "Cannot re-enable PCI device after reset.\n");
9040                 result = PCI_ERS_RESULT_DISCONNECT;
9041         } else {
9042                 pci_set_master(pdev);
9043                 pci_restore_state(pdev);
9044                 pci_save_state(pdev);
9045
9046                 pci_enable_wake(pdev, PCI_D3hot, 0);
9047                 pci_enable_wake(pdev, PCI_D3cold, 0);
9048
9049                 /* In case of PCI error, adapter lose its HW address
9050                  * so we should re-assign it here.
9051                  */
9052                 hw->hw_addr = adapter->io_addr;
9053
9054                 igb_reset(adapter);
9055                 wr32(E1000_WUS, ~0);
9056                 result = PCI_ERS_RESULT_RECOVERED;
9057         }
9058
9059         return result;
9060 }
9061
9062 /**
9063  *  igb_io_resume - called when traffic can start flowing again.
9064  *  @pdev: Pointer to PCI device
9065  *
9066  *  This callback is called when the error recovery driver tells us that
9067  *  its OK to resume normal operation. Implementation resembles the
9068  *  second-half of the igb_resume routine.
9069  */
9070 static void igb_io_resume(struct pci_dev *pdev)
9071 {
9072         struct net_device *netdev = pci_get_drvdata(pdev);
9073         struct igb_adapter *adapter = netdev_priv(netdev);
9074
9075         if (netif_running(netdev)) {
9076                 if (igb_up(adapter)) {
9077                         dev_err(&pdev->dev, "igb_up failed after reset\n");
9078                         return;
9079                 }
9080         }
9081
9082         netif_device_attach(netdev);
9083
9084         /* let the f/w know that the h/w is now under the control of the
9085          * driver.
9086          */
9087         igb_get_hw_control(adapter);
9088 }
9089
9090 /**
9091  *  igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table
9092  *  @adapter: Pointer to adapter structure
9093  *  @index: Index of the RAR entry which need to be synced with MAC table
9094  **/
9095 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)
9096 {
9097         struct e1000_hw *hw = &adapter->hw;
9098         u32 rar_low, rar_high;
9099         u8 *addr = adapter->mac_table[index].addr;
9100
9101         /* HW expects these to be in network order when they are plugged
9102          * into the registers which are little endian.  In order to guarantee
9103          * that ordering we need to do an leXX_to_cpup here in order to be
9104          * ready for the byteswap that occurs with writel
9105          */
9106         rar_low = le32_to_cpup((__le32 *)(addr));
9107         rar_high = le16_to_cpup((__le16 *)(addr + 4));
9108
9109         /* Indicate to hardware the Address is Valid. */
9110         if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) {
9111                 if (is_valid_ether_addr(addr))
9112                         rar_high |= E1000_RAH_AV;
9113
9114                 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR)
9115                         rar_high |= E1000_RAH_ASEL_SRC_ADDR;
9116
9117                 switch (hw->mac.type) {
9118                 case e1000_82575:
9119                 case e1000_i210:
9120                         if (adapter->mac_table[index].state &
9121                             IGB_MAC_STATE_QUEUE_STEERING)
9122                                 rar_high |= E1000_RAH_QSEL_ENABLE;
9123
9124                         rar_high |= E1000_RAH_POOL_1 *
9125                                     adapter->mac_table[index].queue;
9126                         break;
9127                 default:
9128                         rar_high |= E1000_RAH_POOL_1 <<
9129                                     adapter->mac_table[index].queue;
9130                         break;
9131                 }
9132         }
9133
9134         wr32(E1000_RAL(index), rar_low);
9135         wrfl();
9136         wr32(E1000_RAH(index), rar_high);
9137         wrfl();
9138 }
9139
9140 static int igb_set_vf_mac(struct igb_adapter *adapter,
9141                           int vf, unsigned char *mac_addr)
9142 {
9143         struct e1000_hw *hw = &adapter->hw;
9144         /* VF MAC addresses start at end of receive addresses and moves
9145          * towards the first, as a result a collision should not be possible
9146          */
9147         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
9148         unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses;
9149
9150         ether_addr_copy(vf_mac_addr, mac_addr);
9151         ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr);
9152         adapter->mac_table[rar_entry].queue = vf;
9153         adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE;
9154         igb_rar_set_index(adapter, rar_entry);
9155
9156         return 0;
9157 }
9158
9159 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
9160 {
9161         struct igb_adapter *adapter = netdev_priv(netdev);
9162
9163         if (vf >= adapter->vfs_allocated_count)
9164                 return -EINVAL;
9165
9166         /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC
9167          * flag and allows to overwrite the MAC via VF netdev.  This
9168          * is necessary to allow libvirt a way to restore the original
9169          * MAC after unbinding vfio-pci and reloading igbvf after shutting
9170          * down a VM.
9171          */
9172         if (is_zero_ether_addr(mac)) {
9173                 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC;
9174                 dev_info(&adapter->pdev->dev,
9175                          "remove administratively set MAC on VF %d\n",
9176                          vf);
9177         } else if (is_valid_ether_addr(mac)) {
9178                 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
9179                 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n",
9180                          mac, vf);
9181                 dev_info(&adapter->pdev->dev,
9182                          "Reload the VF driver to make this change effective.");
9183                 /* Generate additional warning if PF is down */
9184                 if (test_bit(__IGB_DOWN, &adapter->state)) {
9185                         dev_warn(&adapter->pdev->dev,
9186                                  "The VF MAC address has been set, but the PF device is not up.\n");
9187                         dev_warn(&adapter->pdev->dev,
9188                                  "Bring the PF device up before attempting to use the VF device.\n");
9189                 }
9190         } else {
9191                 return -EINVAL;
9192         }
9193         return igb_set_vf_mac(adapter, vf, mac);
9194 }
9195
9196 static int igb_link_mbps(int internal_link_speed)
9197 {
9198         switch (internal_link_speed) {
9199         case SPEED_100:
9200                 return 100;
9201         case SPEED_1000:
9202                 return 1000;
9203         default:
9204                 return 0;
9205         }
9206 }
9207
9208 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
9209                                   int link_speed)
9210 {
9211         int rf_dec, rf_int;
9212         u32 bcnrc_val;
9213
9214         if (tx_rate != 0) {
9215                 /* Calculate the rate factor values to set */
9216                 rf_int = link_speed / tx_rate;
9217                 rf_dec = (link_speed - (rf_int * tx_rate));
9218                 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
9219                          tx_rate;
9220
9221                 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
9222                 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
9223                               E1000_RTTBCNRC_RF_INT_MASK);
9224                 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
9225         } else {
9226                 bcnrc_val = 0;
9227         }
9228
9229         wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
9230         /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
9231          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
9232          */
9233         wr32(E1000_RTTBCNRM, 0x14);
9234         wr32(E1000_RTTBCNRC, bcnrc_val);
9235 }
9236
9237 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
9238 {
9239         int actual_link_speed, i;
9240         bool reset_rate = false;
9241
9242         /* VF TX rate limit was not set or not supported */
9243         if ((adapter->vf_rate_link_speed == 0) ||
9244             (adapter->hw.mac.type != e1000_82576))
9245                 return;
9246
9247         actual_link_speed = igb_link_mbps(adapter->link_speed);
9248         if (actual_link_speed != adapter->vf_rate_link_speed) {
9249                 reset_rate = true;
9250                 adapter->vf_rate_link_speed = 0;
9251                 dev_info(&adapter->pdev->dev,
9252                          "Link speed has been changed. VF Transmit rate is disabled\n");
9253         }
9254
9255         for (i = 0; i < adapter->vfs_allocated_count; i++) {
9256                 if (reset_rate)
9257                         adapter->vf_data[i].tx_rate = 0;
9258
9259                 igb_set_vf_rate_limit(&adapter->hw, i,
9260                                       adapter->vf_data[i].tx_rate,
9261                                       actual_link_speed);
9262         }
9263 }
9264
9265 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
9266                              int min_tx_rate, int max_tx_rate)
9267 {
9268         struct igb_adapter *adapter = netdev_priv(netdev);
9269         struct e1000_hw *hw = &adapter->hw;
9270         int actual_link_speed;
9271
9272         if (hw->mac.type != e1000_82576)
9273                 return -EOPNOTSUPP;
9274
9275         if (min_tx_rate)
9276                 return -EINVAL;
9277
9278         actual_link_speed = igb_link_mbps(adapter->link_speed);
9279         if ((vf >= adapter->vfs_allocated_count) ||
9280             (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
9281             (max_tx_rate < 0) ||
9282             (max_tx_rate > actual_link_speed))
9283                 return -EINVAL;
9284
9285         adapter->vf_rate_link_speed = actual_link_speed;
9286         adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
9287         igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
9288
9289         return 0;
9290 }
9291
9292 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
9293                                    bool setting)
9294 {
9295         struct igb_adapter *adapter = netdev_priv(netdev);
9296         struct e1000_hw *hw = &adapter->hw;
9297         u32 reg_val, reg_offset;
9298
9299         if (!adapter->vfs_allocated_count)
9300                 return -EOPNOTSUPP;
9301
9302         if (vf >= adapter->vfs_allocated_count)
9303                 return -EINVAL;
9304
9305         reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
9306         reg_val = rd32(reg_offset);
9307         if (setting)
9308                 reg_val |= (BIT(vf) |
9309                             BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9310         else
9311                 reg_val &= ~(BIT(vf) |
9312                              BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9313         wr32(reg_offset, reg_val);
9314
9315         adapter->vf_data[vf].spoofchk_enabled = setting;
9316         return 0;
9317 }
9318
9319 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting)
9320 {
9321         struct igb_adapter *adapter = netdev_priv(netdev);
9322
9323         if (vf >= adapter->vfs_allocated_count)
9324                 return -EINVAL;
9325         if (adapter->vf_data[vf].trusted == setting)
9326                 return 0;
9327
9328         adapter->vf_data[vf].trusted = setting;
9329
9330         dev_info(&adapter->pdev->dev, "VF %u is %strusted\n",
9331                  vf, setting ? "" : "not ");
9332         return 0;
9333 }
9334
9335 static int igb_ndo_get_vf_config(struct net_device *netdev,
9336                                  int vf, struct ifla_vf_info *ivi)
9337 {
9338         struct igb_adapter *adapter = netdev_priv(netdev);
9339         if (vf >= adapter->vfs_allocated_count)
9340                 return -EINVAL;
9341         ivi->vf = vf;
9342         memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
9343         ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
9344         ivi->min_tx_rate = 0;
9345         ivi->vlan = adapter->vf_data[vf].pf_vlan;
9346         ivi->qos = adapter->vf_data[vf].pf_qos;
9347         ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
9348         ivi->trusted = adapter->vf_data[vf].trusted;
9349         return 0;
9350 }
9351
9352 static void igb_vmm_control(struct igb_adapter *adapter)
9353 {
9354         struct e1000_hw *hw = &adapter->hw;
9355         u32 reg;
9356
9357         switch (hw->mac.type) {
9358         case e1000_82575:
9359         case e1000_i210:
9360         case e1000_i211:
9361         case e1000_i354:
9362         default:
9363                 /* replication is not supported for 82575 */
9364                 return;
9365         case e1000_82576:
9366                 /* notify HW that the MAC is adding vlan tags */
9367                 reg = rd32(E1000_DTXCTL);
9368                 reg |= E1000_DTXCTL_VLAN_ADDED;
9369                 wr32(E1000_DTXCTL, reg);
9370                 /* Fall through */
9371         case e1000_82580:
9372                 /* enable replication vlan tag stripping */
9373                 reg = rd32(E1000_RPLOLR);
9374                 reg |= E1000_RPLOLR_STRVLAN;
9375                 wr32(E1000_RPLOLR, reg);
9376                 /* Fall through */
9377         case e1000_i350:
9378                 /* none of the above registers are supported by i350 */
9379                 break;
9380         }
9381
9382         if (adapter->vfs_allocated_count) {
9383                 igb_vmdq_set_loopback_pf(hw, true);
9384                 igb_vmdq_set_replication_pf(hw, true);
9385                 igb_vmdq_set_anti_spoofing_pf(hw, true,
9386                                               adapter->vfs_allocated_count);
9387         } else {
9388                 igb_vmdq_set_loopback_pf(hw, false);
9389                 igb_vmdq_set_replication_pf(hw, false);
9390         }
9391 }
9392
9393 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
9394 {
9395         struct e1000_hw *hw = &adapter->hw;
9396         u32 dmac_thr;
9397         u16 hwm;
9398
9399         if (hw->mac.type > e1000_82580) {
9400                 if (adapter->flags & IGB_FLAG_DMAC) {
9401                         u32 reg;
9402
9403                         /* force threshold to 0. */
9404                         wr32(E1000_DMCTXTH, 0);
9405
9406                         /* DMA Coalescing high water mark needs to be greater
9407                          * than the Rx threshold. Set hwm to PBA - max frame
9408                          * size in 16B units, capping it at PBA - 6KB.
9409                          */
9410                         hwm = 64 * (pba - 6);
9411                         reg = rd32(E1000_FCRTC);
9412                         reg &= ~E1000_FCRTC_RTH_COAL_MASK;
9413                         reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
9414                                 & E1000_FCRTC_RTH_COAL_MASK);
9415                         wr32(E1000_FCRTC, reg);
9416
9417                         /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
9418                          * frame size, capping it at PBA - 10KB.
9419                          */
9420                         dmac_thr = pba - 10;
9421                         reg = rd32(E1000_DMACR);
9422                         reg &= ~E1000_DMACR_DMACTHR_MASK;
9423                         reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
9424                                 & E1000_DMACR_DMACTHR_MASK);
9425
9426                         /* transition to L0x or L1 if available..*/
9427                         reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
9428
9429                         /* watchdog timer= +-1000 usec in 32usec intervals */
9430                         reg |= (1000 >> 5);
9431
9432                         /* Disable BMC-to-OS Watchdog Enable */
9433                         if (hw->mac.type != e1000_i354)
9434                                 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
9435
9436                         wr32(E1000_DMACR, reg);
9437
9438                         /* no lower threshold to disable
9439                          * coalescing(smart fifb)-UTRESH=0
9440                          */
9441                         wr32(E1000_DMCRTRH, 0);
9442
9443                         reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
9444
9445                         wr32(E1000_DMCTLX, reg);
9446
9447                         /* free space in tx packet buffer to wake from
9448                          * DMA coal
9449                          */
9450                         wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
9451                              (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
9452
9453                         /* make low power state decision controlled
9454                          * by DMA coal
9455                          */
9456                         reg = rd32(E1000_PCIEMISC);
9457                         reg &= ~E1000_PCIEMISC_LX_DECISION;
9458                         wr32(E1000_PCIEMISC, reg);
9459                 } /* endif adapter->dmac is not disabled */
9460         } else if (hw->mac.type == e1000_82580) {
9461                 u32 reg = rd32(E1000_PCIEMISC);
9462
9463                 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
9464                 wr32(E1000_DMACR, 0);
9465         }
9466 }
9467
9468 /**
9469  *  igb_read_i2c_byte - Reads 8 bit word over I2C
9470  *  @hw: pointer to hardware structure
9471  *  @byte_offset: byte offset to read
9472  *  @dev_addr: device address
9473  *  @data: value read
9474  *
9475  *  Performs byte read operation over I2C interface at
9476  *  a specified device address.
9477  **/
9478 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
9479                       u8 dev_addr, u8 *data)
9480 {
9481         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
9482         struct i2c_client *this_client = adapter->i2c_client;
9483         s32 status;
9484         u16 swfw_mask = 0;
9485
9486         if (!this_client)
9487                 return E1000_ERR_I2C;
9488
9489         swfw_mask = E1000_SWFW_PHY0_SM;
9490
9491         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
9492                 return E1000_ERR_SWFW_SYNC;
9493
9494         status = i2c_smbus_read_byte_data(this_client, byte_offset);
9495         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
9496
9497         if (status < 0)
9498                 return E1000_ERR_I2C;
9499         else {
9500                 *data = status;
9501                 return 0;
9502         }
9503 }
9504
9505 /**
9506  *  igb_write_i2c_byte - Writes 8 bit word over I2C
9507  *  @hw: pointer to hardware structure
9508  *  @byte_offset: byte offset to write
9509  *  @dev_addr: device address
9510  *  @data: value to write
9511  *
9512  *  Performs byte write operation over I2C interface at
9513  *  a specified device address.
9514  **/
9515 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
9516                        u8 dev_addr, u8 data)
9517 {
9518         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
9519         struct i2c_client *this_client = adapter->i2c_client;
9520         s32 status;
9521         u16 swfw_mask = E1000_SWFW_PHY0_SM;
9522
9523         if (!this_client)
9524                 return E1000_ERR_I2C;
9525
9526         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
9527                 return E1000_ERR_SWFW_SYNC;
9528         status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
9529         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
9530
9531         if (status)
9532                 return E1000_ERR_I2C;
9533         else
9534                 return 0;
9535
9536 }
9537
9538 int igb_reinit_queues(struct igb_adapter *adapter)
9539 {
9540         struct net_device *netdev = adapter->netdev;
9541         struct pci_dev *pdev = adapter->pdev;
9542         int err = 0;
9543
9544         if (netif_running(netdev))
9545                 igb_close(netdev);
9546
9547         igb_reset_interrupt_capability(adapter);
9548
9549         if (igb_init_interrupt_scheme(adapter, true)) {
9550                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9551                 return -ENOMEM;
9552         }
9553
9554         if (netif_running(netdev))
9555                 err = igb_open(netdev);
9556
9557         return err;
9558 }
9559
9560 static void igb_nfc_filter_exit(struct igb_adapter *adapter)
9561 {
9562         struct igb_nfc_filter *rule;
9563
9564         spin_lock(&adapter->nfc_lock);
9565
9566         hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
9567                 igb_erase_filter(adapter, rule);
9568
9569         hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node)
9570                 igb_erase_filter(adapter, rule);
9571
9572         spin_unlock(&adapter->nfc_lock);
9573 }
9574
9575 static void igb_nfc_filter_restore(struct igb_adapter *adapter)
9576 {
9577         struct igb_nfc_filter *rule;
9578
9579         spin_lock(&adapter->nfc_lock);
9580
9581         hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
9582                 igb_add_filter(adapter, rule);
9583
9584         spin_unlock(&adapter->nfc_lock);
9585 }
9586 /* igb_main.c */