2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
26 #include "amdgpu_ih.h"
27 #include "amdgpu_gfx.h"
31 #include "amdgpu_ucode.h"
32 #include "clearstate_ci.h"
34 #include "dce/dce_8_0_d.h"
35 #include "dce/dce_8_0_sh_mask.h"
37 #include "bif/bif_4_1_d.h"
38 #include "bif/bif_4_1_sh_mask.h"
40 #include "gca/gfx_7_0_d.h"
41 #include "gca/gfx_7_2_enum.h"
42 #include "gca/gfx_7_2_sh_mask.h"
44 #include "gmc/gmc_7_0_d.h"
45 #include "gmc/gmc_7_0_sh_mask.h"
47 #include "oss/oss_2_0_d.h"
48 #include "oss/oss_2_0_sh_mask.h"
50 #define GFX7_NUM_GFX_RINGS 1
51 #define GFX7_NUM_COMPUTE_RINGS 8
53 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
54 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
57 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
58 MODULE_FIRMWARE("radeon/bonaire_me.bin");
59 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
60 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
61 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
63 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
64 MODULE_FIRMWARE("radeon/hawaii_me.bin");
65 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
66 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
67 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
69 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
70 MODULE_FIRMWARE("radeon/kaveri_me.bin");
71 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
72 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
73 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
74 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
76 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
77 MODULE_FIRMWARE("radeon/kabini_me.bin");
78 MODULE_FIRMWARE("radeon/kabini_ce.bin");
79 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
80 MODULE_FIRMWARE("radeon/kabini_mec.bin");
82 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
83 MODULE_FIRMWARE("radeon/mullins_me.bin");
84 MODULE_FIRMWARE("radeon/mullins_ce.bin");
85 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
86 MODULE_FIRMWARE("radeon/mullins_mec.bin");
88 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
90 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
91 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
92 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
93 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
94 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
95 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
96 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
97 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
98 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
99 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
100 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
101 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
102 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
103 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
104 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
105 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
108 static const u32 spectre_rlc_save_restore_register_list[] =
110 (0x0e00 << 16) | (0xc12c >> 2),
112 (0x0e00 << 16) | (0xc140 >> 2),
114 (0x0e00 << 16) | (0xc150 >> 2),
116 (0x0e00 << 16) | (0xc15c >> 2),
118 (0x0e00 << 16) | (0xc168 >> 2),
120 (0x0e00 << 16) | (0xc170 >> 2),
122 (0x0e00 << 16) | (0xc178 >> 2),
124 (0x0e00 << 16) | (0xc204 >> 2),
126 (0x0e00 << 16) | (0xc2b4 >> 2),
128 (0x0e00 << 16) | (0xc2b8 >> 2),
130 (0x0e00 << 16) | (0xc2bc >> 2),
132 (0x0e00 << 16) | (0xc2c0 >> 2),
134 (0x0e00 << 16) | (0x8228 >> 2),
136 (0x0e00 << 16) | (0x829c >> 2),
138 (0x0e00 << 16) | (0x869c >> 2),
140 (0x0600 << 16) | (0x98f4 >> 2),
142 (0x0e00 << 16) | (0x98f8 >> 2),
144 (0x0e00 << 16) | (0x9900 >> 2),
146 (0x0e00 << 16) | (0xc260 >> 2),
148 (0x0e00 << 16) | (0x90e8 >> 2),
150 (0x0e00 << 16) | (0x3c000 >> 2),
152 (0x0e00 << 16) | (0x3c00c >> 2),
154 (0x0e00 << 16) | (0x8c1c >> 2),
156 (0x0e00 << 16) | (0x9700 >> 2),
158 (0x0e00 << 16) | (0xcd20 >> 2),
160 (0x4e00 << 16) | (0xcd20 >> 2),
162 (0x5e00 << 16) | (0xcd20 >> 2),
164 (0x6e00 << 16) | (0xcd20 >> 2),
166 (0x7e00 << 16) | (0xcd20 >> 2),
168 (0x8e00 << 16) | (0xcd20 >> 2),
170 (0x9e00 << 16) | (0xcd20 >> 2),
172 (0xae00 << 16) | (0xcd20 >> 2),
174 (0xbe00 << 16) | (0xcd20 >> 2),
176 (0x0e00 << 16) | (0x89bc >> 2),
178 (0x0e00 << 16) | (0x8900 >> 2),
181 (0x0e00 << 16) | (0xc130 >> 2),
183 (0x0e00 << 16) | (0xc134 >> 2),
185 (0x0e00 << 16) | (0xc1fc >> 2),
187 (0x0e00 << 16) | (0xc208 >> 2),
189 (0x0e00 << 16) | (0xc264 >> 2),
191 (0x0e00 << 16) | (0xc268 >> 2),
193 (0x0e00 << 16) | (0xc26c >> 2),
195 (0x0e00 << 16) | (0xc270 >> 2),
197 (0x0e00 << 16) | (0xc274 >> 2),
199 (0x0e00 << 16) | (0xc278 >> 2),
201 (0x0e00 << 16) | (0xc27c >> 2),
203 (0x0e00 << 16) | (0xc280 >> 2),
205 (0x0e00 << 16) | (0xc284 >> 2),
207 (0x0e00 << 16) | (0xc288 >> 2),
209 (0x0e00 << 16) | (0xc28c >> 2),
211 (0x0e00 << 16) | (0xc290 >> 2),
213 (0x0e00 << 16) | (0xc294 >> 2),
215 (0x0e00 << 16) | (0xc298 >> 2),
217 (0x0e00 << 16) | (0xc29c >> 2),
219 (0x0e00 << 16) | (0xc2a0 >> 2),
221 (0x0e00 << 16) | (0xc2a4 >> 2),
223 (0x0e00 << 16) | (0xc2a8 >> 2),
225 (0x0e00 << 16) | (0xc2ac >> 2),
227 (0x0e00 << 16) | (0xc2b0 >> 2),
229 (0x0e00 << 16) | (0x301d0 >> 2),
231 (0x0e00 << 16) | (0x30238 >> 2),
233 (0x0e00 << 16) | (0x30250 >> 2),
235 (0x0e00 << 16) | (0x30254 >> 2),
237 (0x0e00 << 16) | (0x30258 >> 2),
239 (0x0e00 << 16) | (0x3025c >> 2),
241 (0x4e00 << 16) | (0xc900 >> 2),
243 (0x5e00 << 16) | (0xc900 >> 2),
245 (0x6e00 << 16) | (0xc900 >> 2),
247 (0x7e00 << 16) | (0xc900 >> 2),
249 (0x8e00 << 16) | (0xc900 >> 2),
251 (0x9e00 << 16) | (0xc900 >> 2),
253 (0xae00 << 16) | (0xc900 >> 2),
255 (0xbe00 << 16) | (0xc900 >> 2),
257 (0x4e00 << 16) | (0xc904 >> 2),
259 (0x5e00 << 16) | (0xc904 >> 2),
261 (0x6e00 << 16) | (0xc904 >> 2),
263 (0x7e00 << 16) | (0xc904 >> 2),
265 (0x8e00 << 16) | (0xc904 >> 2),
267 (0x9e00 << 16) | (0xc904 >> 2),
269 (0xae00 << 16) | (0xc904 >> 2),
271 (0xbe00 << 16) | (0xc904 >> 2),
273 (0x4e00 << 16) | (0xc908 >> 2),
275 (0x5e00 << 16) | (0xc908 >> 2),
277 (0x6e00 << 16) | (0xc908 >> 2),
279 (0x7e00 << 16) | (0xc908 >> 2),
281 (0x8e00 << 16) | (0xc908 >> 2),
283 (0x9e00 << 16) | (0xc908 >> 2),
285 (0xae00 << 16) | (0xc908 >> 2),
287 (0xbe00 << 16) | (0xc908 >> 2),
289 (0x4e00 << 16) | (0xc90c >> 2),
291 (0x5e00 << 16) | (0xc90c >> 2),
293 (0x6e00 << 16) | (0xc90c >> 2),
295 (0x7e00 << 16) | (0xc90c >> 2),
297 (0x8e00 << 16) | (0xc90c >> 2),
299 (0x9e00 << 16) | (0xc90c >> 2),
301 (0xae00 << 16) | (0xc90c >> 2),
303 (0xbe00 << 16) | (0xc90c >> 2),
305 (0x4e00 << 16) | (0xc910 >> 2),
307 (0x5e00 << 16) | (0xc910 >> 2),
309 (0x6e00 << 16) | (0xc910 >> 2),
311 (0x7e00 << 16) | (0xc910 >> 2),
313 (0x8e00 << 16) | (0xc910 >> 2),
315 (0x9e00 << 16) | (0xc910 >> 2),
317 (0xae00 << 16) | (0xc910 >> 2),
319 (0xbe00 << 16) | (0xc910 >> 2),
321 (0x0e00 << 16) | (0xc99c >> 2),
323 (0x0e00 << 16) | (0x9834 >> 2),
325 (0x0000 << 16) | (0x30f00 >> 2),
327 (0x0001 << 16) | (0x30f00 >> 2),
329 (0x0000 << 16) | (0x30f04 >> 2),
331 (0x0001 << 16) | (0x30f04 >> 2),
333 (0x0000 << 16) | (0x30f08 >> 2),
335 (0x0001 << 16) | (0x30f08 >> 2),
337 (0x0000 << 16) | (0x30f0c >> 2),
339 (0x0001 << 16) | (0x30f0c >> 2),
341 (0x0600 << 16) | (0x9b7c >> 2),
343 (0x0e00 << 16) | (0x8a14 >> 2),
345 (0x0e00 << 16) | (0x8a18 >> 2),
347 (0x0600 << 16) | (0x30a00 >> 2),
349 (0x0e00 << 16) | (0x8bf0 >> 2),
351 (0x0e00 << 16) | (0x8bcc >> 2),
353 (0x0e00 << 16) | (0x8b24 >> 2),
355 (0x0e00 << 16) | (0x30a04 >> 2),
357 (0x0600 << 16) | (0x30a10 >> 2),
359 (0x0600 << 16) | (0x30a14 >> 2),
361 (0x0600 << 16) | (0x30a18 >> 2),
363 (0x0600 << 16) | (0x30a2c >> 2),
365 (0x0e00 << 16) | (0xc700 >> 2),
367 (0x0e00 << 16) | (0xc704 >> 2),
369 (0x0e00 << 16) | (0xc708 >> 2),
371 (0x0e00 << 16) | (0xc768 >> 2),
373 (0x0400 << 16) | (0xc770 >> 2),
375 (0x0400 << 16) | (0xc774 >> 2),
377 (0x0400 << 16) | (0xc778 >> 2),
379 (0x0400 << 16) | (0xc77c >> 2),
381 (0x0400 << 16) | (0xc780 >> 2),
383 (0x0400 << 16) | (0xc784 >> 2),
385 (0x0400 << 16) | (0xc788 >> 2),
387 (0x0400 << 16) | (0xc78c >> 2),
389 (0x0400 << 16) | (0xc798 >> 2),
391 (0x0400 << 16) | (0xc79c >> 2),
393 (0x0400 << 16) | (0xc7a0 >> 2),
395 (0x0400 << 16) | (0xc7a4 >> 2),
397 (0x0400 << 16) | (0xc7a8 >> 2),
399 (0x0400 << 16) | (0xc7ac >> 2),
401 (0x0400 << 16) | (0xc7b0 >> 2),
403 (0x0400 << 16) | (0xc7b4 >> 2),
405 (0x0e00 << 16) | (0x9100 >> 2),
407 (0x0e00 << 16) | (0x3c010 >> 2),
409 (0x0e00 << 16) | (0x92a8 >> 2),
411 (0x0e00 << 16) | (0x92ac >> 2),
413 (0x0e00 << 16) | (0x92b4 >> 2),
415 (0x0e00 << 16) | (0x92b8 >> 2),
417 (0x0e00 << 16) | (0x92bc >> 2),
419 (0x0e00 << 16) | (0x92c0 >> 2),
421 (0x0e00 << 16) | (0x92c4 >> 2),
423 (0x0e00 << 16) | (0x92c8 >> 2),
425 (0x0e00 << 16) | (0x92cc >> 2),
427 (0x0e00 << 16) | (0x92d0 >> 2),
429 (0x0e00 << 16) | (0x8c00 >> 2),
431 (0x0e00 << 16) | (0x8c04 >> 2),
433 (0x0e00 << 16) | (0x8c20 >> 2),
435 (0x0e00 << 16) | (0x8c38 >> 2),
437 (0x0e00 << 16) | (0x8c3c >> 2),
439 (0x0e00 << 16) | (0xae00 >> 2),
441 (0x0e00 << 16) | (0x9604 >> 2),
443 (0x0e00 << 16) | (0xac08 >> 2),
445 (0x0e00 << 16) | (0xac0c >> 2),
447 (0x0e00 << 16) | (0xac10 >> 2),
449 (0x0e00 << 16) | (0xac14 >> 2),
451 (0x0e00 << 16) | (0xac58 >> 2),
453 (0x0e00 << 16) | (0xac68 >> 2),
455 (0x0e00 << 16) | (0xac6c >> 2),
457 (0x0e00 << 16) | (0xac70 >> 2),
459 (0x0e00 << 16) | (0xac74 >> 2),
461 (0x0e00 << 16) | (0xac78 >> 2),
463 (0x0e00 << 16) | (0xac7c >> 2),
465 (0x0e00 << 16) | (0xac80 >> 2),
467 (0x0e00 << 16) | (0xac84 >> 2),
469 (0x0e00 << 16) | (0xac88 >> 2),
471 (0x0e00 << 16) | (0xac8c >> 2),
473 (0x0e00 << 16) | (0x970c >> 2),
475 (0x0e00 << 16) | (0x9714 >> 2),
477 (0x0e00 << 16) | (0x9718 >> 2),
479 (0x0e00 << 16) | (0x971c >> 2),
481 (0x0e00 << 16) | (0x31068 >> 2),
483 (0x4e00 << 16) | (0x31068 >> 2),
485 (0x5e00 << 16) | (0x31068 >> 2),
487 (0x6e00 << 16) | (0x31068 >> 2),
489 (0x7e00 << 16) | (0x31068 >> 2),
491 (0x8e00 << 16) | (0x31068 >> 2),
493 (0x9e00 << 16) | (0x31068 >> 2),
495 (0xae00 << 16) | (0x31068 >> 2),
497 (0xbe00 << 16) | (0x31068 >> 2),
499 (0x0e00 << 16) | (0xcd10 >> 2),
501 (0x0e00 << 16) | (0xcd14 >> 2),
503 (0x0e00 << 16) | (0x88b0 >> 2),
505 (0x0e00 << 16) | (0x88b4 >> 2),
507 (0x0e00 << 16) | (0x88b8 >> 2),
509 (0x0e00 << 16) | (0x88bc >> 2),
511 (0x0400 << 16) | (0x89c0 >> 2),
513 (0x0e00 << 16) | (0x88c4 >> 2),
515 (0x0e00 << 16) | (0x88c8 >> 2),
517 (0x0e00 << 16) | (0x88d0 >> 2),
519 (0x0e00 << 16) | (0x88d4 >> 2),
521 (0x0e00 << 16) | (0x88d8 >> 2),
523 (0x0e00 << 16) | (0x8980 >> 2),
525 (0x0e00 << 16) | (0x30938 >> 2),
527 (0x0e00 << 16) | (0x3093c >> 2),
529 (0x0e00 << 16) | (0x30940 >> 2),
531 (0x0e00 << 16) | (0x89a0 >> 2),
533 (0x0e00 << 16) | (0x30900 >> 2),
535 (0x0e00 << 16) | (0x30904 >> 2),
537 (0x0e00 << 16) | (0x89b4 >> 2),
539 (0x0e00 << 16) | (0x3c210 >> 2),
541 (0x0e00 << 16) | (0x3c214 >> 2),
543 (0x0e00 << 16) | (0x3c218 >> 2),
545 (0x0e00 << 16) | (0x8904 >> 2),
548 (0x0e00 << 16) | (0x8c28 >> 2),
549 (0x0e00 << 16) | (0x8c2c >> 2),
550 (0x0e00 << 16) | (0x8c30 >> 2),
551 (0x0e00 << 16) | (0x8c34 >> 2),
552 (0x0e00 << 16) | (0x9600 >> 2),
555 static const u32 kalindi_rlc_save_restore_register_list[] =
557 (0x0e00 << 16) | (0xc12c >> 2),
559 (0x0e00 << 16) | (0xc140 >> 2),
561 (0x0e00 << 16) | (0xc150 >> 2),
563 (0x0e00 << 16) | (0xc15c >> 2),
565 (0x0e00 << 16) | (0xc168 >> 2),
567 (0x0e00 << 16) | (0xc170 >> 2),
569 (0x0e00 << 16) | (0xc204 >> 2),
571 (0x0e00 << 16) | (0xc2b4 >> 2),
573 (0x0e00 << 16) | (0xc2b8 >> 2),
575 (0x0e00 << 16) | (0xc2bc >> 2),
577 (0x0e00 << 16) | (0xc2c0 >> 2),
579 (0x0e00 << 16) | (0x8228 >> 2),
581 (0x0e00 << 16) | (0x829c >> 2),
583 (0x0e00 << 16) | (0x869c >> 2),
585 (0x0600 << 16) | (0x98f4 >> 2),
587 (0x0e00 << 16) | (0x98f8 >> 2),
589 (0x0e00 << 16) | (0x9900 >> 2),
591 (0x0e00 << 16) | (0xc260 >> 2),
593 (0x0e00 << 16) | (0x90e8 >> 2),
595 (0x0e00 << 16) | (0x3c000 >> 2),
597 (0x0e00 << 16) | (0x3c00c >> 2),
599 (0x0e00 << 16) | (0x8c1c >> 2),
601 (0x0e00 << 16) | (0x9700 >> 2),
603 (0x0e00 << 16) | (0xcd20 >> 2),
605 (0x4e00 << 16) | (0xcd20 >> 2),
607 (0x5e00 << 16) | (0xcd20 >> 2),
609 (0x6e00 << 16) | (0xcd20 >> 2),
611 (0x7e00 << 16) | (0xcd20 >> 2),
613 (0x0e00 << 16) | (0x89bc >> 2),
615 (0x0e00 << 16) | (0x8900 >> 2),
618 (0x0e00 << 16) | (0xc130 >> 2),
620 (0x0e00 << 16) | (0xc134 >> 2),
622 (0x0e00 << 16) | (0xc1fc >> 2),
624 (0x0e00 << 16) | (0xc208 >> 2),
626 (0x0e00 << 16) | (0xc264 >> 2),
628 (0x0e00 << 16) | (0xc268 >> 2),
630 (0x0e00 << 16) | (0xc26c >> 2),
632 (0x0e00 << 16) | (0xc270 >> 2),
634 (0x0e00 << 16) | (0xc274 >> 2),
636 (0x0e00 << 16) | (0xc28c >> 2),
638 (0x0e00 << 16) | (0xc290 >> 2),
640 (0x0e00 << 16) | (0xc294 >> 2),
642 (0x0e00 << 16) | (0xc298 >> 2),
644 (0x0e00 << 16) | (0xc2a0 >> 2),
646 (0x0e00 << 16) | (0xc2a4 >> 2),
648 (0x0e00 << 16) | (0xc2a8 >> 2),
650 (0x0e00 << 16) | (0xc2ac >> 2),
652 (0x0e00 << 16) | (0x301d0 >> 2),
654 (0x0e00 << 16) | (0x30238 >> 2),
656 (0x0e00 << 16) | (0x30250 >> 2),
658 (0x0e00 << 16) | (0x30254 >> 2),
660 (0x0e00 << 16) | (0x30258 >> 2),
662 (0x0e00 << 16) | (0x3025c >> 2),
664 (0x4e00 << 16) | (0xc900 >> 2),
666 (0x5e00 << 16) | (0xc900 >> 2),
668 (0x6e00 << 16) | (0xc900 >> 2),
670 (0x7e00 << 16) | (0xc900 >> 2),
672 (0x4e00 << 16) | (0xc904 >> 2),
674 (0x5e00 << 16) | (0xc904 >> 2),
676 (0x6e00 << 16) | (0xc904 >> 2),
678 (0x7e00 << 16) | (0xc904 >> 2),
680 (0x4e00 << 16) | (0xc908 >> 2),
682 (0x5e00 << 16) | (0xc908 >> 2),
684 (0x6e00 << 16) | (0xc908 >> 2),
686 (0x7e00 << 16) | (0xc908 >> 2),
688 (0x4e00 << 16) | (0xc90c >> 2),
690 (0x5e00 << 16) | (0xc90c >> 2),
692 (0x6e00 << 16) | (0xc90c >> 2),
694 (0x7e00 << 16) | (0xc90c >> 2),
696 (0x4e00 << 16) | (0xc910 >> 2),
698 (0x5e00 << 16) | (0xc910 >> 2),
700 (0x6e00 << 16) | (0xc910 >> 2),
702 (0x7e00 << 16) | (0xc910 >> 2),
704 (0x0e00 << 16) | (0xc99c >> 2),
706 (0x0e00 << 16) | (0x9834 >> 2),
708 (0x0000 << 16) | (0x30f00 >> 2),
710 (0x0000 << 16) | (0x30f04 >> 2),
712 (0x0000 << 16) | (0x30f08 >> 2),
714 (0x0000 << 16) | (0x30f0c >> 2),
716 (0x0600 << 16) | (0x9b7c >> 2),
718 (0x0e00 << 16) | (0x8a14 >> 2),
720 (0x0e00 << 16) | (0x8a18 >> 2),
722 (0x0600 << 16) | (0x30a00 >> 2),
724 (0x0e00 << 16) | (0x8bf0 >> 2),
726 (0x0e00 << 16) | (0x8bcc >> 2),
728 (0x0e00 << 16) | (0x8b24 >> 2),
730 (0x0e00 << 16) | (0x30a04 >> 2),
732 (0x0600 << 16) | (0x30a10 >> 2),
734 (0x0600 << 16) | (0x30a14 >> 2),
736 (0x0600 << 16) | (0x30a18 >> 2),
738 (0x0600 << 16) | (0x30a2c >> 2),
740 (0x0e00 << 16) | (0xc700 >> 2),
742 (0x0e00 << 16) | (0xc704 >> 2),
744 (0x0e00 << 16) | (0xc708 >> 2),
746 (0x0e00 << 16) | (0xc768 >> 2),
748 (0x0400 << 16) | (0xc770 >> 2),
750 (0x0400 << 16) | (0xc774 >> 2),
752 (0x0400 << 16) | (0xc798 >> 2),
754 (0x0400 << 16) | (0xc79c >> 2),
756 (0x0e00 << 16) | (0x9100 >> 2),
758 (0x0e00 << 16) | (0x3c010 >> 2),
760 (0x0e00 << 16) | (0x8c00 >> 2),
762 (0x0e00 << 16) | (0x8c04 >> 2),
764 (0x0e00 << 16) | (0x8c20 >> 2),
766 (0x0e00 << 16) | (0x8c38 >> 2),
768 (0x0e00 << 16) | (0x8c3c >> 2),
770 (0x0e00 << 16) | (0xae00 >> 2),
772 (0x0e00 << 16) | (0x9604 >> 2),
774 (0x0e00 << 16) | (0xac08 >> 2),
776 (0x0e00 << 16) | (0xac0c >> 2),
778 (0x0e00 << 16) | (0xac10 >> 2),
780 (0x0e00 << 16) | (0xac14 >> 2),
782 (0x0e00 << 16) | (0xac58 >> 2),
784 (0x0e00 << 16) | (0xac68 >> 2),
786 (0x0e00 << 16) | (0xac6c >> 2),
788 (0x0e00 << 16) | (0xac70 >> 2),
790 (0x0e00 << 16) | (0xac74 >> 2),
792 (0x0e00 << 16) | (0xac78 >> 2),
794 (0x0e00 << 16) | (0xac7c >> 2),
796 (0x0e00 << 16) | (0xac80 >> 2),
798 (0x0e00 << 16) | (0xac84 >> 2),
800 (0x0e00 << 16) | (0xac88 >> 2),
802 (0x0e00 << 16) | (0xac8c >> 2),
804 (0x0e00 << 16) | (0x970c >> 2),
806 (0x0e00 << 16) | (0x9714 >> 2),
808 (0x0e00 << 16) | (0x9718 >> 2),
810 (0x0e00 << 16) | (0x971c >> 2),
812 (0x0e00 << 16) | (0x31068 >> 2),
814 (0x4e00 << 16) | (0x31068 >> 2),
816 (0x5e00 << 16) | (0x31068 >> 2),
818 (0x6e00 << 16) | (0x31068 >> 2),
820 (0x7e00 << 16) | (0x31068 >> 2),
822 (0x0e00 << 16) | (0xcd10 >> 2),
824 (0x0e00 << 16) | (0xcd14 >> 2),
826 (0x0e00 << 16) | (0x88b0 >> 2),
828 (0x0e00 << 16) | (0x88b4 >> 2),
830 (0x0e00 << 16) | (0x88b8 >> 2),
832 (0x0e00 << 16) | (0x88bc >> 2),
834 (0x0400 << 16) | (0x89c0 >> 2),
836 (0x0e00 << 16) | (0x88c4 >> 2),
838 (0x0e00 << 16) | (0x88c8 >> 2),
840 (0x0e00 << 16) | (0x88d0 >> 2),
842 (0x0e00 << 16) | (0x88d4 >> 2),
844 (0x0e00 << 16) | (0x88d8 >> 2),
846 (0x0e00 << 16) | (0x8980 >> 2),
848 (0x0e00 << 16) | (0x30938 >> 2),
850 (0x0e00 << 16) | (0x3093c >> 2),
852 (0x0e00 << 16) | (0x30940 >> 2),
854 (0x0e00 << 16) | (0x89a0 >> 2),
856 (0x0e00 << 16) | (0x30900 >> 2),
858 (0x0e00 << 16) | (0x30904 >> 2),
860 (0x0e00 << 16) | (0x89b4 >> 2),
862 (0x0e00 << 16) | (0x3e1fc >> 2),
864 (0x0e00 << 16) | (0x3c210 >> 2),
866 (0x0e00 << 16) | (0x3c214 >> 2),
868 (0x0e00 << 16) | (0x3c218 >> 2),
870 (0x0e00 << 16) | (0x8904 >> 2),
873 (0x0e00 << 16) | (0x8c28 >> 2),
874 (0x0e00 << 16) | (0x8c2c >> 2),
875 (0x0e00 << 16) | (0x8c30 >> 2),
876 (0x0e00 << 16) | (0x8c34 >> 2),
877 (0x0e00 << 16) | (0x9600 >> 2),
880 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
881 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
882 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
883 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
884 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
890 * gfx_v7_0_init_microcode - load ucode images from disk
892 * @adev: amdgpu_device pointer
894 * Use the firmware interface to load the ucode images into
895 * the driver (not loaded into hw).
896 * Returns 0 on success, error on failure.
898 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
900 const char *chip_name;
906 switch (adev->asic_type) {
908 chip_name = "bonaire";
911 chip_name = "hawaii";
914 chip_name = "kaveri";
917 chip_name = "kabini";
920 chip_name = "mullins";
925 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
926 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
929 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
933 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
934 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
937 err = amdgpu_ucode_validate(adev->gfx.me_fw);
941 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
942 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
945 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
949 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
950 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
953 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
957 if (adev->asic_type == CHIP_KAVERI) {
958 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
959 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
962 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
967 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
968 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
971 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
976 "gfx7: Failed to load firmware \"%s\"\n",
978 release_firmware(adev->gfx.pfp_fw);
979 adev->gfx.pfp_fw = NULL;
980 release_firmware(adev->gfx.me_fw);
981 adev->gfx.me_fw = NULL;
982 release_firmware(adev->gfx.ce_fw);
983 adev->gfx.ce_fw = NULL;
984 release_firmware(adev->gfx.mec_fw);
985 adev->gfx.mec_fw = NULL;
986 release_firmware(adev->gfx.mec2_fw);
987 adev->gfx.mec2_fw = NULL;
988 release_firmware(adev->gfx.rlc_fw);
989 adev->gfx.rlc_fw = NULL;
994 static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
996 release_firmware(adev->gfx.pfp_fw);
997 adev->gfx.pfp_fw = NULL;
998 release_firmware(adev->gfx.me_fw);
999 adev->gfx.me_fw = NULL;
1000 release_firmware(adev->gfx.ce_fw);
1001 adev->gfx.ce_fw = NULL;
1002 release_firmware(adev->gfx.mec_fw);
1003 adev->gfx.mec_fw = NULL;
1004 release_firmware(adev->gfx.mec2_fw);
1005 adev->gfx.mec2_fw = NULL;
1006 release_firmware(adev->gfx.rlc_fw);
1007 adev->gfx.rlc_fw = NULL;
1011 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1013 * @adev: amdgpu_device pointer
1015 * Starting with SI, the tiling setup is done globally in a
1016 * set of 32 tiling modes. Rather than selecting each set of
1017 * parameters per surface as on older asics, we just select
1018 * which index in the tiling table we want to use, and the
1019 * surface uses those parameters (CIK).
1021 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1023 const u32 num_tile_mode_states =
1024 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1025 const u32 num_secondary_tile_mode_states =
1026 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1027 u32 reg_offset, split_equal_to_row_size;
1028 uint32_t *tile, *macrotile;
1030 tile = adev->gfx.config.tile_mode_array;
1031 macrotile = adev->gfx.config.macrotile_mode_array;
1033 switch (adev->gfx.config.mem_row_size_in_kb) {
1035 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1039 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1042 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1046 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1047 tile[reg_offset] = 0;
1048 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1049 macrotile[reg_offset] = 0;
1051 switch (adev->asic_type) {
1053 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1056 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1057 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1058 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1059 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1060 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1061 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1062 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1064 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1065 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1066 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1067 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1068 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1069 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1071 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1072 TILE_SPLIT(split_equal_to_row_size));
1073 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1074 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1075 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1076 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1077 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1078 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1079 TILE_SPLIT(split_equal_to_row_size));
1080 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1081 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1082 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1083 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1084 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1085 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1086 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1088 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1090 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1092 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1094 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1095 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1096 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1098 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1099 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1100 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1101 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1102 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1103 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1106 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1107 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1110 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1111 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1112 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1113 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1114 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1115 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1116 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1118 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1119 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1120 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1121 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1122 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1123 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1124 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1125 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1126 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1127 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1128 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1129 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1130 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1131 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1132 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1133 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1134 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1135 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1136 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1137 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1138 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1139 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1140 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1141 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1143 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1144 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1145 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1146 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1147 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1148 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1149 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1150 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1151 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1152 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1153 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1154 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1156 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1159 NUM_BANKS(ADDR_SURF_16_BANK));
1160 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1163 NUM_BANKS(ADDR_SURF_16_BANK));
1164 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1167 NUM_BANKS(ADDR_SURF_16_BANK));
1168 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1171 NUM_BANKS(ADDR_SURF_16_BANK));
1172 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1175 NUM_BANKS(ADDR_SURF_16_BANK));
1176 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1179 NUM_BANKS(ADDR_SURF_8_BANK));
1180 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1183 NUM_BANKS(ADDR_SURF_4_BANK));
1184 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1187 NUM_BANKS(ADDR_SURF_16_BANK));
1188 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1191 NUM_BANKS(ADDR_SURF_16_BANK));
1192 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1195 NUM_BANKS(ADDR_SURF_16_BANK));
1196 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1199 NUM_BANKS(ADDR_SURF_16_BANK));
1200 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1203 NUM_BANKS(ADDR_SURF_16_BANK));
1204 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1207 NUM_BANKS(ADDR_SURF_8_BANK));
1208 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1211 NUM_BANKS(ADDR_SURF_4_BANK));
1213 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1214 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1215 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1216 if (reg_offset != 7)
1217 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1220 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1222 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1223 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1224 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1226 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1227 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1228 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1230 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1231 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1232 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1233 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1235 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1236 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1238 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1239 TILE_SPLIT(split_equal_to_row_size));
1240 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1241 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1242 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1243 TILE_SPLIT(split_equal_to_row_size));
1244 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1245 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1246 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1247 TILE_SPLIT(split_equal_to_row_size));
1248 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1249 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1250 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1251 TILE_SPLIT(split_equal_to_row_size));
1252 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1253 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1254 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1255 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1256 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1257 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1259 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1260 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1261 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1262 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1263 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1264 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1265 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1266 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1267 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1268 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1269 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1270 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1271 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1272 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1276 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1279 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1280 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1281 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1282 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1283 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1284 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1285 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1286 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1287 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1288 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1289 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1290 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1291 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1292 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1293 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1294 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1295 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1299 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1301 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1303 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1307 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1308 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1309 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1310 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1311 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1312 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1313 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1314 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1315 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1316 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1317 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1318 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1319 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1320 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1321 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1322 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1323 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1324 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1325 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1326 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1328 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1329 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1330 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1332 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1333 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1334 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1335 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1336 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1337 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1339 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1342 NUM_BANKS(ADDR_SURF_16_BANK));
1343 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1346 NUM_BANKS(ADDR_SURF_16_BANK));
1347 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1350 NUM_BANKS(ADDR_SURF_16_BANK));
1351 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1354 NUM_BANKS(ADDR_SURF_16_BANK));
1355 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1358 NUM_BANKS(ADDR_SURF_8_BANK));
1359 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1362 NUM_BANKS(ADDR_SURF_4_BANK));
1363 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1366 NUM_BANKS(ADDR_SURF_4_BANK));
1367 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1370 NUM_BANKS(ADDR_SURF_16_BANK));
1371 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1374 NUM_BANKS(ADDR_SURF_16_BANK));
1375 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1378 NUM_BANKS(ADDR_SURF_16_BANK));
1379 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1382 NUM_BANKS(ADDR_SURF_8_BANK));
1383 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1384 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1385 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1386 NUM_BANKS(ADDR_SURF_16_BANK));
1387 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1388 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1389 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1390 NUM_BANKS(ADDR_SURF_8_BANK));
1391 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1394 NUM_BANKS(ADDR_SURF_4_BANK));
1396 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1397 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1398 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1399 if (reg_offset != 7)
1400 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1406 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1407 PIPE_CONFIG(ADDR_SURF_P2) |
1408 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1409 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1410 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1411 PIPE_CONFIG(ADDR_SURF_P2) |
1412 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1413 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1414 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1415 PIPE_CONFIG(ADDR_SURF_P2) |
1416 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1417 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1418 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1419 PIPE_CONFIG(ADDR_SURF_P2) |
1420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1421 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1422 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1423 PIPE_CONFIG(ADDR_SURF_P2) |
1424 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1425 TILE_SPLIT(split_equal_to_row_size));
1426 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1427 PIPE_CONFIG(ADDR_SURF_P2) |
1428 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1429 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1430 PIPE_CONFIG(ADDR_SURF_P2) |
1431 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1432 TILE_SPLIT(split_equal_to_row_size));
1433 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1434 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1435 PIPE_CONFIG(ADDR_SURF_P2));
1436 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1437 PIPE_CONFIG(ADDR_SURF_P2) |
1438 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1439 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1440 PIPE_CONFIG(ADDR_SURF_P2) |
1441 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1443 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1444 PIPE_CONFIG(ADDR_SURF_P2) |
1445 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1447 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1448 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1449 PIPE_CONFIG(ADDR_SURF_P2) |
1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1451 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1452 PIPE_CONFIG(ADDR_SURF_P2) |
1453 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1454 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1455 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1456 PIPE_CONFIG(ADDR_SURF_P2) |
1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1459 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1460 PIPE_CONFIG(ADDR_SURF_P2) |
1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1463 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1464 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1465 PIPE_CONFIG(ADDR_SURF_P2) |
1466 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1467 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1468 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1469 PIPE_CONFIG(ADDR_SURF_P2) |
1470 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1471 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1472 PIPE_CONFIG(ADDR_SURF_P2) |
1473 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1474 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1475 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1476 PIPE_CONFIG(ADDR_SURF_P2) |
1477 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1478 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1479 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1480 PIPE_CONFIG(ADDR_SURF_P2) |
1481 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1482 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1483 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1484 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1485 PIPE_CONFIG(ADDR_SURF_P2) |
1486 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1487 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1488 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1489 PIPE_CONFIG(ADDR_SURF_P2) |
1490 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1491 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1492 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1493 PIPE_CONFIG(ADDR_SURF_P2) |
1494 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1495 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1496 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1497 PIPE_CONFIG(ADDR_SURF_P2) |
1498 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1499 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1500 PIPE_CONFIG(ADDR_SURF_P2) |
1501 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1502 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1503 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1504 PIPE_CONFIG(ADDR_SURF_P2) |
1505 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1506 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1507 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1509 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1512 NUM_BANKS(ADDR_SURF_8_BANK));
1513 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1516 NUM_BANKS(ADDR_SURF_8_BANK));
1517 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1520 NUM_BANKS(ADDR_SURF_8_BANK));
1521 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1524 NUM_BANKS(ADDR_SURF_8_BANK));
1525 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1528 NUM_BANKS(ADDR_SURF_8_BANK));
1529 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1532 NUM_BANKS(ADDR_SURF_8_BANK));
1533 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1536 NUM_BANKS(ADDR_SURF_8_BANK));
1537 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1540 NUM_BANKS(ADDR_SURF_16_BANK));
1541 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1544 NUM_BANKS(ADDR_SURF_16_BANK));
1545 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1548 NUM_BANKS(ADDR_SURF_16_BANK));
1549 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1550 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1551 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1552 NUM_BANKS(ADDR_SURF_16_BANK));
1553 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1556 NUM_BANKS(ADDR_SURF_16_BANK));
1557 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1559 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1560 NUM_BANKS(ADDR_SURF_16_BANK));
1561 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1562 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1563 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1564 NUM_BANKS(ADDR_SURF_8_BANK));
1566 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1567 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1568 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1569 if (reg_offset != 7)
1570 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1576 * gfx_v7_0_select_se_sh - select which SE, SH to address
1578 * @adev: amdgpu_device pointer
1579 * @se_num: shader engine to address
1580 * @sh_num: sh block to address
1582 * Select which SE, SH combinations to address. Certain
1583 * registers are instanced per SE or SH. 0xffffffff means
1584 * broadcast to all SEs or SHs (CIK).
1586 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev,
1587 u32 se_num, u32 sh_num, u32 instance)
1591 if (instance == 0xffffffff)
1592 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1594 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1596 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1597 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1598 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1599 else if (se_num == 0xffffffff)
1600 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1601 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1602 else if (sh_num == 0xffffffff)
1603 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1604 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1606 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1607 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1608 WREG32(mmGRBM_GFX_INDEX, data);
1612 * gfx_v7_0_create_bitmask - create a bitmask
1614 * @bit_width: length of the mask
1616 * create a variable length bit mask (CIK).
1617 * Returns the bitmask.
1619 static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1621 return (u32)((1ULL << bit_width) - 1);
1625 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1627 * @adev: amdgpu_device pointer
1629 * Calculates the bitmask of enabled RBs (CIK).
1630 * Returns the enabled RB bitmask.
1632 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1636 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1637 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1639 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1640 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1642 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1643 adev->gfx.config.max_sh_per_se);
1645 return (~data) & mask;
1649 gfx_v7_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
1651 switch (adev->asic_type) {
1653 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
1654 SE_XSEL(1) | SE_YSEL(1);
1658 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
1659 RB_XSEL2(1) | PKR_MAP(2) | PKR_XSEL(1) |
1660 PKR_YSEL(1) | SE_MAP(2) | SE_XSEL(2) |
1662 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
1666 *rconf |= RB_MAP_PKR0(2);
1675 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1681 gfx_v7_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1682 u32 raster_config, u32 raster_config_1,
1683 unsigned rb_mask, unsigned num_rb)
1685 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1686 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1687 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1688 unsigned rb_per_se = num_rb / num_se;
1689 unsigned se_mask[4];
1692 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1693 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1694 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1695 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1697 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1698 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1699 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1701 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1702 (!se_mask[2] && !se_mask[3]))) {
1703 raster_config_1 &= ~SE_PAIR_MAP_MASK;
1705 if (!se_mask[0] && !se_mask[1]) {
1707 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
1710 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
1714 for (se = 0; se < num_se; se++) {
1715 unsigned raster_config_se = raster_config;
1716 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1717 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1718 int idx = (se / 2) * 2;
1720 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1721 raster_config_se &= ~SE_MAP_MASK;
1723 if (!se_mask[idx]) {
1724 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
1726 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
1730 pkr0_mask &= rb_mask;
1731 pkr1_mask &= rb_mask;
1732 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1733 raster_config_se &= ~PKR_MAP_MASK;
1736 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
1738 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
1742 if (rb_per_se >= 2) {
1743 unsigned rb0_mask = 1 << (se * rb_per_se);
1744 unsigned rb1_mask = rb0_mask << 1;
1746 rb0_mask &= rb_mask;
1747 rb1_mask &= rb_mask;
1748 if (!rb0_mask || !rb1_mask) {
1749 raster_config_se &= ~RB_MAP_PKR0_MASK;
1753 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
1756 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
1760 if (rb_per_se > 2) {
1761 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1762 rb1_mask = rb0_mask << 1;
1763 rb0_mask &= rb_mask;
1764 rb1_mask &= rb_mask;
1765 if (!rb0_mask || !rb1_mask) {
1766 raster_config_se &= ~RB_MAP_PKR1_MASK;
1770 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
1773 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
1779 /* GRBM_GFX_INDEX has a different offset on CI+ */
1780 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1781 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1782 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1785 /* GRBM_GFX_INDEX has a different offset on CI+ */
1786 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1790 * gfx_v7_0_setup_rb - setup the RBs on the asic
1792 * @adev: amdgpu_device pointer
1793 * @se_num: number of SEs (shader engines) for the asic
1794 * @sh_per_se: number of SH blocks per SE for the asic
1796 * Configures per-SE/SH RB registers (CIK).
1798 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1802 u32 raster_config = 0, raster_config_1 = 0;
1804 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1805 adev->gfx.config.max_sh_per_se;
1806 unsigned num_rb_pipes;
1808 mutex_lock(&adev->grbm_idx_mutex);
1809 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1810 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1811 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
1812 data = gfx_v7_0_get_rb_active_bitmap(adev);
1813 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1814 rb_bitmap_width_per_sh);
1817 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1819 adev->gfx.config.backend_enable_mask = active_rbs;
1820 adev->gfx.config.num_rbs = hweight32(active_rbs);
1822 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1823 adev->gfx.config.max_shader_engines, 16);
1825 gfx_v7_0_raster_config(adev, &raster_config, &raster_config_1);
1827 if (!adev->gfx.config.backend_enable_mask ||
1828 adev->gfx.config.num_rbs >= num_rb_pipes) {
1829 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1830 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
1832 gfx_v7_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
1833 adev->gfx.config.backend_enable_mask,
1836 mutex_unlock(&adev->grbm_idx_mutex);
1840 * gmc_v7_0_init_compute_vmid - gart enable
1842 * @rdev: amdgpu_device pointer
1844 * Initialize compute vmid sh_mem registers
1847 #define DEFAULT_SH_MEM_BASES (0x6000)
1848 #define FIRST_COMPUTE_VMID (8)
1849 #define LAST_COMPUTE_VMID (16)
1850 static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1853 uint32_t sh_mem_config;
1854 uint32_t sh_mem_bases;
1857 * Configure apertures:
1858 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1859 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1860 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1862 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1863 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1864 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1865 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1866 mutex_lock(&adev->srbm_mutex);
1867 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1868 cik_srbm_select(adev, 0, 0, 0, i);
1869 /* CP and shaders */
1870 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1871 WREG32(mmSH_MEM_APE1_BASE, 1);
1872 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1873 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1875 cik_srbm_select(adev, 0, 0, 0, 0);
1876 mutex_unlock(&adev->srbm_mutex);
1880 * gfx_v7_0_gpu_init - setup the 3D engine
1882 * @adev: amdgpu_device pointer
1884 * Configures the 3D engine and tiling configuration
1885 * registers so that the 3D engine is usable.
1887 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1889 u32 tmp, sh_mem_cfg;
1892 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1894 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1895 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1896 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1898 gfx_v7_0_tiling_mode_table_init(adev);
1900 gfx_v7_0_setup_rb(adev);
1901 gfx_v7_0_get_cu_info(adev);
1903 /* set HW defaults for 3D engine */
1904 WREG32(mmCP_MEQ_THRESHOLDS,
1905 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1906 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1908 mutex_lock(&adev->grbm_idx_mutex);
1910 * making sure that the following register writes will be broadcasted
1911 * to all the shaders
1913 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1915 /* XXX SH_MEM regs */
1916 /* where to put LDS, scratch, GPUVM in FSA64 space */
1917 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1918 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1920 mutex_lock(&adev->srbm_mutex);
1921 for (i = 0; i < 16; i++) {
1922 cik_srbm_select(adev, 0, 0, 0, i);
1923 /* CP and shaders */
1924 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1925 WREG32(mmSH_MEM_APE1_BASE, 1);
1926 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1927 WREG32(mmSH_MEM_BASES, 0);
1929 cik_srbm_select(adev, 0, 0, 0, 0);
1930 mutex_unlock(&adev->srbm_mutex);
1932 gmc_v7_0_init_compute_vmid(adev);
1934 WREG32(mmSX_DEBUG_1, 0x20);
1936 WREG32(mmTA_CNTL_AUX, 0x00010000);
1938 tmp = RREG32(mmSPI_CONFIG_CNTL);
1940 WREG32(mmSPI_CONFIG_CNTL, tmp);
1942 WREG32(mmSQ_CONFIG, 1);
1944 WREG32(mmDB_DEBUG, 0);
1946 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1948 WREG32(mmDB_DEBUG2, tmp);
1950 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1952 WREG32(mmDB_DEBUG3, tmp);
1954 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1956 WREG32(mmCB_HW_CONTROL, tmp);
1958 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1960 WREG32(mmPA_SC_FIFO_SIZE,
1961 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1962 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1963 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1964 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1966 WREG32(mmVGT_NUM_INSTANCES, 1);
1968 WREG32(mmCP_PERFMON_CNTL, 0);
1970 WREG32(mmSQ_CONFIG, 0);
1972 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1973 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1974 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1976 WREG32(mmVGT_CACHE_INVALIDATION,
1977 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1978 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1980 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1981 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1983 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1984 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1985 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1986 mutex_unlock(&adev->grbm_idx_mutex);
1992 * GPU scratch registers helpers function.
1995 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
1997 * @adev: amdgpu_device pointer
1999 * Set up the number and offset of the CP scratch registers.
2000 * NOTE: use of CP scratch registers is a legacy inferface and
2001 * is not used by default on newer asics (r6xx+). On newer asics,
2002 * memory buffers are used for fences rather than scratch regs.
2004 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
2006 adev->gfx.scratch.num_reg = 7;
2007 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
2008 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
2012 * gfx_v7_0_ring_test_ring - basic gfx ring test
2014 * @adev: amdgpu_device pointer
2015 * @ring: amdgpu_ring structure holding ring information
2017 * Allocate a scratch register and write to it using the gfx ring (CIK).
2018 * Provides a basic gfx ring test to verify that the ring is working.
2019 * Used by gfx_v7_0_cp_gfx_resume();
2020 * Returns 0 on success, error on failure.
2022 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2024 struct amdgpu_device *adev = ring->adev;
2030 r = amdgpu_gfx_scratch_get(adev, &scratch);
2032 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
2035 WREG32(scratch, 0xCAFEDEAD);
2036 r = amdgpu_ring_alloc(ring, 3);
2038 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
2039 amdgpu_gfx_scratch_free(adev, scratch);
2042 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2043 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2044 amdgpu_ring_write(ring, 0xDEADBEEF);
2045 amdgpu_ring_commit(ring);
2047 for (i = 0; i < adev->usec_timeout; i++) {
2048 tmp = RREG32(scratch);
2049 if (tmp == 0xDEADBEEF)
2053 if (i < adev->usec_timeout) {
2054 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2056 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2057 ring->idx, scratch, tmp);
2060 amdgpu_gfx_scratch_free(adev, scratch);
2065 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
2067 * @adev: amdgpu_device pointer
2068 * @ridx: amdgpu ring index
2070 * Emits an hdp flush on the cp.
2072 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2075 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
2077 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2080 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2083 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2089 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2092 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2093 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2094 WAIT_REG_MEM_FUNCTION(3) | /* == */
2095 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2096 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2097 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2098 amdgpu_ring_write(ring, ref_and_mask);
2099 amdgpu_ring_write(ring, ref_and_mask);
2100 amdgpu_ring_write(ring, 0x20); /* poll interval */
2103 static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
2105 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2106 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
2109 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2110 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
2116 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
2118 * @adev: amdgpu_device pointer
2119 * @ridx: amdgpu ring index
2121 * Emits an hdp invalidate on the cp.
2123 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
2125 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2126 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2127 WRITE_DATA_DST_SEL(0) |
2129 amdgpu_ring_write(ring, mmHDP_DEBUG0);
2130 amdgpu_ring_write(ring, 0);
2131 amdgpu_ring_write(ring, 1);
2135 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2137 * @adev: amdgpu_device pointer
2138 * @fence: amdgpu fence object
2140 * Emits a fence sequnce number on the gfx ring and flushes
2143 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2144 u64 seq, unsigned flags)
2146 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2147 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2148 /* Workaround for cache flush problems. First send a dummy EOP
2149 * event down the pipe with seq one below.
2151 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2152 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2154 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2156 amdgpu_ring_write(ring, addr & 0xfffffffc);
2157 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2158 DATA_SEL(1) | INT_SEL(0));
2159 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2160 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2162 /* Then send the real EOP event down the pipe. */
2163 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2164 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2166 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2168 amdgpu_ring_write(ring, addr & 0xfffffffc);
2169 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2170 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2171 amdgpu_ring_write(ring, lower_32_bits(seq));
2172 amdgpu_ring_write(ring, upper_32_bits(seq));
2176 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2178 * @adev: amdgpu_device pointer
2179 * @fence: amdgpu fence object
2181 * Emits a fence sequnce number on the compute ring and flushes
2184 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2188 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2189 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2191 /* RELEASE_MEM - flush caches, send int */
2192 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2193 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2195 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2197 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2198 amdgpu_ring_write(ring, addr & 0xfffffffc);
2199 amdgpu_ring_write(ring, upper_32_bits(addr));
2200 amdgpu_ring_write(ring, lower_32_bits(seq));
2201 amdgpu_ring_write(ring, upper_32_bits(seq));
2208 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2210 * @ring: amdgpu_ring structure holding ring information
2211 * @ib: amdgpu indirect buffer object
2213 * Emits an DE (drawing engine) or CE (constant engine) IB
2214 * on the gfx ring. IBs are usually generated by userspace
2215 * acceleration drivers and submitted to the kernel for
2216 * sheduling on the ring. This function schedules the IB
2217 * on the gfx ring for execution by the GPU.
2219 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2220 struct amdgpu_ib *ib,
2221 unsigned vm_id, bool ctx_switch)
2223 u32 header, control = 0;
2225 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2227 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2228 amdgpu_ring_write(ring, 0);
2231 if (ib->flags & AMDGPU_IB_FLAG_CE)
2232 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2234 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2236 control |= ib->length_dw | (vm_id << 24);
2238 amdgpu_ring_write(ring, header);
2239 amdgpu_ring_write(ring,
2243 (ib->gpu_addr & 0xFFFFFFFC));
2244 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2245 amdgpu_ring_write(ring, control);
2248 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2249 struct amdgpu_ib *ib,
2250 unsigned vm_id, bool ctx_switch)
2252 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
2254 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2255 amdgpu_ring_write(ring,
2259 (ib->gpu_addr & 0xFFFFFFFC));
2260 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2261 amdgpu_ring_write(ring, control);
2264 static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2268 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
2269 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
2270 gfx_v7_0_ring_emit_vgt_flush(ring);
2271 /* set load_global_config & load_global_uconfig */
2273 /* set load_cs_sh_regs */
2275 /* set load_per_context_state & load_gfx_sh_regs */
2279 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2280 amdgpu_ring_write(ring, dw2);
2281 amdgpu_ring_write(ring, 0);
2285 * gfx_v7_0_ring_test_ib - basic ring IB test
2287 * @ring: amdgpu_ring structure holding ring information
2289 * Allocate an IB and execute it on the gfx ring (CIK).
2290 * Provides a basic gfx ring test to verify that IBs are working.
2291 * Returns 0 on success, error on failure.
2293 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
2295 struct amdgpu_device *adev = ring->adev;
2296 struct amdgpu_ib ib;
2297 struct dma_fence *f = NULL;
2302 r = amdgpu_gfx_scratch_get(adev, &scratch);
2304 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
2307 WREG32(scratch, 0xCAFEDEAD);
2308 memset(&ib, 0, sizeof(ib));
2309 r = amdgpu_ib_get(adev, NULL, 256, &ib);
2311 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
2314 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2315 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2316 ib.ptr[2] = 0xDEADBEEF;
2319 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
2323 r = dma_fence_wait_timeout(f, false, timeout);
2325 DRM_ERROR("amdgpu: IB test timed out\n");
2329 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
2332 tmp = RREG32(scratch);
2333 if (tmp == 0xDEADBEEF) {
2334 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
2337 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2343 amdgpu_ib_free(adev, &ib, NULL);
2346 amdgpu_gfx_scratch_free(adev, scratch);
2352 * On CIK, gfx and compute now have independant command processors.
2355 * Gfx consists of a single ring and can process both gfx jobs and
2356 * compute jobs. The gfx CP consists of three microengines (ME):
2357 * PFP - Pre-Fetch Parser
2359 * CE - Constant Engine
2360 * The PFP and ME make up what is considered the Drawing Engine (DE).
2361 * The CE is an asynchronous engine used for updating buffer desciptors
2362 * used by the DE so that they can be loaded into cache in parallel
2363 * while the DE is processing state update packets.
2366 * The compute CP consists of two microengines (ME):
2367 * MEC1 - Compute MicroEngine 1
2368 * MEC2 - Compute MicroEngine 2
2369 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2370 * The queues are exposed to userspace and are programmed directly
2371 * by the compute runtime.
2374 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2376 * @adev: amdgpu_device pointer
2377 * @enable: enable or disable the MEs
2379 * Halts or unhalts the gfx MEs.
2381 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2386 WREG32(mmCP_ME_CNTL, 0);
2388 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2389 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2390 adev->gfx.gfx_ring[i].ready = false;
2396 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2398 * @adev: amdgpu_device pointer
2400 * Loads the gfx PFP, ME, and CE ucode.
2401 * Returns 0 for success, -EINVAL if the ucode is not available.
2403 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2405 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2406 const struct gfx_firmware_header_v1_0 *ce_hdr;
2407 const struct gfx_firmware_header_v1_0 *me_hdr;
2408 const __le32 *fw_data;
2409 unsigned i, fw_size;
2411 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2414 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2415 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2416 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2418 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2419 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2420 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2421 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2422 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2423 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2424 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2425 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2426 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2428 gfx_v7_0_cp_gfx_enable(adev, false);
2431 fw_data = (const __le32 *)
2432 (adev->gfx.pfp_fw->data +
2433 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2434 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2435 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2436 for (i = 0; i < fw_size; i++)
2437 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2438 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2441 fw_data = (const __le32 *)
2442 (adev->gfx.ce_fw->data +
2443 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2444 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2445 WREG32(mmCP_CE_UCODE_ADDR, 0);
2446 for (i = 0; i < fw_size; i++)
2447 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2448 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2451 fw_data = (const __le32 *)
2452 (adev->gfx.me_fw->data +
2453 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2454 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2455 WREG32(mmCP_ME_RAM_WADDR, 0);
2456 for (i = 0; i < fw_size; i++)
2457 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2458 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2464 * gfx_v7_0_cp_gfx_start - start the gfx ring
2466 * @adev: amdgpu_device pointer
2468 * Enables the ring and loads the clear state context and other
2469 * packets required to init the ring.
2470 * Returns 0 for success, error for failure.
2472 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2474 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2475 const struct cs_section_def *sect = NULL;
2476 const struct cs_extent_def *ext = NULL;
2480 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2481 WREG32(mmCP_ENDIAN_SWAP, 0);
2482 WREG32(mmCP_DEVICE_ID, 1);
2484 gfx_v7_0_cp_gfx_enable(adev, true);
2486 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2488 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2492 /* init the CE partitions. CE only used for gfx on CIK */
2493 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2494 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2495 amdgpu_ring_write(ring, 0x8000);
2496 amdgpu_ring_write(ring, 0x8000);
2498 /* clear state buffer */
2499 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2500 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2502 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2503 amdgpu_ring_write(ring, 0x80000000);
2504 amdgpu_ring_write(ring, 0x80000000);
2506 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2507 for (ext = sect->section; ext->extent != NULL; ++ext) {
2508 if (sect->id == SECT_CONTEXT) {
2509 amdgpu_ring_write(ring,
2510 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2511 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2512 for (i = 0; i < ext->reg_count; i++)
2513 amdgpu_ring_write(ring, ext->extent[i]);
2518 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2519 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2520 switch (adev->asic_type) {
2522 amdgpu_ring_write(ring, 0x16000012);
2523 amdgpu_ring_write(ring, 0x00000000);
2526 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2527 amdgpu_ring_write(ring, 0x00000000);
2531 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2532 amdgpu_ring_write(ring, 0x00000000);
2535 amdgpu_ring_write(ring, 0x3a00161a);
2536 amdgpu_ring_write(ring, 0x0000002e);
2539 amdgpu_ring_write(ring, 0x00000000);
2540 amdgpu_ring_write(ring, 0x00000000);
2544 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2545 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2547 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2548 amdgpu_ring_write(ring, 0);
2550 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2551 amdgpu_ring_write(ring, 0x00000316);
2552 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2553 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2555 amdgpu_ring_commit(ring);
2561 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2563 * @adev: amdgpu_device pointer
2565 * Program the location and size of the gfx ring buffer
2566 * and test it to make sure it's working.
2567 * Returns 0 for success, error for failure.
2569 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2571 struct amdgpu_ring *ring;
2574 u64 rb_addr, rptr_addr;
2577 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2578 if (adev->asic_type != CHIP_HAWAII)
2579 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2581 /* Set the write pointer delay */
2582 WREG32(mmCP_RB_WPTR_DELAY, 0);
2584 /* set the RB to use vmid 0 */
2585 WREG32(mmCP_RB_VMID, 0);
2587 WREG32(mmSCRATCH_ADDR, 0);
2589 /* ring 0 - compute and gfx */
2590 /* Set ring buffer size */
2591 ring = &adev->gfx.gfx_ring[0];
2592 rb_bufsz = order_base_2(ring->ring_size / 8);
2593 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2595 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2597 WREG32(mmCP_RB0_CNTL, tmp);
2599 /* Initialize the ring buffer's read and write pointers */
2600 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2602 WREG32(mmCP_RB0_WPTR, ring->wptr);
2604 /* set the wb address wether it's enabled or not */
2605 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2606 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2607 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2609 /* scratch register shadowing is no longer supported */
2610 WREG32(mmSCRATCH_UMSK, 0);
2613 WREG32(mmCP_RB0_CNTL, tmp);
2615 rb_addr = ring->gpu_addr >> 8;
2616 WREG32(mmCP_RB0_BASE, rb_addr);
2617 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2619 /* start the ring */
2620 gfx_v7_0_cp_gfx_start(adev);
2622 r = amdgpu_ring_test_ring(ring);
2624 ring->ready = false;
2631 static u32 gfx_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
2633 return ring->adev->wb.wb[ring->rptr_offs];
2636 static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2638 struct amdgpu_device *adev = ring->adev;
2640 return RREG32(mmCP_RB0_WPTR);
2643 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2645 struct amdgpu_device *adev = ring->adev;
2647 WREG32(mmCP_RB0_WPTR, ring->wptr);
2648 (void)RREG32(mmCP_RB0_WPTR);
2651 static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2653 /* XXX check if swapping is necessary on BE */
2654 return ring->adev->wb.wb[ring->wptr_offs];
2657 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2659 struct amdgpu_device *adev = ring->adev;
2661 /* XXX check if swapping is necessary on BE */
2662 adev->wb.wb[ring->wptr_offs] = ring->wptr;
2663 WDOORBELL32(ring->doorbell_index, ring->wptr);
2667 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2669 * @adev: amdgpu_device pointer
2670 * @enable: enable or disable the MEs
2672 * Halts or unhalts the compute MEs.
2674 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2679 WREG32(mmCP_MEC_CNTL, 0);
2681 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2682 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2683 adev->gfx.compute_ring[i].ready = false;
2689 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2691 * @adev: amdgpu_device pointer
2693 * Loads the compute MEC1&2 ucode.
2694 * Returns 0 for success, -EINVAL if the ucode is not available.
2696 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2698 const struct gfx_firmware_header_v1_0 *mec_hdr;
2699 const __le32 *fw_data;
2700 unsigned i, fw_size;
2702 if (!adev->gfx.mec_fw)
2705 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2706 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2707 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2708 adev->gfx.mec_feature_version = le32_to_cpu(
2709 mec_hdr->ucode_feature_version);
2711 gfx_v7_0_cp_compute_enable(adev, false);
2714 fw_data = (const __le32 *)
2715 (adev->gfx.mec_fw->data +
2716 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2717 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2718 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2719 for (i = 0; i < fw_size; i++)
2720 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2721 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2723 if (adev->asic_type == CHIP_KAVERI) {
2724 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2726 if (!adev->gfx.mec2_fw)
2729 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2730 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2731 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2732 adev->gfx.mec2_feature_version = le32_to_cpu(
2733 mec2_hdr->ucode_feature_version);
2736 fw_data = (const __le32 *)
2737 (adev->gfx.mec2_fw->data +
2738 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2739 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2740 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2741 for (i = 0; i < fw_size; i++)
2742 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2743 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2750 * gfx_v7_0_cp_compute_fini - stop the compute queues
2752 * @adev: amdgpu_device pointer
2754 * Stop the compute queues and tear down the driver queue
2757 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2761 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2762 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2764 if (ring->mqd_obj) {
2765 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2766 if (unlikely(r != 0))
2767 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2769 amdgpu_bo_unpin(ring->mqd_obj);
2770 amdgpu_bo_unreserve(ring->mqd_obj);
2772 amdgpu_bo_unref(&ring->mqd_obj);
2773 ring->mqd_obj = NULL;
2778 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2782 if (adev->gfx.mec.hpd_eop_obj) {
2783 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2784 if (unlikely(r != 0))
2785 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2786 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2787 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2789 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2790 adev->gfx.mec.hpd_eop_obj = NULL;
2794 #define MEC_HPD_SIZE 2048
2796 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2802 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2803 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2804 * Nonetheless, we assign only 1 pipe because all other pipes will
2807 adev->gfx.mec.num_mec = 1;
2808 adev->gfx.mec.num_pipe = 1;
2809 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
2811 if (adev->gfx.mec.hpd_eop_obj == NULL) {
2812 r = amdgpu_bo_create(adev,
2813 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
2815 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2816 &adev->gfx.mec.hpd_eop_obj);
2818 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2823 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2824 if (unlikely(r != 0)) {
2825 gfx_v7_0_mec_fini(adev);
2828 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2829 &adev->gfx.mec.hpd_eop_gpu_addr);
2831 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2832 gfx_v7_0_mec_fini(adev);
2835 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2837 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2838 gfx_v7_0_mec_fini(adev);
2842 /* clear memory. Not sure if this is required or not */
2843 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
2845 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2846 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2851 struct hqd_registers
2853 u32 cp_mqd_base_addr;
2854 u32 cp_mqd_base_addr_hi;
2857 u32 cp_hqd_persistent_state;
2858 u32 cp_hqd_pipe_priority;
2859 u32 cp_hqd_queue_priority;
2862 u32 cp_hqd_pq_base_hi;
2864 u32 cp_hqd_pq_rptr_report_addr;
2865 u32 cp_hqd_pq_rptr_report_addr_hi;
2866 u32 cp_hqd_pq_wptr_poll_addr;
2867 u32 cp_hqd_pq_wptr_poll_addr_hi;
2868 u32 cp_hqd_pq_doorbell_control;
2870 u32 cp_hqd_pq_control;
2871 u32 cp_hqd_ib_base_addr;
2872 u32 cp_hqd_ib_base_addr_hi;
2874 u32 cp_hqd_ib_control;
2875 u32 cp_hqd_iq_timer;
2877 u32 cp_hqd_dequeue_request;
2878 u32 cp_hqd_dma_offload;
2879 u32 cp_hqd_sema_cmd;
2880 u32 cp_hqd_msg_type;
2881 u32 cp_hqd_atomic0_preop_lo;
2882 u32 cp_hqd_atomic0_preop_hi;
2883 u32 cp_hqd_atomic1_preop_lo;
2884 u32 cp_hqd_atomic1_preop_hi;
2885 u32 cp_hqd_hq_scheduler0;
2886 u32 cp_hqd_hq_scheduler1;
2893 u32 dispatch_initiator;
2897 u32 pipeline_stat_enable;
2898 u32 perf_counter_enable;
2904 u32 resource_limits;
2905 u32 static_thread_mgmt01[2];
2907 u32 static_thread_mgmt23[2];
2909 u32 thread_trace_enable;
2912 u32 vgtcs_invoke_count[2];
2913 struct hqd_registers queue_state;
2915 u32 interrupt_queue[64];
2919 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2921 * @adev: amdgpu_device pointer
2923 * Program the compute queues and test them to make sure they
2925 * Returns 0 for success, error for failure.
2927 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
2931 bool use_doorbell = true;
2937 struct bonaire_mqd *mqd;
2938 struct amdgpu_ring *ring;
2940 /* fix up chicken bits */
2941 tmp = RREG32(mmCP_CPF_DEBUG);
2943 WREG32(mmCP_CPF_DEBUG, tmp);
2945 /* init the pipes */
2946 mutex_lock(&adev->srbm_mutex);
2947 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2948 int me = (i < 4) ? 1 : 2;
2949 int pipe = (i < 4) ? i : (i - 4);
2951 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
2953 cik_srbm_select(adev, me, pipe, 0, 0);
2955 /* write the EOP addr */
2956 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2957 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2959 /* set the VMID assigned */
2960 WREG32(mmCP_HPD_EOP_VMID, 0);
2962 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2963 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2964 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2965 tmp |= order_base_2(MEC_HPD_SIZE / 8);
2966 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2968 cik_srbm_select(adev, 0, 0, 0, 0);
2969 mutex_unlock(&adev->srbm_mutex);
2971 /* init the queues. Just two for now. */
2972 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2973 ring = &adev->gfx.compute_ring[i];
2975 if (ring->mqd_obj == NULL) {
2976 r = amdgpu_bo_create(adev,
2977 sizeof(struct bonaire_mqd),
2979 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2982 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2987 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2988 if (unlikely(r != 0)) {
2989 gfx_v7_0_cp_compute_fini(adev);
2992 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2995 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2996 gfx_v7_0_cp_compute_fini(adev);
2999 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3001 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3002 gfx_v7_0_cp_compute_fini(adev);
3006 /* init the mqd struct */
3007 memset(buf, 0, sizeof(struct bonaire_mqd));
3009 mqd = (struct bonaire_mqd *)buf;
3010 mqd->header = 0xC0310800;
3011 mqd->static_thread_mgmt01[0] = 0xffffffff;
3012 mqd->static_thread_mgmt01[1] = 0xffffffff;
3013 mqd->static_thread_mgmt23[0] = 0xffffffff;
3014 mqd->static_thread_mgmt23[1] = 0xffffffff;
3016 mutex_lock(&adev->srbm_mutex);
3017 cik_srbm_select(adev, ring->me,
3021 /* disable wptr polling */
3022 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3023 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
3024 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3026 /* enable doorbell? */
3027 mqd->queue_state.cp_hqd_pq_doorbell_control =
3028 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3030 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3032 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3033 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3034 mqd->queue_state.cp_hqd_pq_doorbell_control);
3036 /* disable the queue if it's active */
3037 mqd->queue_state.cp_hqd_dequeue_request = 0;
3038 mqd->queue_state.cp_hqd_pq_rptr = 0;
3039 mqd->queue_state.cp_hqd_pq_wptr= 0;
3040 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3041 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3042 for (j = 0; j < adev->usec_timeout; j++) {
3043 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3047 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
3048 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
3049 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3052 /* set the pointer to the MQD */
3053 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
3054 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3055 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
3056 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
3057 /* set MQD vmid to 0 */
3058 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
3059 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
3060 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
3062 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3063 hqd_gpu_addr = ring->gpu_addr >> 8;
3064 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
3065 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3066 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
3067 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
3069 /* set up the HQD, this is similar to CP_RB0_CNTL */
3070 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
3071 mqd->queue_state.cp_hqd_pq_control &=
3072 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
3073 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
3075 mqd->queue_state.cp_hqd_pq_control |=
3076 order_base_2(ring->ring_size / 8);
3077 mqd->queue_state.cp_hqd_pq_control |=
3078 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
3080 mqd->queue_state.cp_hqd_pq_control |=
3081 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
3083 mqd->queue_state.cp_hqd_pq_control &=
3084 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
3085 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
3086 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
3087 mqd->queue_state.cp_hqd_pq_control |=
3088 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
3089 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
3090 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
3092 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3093 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3094 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3095 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3096 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
3097 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3098 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
3100 /* set the wb address wether it's enabled or not */
3101 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3102 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
3103 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
3104 upper_32_bits(wb_gpu_addr) & 0xffff;
3105 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3106 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
3107 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3108 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
3110 /* enable the doorbell if requested */
3112 mqd->queue_state.cp_hqd_pq_doorbell_control =
3113 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3114 mqd->queue_state.cp_hqd_pq_doorbell_control &=
3115 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
3116 mqd->queue_state.cp_hqd_pq_doorbell_control |=
3117 (ring->doorbell_index <<
3118 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
3119 mqd->queue_state.cp_hqd_pq_doorbell_control |=
3120 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3121 mqd->queue_state.cp_hqd_pq_doorbell_control &=
3122 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
3123 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
3126 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
3128 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3129 mqd->queue_state.cp_hqd_pq_doorbell_control);
3131 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3133 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
3134 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3135 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3137 /* set the vmid for the queue */
3138 mqd->queue_state.cp_hqd_vmid = 0;
3139 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
3141 /* activate the queue */
3142 mqd->queue_state.cp_hqd_active = 1;
3143 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
3145 cik_srbm_select(adev, 0, 0, 0, 0);
3146 mutex_unlock(&adev->srbm_mutex);
3148 amdgpu_bo_kunmap(ring->mqd_obj);
3149 amdgpu_bo_unreserve(ring->mqd_obj);
3154 gfx_v7_0_cp_compute_enable(adev, true);
3156 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3157 ring = &adev->gfx.compute_ring[i];
3159 r = amdgpu_ring_test_ring(ring);
3161 ring->ready = false;
3167 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3169 gfx_v7_0_cp_gfx_enable(adev, enable);
3170 gfx_v7_0_cp_compute_enable(adev, enable);
3173 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3177 r = gfx_v7_0_cp_gfx_load_microcode(adev);
3180 r = gfx_v7_0_cp_compute_load_microcode(adev);
3187 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3190 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3193 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3194 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3196 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3197 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3198 WREG32(mmCP_INT_CNTL_RING0, tmp);
3201 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3205 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3207 r = gfx_v7_0_cp_load_microcode(adev);
3211 r = gfx_v7_0_cp_gfx_resume(adev);
3214 r = gfx_v7_0_cp_compute_resume(adev);
3218 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3224 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3226 * @ring: the ring to emmit the commands to
3228 * Sync the command pipeline with the PFP. E.g. wait for everything
3231 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3233 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3234 uint32_t seq = ring->fence_drv.sync_seq;
3235 uint64_t addr = ring->fence_drv.gpu_addr;
3237 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3238 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3239 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3240 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3241 amdgpu_ring_write(ring, addr & 0xfffffffc);
3242 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3243 amdgpu_ring_write(ring, seq);
3244 amdgpu_ring_write(ring, 0xffffffff);
3245 amdgpu_ring_write(ring, 4); /* poll interval */
3248 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3249 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3250 amdgpu_ring_write(ring, 0);
3251 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3252 amdgpu_ring_write(ring, 0);
3258 * VMID 0 is the physical GPU addresses as used by the kernel.
3259 * VMIDs 1-15 are used for userspace clients and are handled
3260 * by the amdgpu vm/hsa code.
3263 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3265 * @adev: amdgpu_device pointer
3267 * Update the page table base and flush the VM TLB
3268 * using the CP (CIK).
3270 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3271 unsigned vm_id, uint64_t pd_addr)
3273 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
3275 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3276 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3277 WRITE_DATA_DST_SEL(0)));
3279 amdgpu_ring_write(ring,
3280 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3282 amdgpu_ring_write(ring,
3283 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3285 amdgpu_ring_write(ring, 0);
3286 amdgpu_ring_write(ring, pd_addr >> 12);
3288 /* bits 0-15 are the VM contexts0-15 */
3289 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3290 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3291 WRITE_DATA_DST_SEL(0)));
3292 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3293 amdgpu_ring_write(ring, 0);
3294 amdgpu_ring_write(ring, 1 << vm_id);
3296 /* wait for the invalidate to complete */
3297 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3298 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3299 WAIT_REG_MEM_FUNCTION(0) | /* always */
3300 WAIT_REG_MEM_ENGINE(0))); /* me */
3301 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3302 amdgpu_ring_write(ring, 0);
3303 amdgpu_ring_write(ring, 0); /* ref */
3304 amdgpu_ring_write(ring, 0); /* mask */
3305 amdgpu_ring_write(ring, 0x20); /* poll interval */
3307 /* compute doesn't have PFP */
3309 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3310 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3311 amdgpu_ring_write(ring, 0x0);
3313 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3314 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3315 amdgpu_ring_write(ring, 0);
3316 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3317 amdgpu_ring_write(ring, 0);
3323 * The RLC is a multi-purpose microengine that handles a
3324 * variety of functions.
3326 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3330 /* save restore block */
3331 if (adev->gfx.rlc.save_restore_obj) {
3332 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3333 if (unlikely(r != 0))
3334 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3335 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3336 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3338 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3339 adev->gfx.rlc.save_restore_obj = NULL;
3342 /* clear state block */
3343 if (adev->gfx.rlc.clear_state_obj) {
3344 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3345 if (unlikely(r != 0))
3346 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3347 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3348 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3350 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3351 adev->gfx.rlc.clear_state_obj = NULL;
3354 /* clear state block */
3355 if (adev->gfx.rlc.cp_table_obj) {
3356 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3357 if (unlikely(r != 0))
3358 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3359 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3360 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3362 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3363 adev->gfx.rlc.cp_table_obj = NULL;
3367 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3370 volatile u32 *dst_ptr;
3372 const struct cs_section_def *cs_data;
3375 /* allocate rlc buffers */
3376 if (adev->flags & AMD_IS_APU) {
3377 if (adev->asic_type == CHIP_KAVERI) {
3378 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3379 adev->gfx.rlc.reg_list_size =
3380 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3382 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3383 adev->gfx.rlc.reg_list_size =
3384 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3387 adev->gfx.rlc.cs_data = ci_cs_data;
3388 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3389 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3391 src_ptr = adev->gfx.rlc.reg_list;
3392 dws = adev->gfx.rlc.reg_list_size;
3393 dws += (5 * 16) + 48 + 48 + 64;
3395 cs_data = adev->gfx.rlc.cs_data;
3398 /* save restore block */
3399 if (adev->gfx.rlc.save_restore_obj == NULL) {
3400 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3401 AMDGPU_GEM_DOMAIN_VRAM,
3402 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
3403 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
3405 &adev->gfx.rlc.save_restore_obj);
3407 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3412 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3413 if (unlikely(r != 0)) {
3414 gfx_v7_0_rlc_fini(adev);
3417 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3418 &adev->gfx.rlc.save_restore_gpu_addr);
3420 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3421 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3422 gfx_v7_0_rlc_fini(adev);
3426 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3428 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3429 gfx_v7_0_rlc_fini(adev);
3432 /* write the sr buffer */
3433 dst_ptr = adev->gfx.rlc.sr_ptr;
3434 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3435 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3436 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3437 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3441 /* clear state block */
3442 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3444 if (adev->gfx.rlc.clear_state_obj == NULL) {
3445 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3446 AMDGPU_GEM_DOMAIN_VRAM,
3447 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
3448 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
3450 &adev->gfx.rlc.clear_state_obj);
3452 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3453 gfx_v7_0_rlc_fini(adev);
3457 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3458 if (unlikely(r != 0)) {
3459 gfx_v7_0_rlc_fini(adev);
3462 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3463 &adev->gfx.rlc.clear_state_gpu_addr);
3465 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3466 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3467 gfx_v7_0_rlc_fini(adev);
3471 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3473 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3474 gfx_v7_0_rlc_fini(adev);
3477 /* set up the cs buffer */
3478 dst_ptr = adev->gfx.rlc.cs_ptr;
3479 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3480 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3481 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3484 if (adev->gfx.rlc.cp_table_size) {
3485 if (adev->gfx.rlc.cp_table_obj == NULL) {
3486 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
3487 AMDGPU_GEM_DOMAIN_VRAM,
3488 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
3489 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
3491 &adev->gfx.rlc.cp_table_obj);
3493 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3494 gfx_v7_0_rlc_fini(adev);
3499 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3500 if (unlikely(r != 0)) {
3501 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3502 gfx_v7_0_rlc_fini(adev);
3505 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3506 &adev->gfx.rlc.cp_table_gpu_addr);
3508 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3509 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3510 gfx_v7_0_rlc_fini(adev);
3513 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3515 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3516 gfx_v7_0_rlc_fini(adev);
3520 gfx_v7_0_init_cp_pg_table(adev);
3522 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3523 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3530 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3534 tmp = RREG32(mmRLC_LB_CNTL);
3536 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3538 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3539 WREG32(mmRLC_LB_CNTL, tmp);
3542 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3547 mutex_lock(&adev->grbm_idx_mutex);
3548 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3549 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3550 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
3551 for (k = 0; k < adev->usec_timeout; k++) {
3552 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3558 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3559 mutex_unlock(&adev->grbm_idx_mutex);
3561 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3562 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3563 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3564 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3565 for (k = 0; k < adev->usec_timeout; k++) {
3566 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3572 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3576 tmp = RREG32(mmRLC_CNTL);
3578 WREG32(mmRLC_CNTL, rlc);
3581 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3585 orig = data = RREG32(mmRLC_CNTL);
3587 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3590 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3591 WREG32(mmRLC_CNTL, data);
3593 for (i = 0; i < adev->usec_timeout; i++) {
3594 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3599 gfx_v7_0_wait_for_rlc_serdes(adev);
3605 static void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3609 tmp = 0x1 | (1 << 1);
3610 WREG32(mmRLC_GPR_REG2, tmp);
3612 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3613 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3614 for (i = 0; i < adev->usec_timeout; i++) {
3615 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3620 for (i = 0; i < adev->usec_timeout; i++) {
3621 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3627 static void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3631 tmp = 0x1 | (0 << 1);
3632 WREG32(mmRLC_GPR_REG2, tmp);
3636 * gfx_v7_0_rlc_stop - stop the RLC ME
3638 * @adev: amdgpu_device pointer
3640 * Halt the RLC ME (MicroEngine) (CIK).
3642 static void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3644 WREG32(mmRLC_CNTL, 0);
3646 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3648 gfx_v7_0_wait_for_rlc_serdes(adev);
3652 * gfx_v7_0_rlc_start - start the RLC ME
3654 * @adev: amdgpu_device pointer
3656 * Unhalt the RLC ME (MicroEngine) (CIK).
3658 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3660 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3662 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3667 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3669 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3671 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3672 WREG32(mmGRBM_SOFT_RESET, tmp);
3674 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3675 WREG32(mmGRBM_SOFT_RESET, tmp);
3680 * gfx_v7_0_rlc_resume - setup the RLC hw
3682 * @adev: amdgpu_device pointer
3684 * Initialize the RLC registers, load the ucode,
3685 * and start the RLC (CIK).
3686 * Returns 0 for success, -EINVAL if the ucode is not available.
3688 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3690 const struct rlc_firmware_header_v1_0 *hdr;
3691 const __le32 *fw_data;
3692 unsigned i, fw_size;
3695 if (!adev->gfx.rlc_fw)
3698 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3699 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3700 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3701 adev->gfx.rlc_feature_version = le32_to_cpu(
3702 hdr->ucode_feature_version);
3704 gfx_v7_0_rlc_stop(adev);
3707 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3708 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3710 gfx_v7_0_rlc_reset(adev);
3712 gfx_v7_0_init_pg(adev);
3714 WREG32(mmRLC_LB_CNTR_INIT, 0);
3715 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3717 mutex_lock(&adev->grbm_idx_mutex);
3718 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3719 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3720 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3721 WREG32(mmRLC_LB_CNTL, 0x80000004);
3722 mutex_unlock(&adev->grbm_idx_mutex);
3724 WREG32(mmRLC_MC_CNTL, 0);
3725 WREG32(mmRLC_UCODE_CNTL, 0);
3727 fw_data = (const __le32 *)
3728 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3729 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3730 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3731 for (i = 0; i < fw_size; i++)
3732 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3733 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3735 /* XXX - find out what chips support lbpw */
3736 gfx_v7_0_enable_lbpw(adev, false);
3738 if (adev->asic_type == CHIP_BONAIRE)
3739 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3741 gfx_v7_0_rlc_start(adev);
3746 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3748 u32 data, orig, tmp, tmp2;
3750 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3752 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3753 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3755 tmp = gfx_v7_0_halt_rlc(adev);
3757 mutex_lock(&adev->grbm_idx_mutex);
3758 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3759 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3760 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3761 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3762 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3763 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3764 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3765 mutex_unlock(&adev->grbm_idx_mutex);
3767 gfx_v7_0_update_rlc(adev, tmp);
3769 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3771 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3773 RREG32(mmCB_CGTT_SCLK_CTRL);
3774 RREG32(mmCB_CGTT_SCLK_CTRL);
3775 RREG32(mmCB_CGTT_SCLK_CTRL);
3776 RREG32(mmCB_CGTT_SCLK_CTRL);
3778 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3782 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3786 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3788 u32 data, orig, tmp = 0;
3790 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3791 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3792 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3793 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3794 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3796 WREG32(mmCP_MEM_SLP_CNTL, data);
3800 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3804 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3806 tmp = gfx_v7_0_halt_rlc(adev);
3808 mutex_lock(&adev->grbm_idx_mutex);
3809 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3810 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3811 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3812 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3813 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3814 WREG32(mmRLC_SERDES_WR_CTRL, data);
3815 mutex_unlock(&adev->grbm_idx_mutex);
3817 gfx_v7_0_update_rlc(adev, tmp);
3819 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3820 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3821 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3822 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3823 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3824 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3825 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3826 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3827 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3828 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3829 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3830 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3832 WREG32(mmCGTS_SM_CTRL_REG, data);
3835 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3838 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3840 data = RREG32(mmRLC_MEM_SLP_CNTL);
3841 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3842 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3843 WREG32(mmRLC_MEM_SLP_CNTL, data);
3846 data = RREG32(mmCP_MEM_SLP_CNTL);
3847 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3848 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3849 WREG32(mmCP_MEM_SLP_CNTL, data);
3852 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3853 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3855 WREG32(mmCGTS_SM_CTRL_REG, data);
3857 tmp = gfx_v7_0_halt_rlc(adev);
3859 mutex_lock(&adev->grbm_idx_mutex);
3860 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3861 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3862 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3863 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3864 WREG32(mmRLC_SERDES_WR_CTRL, data);
3865 mutex_unlock(&adev->grbm_idx_mutex);
3867 gfx_v7_0_update_rlc(adev, tmp);
3871 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3874 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3875 /* order matters! */
3877 gfx_v7_0_enable_mgcg(adev, true);
3878 gfx_v7_0_enable_cgcg(adev, true);
3880 gfx_v7_0_enable_cgcg(adev, false);
3881 gfx_v7_0_enable_mgcg(adev, false);
3883 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3886 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3891 orig = data = RREG32(mmRLC_PG_CNTL);
3892 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3893 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3895 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3897 WREG32(mmRLC_PG_CNTL, data);
3900 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3905 orig = data = RREG32(mmRLC_PG_CNTL);
3906 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3907 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3909 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3911 WREG32(mmRLC_PG_CNTL, data);
3914 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3918 orig = data = RREG32(mmRLC_PG_CNTL);
3919 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3924 WREG32(mmRLC_PG_CNTL, data);
3927 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3931 orig = data = RREG32(mmRLC_PG_CNTL);
3932 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3937 WREG32(mmRLC_PG_CNTL, data);
3940 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3942 const __le32 *fw_data;
3943 volatile u32 *dst_ptr;
3944 int me, i, max_me = 4;
3946 u32 table_offset, table_size;
3948 if (adev->asic_type == CHIP_KAVERI)
3951 if (adev->gfx.rlc.cp_table_ptr == NULL)
3954 /* write the cp table buffer */
3955 dst_ptr = adev->gfx.rlc.cp_table_ptr;
3956 for (me = 0; me < max_me; me++) {
3958 const struct gfx_firmware_header_v1_0 *hdr =
3959 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3960 fw_data = (const __le32 *)
3961 (adev->gfx.ce_fw->data +
3962 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3963 table_offset = le32_to_cpu(hdr->jt_offset);
3964 table_size = le32_to_cpu(hdr->jt_size);
3965 } else if (me == 1) {
3966 const struct gfx_firmware_header_v1_0 *hdr =
3967 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3968 fw_data = (const __le32 *)
3969 (adev->gfx.pfp_fw->data +
3970 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3971 table_offset = le32_to_cpu(hdr->jt_offset);
3972 table_size = le32_to_cpu(hdr->jt_size);
3973 } else if (me == 2) {
3974 const struct gfx_firmware_header_v1_0 *hdr =
3975 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3976 fw_data = (const __le32 *)
3977 (adev->gfx.me_fw->data +
3978 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3979 table_offset = le32_to_cpu(hdr->jt_offset);
3980 table_size = le32_to_cpu(hdr->jt_size);
3981 } else if (me == 3) {
3982 const struct gfx_firmware_header_v1_0 *hdr =
3983 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3984 fw_data = (const __le32 *)
3985 (adev->gfx.mec_fw->data +
3986 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3987 table_offset = le32_to_cpu(hdr->jt_offset);
3988 table_size = le32_to_cpu(hdr->jt_size);
3990 const struct gfx_firmware_header_v1_0 *hdr =
3991 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3992 fw_data = (const __le32 *)
3993 (adev->gfx.mec2_fw->data +
3994 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3995 table_offset = le32_to_cpu(hdr->jt_offset);
3996 table_size = le32_to_cpu(hdr->jt_size);
3999 for (i = 0; i < table_size; i ++) {
4000 dst_ptr[bo_offset + i] =
4001 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
4004 bo_offset += table_size;
4008 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
4013 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
4014 orig = data = RREG32(mmRLC_PG_CNTL);
4015 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4017 WREG32(mmRLC_PG_CNTL, data);
4019 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4020 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4022 WREG32(mmRLC_AUTO_PG_CTRL, data);
4024 orig = data = RREG32(mmRLC_PG_CNTL);
4025 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4027 WREG32(mmRLC_PG_CNTL, data);
4029 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4030 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4032 WREG32(mmRLC_AUTO_PG_CTRL, data);
4034 data = RREG32(mmDB_RENDER_CONTROL);
4038 static void gfx_v7_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4046 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4047 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4049 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
4052 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4056 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4057 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4059 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4060 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4062 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
4064 return (~data) & mask;
4067 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
4071 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4073 tmp = RREG32(mmRLC_MAX_PG_CU);
4074 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
4075 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
4076 WREG32(mmRLC_MAX_PG_CU, tmp);
4079 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
4084 orig = data = RREG32(mmRLC_PG_CNTL);
4085 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
4086 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4088 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4090 WREG32(mmRLC_PG_CNTL, data);
4093 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
4098 orig = data = RREG32(mmRLC_PG_CNTL);
4099 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
4100 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4102 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4104 WREG32(mmRLC_PG_CNTL, data);
4107 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
4108 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
4110 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
4115 if (adev->gfx.rlc.cs_data) {
4116 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4117 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4118 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4119 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
4121 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4122 for (i = 0; i < 3; i++)
4123 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
4125 if (adev->gfx.rlc.reg_list) {
4126 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
4127 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
4128 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
4131 orig = data = RREG32(mmRLC_PG_CNTL);
4132 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
4134 WREG32(mmRLC_PG_CNTL, data);
4136 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
4137 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4139 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
4140 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
4141 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4142 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
4145 WREG32(mmRLC_PG_DELAY, data);
4147 data = RREG32(mmRLC_PG_DELAY_2);
4150 WREG32(mmRLC_PG_DELAY_2, data);
4152 data = RREG32(mmRLC_AUTO_PG_CTRL);
4153 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
4154 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
4155 WREG32(mmRLC_AUTO_PG_CTRL, data);
4159 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
4161 gfx_v7_0_enable_gfx_cgpg(adev, enable);
4162 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
4163 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
4166 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4169 const struct cs_section_def *sect = NULL;
4170 const struct cs_extent_def *ext = NULL;
4172 if (adev->gfx.rlc.cs_data == NULL)
4175 /* begin clear state */
4177 /* context control state */
4180 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4181 for (ext = sect->section; ext->extent != NULL; ++ext) {
4182 if (sect->id == SECT_CONTEXT)
4183 count += 2 + ext->reg_count;
4188 /* pa_sc_raster_config/pa_sc_raster_config1 */
4190 /* end clear state */
4198 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4199 volatile u32 *buffer)
4202 const struct cs_section_def *sect = NULL;
4203 const struct cs_extent_def *ext = NULL;
4205 if (adev->gfx.rlc.cs_data == NULL)
4210 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4211 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4213 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4214 buffer[count++] = cpu_to_le32(0x80000000);
4215 buffer[count++] = cpu_to_le32(0x80000000);
4217 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4218 for (ext = sect->section; ext->extent != NULL; ++ext) {
4219 if (sect->id == SECT_CONTEXT) {
4221 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4222 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4223 for (i = 0; i < ext->reg_count; i++)
4224 buffer[count++] = cpu_to_le32(ext->extent[i]);
4231 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4232 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4233 switch (adev->asic_type) {
4235 buffer[count++] = cpu_to_le32(0x16000012);
4236 buffer[count++] = cpu_to_le32(0x00000000);
4239 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4240 buffer[count++] = cpu_to_le32(0x00000000);
4244 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4245 buffer[count++] = cpu_to_le32(0x00000000);
4248 buffer[count++] = cpu_to_le32(0x3a00161a);
4249 buffer[count++] = cpu_to_le32(0x0000002e);
4252 buffer[count++] = cpu_to_le32(0x00000000);
4253 buffer[count++] = cpu_to_le32(0x00000000);
4257 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4258 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4260 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4261 buffer[count++] = cpu_to_le32(0);
4264 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4266 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4267 AMD_PG_SUPPORT_GFX_SMG |
4268 AMD_PG_SUPPORT_GFX_DMG |
4270 AMD_PG_SUPPORT_GDS |
4271 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4272 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4273 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4274 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4275 gfx_v7_0_init_gfx_cgpg(adev);
4276 gfx_v7_0_enable_cp_pg(adev, true);
4277 gfx_v7_0_enable_gds_pg(adev, true);
4279 gfx_v7_0_init_ao_cu_mask(adev);
4280 gfx_v7_0_update_gfx_pg(adev, true);
4284 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4286 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4287 AMD_PG_SUPPORT_GFX_SMG |
4288 AMD_PG_SUPPORT_GFX_DMG |
4290 AMD_PG_SUPPORT_GDS |
4291 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4292 gfx_v7_0_update_gfx_pg(adev, false);
4293 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4294 gfx_v7_0_enable_cp_pg(adev, false);
4295 gfx_v7_0_enable_gds_pg(adev, false);
4301 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4303 * @adev: amdgpu_device pointer
4305 * Fetches a GPU clock counter snapshot (SI).
4306 * Returns the 64 bit clock counter snapshot.
4308 static uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4312 mutex_lock(&adev->gfx.gpu_clock_mutex);
4313 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4314 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4315 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4316 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4320 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4322 uint32_t gds_base, uint32_t gds_size,
4323 uint32_t gws_base, uint32_t gws_size,
4324 uint32_t oa_base, uint32_t oa_size)
4326 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4327 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4329 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4330 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4332 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4333 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4336 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4337 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4338 WRITE_DATA_DST_SEL(0)));
4339 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4340 amdgpu_ring_write(ring, 0);
4341 amdgpu_ring_write(ring, gds_base);
4344 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4345 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4346 WRITE_DATA_DST_SEL(0)));
4347 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4348 amdgpu_ring_write(ring, 0);
4349 amdgpu_ring_write(ring, gds_size);
4352 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4353 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4354 WRITE_DATA_DST_SEL(0)));
4355 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4356 amdgpu_ring_write(ring, 0);
4357 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4360 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4361 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4362 WRITE_DATA_DST_SEL(0)));
4363 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4364 amdgpu_ring_write(ring, 0);
4365 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4368 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4370 WREG32(mmSQ_IND_INDEX,
4371 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4372 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4373 (address << SQ_IND_INDEX__INDEX__SHIFT) |
4374 (SQ_IND_INDEX__FORCE_READ_MASK));
4375 return RREG32(mmSQ_IND_DATA);
4378 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4379 uint32_t wave, uint32_t thread,
4380 uint32_t regno, uint32_t num, uint32_t *out)
4382 WREG32(mmSQ_IND_INDEX,
4383 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4384 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4385 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4386 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4387 (SQ_IND_INDEX__FORCE_READ_MASK) |
4388 (SQ_IND_INDEX__AUTO_INCR_MASK));
4390 *(out++) = RREG32(mmSQ_IND_DATA);
4393 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4395 /* type 0 wave data */
4396 dst[(*no_fields)++] = 0;
4397 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
4398 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
4399 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
4400 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
4401 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
4402 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
4403 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
4404 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
4405 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
4406 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
4407 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
4408 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
4409 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
4410 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
4411 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
4412 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
4413 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
4414 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
4417 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4418 uint32_t wave, uint32_t start,
4419 uint32_t size, uint32_t *dst)
4422 adev, simd, wave, 0,
4423 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4426 static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4427 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4428 .select_se_sh = &gfx_v7_0_select_se_sh,
4429 .read_wave_data = &gfx_v7_0_read_wave_data,
4430 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4433 static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
4434 .enter_safe_mode = gfx_v7_0_enter_rlc_safe_mode,
4435 .exit_safe_mode = gfx_v7_0_exit_rlc_safe_mode
4438 static int gfx_v7_0_early_init(void *handle)
4440 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4442 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4443 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
4444 adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
4445 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
4446 gfx_v7_0_set_ring_funcs(adev);
4447 gfx_v7_0_set_irq_funcs(adev);
4448 gfx_v7_0_set_gds_init(adev);
4453 static int gfx_v7_0_late_init(void *handle)
4455 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4458 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4462 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4469 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4472 u32 mc_shared_chmap, mc_arb_ramcfg;
4473 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4476 switch (adev->asic_type) {
4478 adev->gfx.config.max_shader_engines = 2;
4479 adev->gfx.config.max_tile_pipes = 4;
4480 adev->gfx.config.max_cu_per_sh = 7;
4481 adev->gfx.config.max_sh_per_se = 1;
4482 adev->gfx.config.max_backends_per_se = 2;
4483 adev->gfx.config.max_texture_channel_caches = 4;
4484 adev->gfx.config.max_gprs = 256;
4485 adev->gfx.config.max_gs_threads = 32;
4486 adev->gfx.config.max_hw_contexts = 8;
4488 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4489 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4490 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4491 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4492 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4495 adev->gfx.config.max_shader_engines = 4;
4496 adev->gfx.config.max_tile_pipes = 16;
4497 adev->gfx.config.max_cu_per_sh = 11;
4498 adev->gfx.config.max_sh_per_se = 1;
4499 adev->gfx.config.max_backends_per_se = 4;
4500 adev->gfx.config.max_texture_channel_caches = 16;
4501 adev->gfx.config.max_gprs = 256;
4502 adev->gfx.config.max_gs_threads = 32;
4503 adev->gfx.config.max_hw_contexts = 8;
4505 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4506 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4507 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4508 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4509 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4512 adev->gfx.config.max_shader_engines = 1;
4513 adev->gfx.config.max_tile_pipes = 4;
4514 if ((adev->pdev->device == 0x1304) ||
4515 (adev->pdev->device == 0x1305) ||
4516 (adev->pdev->device == 0x130C) ||
4517 (adev->pdev->device == 0x130F) ||
4518 (adev->pdev->device == 0x1310) ||
4519 (adev->pdev->device == 0x1311) ||
4520 (adev->pdev->device == 0x131C)) {
4521 adev->gfx.config.max_cu_per_sh = 8;
4522 adev->gfx.config.max_backends_per_se = 2;
4523 } else if ((adev->pdev->device == 0x1309) ||
4524 (adev->pdev->device == 0x130A) ||
4525 (adev->pdev->device == 0x130D) ||
4526 (adev->pdev->device == 0x1313) ||
4527 (adev->pdev->device == 0x131D)) {
4528 adev->gfx.config.max_cu_per_sh = 6;
4529 adev->gfx.config.max_backends_per_se = 2;
4530 } else if ((adev->pdev->device == 0x1306) ||
4531 (adev->pdev->device == 0x1307) ||
4532 (adev->pdev->device == 0x130B) ||
4533 (adev->pdev->device == 0x130E) ||
4534 (adev->pdev->device == 0x1315) ||
4535 (adev->pdev->device == 0x131B)) {
4536 adev->gfx.config.max_cu_per_sh = 4;
4537 adev->gfx.config.max_backends_per_se = 1;
4539 adev->gfx.config.max_cu_per_sh = 3;
4540 adev->gfx.config.max_backends_per_se = 1;
4542 adev->gfx.config.max_sh_per_se = 1;
4543 adev->gfx.config.max_texture_channel_caches = 4;
4544 adev->gfx.config.max_gprs = 256;
4545 adev->gfx.config.max_gs_threads = 16;
4546 adev->gfx.config.max_hw_contexts = 8;
4548 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4549 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4550 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4551 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4552 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4557 adev->gfx.config.max_shader_engines = 1;
4558 adev->gfx.config.max_tile_pipes = 2;
4559 adev->gfx.config.max_cu_per_sh = 2;
4560 adev->gfx.config.max_sh_per_se = 1;
4561 adev->gfx.config.max_backends_per_se = 1;
4562 adev->gfx.config.max_texture_channel_caches = 2;
4563 adev->gfx.config.max_gprs = 256;
4564 adev->gfx.config.max_gs_threads = 16;
4565 adev->gfx.config.max_hw_contexts = 8;
4567 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4568 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4569 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4570 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4571 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4575 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4576 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4577 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4579 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4580 adev->gfx.config.mem_max_burst_length_bytes = 256;
4581 if (adev->flags & AMD_IS_APU) {
4582 /* Get memory bank mapping mode. */
4583 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4584 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4585 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4587 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4588 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4589 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4591 /* Validate settings in case only one DIMM installed. */
4592 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4593 dimm00_addr_map = 0;
4594 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4595 dimm01_addr_map = 0;
4596 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4597 dimm10_addr_map = 0;
4598 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4599 dimm11_addr_map = 0;
4601 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4602 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4603 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4604 adev->gfx.config.mem_row_size_in_kb = 2;
4606 adev->gfx.config.mem_row_size_in_kb = 1;
4608 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4609 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4610 if (adev->gfx.config.mem_row_size_in_kb > 4)
4611 adev->gfx.config.mem_row_size_in_kb = 4;
4613 /* XXX use MC settings? */
4614 adev->gfx.config.shader_engine_tile_size = 32;
4615 adev->gfx.config.num_gpus = 1;
4616 adev->gfx.config.multi_gpu_tile_size = 64;
4618 /* fix up row size */
4619 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4620 switch (adev->gfx.config.mem_row_size_in_kb) {
4623 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4626 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4629 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4632 adev->gfx.config.gb_addr_config = gb_addr_config;
4635 static int gfx_v7_0_sw_init(void *handle)
4637 struct amdgpu_ring *ring;
4638 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4642 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4646 /* Privileged reg */
4647 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4651 /* Privileged inst */
4652 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4656 gfx_v7_0_scratch_init(adev);
4658 r = gfx_v7_0_init_microcode(adev);
4660 DRM_ERROR("Failed to load gfx firmware!\n");
4664 r = gfx_v7_0_rlc_init(adev);
4666 DRM_ERROR("Failed to init rlc BOs!\n");
4670 /* allocate mec buffers */
4671 r = gfx_v7_0_mec_init(adev);
4673 DRM_ERROR("Failed to init MEC BOs!\n");
4677 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4678 ring = &adev->gfx.gfx_ring[i];
4679 ring->ring_obj = NULL;
4680 sprintf(ring->name, "gfx");
4681 r = amdgpu_ring_init(adev, ring, 1024,
4682 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
4687 /* set up the compute queues */
4688 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4691 /* max 32 queues per MEC */
4692 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4693 DRM_ERROR("Too many (%d) compute rings!\n", i);
4696 ring = &adev->gfx.compute_ring[i];
4697 ring->ring_obj = NULL;
4698 ring->use_doorbell = true;
4699 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4700 ring->me = 1; /* first MEC */
4702 ring->queue = i % 8;
4703 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4704 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4705 /* type-2 packets are deprecated on MEC, use type-3 instead */
4706 r = amdgpu_ring_init(adev, ring, 1024,
4707 &adev->gfx.eop_irq, irq_type);
4712 /* reserve GDS, GWS and OA resource for gfx */
4713 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
4714 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
4715 &adev->gds.gds_gfx_bo, NULL, NULL);
4719 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
4720 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
4721 &adev->gds.gws_gfx_bo, NULL, NULL);
4725 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
4726 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
4727 &adev->gds.oa_gfx_bo, NULL, NULL);
4731 adev->gfx.ce_ram_size = 0x8000;
4733 gfx_v7_0_gpu_early_init(adev);
4738 static int gfx_v7_0_sw_fini(void *handle)
4741 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4743 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
4744 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
4745 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
4747 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4748 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4749 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4750 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4752 gfx_v7_0_cp_compute_fini(adev);
4753 gfx_v7_0_rlc_fini(adev);
4754 gfx_v7_0_mec_fini(adev);
4755 gfx_v7_0_free_microcode(adev);
4760 static int gfx_v7_0_hw_init(void *handle)
4763 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4765 gfx_v7_0_gpu_init(adev);
4768 r = gfx_v7_0_rlc_resume(adev);
4772 r = gfx_v7_0_cp_resume(adev);
4779 static int gfx_v7_0_hw_fini(void *handle)
4781 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4783 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4784 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4785 gfx_v7_0_cp_enable(adev, false);
4786 gfx_v7_0_rlc_stop(adev);
4787 gfx_v7_0_fini_pg(adev);
4792 static int gfx_v7_0_suspend(void *handle)
4794 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4796 return gfx_v7_0_hw_fini(adev);
4799 static int gfx_v7_0_resume(void *handle)
4801 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4803 return gfx_v7_0_hw_init(adev);
4806 static bool gfx_v7_0_is_idle(void *handle)
4808 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4810 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4816 static int gfx_v7_0_wait_for_idle(void *handle)
4820 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4822 for (i = 0; i < adev->usec_timeout; i++) {
4823 /* read MC_STATUS */
4824 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4833 static int gfx_v7_0_soft_reset(void *handle)
4835 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4837 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4840 tmp = RREG32(mmGRBM_STATUS);
4841 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4842 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4843 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4844 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4845 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4846 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4847 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4848 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4850 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4851 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4852 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4856 tmp = RREG32(mmGRBM_STATUS2);
4857 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4858 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4861 tmp = RREG32(mmSRBM_STATUS);
4862 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4863 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4865 if (grbm_soft_reset || srbm_soft_reset) {
4867 gfx_v7_0_fini_pg(adev);
4868 gfx_v7_0_update_cg(adev, false);
4871 gfx_v7_0_rlc_stop(adev);
4873 /* Disable GFX parsing/prefetching */
4874 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4876 /* Disable MEC parsing/prefetching */
4877 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4879 if (grbm_soft_reset) {
4880 tmp = RREG32(mmGRBM_SOFT_RESET);
4881 tmp |= grbm_soft_reset;
4882 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4883 WREG32(mmGRBM_SOFT_RESET, tmp);
4884 tmp = RREG32(mmGRBM_SOFT_RESET);
4888 tmp &= ~grbm_soft_reset;
4889 WREG32(mmGRBM_SOFT_RESET, tmp);
4890 tmp = RREG32(mmGRBM_SOFT_RESET);
4893 if (srbm_soft_reset) {
4894 tmp = RREG32(mmSRBM_SOFT_RESET);
4895 tmp |= srbm_soft_reset;
4896 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4897 WREG32(mmSRBM_SOFT_RESET, tmp);
4898 tmp = RREG32(mmSRBM_SOFT_RESET);
4902 tmp &= ~srbm_soft_reset;
4903 WREG32(mmSRBM_SOFT_RESET, tmp);
4904 tmp = RREG32(mmSRBM_SOFT_RESET);
4906 /* Wait a little for things to settle down */
4912 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4913 enum amdgpu_interrupt_state state)
4918 case AMDGPU_IRQ_STATE_DISABLE:
4919 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4920 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4921 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4923 case AMDGPU_IRQ_STATE_ENABLE:
4924 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4925 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4926 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4933 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4935 enum amdgpu_interrupt_state state)
4937 u32 mec_int_cntl, mec_int_cntl_reg;
4940 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4941 * handles the setting of interrupts for this specific pipe. All other
4942 * pipes' interrupts are set by amdkfd.
4948 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4951 DRM_DEBUG("invalid pipe %d\n", pipe);
4955 DRM_DEBUG("invalid me %d\n", me);
4960 case AMDGPU_IRQ_STATE_DISABLE:
4961 mec_int_cntl = RREG32(mec_int_cntl_reg);
4962 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4963 WREG32(mec_int_cntl_reg, mec_int_cntl);
4965 case AMDGPU_IRQ_STATE_ENABLE:
4966 mec_int_cntl = RREG32(mec_int_cntl_reg);
4967 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4968 WREG32(mec_int_cntl_reg, mec_int_cntl);
4975 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4976 struct amdgpu_irq_src *src,
4978 enum amdgpu_interrupt_state state)
4983 case AMDGPU_IRQ_STATE_DISABLE:
4984 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4985 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4986 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4988 case AMDGPU_IRQ_STATE_ENABLE:
4989 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4990 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4991 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5000 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5001 struct amdgpu_irq_src *src,
5003 enum amdgpu_interrupt_state state)
5008 case AMDGPU_IRQ_STATE_DISABLE:
5009 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5010 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5011 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5013 case AMDGPU_IRQ_STATE_ENABLE:
5014 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5015 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5016 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5025 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5026 struct amdgpu_irq_src *src,
5028 enum amdgpu_interrupt_state state)
5031 case AMDGPU_CP_IRQ_GFX_EOP:
5032 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
5034 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5035 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5037 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5038 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5040 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5041 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5043 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5044 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5046 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5047 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5049 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5050 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5052 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5053 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5055 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5056 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5064 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
5065 struct amdgpu_irq_src *source,
5066 struct amdgpu_iv_entry *entry)
5069 struct amdgpu_ring *ring;
5072 DRM_DEBUG("IH: CP EOP\n");
5073 me_id = (entry->ring_id & 0x0c) >> 2;
5074 pipe_id = (entry->ring_id & 0x03) >> 0;
5077 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5081 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5082 ring = &adev->gfx.compute_ring[i];
5083 if ((ring->me == me_id) && (ring->pipe == pipe_id))
5084 amdgpu_fence_process(ring);
5091 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
5092 struct amdgpu_irq_src *source,
5093 struct amdgpu_iv_entry *entry)
5095 DRM_ERROR("Illegal register access in command stream\n");
5096 schedule_work(&adev->reset_work);
5100 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5101 struct amdgpu_irq_src *source,
5102 struct amdgpu_iv_entry *entry)
5104 DRM_ERROR("Illegal instruction in command stream\n");
5105 // XXX soft reset the gfx block only
5106 schedule_work(&adev->reset_work);
5110 static int gfx_v7_0_set_clockgating_state(void *handle,
5111 enum amd_clockgating_state state)
5114 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5116 if (state == AMD_CG_STATE_GATE)
5119 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
5120 /* order matters! */
5122 gfx_v7_0_enable_mgcg(adev, true);
5123 gfx_v7_0_enable_cgcg(adev, true);
5125 gfx_v7_0_enable_cgcg(adev, false);
5126 gfx_v7_0_enable_mgcg(adev, false);
5128 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5133 static int gfx_v7_0_set_powergating_state(void *handle,
5134 enum amd_powergating_state state)
5137 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5139 if (state == AMD_PG_STATE_GATE)
5142 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
5143 AMD_PG_SUPPORT_GFX_SMG |
5144 AMD_PG_SUPPORT_GFX_DMG |
5146 AMD_PG_SUPPORT_GDS |
5147 AMD_PG_SUPPORT_RLC_SMU_HS)) {
5148 gfx_v7_0_update_gfx_pg(adev, gate);
5149 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
5150 gfx_v7_0_enable_cp_pg(adev, gate);
5151 gfx_v7_0_enable_gds_pg(adev, gate);
5158 static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5160 .early_init = gfx_v7_0_early_init,
5161 .late_init = gfx_v7_0_late_init,
5162 .sw_init = gfx_v7_0_sw_init,
5163 .sw_fini = gfx_v7_0_sw_fini,
5164 .hw_init = gfx_v7_0_hw_init,
5165 .hw_fini = gfx_v7_0_hw_fini,
5166 .suspend = gfx_v7_0_suspend,
5167 .resume = gfx_v7_0_resume,
5168 .is_idle = gfx_v7_0_is_idle,
5169 .wait_for_idle = gfx_v7_0_wait_for_idle,
5170 .soft_reset = gfx_v7_0_soft_reset,
5171 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5172 .set_powergating_state = gfx_v7_0_set_powergating_state,
5175 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5176 .type = AMDGPU_RING_TYPE_GFX,
5178 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5179 .get_rptr = gfx_v7_0_ring_get_rptr,
5180 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5181 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5183 20 + /* gfx_v7_0_ring_emit_gds_switch */
5184 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5185 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5186 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
5187 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
5188 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
5189 3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
5190 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
5191 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
5192 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
5193 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5194 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5195 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5196 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5197 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
5198 .test_ring = gfx_v7_0_ring_test_ring,
5199 .test_ib = gfx_v7_0_ring_test_ib,
5200 .insert_nop = amdgpu_ring_insert_nop,
5201 .pad_ib = amdgpu_ring_generic_pad_ib,
5202 .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
5205 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5206 .type = AMDGPU_RING_TYPE_COMPUTE,
5208 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5209 .get_rptr = gfx_v7_0_ring_get_rptr,
5210 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5211 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5213 20 + /* gfx_v7_0_ring_emit_gds_switch */
5214 7 + /* gfx_v7_0_ring_emit_hdp_flush */
5215 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
5216 7 + /* gfx_v7_0_ring_emit_pipeline_sync */
5217 17 + /* gfx_v7_0_ring_emit_vm_flush */
5218 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
5219 .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
5220 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
5221 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
5222 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
5223 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5224 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5225 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5226 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
5227 .test_ring = gfx_v7_0_ring_test_ring,
5228 .test_ib = gfx_v7_0_ring_test_ib,
5229 .insert_nop = amdgpu_ring_insert_nop,
5230 .pad_ib = amdgpu_ring_generic_pad_ib,
5233 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5237 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5238 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5239 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5240 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5243 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5244 .set = gfx_v7_0_set_eop_interrupt_state,
5245 .process = gfx_v7_0_eop_irq,
5248 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5249 .set = gfx_v7_0_set_priv_reg_fault_state,
5250 .process = gfx_v7_0_priv_reg_irq,
5253 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5254 .set = gfx_v7_0_set_priv_inst_fault_state,
5255 .process = gfx_v7_0_priv_inst_irq,
5258 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5260 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5261 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5263 adev->gfx.priv_reg_irq.num_types = 1;
5264 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5266 adev->gfx.priv_inst_irq.num_types = 1;
5267 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5270 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5272 /* init asci gds info */
5273 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5274 adev->gds.gws.total_size = 64;
5275 adev->gds.oa.total_size = 16;
5277 if (adev->gds.mem.total_size == 64 * 1024) {
5278 adev->gds.mem.gfx_partition_size = 4096;
5279 adev->gds.mem.cs_partition_size = 4096;
5281 adev->gds.gws.gfx_partition_size = 4;
5282 adev->gds.gws.cs_partition_size = 4;
5284 adev->gds.oa.gfx_partition_size = 4;
5285 adev->gds.oa.cs_partition_size = 1;
5287 adev->gds.mem.gfx_partition_size = 1024;
5288 adev->gds.mem.cs_partition_size = 1024;
5290 adev->gds.gws.gfx_partition_size = 16;
5291 adev->gds.gws.cs_partition_size = 16;
5293 adev->gds.oa.gfx_partition_size = 4;
5294 adev->gds.oa.cs_partition_size = 4;
5299 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5301 int i, j, k, counter, active_cu_number = 0;
5302 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5303 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5304 unsigned disable_masks[4 * 2];
5306 memset(cu_info, 0, sizeof(*cu_info));
5308 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5310 mutex_lock(&adev->grbm_idx_mutex);
5311 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5312 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5316 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
5318 gfx_v7_0_set_user_cu_inactive_bitmap(
5319 adev, disable_masks[i * 2 + j]);
5320 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5321 cu_info->bitmap[i][j] = bitmap;
5323 for (k = 0; k < 16; k ++) {
5324 if (bitmap & mask) {
5331 active_cu_number += counter;
5332 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5335 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5336 mutex_unlock(&adev->grbm_idx_mutex);
5338 cu_info->number = active_cu_number;
5339 cu_info->ao_cu_mask = ao_cu_mask;
5342 const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
5344 .type = AMD_IP_BLOCK_TYPE_GFX,
5348 .funcs = &gfx_v7_0_ip_funcs,
5351 const struct amdgpu_ip_block_version gfx_v7_1_ip_block =
5353 .type = AMD_IP_BLOCK_TYPE_GFX,
5357 .funcs = &gfx_v7_0_ip_funcs,
5360 const struct amdgpu_ip_block_version gfx_v7_2_ip_block =
5362 .type = AMD_IP_BLOCK_TYPE_GFX,
5366 .funcs = &gfx_v7_0_ip_funcs,
5369 const struct amdgpu_ip_block_version gfx_v7_3_ip_block =
5371 .type = AMD_IP_BLOCK_TYPE_GFX,
5375 .funcs = &gfx_v7_0_ip_funcs,
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