[linux.git] / arch / powerpc / kernel / rtas_pci.c

/*
 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
 * Copyright (C) 2003 Anton Blanchard <[email protected]>, IBM
 *
 * RTAS specific routines for PCI.
 *
 * Based on code from pci.c, chrp_pci.c and pSeries_pci.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/kernel.h>
#include <linux/threads.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>

#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/iommu.h>
#include <asm/rtas.h>
#include <asm/mpic.h>
#include <asm/ppc-pci.h>
#include <asm/eeh.h>

/* RTAS tokens */
static int read_pci_config;
static int write_pci_config;
static int ibm_read_pci_config;
static int ibm_write_pci_config;

static inline int config_access_valid(struct pci_dn *dn, int where)
{
	if (where < 256)
		return 1;
	if (where < 4096 && dn->pci_ext_config_space)
		return 1;

	return 0;
}

int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
{
	int returnval = -1;
	unsigned long buid, addr;
	int ret;

	if (!pdn)
		return PCIBIOS_DEVICE_NOT_FOUND;
	if (!config_access_valid(pdn, where))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
	buid = pdn->phb->buid;
	if (buid) {
		ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
				addr, BUID_HI(buid), BUID_LO(buid), size);
	} else {
		ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
	}
	*val = returnval;

	if (ret)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (returnval == EEH_IO_ERROR_VALUE(size) &&
	    eeh_dn_check_failure (pdn->node, NULL))
		return PCIBIOS_DEVICE_NOT_FOUND;

	return PCIBIOS_SUCCESSFUL;
}

static int rtas_pci_read_config(struct pci_bus *bus,
				unsigned int devfn,
				int where, int size, u32 *val)
{
	struct device_node *busdn, *dn;

	busdn = pci_bus_to_OF_node(bus);

	/* Search only direct children of the bus */
	for (dn = busdn->child; dn; dn = dn->sibling) {
		struct pci_dn *pdn = PCI_DN(dn);
		if (pdn && pdn->devfn == devfn
		    && of_device_is_available(dn))
			return rtas_read_config(pdn, where, size, val);
	}

	return PCIBIOS_DEVICE_NOT_FOUND;
}

int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
{
	unsigned long buid, addr;
	int ret;

	if (!pdn)
		return PCIBIOS_DEVICE_NOT_FOUND;
	if (!config_access_valid(pdn, where))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
	buid = pdn->phb->buid;
	if (buid) {
		ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
			BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
	} else {
		ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
	}

	if (ret)
		return PCIBIOS_DEVICE_NOT_FOUND;

	return PCIBIOS_SUCCESSFUL;
}

static int rtas_pci_write_config(struct pci_bus *bus,
				 unsigned int devfn,
				 int where, int size, u32 val)
{
	struct device_node *busdn, *dn;

	busdn = pci_bus_to_OF_node(bus);

	/* Search only direct children of the bus */
	for (dn = busdn->child; dn; dn = dn->sibling) {
		struct pci_dn *pdn = PCI_DN(dn);
		if (pdn && pdn->devfn == devfn
		    && of_device_is_available(dn))
			return rtas_write_config(pdn, where, size, val);
	}
	return PCIBIOS_DEVICE_NOT_FOUND;
}

static struct pci_ops rtas_pci_ops = {
	.read = rtas_pci_read_config,
	.write = rtas_pci_write_config,
};

static int is_python(struct device_node *dev)
{
	const char *model = of_get_property(dev, "model", NULL);

	if (model && strstr(model, "Python"))
		return 1;

	return 0;
}

static void python_countermeasures(struct device_node *dev)
{
	struct resource registers;
	void __iomem *chip_regs;
	volatile u32 val;

	if (of_address_to_resource(dev, 0, &registers)) {
		printk(KERN_ERR "Can't get address for Python workarounds !\n");
		return;
	}

	/* Python's register file is 1 MB in size. */
	chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000);

	/*
	 * Firmware doesn't always clear this bit which is critical
	 * for good performance - Anton
	 */

#define PRG_CL_RESET_VALID 0x00010000

	val = in_be32(chip_regs + 0xf6030);
	if (val & PRG_CL_RESET_VALID) {
		printk(KERN_INFO "Python workaround: ");
		val &= ~PRG_CL_RESET_VALID;
		out_be32(chip_regs + 0xf6030, val);
		/*
		 * We must read it back for changes to
		 * take effect
		 */
		val = in_be32(chip_regs + 0xf6030);
		printk("reg0: %x\n", val);
	}

	iounmap(chip_regs);
}

void __init init_pci_config_tokens (void)
{
	read_pci_config = rtas_token("read-pci-config");
	write_pci_config = rtas_token("write-pci-config");
	ibm_read_pci_config = rtas_token("ibm,read-pci-config");
	ibm_write_pci_config = rtas_token("ibm,write-pci-config");
}

unsigned long __devinit get_phb_buid (struct device_node *phb)
{
	struct resource r;

	if (ibm_read_pci_config == -1)
		return 0;
	if (of_address_to_resource(phb, 0, &r))
		return 0;
	return r.start;
}

static int phb_set_bus_ranges(struct device_node *dev,
			      struct pci_controller *phb)
{
	const int *bus_range;
	unsigned int len;

	bus_range = of_get_property(dev, "bus-range", &len);
	if (bus_range == NULL || len < 2 * sizeof(int)) {
		return 1;
 	}

	phb->first_busno =  bus_range[0];
	phb->last_busno  =  bus_range[1];

	return 0;
}

int __devinit rtas_setup_phb(struct pci_controller *phb)
{
	struct device_node *dev = phb->dn;

	if (is_python(dev))
		python_countermeasures(dev);

	if (phb_set_bus_ranges(dev, phb))
		return 1;

	phb->ops = &rtas_pci_ops;
	phb->buid = get_phb_buid(dev);

	return 0;
}

void __init find_and_init_phbs(void)
{
	struct device_node *node;
	struct pci_controller *phb;
	struct device_node *root = of_find_node_by_path("/");

	for_each_child_of_node(root, node) {
		if (node->type == NULL || (strcmp(node->type, "pci") != 0 &&
					   strcmp(node->type, "pciex") != 0))
			continue;

		phb = pcibios_alloc_controller(node);
		if (!phb)
			continue;
		rtas_setup_phb(phb);
		pci_process_bridge_OF_ranges(phb, node, 0);
		isa_bridge_find_early(phb);
	}

	of_node_put(root);
	pci_devs_phb_init();

	/* Create EEH devices for all PHBs */
	eeh_dev_phb_init();

	/*
	 * PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
	 * in chosen.
	 */
	if (of_chosen) {
		const int *prop;

		prop = of_get_property(of_chosen,
				"linux,pci-probe-only", NULL);
		if (prop) {
			if (*prop)
				pci_add_flags(PCI_PROBE_ONLY);
			else
				pci_clear_flags(PCI_PROBE_ONLY);
		}

#ifdef CONFIG_PPC32 /* Will be made generic soon */
		prop = of_get_property(of_chosen,
				"linux,pci-assign-all-buses", NULL);
		if (prop && *prop)
			pci_add_flags(PCI_REASSIGN_ALL_BUS);
#endif /* CONFIG_PPC32 */
	}
}
Commit	Line	Data
c5a3c2e5	1	/*
c5a3c2e5 AB	2	* Copyright (C) 2001 Dave Engebretsen, IBM Corporation
	3	* Copyright (C) 2003 Anton Blanchard <[email protected]>, IBM
	4	*
	5	* RTAS specific routines for PCI.
ae65a391	6	*
c5a3c2e5 AB	7	* Based on code from pci.c, chrp_pci.c and pSeries_pci.c
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
ae65a391	13	*
c5a3c2e5 AB	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
ae65a391	18	*
c5a3c2e5 AB	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*/
	23
	24	#include <linux/kernel.h>
	25	#include <linux/threads.h>
	26	#include <linux/pci.h>
	27	#include <linux/string.h>
	28	#include <linux/init.h>
	29	#include <linux/bootmem.h>
	30
	31	#include <asm/io.h>
	32	#include <asm/pgtable.h>
	33	#include <asm/irq.h>
	34	#include <asm/prom.h>
	35	#include <asm/machdep.h>
	36	#include <asm/pci-bridge.h>
	37	#include <asm/iommu.h>
	38	#include <asm/rtas.h>
bbeb3f4c	39	#include <asm/mpic.h>
d387899f	40	#include <asm/ppc-pci.h>
68a64357	41	#include <asm/eeh.h>
c5a3c2e5 AB	42
	43	/* RTAS tokens */
	44	static int read_pci_config;
	45	static int write_pci_config;
	46	static int ibm_read_pci_config;
	47	static int ibm_write_pci_config;
	48
ae65a391	49	static inline int config_access_valid(struct pci_dn *dn, int where)
c5a3c2e5 AB	50	{
	51	if (where < 256)
	52	return 1;
	53	if (where < 4096 && dn->pci_ext_config_space)
	54	return 1;
	55
	56	return 0;
	57	}
	58
7684b40c	59	int rtas_read_config(struct pci_dn pdn, int where, int size, u32 val)
c5a3c2e5 AB	60	{
	61	int returnval = -1;
	62	unsigned long buid, addr;
	63	int ret;
	64
ae65a391	65	if (!pdn)
c5a3c2e5	66	return PCIBIOS_DEVICE_NOT_FOUND;
1635317f	67	if (!config_access_valid(pdn, where))
c5a3c2e5 AB	68	return PCIBIOS_BAD_REGISTER_NUMBER;
c5a3c2e5 AB	69
6f3d5d3c	70	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
1635317f	71	buid = pdn->phb->buid;
c5a3c2e5 AB	72	if (buid) {
c5a3c2e5 AB	73	ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
ae65a391	74	addr, BUID_HI(buid), BUID_LO(buid), size);
c5a3c2e5 AB	75	} else {
	76	ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
	77	}
	78	*val = returnval;
	79
	80	if (ret)
	81	return PCIBIOS_DEVICE_NOT_FOUND;
	82
1635317f	83	if (returnval == EEH_IO_ERROR_VALUE(size) &&
ae65a391	84	eeh_dn_check_failure (pdn->node, NULL))
c5a3c2e5 AB	85	return PCIBIOS_DEVICE_NOT_FOUND;
	86
	87	return PCIBIOS_SUCCESSFUL;
	88	}
	89
	90	static int rtas_pci_read_config(struct pci_bus *bus,
	91	unsigned int devfn,
	92	int where, int size, u32 *val)
	93	{
	94	struct device_node busdn, dn;
	95
2f522976	96	busdn = pci_bus_to_OF_node(bus);
c5a3c2e5 AB	97
c5a3c2e5 AB	98	/* Search only direct children of the bus */
ae65a391 LV	99	for (dn = busdn->child; dn; dn = dn->sibling) {
	100	struct pci_dn *pdn = PCI_DN(dn);
	101	if (pdn && pdn->devfn == devfn
c6d4d5a8	102	&& of_device_is_available(dn))
ae65a391 LV	103	return rtas_read_config(pdn, where, size, val);
ae65a391 LV	104	}
1635317f	105
c5a3c2e5 AB	106	return PCIBIOS_DEVICE_NOT_FOUND;
	107	}
	108
ae65a391	109	int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
c5a3c2e5 AB	110	{
	111	unsigned long buid, addr;
	112	int ret;
	113
ae65a391	114	if (!pdn)
c5a3c2e5	115	return PCIBIOS_DEVICE_NOT_FOUND;
1635317f	116	if (!config_access_valid(pdn, where))
c5a3c2e5 AB	117	return PCIBIOS_BAD_REGISTER_NUMBER;
c5a3c2e5 AB	118
6f3d5d3c	119	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
1635317f	120	buid = pdn->phb->buid;
c5a3c2e5	121	if (buid) {
ae65a391 LV	122	ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
ae65a391 LV	123	BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
c5a3c2e5 AB	124	} else {
	125	ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
	126	}
	127
	128	if (ret)
	129	return PCIBIOS_DEVICE_NOT_FOUND;
	130
	131	return PCIBIOS_SUCCESSFUL;
	132	}
	133
	134	static int rtas_pci_write_config(struct pci_bus *bus,
	135	unsigned int devfn,
	136	int where, int size, u32 val)
	137	{
	138	struct device_node busdn, dn;
	139
2f522976	140	busdn = pci_bus_to_OF_node(bus);
c5a3c2e5 AB	141
c5a3c2e5 AB	142	/* Search only direct children of the bus */
ae65a391 LV	143	for (dn = busdn->child; dn; dn = dn->sibling) {
	144	struct pci_dn *pdn = PCI_DN(dn);
	145	if (pdn && pdn->devfn == devfn
c6d4d5a8	146	&& of_device_is_available(dn))
ae65a391 LV	147	return rtas_write_config(pdn, where, size, val);
ae65a391 LV	148	}
c5a3c2e5 AB	149	return PCIBIOS_DEVICE_NOT_FOUND;
	150	}
	151
1c21a293	152	static struct pci_ops rtas_pci_ops = {
8674e0c9 NL	153	.read = rtas_pci_read_config,
8674e0c9 NL	154	.write = rtas_pci_write_config,
c5a3c2e5 AB	155	};
c5a3c2e5 AB	156
1c21a293	157	static int is_python(struct device_node *dev)
c5a3c2e5	158	{
e2eb6392	159	const char *model = of_get_property(dev, "model", NULL);
c5a3c2e5 AB	160
	161	if (model && strstr(model, "Python"))
	162	return 1;
	163
	164	return 0;
	165	}
	166
cc5d0189	167	static void python_countermeasures(struct device_node *dev)
c5a3c2e5	168	{
cc5d0189	169	struct resource registers;
c5a3c2e5 AB	170	void __iomem *chip_regs;
	171	volatile u32 val;
	172
cc5d0189 BH	173	if (of_address_to_resource(dev, 0, &registers)) {
cc5d0189 BH	174	printk(KERN_ERR "Can't get address for Python workarounds !\n");
c5a3c2e5	175	return;
cc5d0189	176	}
c5a3c2e5 AB	177
c5a3c2e5 AB	178	/* Python's register file is 1 MB in size. */
cc5d0189	179	chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000);
c5a3c2e5	180
ae65a391	181	/*
c5a3c2e5 AB	182	* Firmware doesn't always clear this bit which is critical
	183	* for good performance - Anton
	184	*/
	185
	186	#define PRG_CL_RESET_VALID 0x00010000
	187
	188	val = in_be32(chip_regs + 0xf6030);
	189	if (val & PRG_CL_RESET_VALID) {
	190	printk(KERN_INFO "Python workaround: ");
	191	val &= ~PRG_CL_RESET_VALID;
	192	out_be32(chip_regs + 0xf6030, val);
	193	/*
	194	* We must read it back for changes to
	195	* take effect
	196	*/
	197	val = in_be32(chip_regs + 0xf6030);
	198	printk("reg0: %x\n", val);
	199	}
	200
	201	iounmap(chip_regs);
	202	}
	203
	204	void __init init_pci_config_tokens (void)
	205	{
	206	read_pci_config = rtas_token("read-pci-config");
	207	write_pci_config = rtas_token("write-pci-config");
	208	ibm_read_pci_config = rtas_token("ibm,read-pci-config");
	209	ibm_write_pci_config = rtas_token("ibm,write-pci-config");
	210	}
	211
	212	unsigned long __devinit get_phb_buid (struct device_node *phb)
	213	{
6506e710	214	struct resource r;
c5a3c2e5	215
6506e710	216	if (ibm_read_pci_config == -1)
c5a3c2e5	217	return 0;
6506e710	218	if (of_address_to_resource(phb, 0, &r))
c5a3c2e5	219	return 0;
6506e710	220	return r.start;
c5a3c2e5 AB	221	}
	222
	223	static int phb_set_bus_ranges(struct device_node *dev,
	224	struct pci_controller *phb)
	225	{
a7f67bdf	226	const int *bus_range;
c5a3c2e5 AB	227	unsigned int len;
c5a3c2e5 AB	228
e2eb6392	229	bus_range = of_get_property(dev, "bus-range", &len);
c5a3c2e5 AB	230	if (bus_range == NULL \|\| len < 2 * sizeof(int)) {
	231	return 1;
	232	}
ae65a391	233
c5a3c2e5 AB	234	phb->first_busno = bus_range[0];
	235	phb->last_busno = bus_range[1];
	236
	237	return 0;
	238	}
	239
4c9d2800	240	int __devinit rtas_setup_phb(struct pci_controller *phb)
c5a3c2e5	241	{
44ef3390	242	struct device_node *dev = phb->dn;
4c9d2800	243
c5a3c2e5	244	if (is_python(dev))
cc5d0189	245	python_countermeasures(dev);
c5a3c2e5 AB	246
	247	if (phb_set_bus_ranges(dev, phb))
	248	return 1;
	249
c5a3c2e5 AB	250	phb->ops = &rtas_pci_ops;
	251	phb->buid = get_phb_buid(dev);
	252
	253	return 0;
	254	}
	255
36241ce6	256	void __init find_and_init_phbs(void)
c5a3c2e5 AB	257	{
	258	struct device_node *node;
	259	struct pci_controller *phb;
c5a3c2e5 AB	260	struct device_node *root = of_find_node_by_path("/");
c5a3c2e5 AB	261
85e99b9f	262	for_each_child_of_node(root, node) {
bb53bb3d JM	263	if (node->type == NULL \|\| (strcmp(node->type, "pci") != 0 &&
bb53bb3d JM	264	strcmp(node->type, "pciex") != 0))
c5a3c2e5 AB	265	continue;
c5a3c2e5 AB	266
b5166cc2	267	phb = pcibios_alloc_controller(node);
c5a3c2e5 AB	268	if (!phb)
c5a3c2e5 AB	269	continue;
4c9d2800	270	rtas_setup_phb(phb);
f7abbc19	271	pci_process_bridge_OF_ranges(phb, node, 0);
3d5134ee	272	isa_bridge_find_early(phb);
c5a3c2e5 AB	273	}
	274
	275	of_node_put(root);
	276	pci_devs_phb_init();
	277
eb740b5f GS	278	/* Create EEH devices for all PHBs */
	279	eeh_dev_phb_init();
	280
c5a3c2e5	281	/*
673c9756	282	* PCI_PROBE_ONLY and PCI_REASSIGN_ALL_BUS can be set via properties
c5a3c2e5 AB	283	* in chosen.
	284	*/
	285	if (of_chosen) {
a7f67bdf	286	const int *prop;
c5a3c2e5	287
e2eb6392	288	prop = of_get_property(of_chosen,
a7f67bdf	289	"linux,pci-probe-only", NULL);
673c9756 BH	290	if (prop) {
	291	if (*prop)
	292	pci_add_flags(PCI_PROBE_ONLY);
	293	else
	294	pci_clear_flags(PCI_PROBE_ONLY);
	295	}
c5a3c2e5	296
fc3fb71c	297	#ifdef CONFIG_PPC32 /* Will be made generic soon */
e2eb6392	298	prop = of_get_property(of_chosen,
a7f67bdf	299	"linux,pci-assign-all-buses", NULL);
fc3fb71c	300	if (prop && *prop)
0e47ff1c	301	pci_add_flags(PCI_REASSIGN_ALL_BUS);
fc3fb71c	302	#endif /* CONFIG_PPC32 */
c5a3c2e5	303	}
c5a3c2e5	304	}