[linux.git] / arch / powerpc / kernel / rtas_pci.c

/*
 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
 * Copyright (C) 2003 Anton Blanchard <[email protected]>, IBM
 *
 * RTAS specific routines for PCI.
 *
 * Based on code from pci.c, chrp_pci.c and pSeries_pci.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/kernel.h>
#include <linux/threads.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>

#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/iommu.h>
#include <asm/rtas.h>
#include <asm/mpic.h>
#include <asm/ppc-pci.h>
#include <asm/eeh.h>

/* RTAS tokens */
static int read_pci_config;
static int write_pci_config;
static int ibm_read_pci_config;
static int ibm_write_pci_config;

static inline int config_access_valid(struct pci_dn *dn, int where)
{
	if (where < 256)
		return 1;
	if (where < 4096 && dn->pci_ext_config_space)
		return 1;

	return 0;
}

int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
{
	int returnval = -1;
	unsigned long buid, addr;
	int ret;

	if (!pdn)
		return PCIBIOS_DEVICE_NOT_FOUND;
	if (!config_access_valid(pdn, where))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
	buid = pdn->phb->buid;
	if (buid) {
		ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
				addr, BUID_HI(buid), BUID_LO(buid), size);
	} else {
		ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
	}
	*val = returnval;

	if (ret)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (returnval == EEH_IO_ERROR_VALUE(size) &&
	    eeh_dn_check_failure (pdn->node, NULL))
		return PCIBIOS_DEVICE_NOT_FOUND;

	return PCIBIOS_SUCCESSFUL;
}

static int rtas_pci_read_config(struct pci_bus *bus,
				unsigned int devfn,
				int where, int size, u32 *val)
{
	struct device_node *busdn, *dn;

	if (bus->self)
		busdn = pci_device_to_OF_node(bus->self);
	else
		busdn = bus->sysdata;	/* must be a phb */

	/* Search only direct children of the bus */
	for (dn = busdn->child; dn; dn = dn->sibling) {
		struct pci_dn *pdn = PCI_DN(dn);
		if (pdn && pdn->devfn == devfn
		    && of_device_is_available(dn))
			return rtas_read_config(pdn, where, size, val);
	}

	return PCIBIOS_DEVICE_NOT_FOUND;
}

int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
{
	unsigned long buid, addr;
	int ret;

	if (!pdn)
		return PCIBIOS_DEVICE_NOT_FOUND;
	if (!config_access_valid(pdn, where))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
	buid = pdn->phb->buid;
	if (buid) {
		ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
			BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
	} else {
		ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
	}

	if (ret)
		return PCIBIOS_DEVICE_NOT_FOUND;

	return PCIBIOS_SUCCESSFUL;
}

static int rtas_pci_write_config(struct pci_bus *bus,
				 unsigned int devfn,
				 int where, int size, u32 val)
{
	struct device_node *busdn, *dn;

	if (bus->self)
		busdn = pci_device_to_OF_node(bus->self);
	else
		busdn = bus->sysdata;	/* must be a phb */

	/* Search only direct children of the bus */
	for (dn = busdn->child; dn; dn = dn->sibling) {
		struct pci_dn *pdn = PCI_DN(dn);
		if (pdn && pdn->devfn == devfn
		    && of_device_is_available(dn))
			return rtas_write_config(pdn, where, size, val);
	}
	return PCIBIOS_DEVICE_NOT_FOUND;
}

struct pci_ops rtas_pci_ops = {
	.read = rtas_pci_read_config,
	.write = rtas_pci_write_config,
};

int is_python(struct device_node *dev)
{
	const char *model = of_get_property(dev, "model", NULL);

	if (model && strstr(model, "Python"))
		return 1;

	return 0;
}

static void python_countermeasures(struct device_node *dev)
{
	struct resource registers;
	void __iomem *chip_regs;
	volatile u32 val;

	if (of_address_to_resource(dev, 0, &registers)) {
		printk(KERN_ERR "Can't get address for Python workarounds !\n");
		return;
	}

	/* Python's register file is 1 MB in size. */
	chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000);

	/*
	 * Firmware doesn't always clear this bit which is critical
	 * for good performance - Anton
	 */

#define PRG_CL_RESET_VALID 0x00010000

	val = in_be32(chip_regs + 0xf6030);
	if (val & PRG_CL_RESET_VALID) {
		printk(KERN_INFO "Python workaround: ");
		val &= ~PRG_CL_RESET_VALID;
		out_be32(chip_regs + 0xf6030, val);
		/*
		 * We must read it back for changes to
		 * take effect
		 */
		val = in_be32(chip_regs + 0xf6030);
		printk("reg0: %x\n", val);
	}

	iounmap(chip_regs);
}

void __init init_pci_config_tokens (void)
{
	read_pci_config = rtas_token("read-pci-config");
	write_pci_config = rtas_token("write-pci-config");
	ibm_read_pci_config = rtas_token("ibm,read-pci-config");
	ibm_write_pci_config = rtas_token("ibm,write-pci-config");
}

unsigned long __devinit get_phb_buid (struct device_node *phb)
{
	struct resource r;

	if (ibm_read_pci_config == -1)
		return 0;
	if (of_address_to_resource(phb, 0, &r))
		return 0;
	return r.start;
}

static int phb_set_bus_ranges(struct device_node *dev,
			      struct pci_controller *phb)
{
	const int *bus_range;
	unsigned int len;

	bus_range = of_get_property(dev, "bus-range", &len);
	if (bus_range == NULL || len < 2 * sizeof(int)) {
		return 1;
 	}

	phb->first_busno =  bus_range[0];
	phb->last_busno  =  bus_range[1];

	return 0;
}

int __devinit rtas_setup_phb(struct pci_controller *phb)
{
	struct device_node *dev = phb->dn;

	if (is_python(dev))
		python_countermeasures(dev);

	if (phb_set_bus_ranges(dev, phb))
		return 1;

	phb->ops = &rtas_pci_ops;
	phb->buid = get_phb_buid(dev);

	return 0;
}

void __init find_and_init_phbs(void)
{
	struct device_node *node;
	struct pci_controller *phb;
	struct device_node *root = of_find_node_by_path("/");

	for_each_child_of_node(root, node) {
		if (node->type == NULL || (strcmp(node->type, "pci") != 0 &&
					   strcmp(node->type, "pciex") != 0))
			continue;

		phb = pcibios_alloc_controller(node);
		if (!phb)
			continue;
		rtas_setup_phb(phb);
		pci_process_bridge_OF_ranges(phb, node, 0);
		isa_bridge_find_early(phb);
	}

	of_node_put(root);
	pci_devs_phb_init();

	/*
	 * pci_probe_only and pci_assign_all_buses can be set via properties
	 * in chosen.
	 */
	if (of_chosen) {
		const int *prop;

		prop = of_get_property(of_chosen,
				"linux,pci-probe-only", NULL);
		if (prop)
			pci_probe_only = *prop;

#ifdef CONFIG_PPC32 /* Will be made generic soon */
		prop = of_get_property(of_chosen,
				"linux,pci-assign-all-buses", NULL);
		if (prop && *prop)
			ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS;
#endif /* CONFIG_PPC32 */
	}
}

/* RPA-specific bits for removing PHBs */
int pcibios_remove_root_bus(struct pci_controller *phb)
{
	struct pci_bus *b = phb->bus;
	struct resource *res;
	int rc, i;

	res = b->resource[0];
	if (!res->flags) {
		printk(KERN_ERR "%s: no IO resource for PHB %s\n", __func__,
				b->name);
		return 1;
	}

	rc = pcibios_unmap_io_space(b);
	if (rc) {
		printk(KERN_ERR "%s: failed to unmap IO on bus %s\n",
			__func__, b->name);
		return 1;
	}

	if (release_resource(res)) {
		printk(KERN_ERR "%s: failed to release IO on bus %s\n",
				__func__, b->name);
		return 1;
	}

	for (i = 1; i < 3; ++i) {
		res = b->resource[i];
		if (!res->flags && i == 0) {
			printk(KERN_ERR "%s: no MEM resource for PHB %s\n",
				__func__, b->name);
			return 1;
		}
		if (res->flags && release_resource(res)) {
			printk(KERN_ERR
			       "%s: failed to release IO %d on bus %s\n",
				__func__, i, b->name);
			return 1;
		}
	}

	pcibios_free_controller(phb);

	return 0;
}
EXPORT_SYMBOL(pcibios_remove_root_bus);
Commit	Line	Data
c5a3c2e5	1	/*
c5a3c2e5 AB	2	* Copyright (C) 2001 Dave Engebretsen, IBM Corporation
	3	* Copyright (C) 2003 Anton Blanchard <[email protected]>, IBM
	4	*
	5	* RTAS specific routines for PCI.
ae65a391	6	*
c5a3c2e5 AB	7	* Based on code from pci.c, chrp_pci.c and pSeries_pci.c
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
ae65a391	13	*
c5a3c2e5 AB	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
ae65a391	18	*
c5a3c2e5 AB	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*/
	23
	24	#include <linux/kernel.h>
	25	#include <linux/threads.h>
	26	#include <linux/pci.h>
	27	#include <linux/string.h>
	28	#include <linux/init.h>
	29	#include <linux/bootmem.h>
	30
	31	#include <asm/io.h>
	32	#include <asm/pgtable.h>
	33	#include <asm/irq.h>
	34	#include <asm/prom.h>
	35	#include <asm/machdep.h>
	36	#include <asm/pci-bridge.h>
	37	#include <asm/iommu.h>
	38	#include <asm/rtas.h>
bbeb3f4c	39	#include <asm/mpic.h>
d387899f	40	#include <asm/ppc-pci.h>
68a64357	41	#include <asm/eeh.h>
c5a3c2e5 AB	42
	43	/* RTAS tokens */
	44	static int read_pci_config;
	45	static int write_pci_config;
	46	static int ibm_read_pci_config;
	47	static int ibm_write_pci_config;
	48
ae65a391	49	static inline int config_access_valid(struct pci_dn *dn, int where)
c5a3c2e5 AB	50	{
	51	if (where < 256)
	52	return 1;
	53	if (where < 4096 && dn->pci_ext_config_space)
	54	return 1;
	55
	56	return 0;
	57	}
	58
7684b40c	59	int rtas_read_config(struct pci_dn pdn, int where, int size, u32 val)
c5a3c2e5 AB	60	{
	61	int returnval = -1;
	62	unsigned long buid, addr;
	63	int ret;
	64
ae65a391	65	if (!pdn)
c5a3c2e5	66	return PCIBIOS_DEVICE_NOT_FOUND;
1635317f	67	if (!config_access_valid(pdn, where))
c5a3c2e5 AB	68	return PCIBIOS_BAD_REGISTER_NUMBER;
c5a3c2e5 AB	69
6f3d5d3c	70	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
1635317f	71	buid = pdn->phb->buid;
c5a3c2e5 AB	72	if (buid) {
c5a3c2e5 AB	73	ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
ae65a391	74	addr, BUID_HI(buid), BUID_LO(buid), size);
c5a3c2e5 AB	75	} else {
	76	ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
	77	}
	78	*val = returnval;
	79
	80	if (ret)
	81	return PCIBIOS_DEVICE_NOT_FOUND;
	82
1635317f	83	if (returnval == EEH_IO_ERROR_VALUE(size) &&
ae65a391	84	eeh_dn_check_failure (pdn->node, NULL))
c5a3c2e5 AB	85	return PCIBIOS_DEVICE_NOT_FOUND;
	86
	87	return PCIBIOS_SUCCESSFUL;
	88	}
	89
	90	static int rtas_pci_read_config(struct pci_bus *bus,
	91	unsigned int devfn,
	92	int where, int size, u32 *val)
	93	{
	94	struct device_node busdn, dn;
	95
	96	if (bus->self)
	97	busdn = pci_device_to_OF_node(bus->self);
	98	else
	99	busdn = bus->sysdata; /* must be a phb */
	100
	101	/* Search only direct children of the bus */
ae65a391 LV	102	for (dn = busdn->child; dn; dn = dn->sibling) {
	103	struct pci_dn *pdn = PCI_DN(dn);
	104	if (pdn && pdn->devfn == devfn
c6d4d5a8	105	&& of_device_is_available(dn))
ae65a391 LV	106	return rtas_read_config(pdn, where, size, val);
ae65a391 LV	107	}
1635317f	108
c5a3c2e5 AB	109	return PCIBIOS_DEVICE_NOT_FOUND;
	110	}
	111
ae65a391	112	int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
c5a3c2e5 AB	113	{
	114	unsigned long buid, addr;
	115	int ret;
	116
ae65a391	117	if (!pdn)
c5a3c2e5	118	return PCIBIOS_DEVICE_NOT_FOUND;
1635317f	119	if (!config_access_valid(pdn, where))
c5a3c2e5 AB	120	return PCIBIOS_BAD_REGISTER_NUMBER;
c5a3c2e5 AB	121
6f3d5d3c	122	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
1635317f	123	buid = pdn->phb->buid;
c5a3c2e5	124	if (buid) {
ae65a391 LV	125	ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
ae65a391 LV	126	BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
c5a3c2e5 AB	127	} else {
	128	ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
	129	}
	130
	131	if (ret)
	132	return PCIBIOS_DEVICE_NOT_FOUND;
	133
	134	return PCIBIOS_SUCCESSFUL;
	135	}
	136
	137	static int rtas_pci_write_config(struct pci_bus *bus,
	138	unsigned int devfn,
	139	int where, int size, u32 val)
	140	{
	141	struct device_node busdn, dn;
	142
	143	if (bus->self)
	144	busdn = pci_device_to_OF_node(bus->self);
	145	else
	146	busdn = bus->sysdata; /* must be a phb */
	147
	148	/* Search only direct children of the bus */
ae65a391 LV	149	for (dn = busdn->child; dn; dn = dn->sibling) {
	150	struct pci_dn *pdn = PCI_DN(dn);
	151	if (pdn && pdn->devfn == devfn
c6d4d5a8	152	&& of_device_is_available(dn))
ae65a391 LV	153	return rtas_write_config(pdn, where, size, val);
ae65a391 LV	154	}
c5a3c2e5 AB	155	return PCIBIOS_DEVICE_NOT_FOUND;
	156	}
	157
	158	struct pci_ops rtas_pci_ops = {
8674e0c9 NL	159	.read = rtas_pci_read_config,
8674e0c9 NL	160	.write = rtas_pci_write_config,
c5a3c2e5 AB	161	};
	162
	163	int is_python(struct device_node *dev)
	164	{
e2eb6392	165	const char *model = of_get_property(dev, "model", NULL);
c5a3c2e5 AB	166
	167	if (model && strstr(model, "Python"))
	168	return 1;
	169
	170	return 0;
	171	}
	172
cc5d0189	173	static void python_countermeasures(struct device_node *dev)
c5a3c2e5	174	{
cc5d0189	175	struct resource registers;
c5a3c2e5 AB	176	void __iomem *chip_regs;
	177	volatile u32 val;
	178
cc5d0189 BH	179	if (of_address_to_resource(dev, 0, &registers)) {
cc5d0189 BH	180	printk(KERN_ERR "Can't get address for Python workarounds !\n");
c5a3c2e5	181	return;
cc5d0189	182	}
c5a3c2e5 AB	183
c5a3c2e5 AB	184	/* Python's register file is 1 MB in size. */
cc5d0189	185	chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000);
c5a3c2e5	186
ae65a391	187	/*
c5a3c2e5 AB	188	* Firmware doesn't always clear this bit which is critical
	189	* for good performance - Anton
	190	*/
	191
	192	#define PRG_CL_RESET_VALID 0x00010000
	193
	194	val = in_be32(chip_regs + 0xf6030);
	195	if (val & PRG_CL_RESET_VALID) {
	196	printk(KERN_INFO "Python workaround: ");
	197	val &= ~PRG_CL_RESET_VALID;
	198	out_be32(chip_regs + 0xf6030, val);
	199	/*
	200	* We must read it back for changes to
	201	* take effect
	202	*/
	203	val = in_be32(chip_regs + 0xf6030);
	204	printk("reg0: %x\n", val);
	205	}
	206
	207	iounmap(chip_regs);
	208	}
	209
	210	void __init init_pci_config_tokens (void)
	211	{
	212	read_pci_config = rtas_token("read-pci-config");
	213	write_pci_config = rtas_token("write-pci-config");
	214	ibm_read_pci_config = rtas_token("ibm,read-pci-config");
	215	ibm_write_pci_config = rtas_token("ibm,write-pci-config");
	216	}
	217
	218	unsigned long __devinit get_phb_buid (struct device_node *phb)
	219	{
6506e710	220	struct resource r;
c5a3c2e5	221
6506e710	222	if (ibm_read_pci_config == -1)
c5a3c2e5	223	return 0;
6506e710	224	if (of_address_to_resource(phb, 0, &r))
c5a3c2e5	225	return 0;
6506e710	226	return r.start;
c5a3c2e5 AB	227	}
	228
	229	static int phb_set_bus_ranges(struct device_node *dev,
	230	struct pci_controller *phb)
	231	{
a7f67bdf	232	const int *bus_range;
c5a3c2e5 AB	233	unsigned int len;
c5a3c2e5 AB	234
e2eb6392	235	bus_range = of_get_property(dev, "bus-range", &len);
c5a3c2e5 AB	236	if (bus_range == NULL \|\| len < 2 * sizeof(int)) {
	237	return 1;
	238	}
ae65a391	239
c5a3c2e5 AB	240	phb->first_busno = bus_range[0];
	241	phb->last_busno = bus_range[1];
	242
	243	return 0;
	244	}
	245
4c9d2800	246	int __devinit rtas_setup_phb(struct pci_controller *phb)
c5a3c2e5	247	{
44ef3390	248	struct device_node *dev = phb->dn;
4c9d2800	249
c5a3c2e5	250	if (is_python(dev))
cc5d0189	251	python_countermeasures(dev);
c5a3c2e5 AB	252
	253	if (phb_set_bus_ranges(dev, phb))
	254	return 1;
	255
c5a3c2e5 AB	256	phb->ops = &rtas_pci_ops;
	257	phb->buid = get_phb_buid(dev);
	258
	259	return 0;
	260	}
	261
36241ce6	262	void __init find_and_init_phbs(void)
c5a3c2e5 AB	263	{
	264	struct device_node *node;
	265	struct pci_controller *phb;
c5a3c2e5 AB	266	struct device_node *root = of_find_node_by_path("/");
c5a3c2e5 AB	267
85e99b9f	268	for_each_child_of_node(root, node) {
bb53bb3d JM	269	if (node->type == NULL \|\| (strcmp(node->type, "pci") != 0 &&
bb53bb3d JM	270	strcmp(node->type, "pciex") != 0))
c5a3c2e5 AB	271	continue;
c5a3c2e5 AB	272
b5166cc2	273	phb = pcibios_alloc_controller(node);
c5a3c2e5 AB	274	if (!phb)
c5a3c2e5 AB	275	continue;
4c9d2800	276	rtas_setup_phb(phb);
f7abbc19	277	pci_process_bridge_OF_ranges(phb, node, 0);
3d5134ee	278	isa_bridge_find_early(phb);
c5a3c2e5 AB	279	}
	280
	281	of_node_put(root);
	282	pci_devs_phb_init();
	283
	284	/*
	285	* pci_probe_only and pci_assign_all_buses can be set via properties
	286	* in chosen.
	287	*/
	288	if (of_chosen) {
a7f67bdf	289	const int *prop;
c5a3c2e5	290
e2eb6392	291	prop = of_get_property(of_chosen,
a7f67bdf	292	"linux,pci-probe-only", NULL);
c5a3c2e5 AB	293	if (prop)
	294	pci_probe_only = *prop;
	295
fc3fb71c	296	#ifdef CONFIG_PPC32 /* Will be made generic soon */
e2eb6392	297	prop = of_get_property(of_chosen,
a7f67bdf	298	"linux,pci-assign-all-buses", NULL);
fc3fb71c BH	299	if (prop && *prop)
	300	ppc_pci_flags \|= PPC_PCI_REASSIGN_ALL_BUS;
	301	#endif /* CONFIG_PPC32 */
c5a3c2e5	302	}
c5a3c2e5 AB	303	}
c5a3c2e5 AB	304
c5a3c2e5 AB	305	/* RPA-specific bits for removing PHBs */
	306	int pcibios_remove_root_bus(struct pci_controller *phb)
	307	{
	308	struct pci_bus *b = phb->bus;
	309	struct resource *res;
	310	int rc, i;
	311
	312	res = b->resource[0];
	313	if (!res->flags) {
e48b1b45	314	printk(KERN_ERR "%s: no IO resource for PHB %s\n", __func__,
c5a3c2e5 AB	315	b->name);
	316	return 1;
	317	}
	318
3d5134ee	319	rc = pcibios_unmap_io_space(b);
c5a3c2e5 AB	320	if (rc) {
c5a3c2e5 AB	321	printk(KERN_ERR "%s: failed to unmap IO on bus %s\n",
e48b1b45	322	__func__, b->name);
c5a3c2e5 AB	323	return 1;
	324	}
	325
	326	if (release_resource(res)) {
	327	printk(KERN_ERR "%s: failed to release IO on bus %s\n",
e48b1b45	328	__func__, b->name);
c5a3c2e5 AB	329	return 1;
	330	}
	331
	332	for (i = 1; i < 3; ++i) {
	333	res = b->resource[i];
	334	if (!res->flags && i == 0) {
	335	printk(KERN_ERR "%s: no MEM resource for PHB %s\n",
e48b1b45	336	__func__, b->name);
c5a3c2e5 AB	337	return 1;
	338	}
	339	if (res->flags && release_resource(res)) {
	340	printk(KERN_ERR
	341	"%s: failed to release IO %d on bus %s\n",
e48b1b45	342	__func__, i, b->name);
c5a3c2e5 AB	343	return 1;
	344	}
	345	}
	346
b5166cc2	347	pcibios_free_controller(phb);
c5a3c2e5 AB	348
	349	return 0;
	350	}
	351	EXPORT_SYMBOL(pcibios_remove_root_bus);