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iwlagn: add eeprom command to testmode
[linux.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
b481de9c
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1/******************************************************************************
2 *
901069c7 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <[email protected]>
b481de9c
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23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 */
30
be1f3ab6
EG
31#ifndef __iwl_dev_h__
32#define __iwl_dev_h__
b481de9c 33
5d08cd1d
CH
34#include <linux/pci.h> /* for struct pci_device_id */
35#include <linux/kernel.h>
7194207c 36#include <linux/wait.h>
5ed540ae 37#include <linux/leds.h>
5d08cd1d
CH
38#include <net/ieee80211_radiotap.h>
39
6bc913bd 40#include "iwl-eeprom.h"
6f83eaa1 41#include "iwl-csr.h"
5d08cd1d 42#include "iwl-prph.h"
dbb6654c 43#include "iwl-fh.h"
0a6857e7 44#include "iwl-debug.h"
b744cb79 45#include "iwl-agn-hw.h"
ab53d8af 46#include "iwl-led.h"
5da4b55f 47#include "iwl-power.h"
e227ceac 48#include "iwl-agn-rs.h"
0975cc8f 49#include "iwl-agn-tt.h"
5d08cd1d 50
672639de
WYG
51struct iwl_tx_queue;
52
099b40b7 53/* CT-KILL constants */
672639de
WYG
54#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
55#define CT_KILL_THRESHOLD 114 /* in Celsius */
56#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 57
5d08cd1d
CH
58/* Default noise level to report when noise measurement is not available.
59 * This may be because we're:
60 * 1) Not associated (4965, no beacon statistics being sent to driver)
61 * 2) Scanning (noise measurement does not apply to associated channel)
62 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
63 * Use default noise value of -127 ... this is below the range of measurable
64 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
65 * Also, -127 works better than 0 when averaging frames with/without
66 * noise info (e.g. averaging might be done in app); measured dBm values are
67 * always negative ... using a negative value as the default keeps all
68 * averages within an s8's (used in some apps) range of negative values. */
69#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
70
5d08cd1d
CH
71/*
72 * RTS threshold here is total size [2347] minus 4 FCS bytes
73 * Per spec:
74 * a value of 0 means RTS on all data/management packets
75 * a value > max MSDU size means no RTS
76 * else RTS for data/management frames where MPDU is larger
77 * than RTS value.
78 */
79#define DEFAULT_RTS_THRESHOLD 2347U
80#define MIN_RTS_THRESHOLD 0U
81#define MAX_RTS_THRESHOLD 2347U
82#define MAX_MSDU_SIZE 2304U
83#define MAX_MPDU_SIZE 2346U
84#define DEFAULT_BEACON_INTERVAL 100U
85#define DEFAULT_SHORT_RETRY_LIMIT 7U
86#define DEFAULT_LONG_RETRY_LIMIT 4U
87
a55360e4 88struct iwl_rx_mem_buffer {
2f301227
ZY
89 dma_addr_t page_dma;
90 struct page *page;
5d08cd1d
CH
91 struct list_head list;
92};
93
2f301227
ZY
94#define rxb_addr(r) page_address(r->page)
95
c2acea8e
JB
96/* defined below */
97struct iwl_device_cmd;
98
99struct iwl_cmd_meta {
100 /* only for SYNC commands, iff the reply skb is wanted */
101 struct iwl_host_cmd *source;
102 /*
103 * only for ASYNC commands
104 * (which is somewhat stupid -- look at iwl-sta.c for instance
105 * which duplicates a bunch of code because the callback isn't
106 * invoked for SYNC commands, if it were and its result passed
107 * through it would be simpler...)
108 */
5696aea6
JB
109 void (*callback)(struct iwl_priv *priv,
110 struct iwl_device_cmd *cmd,
2f301227 111 struct iwl_rx_packet *pkt);
c2acea8e 112
c2acea8e
JB
113 u32 flags;
114
2e724443
FT
115 DEFINE_DMA_UNMAP_ADDR(mapping);
116 DEFINE_DMA_UNMAP_LEN(len);
c2acea8e
JB
117};
118
5d08cd1d
CH
119/*
120 * Generic queue structure
121 *
4ce7cc2b
JB
122 * Contains common data for Rx and Tx queues.
123 *
124 * Note the difference between n_bd and n_window: the hardware
125 * always assumes 256 descriptors, so n_bd is always 256 (unless
126 * there might be HW changes in the future). For the normal TX
127 * queues, n_window, which is the size of the software queue data
128 * is also 256; however, for the command queue, n_window is only
129 * 32 since we don't need so many commands pending. Since the HW
130 * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
131 * the software buffers (in the variables @meta, @txb in struct
132 * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
133 * in the same struct) have 256.
134 * This means that we end up with the following:
135 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
136 * SW entries: | 0 | ... | 31 |
137 * where N is a number between 0 and 7. This means that the SW
138 * data is a window overlayed over the HW queue.
5d08cd1d 139 */
443cfd45 140struct iwl_queue {
5d08cd1d
CH
141 int n_bd; /* number of BDs in this queue */
142 int write_ptr; /* 1-st empty entry (index) host_w*/
143 int read_ptr; /* last used entry (index) host_r*/
b74e31a9 144 /* use for monitoring and recovering the stuck queue */
5d08cd1d
CH
145 dma_addr_t dma_addr; /* physical addr for BD's */
146 int n_window; /* safe queue window */
147 u32 id;
148 int low_mark; /* low watermark, resume queue if free
149 * space more than this */
150 int high_mark; /* high watermark, stop queue if free
151 * space less than this */
a839cf69 152};
5d08cd1d 153
bc47279f 154/* One for each TFD */
8567c63e 155struct iwl_tx_info {
ff0d91c3 156 struct sk_buff *skb;
c90cbbbd 157 struct iwl_rxon_context *ctx;
5d08cd1d
CH
158};
159
160/**
16466903 161 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
162 * @q: generic Rx/Tx queue descriptor
163 * @bd: base of circular buffer of TFDs
c2acea8e
JB
164 * @cmd: array of command/TX buffer pointers
165 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
166 * @dma_addr_cmd: physical address of cmd/tx buffer array
167 * @txb: array of per-TFD driver data
22de94de 168 * @time_stamp: time (in jiffies) of last read_ptr change
bc47279f
BC
169 * @need_update: indicates need to update read/write index
170 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 171 *
bc47279f
BC
172 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
173 * descriptors) and required locking structures.
5d08cd1d 174 */
188cf6c7
SO
175#define TFD_TX_CMD_SLOTS 256
176#define TFD_CMD_SLOTS 32
177
16466903 178struct iwl_tx_queue {
443cfd45 179 struct iwl_queue q;
4ce7cc2b 180 struct iwl_tfd *tfds;
c2acea8e
JB
181 struct iwl_device_cmd **cmd;
182 struct iwl_cmd_meta *meta;
8567c63e 183 struct iwl_tx_info *txb;
22de94de 184 unsigned long time_stamp;
3fd07a1e
TW
185 u8 need_update;
186 u8 sched_retry;
187 u8 active;
188 u8 swq_id;
5d08cd1d
CH
189};
190
191#define IWL_NUM_SCAN_RATES (2)
192
5d08cd1d
CH
193/*
194 * One for each channel, holds all channel setup data
195 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
196 * with one another!
197 */
bf85ea4f 198struct iwl_channel_info {
073d3f5f 199 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
200 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
201 * HT40 channel */
5d08cd1d
CH
202
203 u8 channel; /* channel number */
204 u8 flags; /* flags copied from EEPROM */
205 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 206 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
207 s8 min_power; /* always 0 */
208 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
209
210 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
211 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 212 enum ieee80211_band band;
5d08cd1d 213
7aafef1c
WYG
214 /* HT40 channel info */
215 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
216 u8 ht40_flags; /* flags copied from EEPROM */
217 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
5d08cd1d
CH
218};
219
751ca305 220#define IWL_TX_FIFO_BK 0 /* shared */
edc1a3a0 221#define IWL_TX_FIFO_BE 1
751ca305 222#define IWL_TX_FIFO_VI 2 /* shared */
edc1a3a0 223#define IWL_TX_FIFO_VO 3
751ca305
JB
224#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
225#define IWL_TX_FIFO_BE_IPAN 4
226#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
227#define IWL_TX_FIFO_VO_IPAN 5
edc1a3a0 228#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 229
01a7e084
RC
230/* Minimum number of queues. MAX_NUM is defined in hw specific files.
231 * Set the minimum to accommodate the 4 standard TX queues, 1 command
232 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
233#define IWL_MIN_NUM_QUEUES 10
5d08cd1d 234
bd35f150 235/*
13bb9483 236 * Command queue depends on iPAN support.
bd35f150 237 */
13bb9483
JB
238#define IWL_DEFAULT_CMD_QUEUE_NUM 4
239#define IWL_IPAN_CMD_QUEUE_NUM 9
bd35f150 240
751ca305
JB
241/*
242 * This queue number is required for proper operation
243 * because the ucode will stop/start the scheduler as
244 * required.
245 */
246#define IWL_IPAN_MCAST_QUEUE 8
247
5d08cd1d
CH
248#define IEEE80211_DATA_LEN 2304
249#define IEEE80211_4ADDR_LEN 30
250#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
251#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
252
5d08cd1d 253
5d08cd1d
CH
254#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
255#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
256#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
257
258enum {
c587de0b
TW
259 CMD_SYNC = 0,
260 CMD_SIZE_NORMAL = 0,
261 CMD_NO_SKB = 0,
5d08cd1d 262 CMD_ASYNC = (1 << 1),
5d08cd1d 263 CMD_WANT_SKB = (1 << 2),
3598e177 264 CMD_MAPPED = (1 << 3),
5d08cd1d
CH
265};
266
c8c24872 267#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 268
bc47279f 269/**
c2acea8e 270 * struct iwl_device_cmd
bc47279f
BC
271 *
272 * For allocation of the command and tx queues, this establishes the overall
4ce7cc2b
JB
273 * size of the largest command we send to uCode, except for commands that
274 * aren't fully copied and use other TFD space.
bc47279f 275 */
c2acea8e 276struct iwl_device_cmd {
857485c0 277 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 278 union {
5d08cd1d
CH
279 u32 flags;
280 u8 val8;
281 u16 val16;
282 u32 val32;
83d527d9 283 struct iwl_tx_cmd tx;
c8c24872
WYG
284 struct iwl6000_channel_switch_cmd chswitch;
285 u8 payload[DEF_CMD_PAYLOAD_SIZE];
ba2d3587
ED
286 } __packed cmd;
287} __packed;
5d08cd1d 288
c2acea8e
JB
289#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
290
4ce7cc2b
JB
291#define IWL_MAX_CMD_TFDS 2
292
293enum iwl_hcmd_dataflag {
294 IWL_HCMD_DFL_NOCOPY = BIT(0),
295};
3257e5d4 296
857485c0 297struct iwl_host_cmd {
3fa50738 298 const void *data[IWL_MAX_CMD_TFDS];
2f301227 299 unsigned long reply_page;
5696aea6
JB
300 void (*callback)(struct iwl_priv *priv,
301 struct iwl_device_cmd *cmd,
2f301227 302 struct iwl_rx_packet *pkt);
c2acea8e 303 u32 flags;
3fa50738 304 u16 len[IWL_MAX_CMD_TFDS];
4ce7cc2b 305 u8 dataflags[IWL_MAX_CMD_TFDS];
c2acea8e 306 u8 id;
5d08cd1d
CH
307};
308
5d08cd1d
CH
309#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
310#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
311#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
312
313/**
a55360e4 314 * struct iwl_rx_queue - Rx queue
df833b1d 315 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
d5b25c90 316 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
317 * @read: Shared index to newest available Rx buffer
318 * @write: Shared index to oldest written Rx packet
319 * @free_count: Number of pre-allocated buffers in rx_free
320 * @rx_free: list of free SKBs for use
321 * @rx_used: List of Rx buffers with no SKB
322 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
323 * @rb_stts: driver's pointer to receive buffer status
324 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 325 *
a55360e4 326 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 327 */
a55360e4 328struct iwl_rx_queue {
5d08cd1d 329 __le32 *bd;
d5b25c90 330 dma_addr_t bd_dma;
a55360e4
TW
331 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
332 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
333 u32 read;
334 u32 write;
335 u32 free_count;
4752c93c 336 u32 write_actual;
5d08cd1d
CH
337 struct list_head rx_free;
338 struct list_head rx_used;
339 int need_update;
8d86422a
WT
340 struct iwl_rb_status *rb_stts;
341 dma_addr_t rb_stts_dma;
5d08cd1d
CH
342 spinlock_t lock;
343};
344
345#define IWL_SUPPORTED_RATES_IE_LEN 8
346
5d08cd1d
CH
347#define MAX_TID_COUNT 9
348
349#define IWL_INVALID_RATE 0xFF
350#define IWL_INVALID_VALUE -1
351
bc47279f 352/**
6def9761 353 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
354 * @txq_id: Tx queue used for Tx attempt
355 * @frame_count: # frames attempted by Tx command
356 * @wait_for_ba: Expect block-ack before next Tx reply
357 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
358 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
359 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
360 * @rate_n_flags: Rate at which Tx was attempted
361 *
362 * If REPLY_TX indicates that aggregation was attempted, driver must wait
363 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
364 * until block ack arrives.
365 */
6def9761 366struct iwl_ht_agg {
5d08cd1d
CH
367 u16 txq_id;
368 u16 frame_count;
369 u16 wait_for_ba;
370 u16 start_idx;
fe01b477 371 u64 bitmap;
5d08cd1d 372 u32 rate_n_flags;
fe01b477
RR
373#define IWL_AGG_OFF 0
374#define IWL_AGG_ON 1
375#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
376#define IWL_EMPTYING_HW_QUEUE_DELBA 3
377 u8 state;
c8823ec1 378 u8 tx_fifo;
5d08cd1d 379};
fe01b477 380
5d08cd1d 381
6def9761 382struct iwl_tid_data {
f862a236 383 u16 seq_number; /* agn only */
fe01b477 384 u16 tfds_in_queue;
6def9761 385 struct iwl_ht_agg agg;
5d08cd1d
CH
386};
387
6def9761 388struct iwl_hw_key {
97359d12 389 u32 cipher;
5d08cd1d 390 int keylen;
0211ddda 391 u8 keyidx;
5d08cd1d
CH
392 u8 key[32];
393};
394
a78fe754 395union iwl_ht_rate_supp {
5d08cd1d
CH
396 u16 rates;
397 struct {
398 u8 siso_rate;
399 u8 mimo_rate;
400 };
401};
402
172c1d11
WYG
403#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
404#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
405#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
406#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
407#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
408#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
409#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
bcc693a1
WYG
410
411/*
412 * Maximal MPDU density for TX aggregation
413 * 4 - 2us density
414 * 5 - 4us density
415 * 6 - 8us density
416 * 7 - 16us density
417 */
172c1d11 418#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
bcc693a1 419#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
172c1d11
WYG
420#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
421#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
bcc693a1 422#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
172c1d11
WYG
423#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
424#define CFG_HT_MPDU_DENSITY_MIN (0x1)
5d08cd1d 425
fad95bf5 426struct iwl_ht_config {
02bb1bea 427 bool single_chain_sufficient;
ba37a3d0 428 enum ieee80211_smps_mode smps; /* current smps mode */
5d08cd1d 429};
5d08cd1d 430
5d08cd1d 431/* QoS structures */
1ff50bda 432struct iwl_qos_info {
5d08cd1d 433 int qos_active;
1ff50bda 434 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 435};
5d08cd1d 436
fe6b23dd
RC
437/*
438 * Structure should be accessed with sta_lock held. When station addition
439 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
440 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
441 * held.
442 */
6def9761 443struct iwl_station_entry {
133636de 444 struct iwl_addsta_cmd sta;
6def9761 445 struct iwl_tid_data tid[MAX_TID_COUNT];
dcef732c 446 u8 used, ctxid;
6def9761 447 struct iwl_hw_key keyinfo;
fe6b23dd 448 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
449};
450
fd1af15d 451struct iwl_station_priv_common {
238d781d 452 struct iwl_rxon_context *ctx;
fd1af15d
JB
453 u8 sta_id;
454};
455
8d9698b3
RC
456/*
457 * iwl_station_priv: Driver's private station information
458 *
459 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
460 * in the structure for use by driver. This structure is places in that
461 * space.
8d9698b3
RC
462 */
463struct iwl_station_priv {
fd1af15d 464 struct iwl_station_priv_common common;
8d9698b3 465 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
466 atomic_t pending_frames;
467 bool client;
468 bool asleep;
7b090687 469 u8 max_agg_bufsize;
8d9698b3
RC
470};
471
fd1af15d
JB
472/**
473 * struct iwl_vif_priv - driver's private per-interface information
474 *
475 * When mac80211 allocates a virtual interface, it can allocate
476 * space for us to put data into.
477 */
478struct iwl_vif_priv {
246ed355 479 struct iwl_rxon_context *ctx;
fd1af15d
JB
480 u8 ibss_bssid_sta_id;
481};
482
5d08cd1d
CH
483/* one for each uCode image (inst/data, boot/init/runtime) */
484struct fw_desc {
485 void *v_addr; /* access by driver */
486 dma_addr_t p_addr; /* access by card's busmaster DMA */
487 u32 len; /* bytes */
488};
489
dbf28e21
JB
490struct fw_img {
491 struct fw_desc code, data;
492};
493
dd7a2509 494/* v1/v2 uCode file layout */
cc0f555d
JS
495struct iwl_ucode_header {
496 __le32 ver; /* major/minor/API/serial */
497 union {
498 struct {
499 __le32 inst_size; /* bytes of runtime code */
500 __le32 data_size; /* bytes of runtime data */
501 __le32 init_size; /* bytes of init code */
502 __le32 init_data_size; /* bytes of init data */
503 __le32 boot_size; /* bytes of bootstrap code */
504 u8 data[0]; /* in same order as sizes */
505 } v1;
506 struct {
507 __le32 build; /* build number */
508 __le32 inst_size; /* bytes of runtime code */
509 __le32 data_size; /* bytes of runtime data */
510 __le32 init_size; /* bytes of init code */
511 __le32 init_data_size; /* bytes of init data */
512 __le32 boot_size; /* bytes of bootstrap code */
513 u8 data[0]; /* in same order as sizes */
514 } v2;
515 } u;
5d08cd1d
CH
516};
517
dd7a2509
JB
518/*
519 * new TLV uCode file layout
520 *
521 * The new TLV file format contains TLVs, that each specify
522 * some piece of data. To facilitate "groups", for example
523 * different instruction image with different capabilities,
524 * bundled with the same init image, an alternative mechanism
525 * is provided:
526 * When the alternative field is 0, that means that the item
527 * is always valid. When it is non-zero, then it is only
528 * valid in conjunction with items of the same alternative,
529 * in which case the driver (user) selects one alternative
530 * to use.
531 */
532
533enum iwl_ucode_tlv_type {
534 IWL_UCODE_TLV_INVALID = 0, /* unused */
535 IWL_UCODE_TLV_INST = 1,
536 IWL_UCODE_TLV_DATA = 2,
537 IWL_UCODE_TLV_INIT = 3,
538 IWL_UCODE_TLV_INIT_DATA = 4,
539 IWL_UCODE_TLV_BOOT = 5,
540 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
ece9c4ee 541 IWL_UCODE_TLV_PAN = 7,
b2e640d4
JB
542 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
543 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
544 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
545 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
546 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
547 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
c8312fac 548 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
6a822d06 549 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
3997ff39
JB
550 /* 16 and 17 reserved for future use */
551 IWL_UCODE_TLV_FLAGS = 18,
552};
553
554/**
555 * enum iwl_ucode_tlv_flag - ucode API flags
556 * @IWL_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
557 * was a separate TLV but moved here to save space.
d2690c0d
JB
558 * @IWL_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
559 * treats good CRC threshold as a boolean
3997ff39
JB
560 * @IWL_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
561 */
562enum iwl_ucode_tlv_flag {
563 IWL_UCODE_TLV_FLAGS_PAN = BIT(0),
d2690c0d 564 IWL_UCODE_TLV_FLAGS_NEWSCAN = BIT(1),
3997ff39 565 IWL_UCODE_TLV_FLAGS_MFP = BIT(2),
dd7a2509
JB
566};
567
568struct iwl_ucode_tlv {
569 __le16 type; /* see above */
570 __le16 alternative; /* see comment */
571 __le32 length; /* not including type/length fields */
572 u8 data[0];
ba2d3587 573} __packed;
dd7a2509
JB
574
575#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
576
577struct iwl_tlv_ucode_header {
578 /*
579 * The TLV style ucode header is distinguished from
580 * the v1/v2 style header by first four bytes being
581 * zero, as such is an invalid combination of
582 * major/minor/API/serial versions.
583 */
584 __le32 zero;
585 __le32 magic;
586 u8 human_readable[64];
587 __le32 ver; /* major/minor/API/serial */
588 __le32 build;
589 __le64 alternatives; /* bitmask of valid alternatives */
590 /*
591 * The data contained herein has a TLV layout,
592 * see above for the TLV header and types.
593 * Note that each TLV is padded to a length
594 * that is a multiple of 4 for alignment.
595 */
596 u8 data[0];
597};
598
f0832f13
EG
599struct iwl_sensitivity_ranges {
600 u16 min_nrg_cck;
601 u16 max_nrg_cck;
602
603 u16 nrg_th_cck;
604 u16 nrg_th_ofdm;
605
606 u16 auto_corr_min_ofdm;
607 u16 auto_corr_min_ofdm_mrc;
608 u16 auto_corr_min_ofdm_x1;
609 u16 auto_corr_min_ofdm_mrc_x1;
610
611 u16 auto_corr_max_ofdm;
612 u16 auto_corr_max_ofdm_mrc;
613 u16 auto_corr_max_ofdm_x1;
614 u16 auto_corr_max_ofdm_mrc_x1;
615
616 u16 auto_corr_max_cck;
617 u16 auto_corr_max_cck_mrc;
618 u16 auto_corr_min_cck;
619 u16 auto_corr_min_cck_mrc;
55036d66
WYG
620
621 u16 barker_corr_th_min;
622 u16 barker_corr_th_min_mrc;
623 u16 nrg_th_cca;
f0832f13
EG
624};
625
099b40b7 626
b5047f78
TW
627#define KELVIN_TO_CELSIUS(x) ((x)-273)
628#define CELSIUS_TO_KELVIN(x) ((x)+273)
629
630
bc47279f 631/**
5425e490 632 * struct iwl_hw_params
bc47279f 633 * @max_txq_num: Max # Tx queues supported
f3f911d1 634 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 635 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 636 * @tfd_size: TFD size
099b40b7
RR
637 * @tx/rx_chains_num: Number of TX/RX chains
638 * @valid_tx/rx_ant: usable antennas
bc47279f 639 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 640 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 641 * @rx_page_order: Rx buffer page order
141c43a3 642 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f 643 * @max_stations:
7aafef1c 644 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
645 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
646 * @sw_crypto: 0 for hw, 1 for sw
647 * @max_xxx_size: for ucode uses
648 * @ct_kill_threshold: temperature threshold
a0ee74cf 649 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
a96a27f9 650 * @calib_init_cfg: setup initial calibrations for the hw
6d6a1afd 651 * @calib_rt_cfg: setup runtime calibrations for the hw
f0832f13 652 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 653 */
5425e490 654struct iwl_hw_params {
f3f911d1
ZY
655 u8 max_txq_num;
656 u8 dma_chnl_num;
4ddbb7d0 657 u16 scd_bc_tbls_size;
a8e74e27 658 u32 tfd_size;
ec35cf2a
TW
659 u8 tx_chains_num;
660 u8 rx_chains_num;
661 u8 valid_tx_ant;
662 u8 valid_rx_ant;
5d08cd1d 663 u16 max_rxq_size;
ec35cf2a 664 u16 max_rxq_log;
2f301227 665 u32 rx_page_order;
141c43a3 666 u32 rx_wrt_ptr_reg;
5d08cd1d 667 u8 max_stations;
7aafef1c 668 u8 ht40_channel;
2c2f3b33 669 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
670 u32 max_inst_size;
671 u32 max_data_size;
099b40b7 672 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
673 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
674 /* for 1000, 6000 series and up */
a0ee74cf 675 u16 beacon_time_tsf_bits;
be5d56ed 676 u32 calib_init_cfg;
6d6a1afd 677 u32 calib_rt_cfg;
f0832f13 678 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
679};
680
5d08cd1d 681
5d08cd1d
CH
682/******************************************************************************
683 *
a33c2f47
EG
684 * Functions implemented in core module which are forward declared here
685 * for use by iwl-[4-5].c
5d08cd1d 686 *
a33c2f47
EG
687 * NOTE: The implementation of these functions are not hardware specific
688 * which is why they are in the core module files.
5d08cd1d
CH
689 *
690 * Naming convention --
a33c2f47 691 * iwl_ <-- Is part of iwlwifi
5d08cd1d 692 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
5d08cd1d
CH
693 *
694 ****************************************************************************/
5b9f8cd3 695extern void iwl_update_chain_flags(struct iwl_priv *priv);
a33c2f47 696extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 697extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 698extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 699extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
700static inline int iwl_queue_used(const struct iwl_queue *q, int i)
701{
c8106d76 702 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
703 (i >= q->read_ptr && i < q->write_ptr) :
704 !(i < q->read_ptr && i >= q->write_ptr);
705}
706
707
4ce7cc2b 708static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
fd4abac5 709{
fd4abac5
TW
710 return index & (q->n_window - 1);
711}
712
713
4ddbb7d0
TW
714struct iwl_dma_ptr {
715 dma_addr_t dma;
716 void *addr;
b481de9c
ZY
717 size_t size;
718};
719
b481de9c
ZY
720#define IWL_OPERATION_MODE_AUTO 0
721#define IWL_OPERATION_MODE_HT_ONLY 1
722#define IWL_OPERATION_MODE_MIXED 2
723#define IWL_OPERATION_MODE_20MHZ 3
724
3195cdb7
TW
725#define IWL_TX_CRC_SIZE 4
726#define IWL_TX_DELIMITER_SIZE 4
b481de9c 727
b481de9c 728#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 729
b481de9c 730/* Sensitivity and chain noise calibration */
b481de9c 731#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a 732#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
733#define MAXIMUM_ALLOWED_PATHLOSS 15
734
b481de9c
ZY
735#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
736
737#define MAX_FA_OFDM 50
738#define MIN_FA_OFDM 5
739#define MAX_FA_CCK 50
740#define MIN_FA_CCK 5
741
b481de9c
ZY
742#define AUTO_CORR_STEP_OFDM 1
743
b481de9c
ZY
744#define AUTO_CORR_STEP_CCK 3
745#define AUTO_CORR_MAX_TH_CCK 160
746
b481de9c
ZY
747#define NRG_DIFF 2
748#define NRG_STEP_CCK 2
749#define NRG_MARGIN 8
750#define MAX_NUMBER_CCK_NO_FA 100
751
752#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
753
754#define CHAIN_A 0
755#define CHAIN_B 1
756#define CHAIN_C 2
757#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
758#define ALL_BAND_FILTER 0xFF00
759#define IN_BAND_FILTER 0xFF
760#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
761
3195cdb7
TW
762#define NRG_NUM_PREV_STAT_L 20
763#define NUM_RX_CHAINS 3
764
3240cab3 765enum iwlagn_false_alarm_state {
b481de9c
ZY
766 IWL_FA_TOO_MANY = 0,
767 IWL_FA_TOO_FEW = 1,
768 IWL_FA_GOOD_RANGE = 2,
769};
770
3240cab3 771enum iwlagn_chain_noise_state {
b481de9c 772 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
773 IWL_CHAIN_NOISE_ACCUMULATE,
774 IWL_CHAIN_NOISE_CALIBRATED,
775 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
776};
777
f69f42a6
TW
778
779/*
780 * enum iwl_calib
781 * defines the order in which results of initial calibrations
782 * should be sent to the runtime uCode
783 */
784enum iwl_calib {
785 IWL_CALIB_XTAL,
819500c5 786 IWL_CALIB_DC,
f69f42a6
TW
787 IWL_CALIB_LO,
788 IWL_CALIB_TX_IQ,
789 IWL_CALIB_TX_IQ_PERD,
201706ac 790 IWL_CALIB_BASE_BAND,
bf53f939 791 IWL_CALIB_TEMP_OFFSET,
f69f42a6
TW
792 IWL_CALIB_MAX
793};
794
6e21f2c1
TW
795/* Opaque calibration results */
796struct iwl_calib_result {
797 void *buf;
798 size_t buf_len;
7c616cba
TW
799};
800
b481de9c 801/* Sensitivity calib data */
f0832f13 802struct iwl_sensitivity_data {
b481de9c
ZY
803 u32 auto_corr_ofdm;
804 u32 auto_corr_ofdm_mrc;
805 u32 auto_corr_ofdm_x1;
806 u32 auto_corr_ofdm_mrc_x1;
807 u32 auto_corr_cck;
808 u32 auto_corr_cck_mrc;
809
810 u32 last_bad_plcp_cnt_ofdm;
811 u32 last_fa_cnt_ofdm;
812 u32 last_bad_plcp_cnt_cck;
813 u32 last_fa_cnt_cck;
814
815 u32 nrg_curr_state;
816 u32 nrg_prev_state;
817 u32 nrg_value[10];
818 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
819 u32 nrg_silence_ref;
820 u32 nrg_energy_idx;
821 u32 nrg_silence_idx;
822 u32 nrg_th_cck;
823 s32 nrg_auto_corr_silence_diff;
824 u32 num_in_cck_no_fa;
825 u32 nrg_th_ofdm;
55036d66
WYG
826
827 u16 barker_corr_th_min;
828 u16 barker_corr_th_min_mrc;
829 u16 nrg_th_cca;
b481de9c
ZY
830};
831
832/* Chain noise (differential Rx gain) calib data */
f0832f13 833struct iwl_chain_noise_data {
04816448 834 u32 active_chains;
b481de9c
ZY
835 u32 chain_noise_a;
836 u32 chain_noise_b;
837 u32 chain_noise_c;
838 u32 chain_signal_a;
839 u32 chain_signal_b;
840 u32 chain_signal_c;
04816448 841 u16 beacon_count;
b481de9c
ZY
842 u8 disconn_array[NUM_RX_CHAINS];
843 u8 delta_gain_code[NUM_RX_CHAINS];
844 u8 radio_write;
04816448 845 u8 state;
b481de9c
ZY
846};
847
abceddb4
BC
848#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
849#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 850
20594eb0
WYG
851#define IWL_TRAFFIC_ENTRIES (256)
852#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 853
5d08cd1d
CH
854enum {
855 MEASUREMENT_READY = (1 << 0),
856 MEASUREMENT_ACTIVE = (1 << 1),
857};
858
0848e297
WYG
859enum iwl_nvm_type {
860 NVM_DEVICE_TYPE_EEPROM = 0,
861 NVM_DEVICE_TYPE_OTP,
862};
863
415e4993
WYG
864/*
865 * Two types of OTP memory access modes
866 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
867 * based on physical memory addressing
868 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
869 * based on logical memory addressing
870 */
871enum iwl_access_mode {
872 IWL_OTP_ACCESS_ABSOLUTE,
873 IWL_OTP_ACCESS_RELATIVE,
874};
65b7998a
WYG
875
876/**
877 * enum iwl_pa_type - Power Amplifier type
878 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
879 * @IWL_PA_INTERNAL: use Internal only
880 */
881enum iwl_pa_type {
882 IWL_PA_SYSTEM = 0,
740e7f51 883 IWL_PA_INTERNAL = 1,
65b7998a
WYG
884};
885
a83b9141
WYG
886/* interrupt statistics */
887struct isr_statistics {
888 u32 hw;
889 u32 sw;
6e6ebf4b 890 u32 err_code;
a83b9141
WYG
891 u32 sch;
892 u32 alive;
893 u32 rfkill;
894 u32 ctkill;
895 u32 wakeup;
896 u32 rx;
897 u32 rx_handlers[REPLY_MAX];
898 u32 tx;
899 u32 unhandled;
900};
5d08cd1d 901
91835ba4
WYG
902/* reply_tx_statistics (for _agn devices) */
903struct reply_tx_error_statistics {
904 u32 pp_delay;
905 u32 pp_few_bytes;
906 u32 pp_bt_prio;
907 u32 pp_quiet_period;
908 u32 pp_calc_ttak;
909 u32 int_crossed_retry;
910 u32 short_limit;
911 u32 long_limit;
912 u32 fifo_underrun;
913 u32 drain_flow;
914 u32 rfkill_flush;
915 u32 life_expire;
916 u32 dest_ps;
917 u32 host_abort;
918 u32 bt_retry;
919 u32 sta_invalid;
920 u32 frag_drop;
921 u32 tid_disable;
922 u32 fifo_flush;
923 u32 insuff_cf_poll;
924 u32 fail_hw_drop;
925 u32 sta_color_mismatch;
926 u32 unknown;
927};
928
814665fe
WYG
929/* reply_agg_tx_statistics (for _agn devices) */
930struct reply_agg_tx_error_statistics {
931 u32 underrun;
932 u32 bt_prio;
933 u32 few_bytes;
934 u32 abort;
935 u32 last_sent_ttl;
936 u32 last_sent_try;
937 u32 last_sent_bt_kill;
938 u32 scd_query;
939 u32 bad_crc32;
940 u32 response;
941 u32 dump_tx;
942 u32 delay_tx;
943 u32 unknown;
944};
945
22fdf3c9
WYG
946/* management statistics */
947enum iwl_mgmt_stats {
948 MANAGEMENT_ASSOC_REQ = 0,
949 MANAGEMENT_ASSOC_RESP,
950 MANAGEMENT_REASSOC_REQ,
951 MANAGEMENT_REASSOC_RESP,
952 MANAGEMENT_PROBE_REQ,
953 MANAGEMENT_PROBE_RESP,
954 MANAGEMENT_BEACON,
955 MANAGEMENT_ATIM,
956 MANAGEMENT_DISASSOC,
957 MANAGEMENT_AUTH,
958 MANAGEMENT_DEAUTH,
959 MANAGEMENT_ACTION,
960 MANAGEMENT_MAX,
961};
962/* control statistics */
963enum iwl_ctrl_stats {
964 CONTROL_BACK_REQ = 0,
965 CONTROL_BACK,
966 CONTROL_PSPOLL,
967 CONTROL_RTS,
968 CONTROL_CTS,
969 CONTROL_ACK,
970 CONTROL_CFEND,
971 CONTROL_CFENDACK,
972 CONTROL_MAX,
973};
974
975struct traffic_stats {
5ed540ae 976#ifdef CONFIG_IWLWIFI_DEBUGFS
22fdf3c9
WYG
977 u32 mgmt[MANAGEMENT_MAX];
978 u32 ctrl[CONTROL_MAX];
979 u32 data_cnt;
980 u64 data_bytes;
22fdf3c9 981#endif
5ed540ae 982};
22fdf3c9 983
0924e519
WYG
984/*
985 * iwl_switch_rxon: "channel switch" structure
986 *
987 * @ switch_in_progress: channel switch in progress
988 * @ channel: new channel
989 */
990struct iwl_switch_rxon {
991 bool switch_in_progress;
992 __le16 channel;
993};
994
a9e1cb6a
WYG
995/*
996 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
997 * to perform continuous uCode event logging operation if enabled
998 */
999#define UCODE_TRACE_PERIOD (100)
1000
1001/*
1002 * iwl_event_log: current uCode event log position
1003 *
1004 * @ucode_trace: enable/disable ucode continuous trace timer
1005 * @num_wraps: how many times the event buffer wraps
1006 * @next_entry: the entry just before the next one that uCode would fill
1007 * @non_wraps_count: counter for no wrap detected when dump ucode events
1008 * @wraps_once_count: counter for wrap once detected when dump ucode events
1009 * @wraps_more_count: counter for wrap more than once detected
1010 * when dump ucode events
1011 */
1012struct iwl_event_log {
1013 bool ucode_trace;
1014 u32 num_wraps;
1015 u32 next_entry;
1016 int non_wraps_count;
1017 int wraps_once_count;
1018 int wraps_more_count;
1019};
1020
2be76703
WYG
1021/*
1022 * host interrupt timeout value
1023 * used with setting interrupt coalescing timer
1024 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1025 *
1026 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1027 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1028 */
1029#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1030#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1031#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1032#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1033#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1034#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1035
3e4fb5fa
TAN
1036/*
1037 * This is the threshold value of plcp error rate per 100mSecs. It is
1038 * used to set and check for the validity of plcp_delta.
1039 */
680788ac 1040#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1)
3e4fb5fa
TAN
1041#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1042#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1043#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa 1044#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
680788ac 1045#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0)
3e4fb5fa 1046
8a472da4
WYG
1047#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1048#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1049
22de94de
SG
1050/* TX queue watchdog timeouts in mSecs */
1051#define IWL_DEF_WD_TIMEOUT (2000)
1052#define IWL_LONG_WD_TIMEOUT (10000)
1053#define IWL_MAX_WD_TIMEOUT (120000)
b74e31a9 1054
bee008b7
WYG
1055/* BT Antenna Coupling Threshold (dB) */
1056#define IWL_BT_ANTENNA_COUPLING_THRESHOLD (35)
1057
491bc292
WYG
1058/* Firmware reload counter and Timestamp */
1059#define IWL_MIN_RELOAD_DURATION 1000 /* 1000 ms */
1060#define IWL_MAX_CONTINUE_RELOAD_CNT 4
1061
1062
a93e7973
WYG
1063enum iwl_reset {
1064 IWL_RF_RESET = 0,
1065 IWL_FW_RESET,
8a472da4
WYG
1066 IWL_MAX_FORCE_RESET,
1067};
1068
1069struct iwl_force_reset {
1070 int reset_request_count;
1071 int reset_success_count;
1072 int reset_reject_count;
1073 unsigned long reset_duration;
1074 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1075};
1076
a0ee74cf 1077/* extend beacon time format bit shifting */
a0ee74cf
WYG
1078/*
1079 * for _agn devices
1080 * bits 31:22 - extended
1081 * bits 21:0 - interval
1082 */
1083#define IWLAGN_EXT_BEACON_TIME_POS 22
1084
7194207c
JB
1085/**
1086 * struct iwl_notification_wait - notification wait entry
1087 * @list: list head for global list
1088 * @fn: function called with the notification
1089 * @cmd: command ID
1090 *
1091 * This structure is not used directly, to wait for a
1092 * notification declare it on the stack, and call
1093 * iwlagn_init_notification_wait() with appropriate
1094 * parameters. Then do whatever will cause the ucode
1095 * to notify the driver, and to wait for that then
1096 * call iwlagn_wait_notification().
1097 *
1098 * Each notification is one-shot. If at some point we
1099 * need to support multi-shot notifications (which
1100 * can't be allocated on the stack) we need to modify
1101 * the code for them.
1102 */
1103struct iwl_notification_wait {
1104 struct list_head list;
1105
09f18afe
JB
1106 void (*fn)(struct iwl_priv *priv, struct iwl_rx_packet *pkt,
1107 void *data);
1108 void *fn_data;
7194207c
JB
1109
1110 u8 cmd;
e74fe233 1111 bool triggered, aborted;
7194207c
JB
1112};
1113
246ed355
JB
1114enum iwl_rxon_context_id {
1115 IWL_RXON_CTX_BSS,
ece9c4ee 1116 IWL_RXON_CTX_PAN,
246ed355
JB
1117
1118 NUM_IWL_RXON_CTX
1119};
1120
1121struct iwl_rxon_context {
8bd413e6 1122 struct ieee80211_vif *vif;
e72f368b
JB
1123
1124 const u8 *ac_to_fifo;
1125 const u8 *ac_to_queue;
1126 u8 mcast_queue;
1127
763cc3bf
JB
1128 /*
1129 * We could use the vif to indicate active, but we
1130 * also need it to be active during disabling when
1131 * we already removed the vif for type setting.
1132 */
1133 bool always_active, is_active;
1134
2295c66b
JB
1135 bool ht_need_multiple_chains;
1136
246ed355 1137 enum iwl_rxon_context_id ctxid;
d0fe478c
JB
1138
1139 u32 interface_modes, exclusive_interface_modes;
1140 u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype;
1141
246ed355
JB
1142 /*
1143 * We declare this const so it can only be
1144 * changed via explicit cast within the
1145 * routines that actually update the physical
1146 * hardware.
1147 */
1148 const struct iwl_rxon_cmd active;
1149 struct iwl_rxon_cmd staging;
1150
1151 struct iwl_rxon_time_cmd timing;
a194e324 1152
8dfdb9d5
JB
1153 struct iwl_qos_info qos_data;
1154
2995bafa 1155 u8 bcast_sta_id, ap_sta_id;
8f2d3d2a
JB
1156
1157 u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd;
8dfdb9d5 1158 u8 qos_cmd;
c10afb6e
JB
1159 u8 wep_key_cmd;
1160
1161 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
1162 u8 key_mapping_keys;
770e13bd
JB
1163
1164 __le32 station_flags;
7e6a5886
JB
1165
1166 struct {
1167 bool non_gf_sta_present;
1168 u8 protection;
1169 bool enabled, is_40mhz;
1170 u8 extension_chan_offset;
1171 } ht;
68b99311
GT
1172
1173 bool last_tx_rejected;
246ed355
JB
1174};
1175
266af4c7
JB
1176enum iwl_scan_type {
1177 IWL_SCAN_NORMAL,
1178 IWL_SCAN_RADIO_RESET,
1179 IWL_SCAN_OFFCH_TX,
1180};
1181
7a4e5281
WYG
1182#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1183struct iwl_testmode_trace {
1184 u8 *cpu_addr;
1185 u8 *trace_addr;
1186 dma_addr_t dma_addr;
1187 bool trace_enabled;
1188};
1189#endif
c79dd5b5 1190struct iwl_priv {
5d08cd1d
CH
1191
1192 /* ieee device used by generic ieee processing code */
1193 struct ieee80211_hw *hw;
1194 struct ieee80211_channel *ieee_channels;
1195 struct ieee80211_rate *ieee_rates;
82b9a121 1196 struct iwl_cfg *cfg;
5d08cd1d 1197
8318d78a 1198 enum ieee80211_band band;
5d08cd1d 1199
4613e72d
CK
1200 void (*pre_rx_handler)(struct iwl_priv *priv,
1201 struct iwl_rx_mem_buffer *rxb);
c79dd5b5 1202 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1203 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1204
8318d78a 1205 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1206
5d08cd1d 1207 /* spectrum measurement report caching */
2aa6ab86 1208 struct iwl_spectrum_notification measure_report;
5d08cd1d 1209 u8 measurement_status;
81963d68 1210
5d08cd1d
CH
1211 /* ucode beacon time */
1212 u32 ucode_beacon_time;
a13d276f 1213 int missed_beacon_threshold;
5d08cd1d 1214
a85d7cca
JB
1215 /* track IBSS manager (last beacon) status */
1216 u32 ibss_manager;
1217
410f2bb3
SG
1218 /* jiffies when last recovery from statistics was performed */
1219 unsigned long rx_statistics_jiffies;
3e4fb5fa 1220
a93e7973 1221 /* force reset */
8a472da4 1222 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1223
491bc292
WYG
1224 /* firmware reload counter and timestamp */
1225 unsigned long reload_jiffies;
1226 int reload_count;
1227
5a2a780c 1228 /* we allocate array of iwl_channel_info for NIC's valid channels.
5d08cd1d 1229 * Access via channel # using indirect index array */
bf85ea4f 1230 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1231 u8 channel_count; /* # of channels */
1232
5d08cd1d
CH
1233 /* thermal calibration */
1234 s32 temperature; /* degrees Kelvin */
1235 s32 last_temperature;
1236
7c616cba 1237 /* init calibration results */
6e21f2c1 1238 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1239
5d08cd1d 1240 /* Scan related variables */
5d08cd1d 1241 unsigned long scan_start;
5d08cd1d 1242 unsigned long scan_start_tsf;
811ecc99 1243 void *scan_cmd;
00700ee0 1244 enum ieee80211_band scan_band;
1ecf9fc1 1245 struct cfg80211_scan_request *scan_request;
f84b29ec 1246 struct ieee80211_vif *scan_vif;
266af4c7 1247 enum iwl_scan_type scan_type;
76eff18b
TW
1248 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1249 u8 mgmt_tx_ant;
5d08cd1d
CH
1250
1251 /* spinlock */
1252 spinlock_t lock; /* protect general shared data */
1253 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1254 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d
CH
1255 struct mutex mutex;
1256
1257 /* basic pci-network driver stuff */
1258 struct pci_dev *pci_dev;
1259
1260 /* pci hardware address support */
1261 void __iomem *hw_base;
1262
246ed355
JB
1263 /* microcode/device supports multiple contexts */
1264 u8 valid_contexts;
1265
13bb9483
JB
1266 /* command queue number */
1267 u8 cmd_queue;
1268
c10afb6e
JB
1269 /* max number of station keys */
1270 u8 sta_key_max_num;
1271
d2690c0d
JB
1272 bool new_scan_threshold_behaviour;
1273
c6fa17ed
WYG
1274 /* EEPROM MAC addresses */
1275 struct mac_address addresses[2];
1276
5d08cd1d 1277 /* uCode images, save to reload in case of failure */
b08dfd04 1278 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1279 u32 ucode_ver; /* version of ucode, copy of
1280 iwl_ucode.ver */
dbf28e21
JB
1281 struct fw_img ucode_rt;
1282 struct fw_img ucode_init;
1283
ca7966c8 1284 enum iwlagn_ucode_subtype ucode_type;
dbb983b7 1285 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1286 char firmware_name[25];
5d08cd1d 1287
246ed355 1288 struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX];
5d08cd1d 1289
0924e519
WYG
1290 struct iwl_switch_rxon switch_rxon;
1291
d7d5783c
JB
1292 struct {
1293 u32 error_event_table;
1294 u32 log_event_table;
1295 } device_pointers;
5d08cd1d 1296
5d08cd1d 1297 u16 active_rate;
5d08cd1d 1298
5d08cd1d 1299 u8 start_calib;
f0832f13
EG
1300 struct iwl_sensitivity_data sensitivity_data;
1301 struct iwl_chain_noise_data chain_noise_data;
c8312fac 1302 bool enhance_sensitivity_table;
5d08cd1d 1303 __le16 sensitivity_tbl[HD_TABLE_SIZE];
c8312fac 1304 __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES];
5d08cd1d 1305
fad95bf5 1306 struct iwl_ht_config current_ht_config;
5d08cd1d 1307
5d08cd1d 1308 /* Rate scaling data */
5d08cd1d
CH
1309 u8 retry_rate;
1310
1311 wait_queue_head_t wait_command_queue;
1312
1313 int activity_timer_active;
1314
1315 /* Rx and Tx DMA processing queues */
a55360e4 1316 struct iwl_rx_queue rxq;
88804e2b 1317 struct iwl_tx_queue *txq;
5d08cd1d 1318 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1319 struct iwl_dma_ptr kw; /* keep warm address */
1320 struct iwl_dma_ptr scd_bc_tbls;
1321
5d08cd1d
CH
1322 u32 scd_base_addr; /* scheduler sram base address */
1323
1324 unsigned long status;
5d08cd1d 1325
19758bef 1326 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1327 struct traffic_stats tx_stats;
1328 struct traffic_stats rx_stats;
19758bef 1329
a83b9141
WYG
1330 /* counts interrupts */
1331 struct isr_statistics isr_stats;
1332
5da4b55f 1333 struct iwl_power_mgr power_data;
3ad3b92a 1334 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1335
9c5ac091
RC
1336 /* station table variables */
1337
1338 /* Note: if lock and sta_lock are needed, lock must be acquired first */
5d08cd1d
CH
1339 spinlock_t sta_lock;
1340 int num_stations;
3240cab3 1341 struct iwl_station_entry stations[IWLAGN_STATION_COUNT];
80fb47a1 1342 unsigned long ucode_key_table;
5d08cd1d 1343
e4e72fb4
JB
1344 /* queue refcounts */
1345#define IWL_MAX_HW_QUEUES 32
1346 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1347 /* for each AC */
1348 atomic_t queue_stop_count[4];
1349
5d08cd1d 1350 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1351 u8 is_open;
5d08cd1d
CH
1352
1353 u8 mac80211_registered;
5d08cd1d 1354
af6b8ee3 1355 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1356 u8 *eeprom;
0848e297 1357 int nvm_device_type;
073d3f5f 1358 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1359
05c914fe 1360 enum nl80211_iftype iw_mode;
5d08cd1d 1361
5d08cd1d 1362 /* Last Rx'd beacon timestamp */
3109ece1 1363 u64 timestamp;
5d08cd1d 1364
0da0e5bf
JB
1365 struct {
1366 __le32 flag;
1367 struct statistics_general_common common;
1368 struct statistics_rx_non_phy rx_non_phy;
1369 struct statistics_rx_phy rx_ofdm;
1370 struct statistics_rx_ht_phy rx_ofdm_ht;
1371 struct statistics_rx_phy rx_cck;
1372 struct statistics_tx tx;
1373#ifdef CONFIG_IWLWIFI_DEBUGFS
1374 struct statistics_bt_activity bt_activity;
1375 __le32 num_bt_kills, accum_num_bt_kills;
1376#endif
1377 } statistics;
1378#ifdef CONFIG_IWLWIFI_DEBUGFS
1379 struct {
1380 struct statistics_general_common common;
1381 struct statistics_rx_non_phy rx_non_phy;
1382 struct statistics_rx_phy rx_ofdm;
1383 struct statistics_rx_ht_phy rx_ofdm_ht;
1384 struct statistics_rx_phy rx_cck;
1385 struct statistics_tx tx;
1386 struct statistics_bt_activity bt_activity;
1387 } accum_stats, delta_stats, max_delta_stats;
1388#endif
1389
3240cab3
JB
1390 struct {
1391 /* INT ICT Table */
1392 __le32 *ict_tbl;
1393 void *ict_tbl_vir;
1394 dma_addr_t ict_tbl_dma;
1395 dma_addr_t aligned_ict_tbl_dma;
1396 int ict_index;
1397 u32 inta;
1398 bool use_ict;
1399 /*
1400 * reporting the number of tids has AGG on. 0 means
1401 * no AGGREGATION
1402 */
1403 u8 agg_tids_count;
1404
1405 struct iwl_rx_phy_res last_phy_res;
1406 bool last_phy_res_valid;
1407
1408 struct completion firmware_loading_complete;
1409
1410 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1411 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1412
1413 /*
1414 * chain noise reset and gain commands are the
1415 * two extra calibration commands follows the standard
1416 * phy calibration commands
1417 */
1418 u8 phy_calib_chain_noise_reset_cmd;
1419 u8 phy_calib_chain_noise_gain_cmd;
1420
3240cab3
JB
1421 /* counts reply_tx error */
1422 struct reply_tx_error_statistics reply_tx_stats;
1423 struct reply_agg_tx_error_statistics reply_agg_tx_stats;
3240cab3
JB
1424 /* notification wait support */
1425 struct list_head notif_waits;
1426 spinlock_t notif_wait_lock;
1427 wait_queue_head_t notif_waitq;
1428
1429 /* remain-on-channel offload support */
1430 struct ieee80211_channel *hw_roc_channel;
1431 struct delayed_work hw_roc_work;
1432 enum nl80211_channel_type hw_roc_chantype;
1433 int hw_roc_duration;
1434 bool hw_roc_setup;
1435
1436 struct sk_buff *offchan_tx_skb;
1437 int offchan_tx_timeout;
1438 struct ieee80211_channel *offchan_tx_chan;
1439 } _agn;
ee525d13 1440
22bf59a0 1441 /* bt coex */
f21dd005 1442 u8 bt_enable_flag;
da5dbb97 1443 u8 bt_status;
66e863a5 1444 u8 bt_traffic_load, last_bt_traffic_load;
f37837c9 1445 bool bt_ch_announce;
bee008b7
WYG
1446 bool bt_full_concurrent;
1447 bool bt_ant_couple_ok;
fbba9410
WYG
1448 __le32 kill_ack_mask;
1449 __le32 kill_cts_mask;
1450 __le16 bt_valid;
22bf59a0
WYG
1451 u16 bt_on_thresh;
1452 u16 bt_duration;
1453 u16 dynamic_frag_thresh;
bee008b7 1454 u8 bt_ci_compliance;
9e4afc21
JB
1455 struct work_struct bt_traffic_change_work;
1456
5425e490 1457 struct iwl_hw_params hw_params;
4ddbb7d0 1458
40cefda9 1459 u32 inta_mask;
5d08cd1d 1460
5d08cd1d
CH
1461 struct workqueue_struct *workqueue;
1462
5d08cd1d 1463 struct work_struct restart;
5d08cd1d
CH
1464 struct work_struct scan_completed;
1465 struct work_struct rx_replenish;
5d08cd1d 1466 struct work_struct abort_scan;
12e934dc 1467
5d08cd1d 1468 struct work_struct beacon_update;
76d04815 1469 struct iwl_rxon_context *beacon_ctx;
12e934dc 1470 struct sk_buff *beacon_skb;
4ce7cc2b 1471 void *beacon_cmd;
76d04815 1472
a28027cd
WYG
1473 struct work_struct tt_work;
1474 struct work_struct ct_enter;
1475 struct work_struct ct_exit;
88be0264 1476 struct work_struct start_internal_scan;
65550636 1477 struct work_struct tx_flush;
bee008b7 1478 struct work_struct bt_full_concurrency;
fbba9410 1479 struct work_struct bt_runtime_config;
5d08cd1d
CH
1480
1481 struct tasklet_struct irq_tasklet;
1482
5d08cd1d 1483 struct delayed_work scan_check;
4a8a4322 1484
630fe9b6
TW
1485 /* TX Power */
1486 s8 tx_power_user_lmt;
dc1b0973 1487 s8 tx_power_device_lmt;
ae16fc3c 1488 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
a25a66ac 1489 s8 tx_power_next;
5d08cd1d 1490
5d08cd1d 1491
d08853a3 1492#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1493 /* debugging info */
3d816c77
RC
1494 u32 debug_level; /* per device debugging will override global
1495 iwl_debug_level if set */
d73e4923 1496#endif /* CONFIG_IWLWIFI_DEBUG */
712b6cf5
TW
1497#ifdef CONFIG_IWLWIFI_DEBUGFS
1498 /* debugfs */
20594eb0
WYG
1499 u16 tx_traffic_idx;
1500 u16 rx_traffic_idx;
1501 u8 *tx_traffic;
1502 u8 *rx_traffic;
4c84a8f1
JB
1503 struct dentry *debugfs_dir;
1504 u32 dbgfs_sram_offset, dbgfs_sram_len;
d73e4923 1505 bool disable_ht40;
712b6cf5 1506#endif /* CONFIG_IWLWIFI_DEBUGFS */
5d08cd1d
CH
1507
1508 struct work_struct txpower_work;
445c2dff
TW
1509 u32 disable_sens_cal;
1510 u32 disable_chain_noise_cal;
16e727e8 1511 struct work_struct run_time_calib_work;
5d08cd1d 1512 struct timer_list statistics_periodic;
a9e1cb6a 1513 struct timer_list ucode_trace;
22de94de 1514 struct timer_list watchdog;
a9e1cb6a
WYG
1515
1516 struct iwl_event_log event_log;
5ed540ae
WYG
1517
1518 struct led_classdev led;
1519 unsigned long blink_on, blink_off;
1520 bool led_registered;
7a4e5281
WYG
1521#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1522 struct iwl_testmode_trace testmode_trace;
1523#endif
c79dd5b5 1524}; /*iwl_priv */
5d08cd1d 1525
36470749
RR
1526static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1527{
1528 set_bit(txq_id, &priv->txq_ctx_active_msk);
1529}
1530
1531static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1532{
1533 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1534}
1535
994d31f7 1536#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77
RC
1537/*
1538 * iwl_get_debug_level: Return active debug level for device
1539 *
1540 * Using sysfs it is possible to set per device debug level. This debug
1541 * level will be used if set, otherwise the global debug level which can be
1542 * set via module parameter is used.
1543 */
1544static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1545{
1546 if (priv->debug_level)
1547 return priv->debug_level;
1548 else
1549 return iwl_debug_level;
1550}
a332f8d6 1551#else
3d816c77
RC
1552static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1553{
1554 return iwl_debug_level;
1555}
a332f8d6
TW
1556#endif
1557
1558
a332f8d6
TW
1559static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1560 int txq_id, int idx)
1561{
ff0d91c3 1562 if (priv->txq[txq_id].txb[idx].skb)
a332f8d6 1563 return (struct ieee80211_hdr *)priv->txq[txq_id].
ff0d91c3 1564 txb[idx].skb->data;
a332f8d6
TW
1565 return NULL;
1566}
a332f8d6 1567
246ed355
JB
1568static inline struct iwl_rxon_context *
1569iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1570{
1571 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1572
1573 return vif_priv->ctx;
1574}
1575
1576#define for_each_context(priv, ctx) \
1577 for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \
1578 ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \
1579 if (priv->valid_contexts & BIT(ctx->ctxid))
1580
054ec924 1581static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx)
246ed355 1582{
054ec924 1583 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
246ed355
JB
1584}
1585
054ec924
JB
1586static inline int iwl_is_associated(struct iwl_priv *priv,
1587 enum iwl_rxon_context_id ctxid)
246ed355 1588{
054ec924 1589 return iwl_is_associated_ctx(&priv->contexts[ctxid]);
246ed355 1590}
a332f8d6 1591
054ec924 1592static inline int iwl_is_any_associated(struct iwl_priv *priv)
5d08cd1d 1593{
054ec924
JB
1594 struct iwl_rxon_context *ctx;
1595 for_each_context(priv, ctx)
1596 if (iwl_is_associated_ctx(ctx))
1597 return true;
1598 return false;
5d08cd1d
CH
1599}
1600
bf85ea4f 1601static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1602{
1603 if (ch_info == NULL)
1604 return 0;
1605 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1606}
1607
bf85ea4f 1608static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1609{
1610 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1611}
1612
bf85ea4f 1613static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1614{
8318d78a 1615 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1616}
1617
bf85ea4f 1618static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1619{
8318d78a 1620 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1621}
1622
bf85ea4f 1623static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1624{
1625 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1626}
1627
bf85ea4f 1628static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1629{
1630 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1631}
1632
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1633static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1634{
1635 __free_pages(page, priv->hw_params.rx_page_order);
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1636}
1637
1638static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1639{
1640 free_pages(page, priv->hw_params.rx_page_order);
64a76b50 1641}
be1f3ab6 1642#endif /* __iwl_dev_h__ */
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