]> Git Repo - linux.git/blame - drivers/net/wireless/iwlwifi/iwl-dev.h
wireless: rt2x00: rt{2500,73}usb.c fix duplicate ids
[linux.git] / drivers / net / wireless / iwlwifi / iwl-dev.h
CommitLineData
b481de9c
ZY
1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <[email protected]>
b481de9c
ZY
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
fcd427bb 26/*
3e0d4cb1 27 * Please use this file (iwl-dev.h) for driver implementation definitions.
5a36ba0e 28 * Please use iwl-commands.h for uCode API definitions.
fcd427bb
BC
29 * Please use iwl-4965-hw.h for hardware-related definitions.
30 */
31
be1f3ab6
EG
32#ifndef __iwl_dev_h__
33#define __iwl_dev_h__
b481de9c 34
5d08cd1d
CH
35#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h>
7194207c 37#include <linux/wait.h>
5ed540ae 38#include <linux/leds.h>
5d08cd1d
CH
39#include <net/ieee80211_radiotap.h>
40
6bc913bd 41#include "iwl-eeprom.h"
6f83eaa1 42#include "iwl-csr.h"
5d08cd1d 43#include "iwl-prph.h"
dbb6654c 44#include "iwl-fh.h"
0a6857e7 45#include "iwl-debug.h"
b744cb79 46#include "iwl-agn-hw.h"
ab53d8af 47#include "iwl-led.h"
5da4b55f 48#include "iwl-power.h"
e227ceac 49#include "iwl-agn-rs.h"
0975cc8f 50#include "iwl-agn-tt.h"
5d08cd1d 51
be663ab6
WYG
52#define U32_PAD(n) ((4-(n))&0x3)
53
672639de
WYG
54struct iwl_tx_queue;
55
099b40b7 56/* CT-KILL constants */
672639de
WYG
57#define CT_KILL_THRESHOLD_LEGACY 110 /* in Celsius */
58#define CT_KILL_THRESHOLD 114 /* in Celsius */
59#define CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
4bf775cd 60
5d08cd1d
CH
61/* Default noise level to report when noise measurement is not available.
62 * This may be because we're:
63 * 1) Not associated (4965, no beacon statistics being sent to driver)
64 * 2) Scanning (noise measurement does not apply to associated channel)
65 * 3) Receiving CCK (3945 delivers noise info only for OFDM frames)
66 * Use default noise value of -127 ... this is below the range of measurable
67 * Rx dBm for either 3945 or 4965, so it can indicate "unmeasurable" to user.
68 * Also, -127 works better than 0 when averaging frames with/without
69 * noise info (e.g. averaging might be done in app); measured dBm values are
70 * always negative ... using a negative value as the default keeps all
71 * averages within an s8's (used in some apps) range of negative values. */
72#define IWL_NOISE_MEAS_NOT_AVAILABLE (-127)
73
5d08cd1d
CH
74/*
75 * RTS threshold here is total size [2347] minus 4 FCS bytes
76 * Per spec:
77 * a value of 0 means RTS on all data/management packets
78 * a value > max MSDU size means no RTS
79 * else RTS for data/management frames where MPDU is larger
80 * than RTS value.
81 */
82#define DEFAULT_RTS_THRESHOLD 2347U
83#define MIN_RTS_THRESHOLD 0U
84#define MAX_RTS_THRESHOLD 2347U
85#define MAX_MSDU_SIZE 2304U
86#define MAX_MPDU_SIZE 2346U
87#define DEFAULT_BEACON_INTERVAL 100U
88#define DEFAULT_SHORT_RETRY_LIMIT 7U
89#define DEFAULT_LONG_RETRY_LIMIT 4U
90
a55360e4 91struct iwl_rx_mem_buffer {
2f301227
ZY
92 dma_addr_t page_dma;
93 struct page *page;
5d08cd1d
CH
94 struct list_head list;
95};
96
2f301227
ZY
97#define rxb_addr(r) page_address(r->page)
98
c2acea8e
JB
99/* defined below */
100struct iwl_device_cmd;
101
102struct iwl_cmd_meta {
103 /* only for SYNC commands, iff the reply skb is wanted */
104 struct iwl_host_cmd *source;
105 /*
106 * only for ASYNC commands
107 * (which is somewhat stupid -- look at iwl-sta.c for instance
108 * which duplicates a bunch of code because the callback isn't
109 * invoked for SYNC commands, if it were and its result passed
110 * through it would be simpler...)
111 */
5696aea6
JB
112 void (*callback)(struct iwl_priv *priv,
113 struct iwl_device_cmd *cmd,
2f301227 114 struct iwl_rx_packet *pkt);
c2acea8e
JB
115
116 /* The CMD_SIZE_HUGE flag bit indicates that the command
117 * structure is stored at the end of the shared queue memory. */
118 u32 flags;
119
2e724443
FT
120 DEFINE_DMA_UNMAP_ADDR(mapping);
121 DEFINE_DMA_UNMAP_LEN(len);
c2acea8e
JB
122};
123
5d08cd1d
CH
124/*
125 * Generic queue structure
126 *
127 * Contains common data for Rx and Tx queues
128 */
443cfd45 129struct iwl_queue {
5d08cd1d
CH
130 int n_bd; /* number of BDs in this queue */
131 int write_ptr; /* 1-st empty entry (index) host_w*/
132 int read_ptr; /* last used entry (index) host_r*/
b74e31a9 133 /* use for monitoring and recovering the stuck queue */
5d08cd1d
CH
134 dma_addr_t dma_addr; /* physical addr for BD's */
135 int n_window; /* safe queue window */
136 u32 id;
137 int low_mark; /* low watermark, resume queue if free
138 * space more than this */
139 int high_mark; /* high watermark, stop queue if free
140 * space less than this */
a839cf69 141};
5d08cd1d 142
bc47279f 143/* One for each TFD */
8567c63e 144struct iwl_tx_info {
ff0d91c3 145 struct sk_buff *skb;
c90cbbbd 146 struct iwl_rxon_context *ctx;
5d08cd1d
CH
147};
148
149/**
16466903 150 * struct iwl_tx_queue - Tx Queue for DMA
bc47279f
BC
151 * @q: generic Rx/Tx queue descriptor
152 * @bd: base of circular buffer of TFDs
c2acea8e
JB
153 * @cmd: array of command/TX buffer pointers
154 * @meta: array of meta data for each command/tx buffer
bc47279f
BC
155 * @dma_addr_cmd: physical address of cmd/tx buffer array
156 * @txb: array of per-TFD driver data
22de94de 157 * @time_stamp: time (in jiffies) of last read_ptr change
bc47279f
BC
158 * @need_update: indicates need to update read/write index
159 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
5d08cd1d 160 *
bc47279f
BC
161 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
162 * descriptors) and required locking structures.
5d08cd1d 163 */
188cf6c7
SO
164#define TFD_TX_CMD_SLOTS 256
165#define TFD_CMD_SLOTS 32
166
16466903 167struct iwl_tx_queue {
443cfd45 168 struct iwl_queue q;
59606ffa 169 void *tfds;
c2acea8e
JB
170 struct iwl_device_cmd **cmd;
171 struct iwl_cmd_meta *meta;
8567c63e 172 struct iwl_tx_info *txb;
22de94de 173 unsigned long time_stamp;
3fd07a1e
TW
174 u8 need_update;
175 u8 sched_retry;
176 u8 active;
177 u8 swq_id;
5d08cd1d
CH
178};
179
180#define IWL_NUM_SCAN_RATES (2)
181
bb8c093b 182struct iwl4965_channel_tgd_info {
5d08cd1d
CH
183 u8 type;
184 s8 max_power;
185};
186
bb8c093b 187struct iwl4965_channel_tgh_info {
5d08cd1d
CH
188 s64 last_radar_time;
189};
190
d20b3c65
SO
191#define IWL4965_MAX_RATE (33)
192
85d41495
KA
193struct iwl3945_clip_group {
194 /* maximum power level to prevent clipping for each rate, derived by
195 * us from this band's saturation power in EEPROM */
196 const s8 clip_powers[IWL_MAX_RATES];
197};
198
d20b3c65
SO
199/* current Tx power values to use, one for each rate for each channel.
200 * requested power is limited by:
201 * -- regulatory EEPROM limits for this channel
202 * -- hardware capabilities (clip-powers)
203 * -- spectrum management
204 * -- user preference (e.g. iwconfig)
205 * when requested power is set, base power index must also be set. */
206struct iwl3945_channel_power_info {
207 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
208 s8 power_table_index; /* actual (compenst'd) index into gain table */
209 s8 base_power_index; /* gain index for power at factory temp. */
210 s8 requested_power; /* power (dBm) requested for this chnl/rate */
211};
212
213/* current scan Tx power values to use, one for each scan rate for each
214 * channel. */
215struct iwl3945_scan_power_info {
216 struct iwl3945_tx_power tpc; /* actual radio and DSP gain settings */
217 s8 power_table_index; /* actual (compenst'd) index into gain table */
218 s8 requested_power; /* scan pwr (dBm) requested for chnl/rate */
219};
220
5d08cd1d
CH
221/*
222 * One for each channel, holds all channel setup data
223 * Some of the fields (e.g. eeprom and flags/max_power_avg) are redundant
224 * with one another!
225 */
bf85ea4f 226struct iwl_channel_info {
bb8c093b
CH
227 struct iwl4965_channel_tgd_info tgd;
228 struct iwl4965_channel_tgh_info tgh;
073d3f5f 229 struct iwl_eeprom_channel eeprom; /* EEPROM regulatory limit */
7aafef1c
WYG
230 struct iwl_eeprom_channel ht40_eeprom; /* EEPROM regulatory limit for
231 * HT40 channel */
5d08cd1d
CH
232
233 u8 channel; /* channel number */
234 u8 flags; /* flags copied from EEPROM */
235 s8 max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
fcd427bb 236 s8 curr_txpow; /* (dBm) regulatory/spectrum/user (not h/w) limit */
5d08cd1d
CH
237 s8 min_power; /* always 0 */
238 s8 scan_power; /* (dBm) regul. eeprom, direct scans, any rate */
239
240 u8 group_index; /* 0-4, maps channel to group1/2/3/4/5 */
241 u8 band_index; /* 0-4, maps channel to band1/2/3/4/5 */
8318d78a 242 enum ieee80211_band band;
5d08cd1d 243
7aafef1c
WYG
244 /* HT40 channel info */
245 s8 ht40_max_power_avg; /* (dBm) regul. eeprom, normal Tx, any rate */
7aafef1c
WYG
246 u8 ht40_flags; /* flags copied from EEPROM */
247 u8 ht40_extension_channel; /* HT_IE_EXT_CHANNEL_* */
d20b3c65
SO
248
249 /* Radio/DSP gain settings for each "normal" data Tx rate.
250 * These include, in addition to RF and DSP gain, a few fields for
251 * remembering/modifying gain settings (indexes). */
252 struct iwl3945_channel_power_info power_info[IWL4965_MAX_RATE];
253
254 /* Radio/DSP gain settings for each scan rate, for directed scans. */
255 struct iwl3945_scan_power_info scan_pwr_info[IWL_NUM_SCAN_RATES];
5d08cd1d
CH
256};
257
751ca305 258#define IWL_TX_FIFO_BK 0 /* shared */
edc1a3a0 259#define IWL_TX_FIFO_BE 1
751ca305 260#define IWL_TX_FIFO_VI 2 /* shared */
edc1a3a0 261#define IWL_TX_FIFO_VO 3
751ca305
JB
262#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
263#define IWL_TX_FIFO_BE_IPAN 4
264#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
265#define IWL_TX_FIFO_VO_IPAN 5
edc1a3a0 266#define IWL_TX_FIFO_UNUSED -1
5d08cd1d 267
01a7e084
RC
268/* Minimum number of queues. MAX_NUM is defined in hw specific files.
269 * Set the minimum to accommodate the 4 standard TX queues, 1 command
270 * queue, 2 (unused) HCCA queues, and 4 HT queues (one for each AC) */
271#define IWL_MIN_NUM_QUEUES 10
5d08cd1d 272
bd35f150 273/*
13bb9483 274 * Command queue depends on iPAN support.
bd35f150 275 */
13bb9483
JB
276#define IWL_DEFAULT_CMD_QUEUE_NUM 4
277#define IWL_IPAN_CMD_QUEUE_NUM 9
bd35f150 278
751ca305
JB
279/*
280 * This queue number is required for proper operation
281 * because the ucode will stop/start the scheduler as
282 * required.
283 */
284#define IWL_IPAN_MCAST_QUEUE 8
285
5d08cd1d
CH
286#define IEEE80211_DATA_LEN 2304
287#define IEEE80211_4ADDR_LEN 30
288#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
289#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
290
fcab423d 291struct iwl_frame {
5d08cd1d
CH
292 union {
293 struct ieee80211_hdr frame;
4bf64efd 294 struct iwl_tx_beacon_cmd beacon;
5d08cd1d
CH
295 u8 raw[IEEE80211_FRAME_LEN];
296 u8 cmd[360];
297 } u;
298 struct list_head list;
299};
300
5d08cd1d
CH
301#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
302#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
303#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
304
305enum {
c587de0b
TW
306 CMD_SYNC = 0,
307 CMD_SIZE_NORMAL = 0,
308 CMD_NO_SKB = 0,
5d08cd1d 309 CMD_SIZE_HUGE = (1 << 0),
5d08cd1d 310 CMD_ASYNC = (1 << 1),
5d08cd1d
CH
311 CMD_WANT_SKB = (1 << 2),
312};
313
c8c24872 314#define DEF_CMD_PAYLOAD_SIZE 320
bd68fb6f 315
bc47279f 316/**
c2acea8e 317 * struct iwl_device_cmd
bc47279f
BC
318 *
319 * For allocation of the command and tx queues, this establishes the overall
320 * size of the largest command we send to uCode, except for a scan command
321 * (which is relatively huge; space is allocated separately).
322 */
c2acea8e 323struct iwl_device_cmd {
857485c0 324 struct iwl_cmd_header hdr; /* uCode API */
5d08cd1d 325 union {
5d08cd1d
CH
326 u32 flags;
327 u8 val8;
328 u16 val16;
329 u32 val32;
83d527d9 330 struct iwl_tx_cmd tx;
c8c24872
WYG
331 struct iwl6000_channel_switch_cmd chswitch;
332 u8 payload[DEF_CMD_PAYLOAD_SIZE];
ba2d3587
ED
333 } __packed cmd;
334} __packed;
5d08cd1d 335
c2acea8e
JB
336#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd))
337
3257e5d4 338
857485c0 339struct iwl_host_cmd {
5d08cd1d 340 const void *data;
2f301227 341 unsigned long reply_page;
5696aea6
JB
342 void (*callback)(struct iwl_priv *priv,
343 struct iwl_device_cmd *cmd,
2f301227 344 struct iwl_rx_packet *pkt);
c2acea8e
JB
345 u32 flags;
346 u16 len;
347 u8 id;
5d08cd1d
CH
348};
349
5d08cd1d
CH
350#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
351#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
352#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
353
354/**
a55360e4 355 * struct iwl_rx_queue - Rx queue
df833b1d 356 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
d5b25c90 357 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
5d08cd1d
CH
358 * @read: Shared index to newest available Rx buffer
359 * @write: Shared index to oldest written Rx packet
360 * @free_count: Number of pre-allocated buffers in rx_free
361 * @rx_free: list of free SKBs for use
362 * @rx_used: List of Rx buffers with no SKB
363 * @need_update: flag to indicate we need to update read/write index
df833b1d
RC
364 * @rb_stts: driver's pointer to receive buffer status
365 * @rb_stts_dma: bus address of receive buffer status
5d08cd1d 366 *
a55360e4 367 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
5d08cd1d 368 */
a55360e4 369struct iwl_rx_queue {
5d08cd1d 370 __le32 *bd;
d5b25c90 371 dma_addr_t bd_dma;
a55360e4
TW
372 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
373 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
5d08cd1d
CH
374 u32 read;
375 u32 write;
376 u32 free_count;
4752c93c 377 u32 write_actual;
5d08cd1d
CH
378 struct list_head rx_free;
379 struct list_head rx_used;
380 int need_update;
8d86422a
WT
381 struct iwl_rb_status *rb_stts;
382 dma_addr_t rb_stts_dma;
5d08cd1d
CH
383 spinlock_t lock;
384};
385
386#define IWL_SUPPORTED_RATES_IE_LEN 8
387
5d08cd1d
CH
388#define MAX_TID_COUNT 9
389
390#define IWL_INVALID_RATE 0xFF
391#define IWL_INVALID_VALUE -1
392
bc47279f 393/**
6def9761 394 * struct iwl_ht_agg -- aggregation status while waiting for block-ack
bc47279f
BC
395 * @txq_id: Tx queue used for Tx attempt
396 * @frame_count: # frames attempted by Tx command
397 * @wait_for_ba: Expect block-ack before next Tx reply
398 * @start_idx: Index of 1st Transmit Frame Descriptor (TFD) in Tx window
399 * @bitmap0: Low order bitmap, one bit for each frame pending ACK in Tx window
400 * @bitmap1: High order, one bit for each frame pending ACK in Tx window
401 * @rate_n_flags: Rate at which Tx was attempted
402 *
403 * If REPLY_TX indicates that aggregation was attempted, driver must wait
404 * for block ack (REPLY_COMPRESSED_BA). This struct stores tx reply info
405 * until block ack arrives.
406 */
6def9761 407struct iwl_ht_agg {
5d08cd1d
CH
408 u16 txq_id;
409 u16 frame_count;
410 u16 wait_for_ba;
411 u16 start_idx;
fe01b477 412 u64 bitmap;
5d08cd1d 413 u32 rate_n_flags;
fe01b477
RR
414#define IWL_AGG_OFF 0
415#define IWL_AGG_ON 1
416#define IWL_EMPTYING_HW_QUEUE_ADDBA 2
417#define IWL_EMPTYING_HW_QUEUE_DELBA 3
418 u8 state;
c8823ec1 419 u8 tx_fifo;
5d08cd1d 420};
fe01b477 421
5d08cd1d 422
6def9761 423struct iwl_tid_data {
f862a236 424 u16 seq_number; /* agn only */
fe01b477 425 u16 tfds_in_queue;
6def9761 426 struct iwl_ht_agg agg;
5d08cd1d
CH
427};
428
6def9761 429struct iwl_hw_key {
97359d12 430 u32 cipher;
5d08cd1d 431 int keylen;
0211ddda 432 u8 keyidx;
5d08cd1d
CH
433 u8 key[32];
434};
435
a78fe754 436union iwl_ht_rate_supp {
5d08cd1d
CH
437 u16 rates;
438 struct {
439 u8 siso_rate;
440 u8 mimo_rate;
441 };
442};
443
172c1d11
WYG
444#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
445#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
446#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
447#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
448#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
449#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
450#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
bcc693a1
WYG
451
452/*
453 * Maximal MPDU density for TX aggregation
454 * 4 - 2us density
455 * 5 - 4us density
456 * 6 - 8us density
457 * 7 - 16us density
458 */
172c1d11 459#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
bcc693a1 460#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
172c1d11
WYG
461#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
462#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
bcc693a1 463#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
172c1d11
WYG
464#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
465#define CFG_HT_MPDU_DENSITY_MIN (0x1)
5d08cd1d 466
fad95bf5 467struct iwl_ht_config {
02bb1bea 468 bool single_chain_sufficient;
ba37a3d0 469 enum ieee80211_smps_mode smps; /* current smps mode */
5d08cd1d 470};
5d08cd1d 471
5d08cd1d 472/* QoS structures */
1ff50bda 473struct iwl_qos_info {
5d08cd1d 474 int qos_active;
1ff50bda 475 struct iwl_qosparam_cmd def_qos_parm;
5d08cd1d 476};
5d08cd1d 477
fe6b23dd
RC
478/*
479 * Structure should be accessed with sta_lock held. When station addition
480 * is in progress (IWL_STA_UCODE_INPROGRESS) it is possible to access only
481 * the commands (iwl_addsta_cmd and iwl_link_quality_cmd) without sta_lock
482 * held.
483 */
6def9761 484struct iwl_station_entry {
133636de 485 struct iwl_addsta_cmd sta;
6def9761 486 struct iwl_tid_data tid[MAX_TID_COUNT];
dcef732c 487 u8 used, ctxid;
6def9761 488 struct iwl_hw_key keyinfo;
fe6b23dd 489 struct iwl_link_quality_cmd *lq;
5d08cd1d
CH
490};
491
fd1af15d 492struct iwl_station_priv_common {
238d781d 493 struct iwl_rxon_context *ctx;
fd1af15d
JB
494 u8 sta_id;
495};
496
8d9698b3
RC
497/*
498 * iwl_station_priv: Driver's private station information
499 *
500 * When mac80211 creates a station it reserves some space (hw->sta_data_size)
501 * in the structure for use by driver. This structure is places in that
502 * space.
fd1af15d
JB
503 *
504 * The common struct MUST be first because it is shared between
505 * 3945 and agn!
8d9698b3
RC
506 */
507struct iwl_station_priv {
fd1af15d 508 struct iwl_station_priv_common common;
8d9698b3 509 struct iwl_lq_sta lq_sta;
6ab10ff8
JB
510 atomic_t pending_frames;
511 bool client;
512 bool asleep;
7b090687 513 u8 max_agg_bufsize;
8d9698b3
RC
514};
515
fd1af15d
JB
516/**
517 * struct iwl_vif_priv - driver's private per-interface information
518 *
519 * When mac80211 allocates a virtual interface, it can allocate
520 * space for us to put data into.
521 */
522struct iwl_vif_priv {
246ed355 523 struct iwl_rxon_context *ctx;
fd1af15d
JB
524 u8 ibss_bssid_sta_id;
525};
526
5d08cd1d
CH
527/* one for each uCode image (inst/data, boot/init/runtime) */
528struct fw_desc {
529 void *v_addr; /* access by driver */
530 dma_addr_t p_addr; /* access by card's busmaster DMA */
531 u32 len; /* bytes */
532};
533
dd7a2509 534/* v1/v2 uCode file layout */
cc0f555d
JS
535struct iwl_ucode_header {
536 __le32 ver; /* major/minor/API/serial */
537 union {
538 struct {
539 __le32 inst_size; /* bytes of runtime code */
540 __le32 data_size; /* bytes of runtime data */
541 __le32 init_size; /* bytes of init code */
542 __le32 init_data_size; /* bytes of init data */
543 __le32 boot_size; /* bytes of bootstrap code */
544 u8 data[0]; /* in same order as sizes */
545 } v1;
546 struct {
547 __le32 build; /* build number */
548 __le32 inst_size; /* bytes of runtime code */
549 __le32 data_size; /* bytes of runtime data */
550 __le32 init_size; /* bytes of init code */
551 __le32 init_data_size; /* bytes of init data */
552 __le32 boot_size; /* bytes of bootstrap code */
553 u8 data[0]; /* in same order as sizes */
554 } v2;
555 } u;
5d08cd1d
CH
556};
557
dd7a2509
JB
558/*
559 * new TLV uCode file layout
560 *
561 * The new TLV file format contains TLVs, that each specify
562 * some piece of data. To facilitate "groups", for example
563 * different instruction image with different capabilities,
564 * bundled with the same init image, an alternative mechanism
565 * is provided:
566 * When the alternative field is 0, that means that the item
567 * is always valid. When it is non-zero, then it is only
568 * valid in conjunction with items of the same alternative,
569 * in which case the driver (user) selects one alternative
570 * to use.
571 */
572
573enum iwl_ucode_tlv_type {
574 IWL_UCODE_TLV_INVALID = 0, /* unused */
575 IWL_UCODE_TLV_INST = 1,
576 IWL_UCODE_TLV_DATA = 2,
577 IWL_UCODE_TLV_INIT = 3,
578 IWL_UCODE_TLV_INIT_DATA = 4,
579 IWL_UCODE_TLV_BOOT = 5,
580 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
ece9c4ee 581 IWL_UCODE_TLV_PAN = 7,
b2e640d4
JB
582 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
583 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
584 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
585 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
586 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
587 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
c8312fac 588 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
6a822d06 589 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
dd7a2509
JB
590};
591
592struct iwl_ucode_tlv {
593 __le16 type; /* see above */
594 __le16 alternative; /* see comment */
595 __le32 length; /* not including type/length fields */
596 u8 data[0];
ba2d3587 597} __packed;
dd7a2509
JB
598
599#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
600
601struct iwl_tlv_ucode_header {
602 /*
603 * The TLV style ucode header is distinguished from
604 * the v1/v2 style header by first four bytes being
605 * zero, as such is an invalid combination of
606 * major/minor/API/serial versions.
607 */
608 __le32 zero;
609 __le32 magic;
610 u8 human_readable[64];
611 __le32 ver; /* major/minor/API/serial */
612 __le32 build;
613 __le64 alternatives; /* bitmask of valid alternatives */
614 /*
615 * The data contained herein has a TLV layout,
616 * see above for the TLV header and types.
617 * Note that each TLV is padded to a length
618 * that is a multiple of 4 for alignment.
619 */
620 u8 data[0];
621};
622
bb8c093b 623struct iwl4965_ibss_seq {
5d08cd1d
CH
624 u8 mac[ETH_ALEN];
625 u16 seq_num;
626 u16 frag_num;
627 unsigned long packet_time;
628 struct list_head list;
629};
630
f0832f13
EG
631struct iwl_sensitivity_ranges {
632 u16 min_nrg_cck;
633 u16 max_nrg_cck;
634
635 u16 nrg_th_cck;
636 u16 nrg_th_ofdm;
637
638 u16 auto_corr_min_ofdm;
639 u16 auto_corr_min_ofdm_mrc;
640 u16 auto_corr_min_ofdm_x1;
641 u16 auto_corr_min_ofdm_mrc_x1;
642
643 u16 auto_corr_max_ofdm;
644 u16 auto_corr_max_ofdm_mrc;
645 u16 auto_corr_max_ofdm_x1;
646 u16 auto_corr_max_ofdm_mrc_x1;
647
648 u16 auto_corr_max_cck;
649 u16 auto_corr_max_cck_mrc;
650 u16 auto_corr_min_cck;
651 u16 auto_corr_min_cck_mrc;
55036d66
WYG
652
653 u16 barker_corr_th_min;
654 u16 barker_corr_th_min_mrc;
655 u16 nrg_th_cca;
f0832f13
EG
656};
657
099b40b7 658
b5047f78
TW
659#define KELVIN_TO_CELSIUS(x) ((x)-273)
660#define CELSIUS_TO_KELVIN(x) ((x)+273)
661
662
bc47279f 663/**
5425e490 664 * struct iwl_hw_params
bc47279f 665 * @max_txq_num: Max # Tx queues supported
f3f911d1 666 * @dma_chnl_num: Number of Tx DMA/FIFO channels
4ddbb7d0 667 * @scd_bc_tbls_size: size of scheduler byte count tables
a8e74e27 668 * @tfd_size: TFD size
099b40b7
RR
669 * @tx/rx_chains_num: Number of TX/RX chains
670 * @valid_tx/rx_ant: usable antennas
bc47279f 671 * @max_rxq_size: Max # Rx frames in Rx queue (must be power-of-2)
bc47279f 672 * @max_rxq_log: Log-base-2 of max_rxq_size
2f301227 673 * @rx_page_order: Rx buffer page order
141c43a3 674 * @rx_wrt_ptr_reg: FH{39}_RSCSR_CHNL0_WPTR
bc47279f 675 * @max_stations:
7aafef1c 676 * @ht40_channel: is 40MHz width possible in band 2.4
099b40b7
RR
677 * BIT(IEEE80211_BAND_5GHZ) BIT(IEEE80211_BAND_5GHZ)
678 * @sw_crypto: 0 for hw, 1 for sw
679 * @max_xxx_size: for ucode uses
680 * @ct_kill_threshold: temperature threshold
a0ee74cf 681 * @beacon_time_tsf_bits: number of valid tsf bits for beacon time
a96a27f9 682 * @calib_init_cfg: setup initial calibrations for the hw
6d6a1afd 683 * @calib_rt_cfg: setup runtime calibrations for the hw
f0832f13 684 * @struct iwl_sensitivity_ranges: range of sensitivity values
bc47279f 685 */
5425e490 686struct iwl_hw_params {
f3f911d1
ZY
687 u8 max_txq_num;
688 u8 dma_chnl_num;
4ddbb7d0 689 u16 scd_bc_tbls_size;
a8e74e27 690 u32 tfd_size;
ec35cf2a
TW
691 u8 tx_chains_num;
692 u8 rx_chains_num;
693 u8 valid_tx_ant;
694 u8 valid_rx_ant;
5d08cd1d 695 u16 max_rxq_size;
ec35cf2a 696 u16 max_rxq_log;
2f301227 697 u32 rx_page_order;
141c43a3 698 u32 rx_wrt_ptr_reg;
5d08cd1d 699 u8 max_stations;
7aafef1c 700 u8 ht40_channel;
2c2f3b33 701 u8 max_beacon_itrvl; /* in 1024 ms */
099b40b7
RR
702 u32 max_inst_size;
703 u32 max_data_size;
704 u32 max_bsm_size;
705 u32 ct_kill_threshold; /* value in hw-dependent units */
672639de
WYG
706 u32 ct_kill_exit_threshold; /* value in hw-dependent units */
707 /* for 1000, 6000 series and up */
a0ee74cf 708 u16 beacon_time_tsf_bits;
be5d56ed 709 u32 calib_init_cfg;
6d6a1afd 710 u32 calib_rt_cfg;
f0832f13 711 const struct iwl_sensitivity_ranges *sens;
5d08cd1d
CH
712};
713
5d08cd1d 714
5d08cd1d
CH
715/******************************************************************************
716 *
a33c2f47
EG
717 * Functions implemented in core module which are forward declared here
718 * for use by iwl-[4-5].c
5d08cd1d 719 *
a33c2f47
EG
720 * NOTE: The implementation of these functions are not hardware specific
721 * which is why they are in the core module files.
5d08cd1d
CH
722 *
723 * Naming convention --
a33c2f47 724 * iwl_ <-- Is part of iwlwifi
5d08cd1d 725 * iwlXXXX_ <-- Hardware specific (implemented in iwl-XXXX.c for XXXX)
bb8c093b
CH
726 * iwl4965_bg_ <-- Called from work queue context
727 * iwl4965_mac_ <-- mac80211 callback
5d08cd1d
CH
728 *
729 ****************************************************************************/
5b9f8cd3 730extern void iwl_update_chain_flags(struct iwl_priv *priv);
a33c2f47 731extern const u8 iwl_bcast_addr[ETH_ALEN];
b3bbacb7 732extern int iwl_rxq_stop(struct iwl_priv *priv);
da1bc453 733extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
443cfd45 734extern int iwl_queue_space(const struct iwl_queue *q);
fd4abac5
TW
735static inline int iwl_queue_used(const struct iwl_queue *q, int i)
736{
c8106d76 737 return q->write_ptr >= q->read_ptr ?
fd4abac5
TW
738 (i >= q->read_ptr && i < q->write_ptr) :
739 !(i < q->read_ptr && i >= q->write_ptr);
740}
741
742
743static inline u8 get_cmd_index(struct iwl_queue *q, u32 index, int is_huge)
744{
c8c24872
WYG
745 /*
746 * This is for init calibration result and scan command which
747 * required buffer > TFD_MAX_PAYLOAD_SIZE,
748 * the big buffer at end of command array
749 */
fd4abac5
TW
750 if (is_huge)
751 return q->n_window; /* must be power of 2 */
752
753 /* Otherwise, use normal size buffers */
754 return index & (q->n_window - 1);
755}
756
757
4ddbb7d0
TW
758struct iwl_dma_ptr {
759 dma_addr_t dma;
760 void *addr;
b481de9c
ZY
761 size_t size;
762};
763
b481de9c
ZY
764#define IWL_OPERATION_MODE_AUTO 0
765#define IWL_OPERATION_MODE_HT_ONLY 1
766#define IWL_OPERATION_MODE_MIXED 2
767#define IWL_OPERATION_MODE_20MHZ 3
768
3195cdb7
TW
769#define IWL_TX_CRC_SIZE 4
770#define IWL_TX_DELIMITER_SIZE 4
b481de9c 771
b481de9c 772#define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000
b481de9c 773
b481de9c 774/* Sensitivity and chain noise calibration */
b481de9c 775#define INITIALIZATION_VALUE 0xFFFF
d8c07e7a
WYG
776#define IWL4965_CAL_NUM_BEACONS 20
777#define IWL_CAL_NUM_BEACONS 16
b481de9c
ZY
778#define MAXIMUM_ALLOWED_PATHLOSS 15
779
b481de9c
ZY
780#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
781
782#define MAX_FA_OFDM 50
783#define MIN_FA_OFDM 5
784#define MAX_FA_CCK 50
785#define MIN_FA_CCK 5
786
b481de9c
ZY
787#define AUTO_CORR_STEP_OFDM 1
788
b481de9c
ZY
789#define AUTO_CORR_STEP_CCK 3
790#define AUTO_CORR_MAX_TH_CCK 160
791
b481de9c
ZY
792#define NRG_DIFF 2
793#define NRG_STEP_CCK 2
794#define NRG_MARGIN 8
795#define MAX_NUMBER_CCK_NO_FA 100
796
797#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
798
799#define CHAIN_A 0
800#define CHAIN_B 1
801#define CHAIN_C 2
802#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
803#define ALL_BAND_FILTER 0xFF00
804#define IN_BAND_FILTER 0xFF
805#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
806
3195cdb7
TW
807#define NRG_NUM_PREV_STAT_L 20
808#define NUM_RX_CHAINS 3
809
bb8c093b 810enum iwl4965_false_alarm_state {
b481de9c
ZY
811 IWL_FA_TOO_MANY = 0,
812 IWL_FA_TOO_FEW = 1,
813 IWL_FA_GOOD_RANGE = 2,
814};
815
bb8c093b 816enum iwl4965_chain_noise_state {
b481de9c 817 IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */
04816448
GE
818 IWL_CHAIN_NOISE_ACCUMULATE,
819 IWL_CHAIN_NOISE_CALIBRATED,
820 IWL_CHAIN_NOISE_DONE,
b481de9c
ZY
821};
822
bb8c093b 823enum iwl4965_calib_enabled_state {
b481de9c
ZY
824 IWL_CALIB_DISABLED = 0, /* must be 0 */
825 IWL_CALIB_ENABLED = 1,
826};
827
f69f42a6
TW
828
829/*
830 * enum iwl_calib
831 * defines the order in which results of initial calibrations
832 * should be sent to the runtime uCode
833 */
834enum iwl_calib {
835 IWL_CALIB_XTAL,
819500c5 836 IWL_CALIB_DC,
f69f42a6
TW
837 IWL_CALIB_LO,
838 IWL_CALIB_TX_IQ,
839 IWL_CALIB_TX_IQ_PERD,
201706ac 840 IWL_CALIB_BASE_BAND,
bf53f939 841 IWL_CALIB_TEMP_OFFSET,
f69f42a6
TW
842 IWL_CALIB_MAX
843};
844
6e21f2c1
TW
845/* Opaque calibration results */
846struct iwl_calib_result {
847 void *buf;
848 size_t buf_len;
7c616cba
TW
849};
850
dbb983b7
RR
851enum ucode_type {
852 UCODE_NONE = 0,
853 UCODE_INIT,
854 UCODE_RT
855};
856
b481de9c 857/* Sensitivity calib data */
f0832f13 858struct iwl_sensitivity_data {
b481de9c
ZY
859 u32 auto_corr_ofdm;
860 u32 auto_corr_ofdm_mrc;
861 u32 auto_corr_ofdm_x1;
862 u32 auto_corr_ofdm_mrc_x1;
863 u32 auto_corr_cck;
864 u32 auto_corr_cck_mrc;
865
866 u32 last_bad_plcp_cnt_ofdm;
867 u32 last_fa_cnt_ofdm;
868 u32 last_bad_plcp_cnt_cck;
869 u32 last_fa_cnt_cck;
870
871 u32 nrg_curr_state;
872 u32 nrg_prev_state;
873 u32 nrg_value[10];
874 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
875 u32 nrg_silence_ref;
876 u32 nrg_energy_idx;
877 u32 nrg_silence_idx;
878 u32 nrg_th_cck;
879 s32 nrg_auto_corr_silence_diff;
880 u32 num_in_cck_no_fa;
881 u32 nrg_th_ofdm;
55036d66
WYG
882
883 u16 barker_corr_th_min;
884 u16 barker_corr_th_min_mrc;
885 u16 nrg_th_cca;
b481de9c
ZY
886};
887
888/* Chain noise (differential Rx gain) calib data */
f0832f13 889struct iwl_chain_noise_data {
04816448 890 u32 active_chains;
b481de9c
ZY
891 u32 chain_noise_a;
892 u32 chain_noise_b;
893 u32 chain_noise_c;
894 u32 chain_signal_a;
895 u32 chain_signal_b;
896 u32 chain_signal_c;
04816448 897 u16 beacon_count;
b481de9c
ZY
898 u8 disconn_array[NUM_RX_CHAINS];
899 u8 delta_gain_code[NUM_RX_CHAINS];
900 u8 radio_write;
04816448 901 u8 state;
b481de9c
ZY
902};
903
abceddb4
BC
904#define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
905#define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
b481de9c 906
20594eb0
WYG
907#define IWL_TRAFFIC_ENTRIES (256)
908#define IWL_TRAFFIC_ENTRY_SIZE (64)
5d08cd1d 909
5d08cd1d
CH
910enum {
911 MEASUREMENT_READY = (1 << 0),
912 MEASUREMENT_ACTIVE = (1 << 1),
913};
914
0848e297
WYG
915enum iwl_nvm_type {
916 NVM_DEVICE_TYPE_EEPROM = 0,
917 NVM_DEVICE_TYPE_OTP,
918};
919
415e4993
WYG
920/*
921 * Two types of OTP memory access modes
922 * IWL_OTP_ACCESS_ABSOLUTE - absolute address mode,
923 * based on physical memory addressing
924 * IWL_OTP_ACCESS_RELATIVE - relative address mode,
925 * based on logical memory addressing
926 */
927enum iwl_access_mode {
928 IWL_OTP_ACCESS_ABSOLUTE,
929 IWL_OTP_ACCESS_RELATIVE,
930};
65b7998a
WYG
931
932/**
933 * enum iwl_pa_type - Power Amplifier type
934 * @IWL_PA_SYSTEM: based on uCode configuration
65b7998a
WYG
935 * @IWL_PA_INTERNAL: use Internal only
936 */
937enum iwl_pa_type {
938 IWL_PA_SYSTEM = 0,
740e7f51 939 IWL_PA_INTERNAL = 1,
65b7998a
WYG
940};
941
a83b9141
WYG
942/* interrupt statistics */
943struct isr_statistics {
944 u32 hw;
945 u32 sw;
6e6ebf4b 946 u32 err_code;
a83b9141
WYG
947 u32 sch;
948 u32 alive;
949 u32 rfkill;
950 u32 ctkill;
951 u32 wakeup;
952 u32 rx;
953 u32 rx_handlers[REPLY_MAX];
954 u32 tx;
955 u32 unhandled;
956};
5d08cd1d 957
91835ba4
WYG
958/* reply_tx_statistics (for _agn devices) */
959struct reply_tx_error_statistics {
960 u32 pp_delay;
961 u32 pp_few_bytes;
962 u32 pp_bt_prio;
963 u32 pp_quiet_period;
964 u32 pp_calc_ttak;
965 u32 int_crossed_retry;
966 u32 short_limit;
967 u32 long_limit;
968 u32 fifo_underrun;
969 u32 drain_flow;
970 u32 rfkill_flush;
971 u32 life_expire;
972 u32 dest_ps;
973 u32 host_abort;
974 u32 bt_retry;
975 u32 sta_invalid;
976 u32 frag_drop;
977 u32 tid_disable;
978 u32 fifo_flush;
979 u32 insuff_cf_poll;
980 u32 fail_hw_drop;
981 u32 sta_color_mismatch;
982 u32 unknown;
983};
984
814665fe
WYG
985/* reply_agg_tx_statistics (for _agn devices) */
986struct reply_agg_tx_error_statistics {
987 u32 underrun;
988 u32 bt_prio;
989 u32 few_bytes;
990 u32 abort;
991 u32 last_sent_ttl;
992 u32 last_sent_try;
993 u32 last_sent_bt_kill;
994 u32 scd_query;
995 u32 bad_crc32;
996 u32 response;
997 u32 dump_tx;
998 u32 delay_tx;
999 u32 unknown;
1000};
1001
22fdf3c9
WYG
1002/* management statistics */
1003enum iwl_mgmt_stats {
1004 MANAGEMENT_ASSOC_REQ = 0,
1005 MANAGEMENT_ASSOC_RESP,
1006 MANAGEMENT_REASSOC_REQ,
1007 MANAGEMENT_REASSOC_RESP,
1008 MANAGEMENT_PROBE_REQ,
1009 MANAGEMENT_PROBE_RESP,
1010 MANAGEMENT_BEACON,
1011 MANAGEMENT_ATIM,
1012 MANAGEMENT_DISASSOC,
1013 MANAGEMENT_AUTH,
1014 MANAGEMENT_DEAUTH,
1015 MANAGEMENT_ACTION,
1016 MANAGEMENT_MAX,
1017};
1018/* control statistics */
1019enum iwl_ctrl_stats {
1020 CONTROL_BACK_REQ = 0,
1021 CONTROL_BACK,
1022 CONTROL_PSPOLL,
1023 CONTROL_RTS,
1024 CONTROL_CTS,
1025 CONTROL_ACK,
1026 CONTROL_CFEND,
1027 CONTROL_CFENDACK,
1028 CONTROL_MAX,
1029};
1030
1031struct traffic_stats {
5ed540ae 1032#ifdef CONFIG_IWLWIFI_DEBUGFS
22fdf3c9
WYG
1033 u32 mgmt[MANAGEMENT_MAX];
1034 u32 ctrl[CONTROL_MAX];
1035 u32 data_cnt;
1036 u64 data_bytes;
22fdf3c9 1037#endif
5ed540ae 1038};
22fdf3c9 1039
0924e519
WYG
1040/*
1041 * iwl_switch_rxon: "channel switch" structure
1042 *
1043 * @ switch_in_progress: channel switch in progress
1044 * @ channel: new channel
1045 */
1046struct iwl_switch_rxon {
1047 bool switch_in_progress;
1048 __le16 channel;
1049};
1050
a9e1cb6a
WYG
1051/*
1052 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
1053 * to perform continuous uCode event logging operation if enabled
1054 */
1055#define UCODE_TRACE_PERIOD (100)
1056
1057/*
1058 * iwl_event_log: current uCode event log position
1059 *
1060 * @ucode_trace: enable/disable ucode continuous trace timer
1061 * @num_wraps: how many times the event buffer wraps
1062 * @next_entry: the entry just before the next one that uCode would fill
1063 * @non_wraps_count: counter for no wrap detected when dump ucode events
1064 * @wraps_once_count: counter for wrap once detected when dump ucode events
1065 * @wraps_more_count: counter for wrap more than once detected
1066 * when dump ucode events
1067 */
1068struct iwl_event_log {
1069 bool ucode_trace;
1070 u32 num_wraps;
1071 u32 next_entry;
1072 int non_wraps_count;
1073 int wraps_once_count;
1074 int wraps_more_count;
1075};
1076
2be76703
WYG
1077/*
1078 * host interrupt timeout value
1079 * used with setting interrupt coalescing timer
1080 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1081 *
1082 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1083 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
1084 */
1085#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
1086#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
1087#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
1088#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1089#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1090#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1091
3e4fb5fa
TAN
1092/*
1093 * This is the threshold value of plcp error rate per 100mSecs. It is
1094 * used to set and check for the validity of plcp_delta.
1095 */
680788ac 1096#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1)
3e4fb5fa
TAN
1097#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
1098#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
6c3872e1 1099#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
3e4fb5fa 1100#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
680788ac 1101#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0)
3e4fb5fa 1102
8a472da4
WYG
1103#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
1104#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1105
22de94de
SG
1106/* TX queue watchdog timeouts in mSecs */
1107#define IWL_DEF_WD_TIMEOUT (2000)
1108#define IWL_LONG_WD_TIMEOUT (10000)
1109#define IWL_MAX_WD_TIMEOUT (120000)
b74e31a9 1110
bee008b7
WYG
1111/* BT Antenna Coupling Threshold (dB) */
1112#define IWL_BT_ANTENNA_COUPLING_THRESHOLD (35)
1113
491bc292
WYG
1114/* Firmware reload counter and Timestamp */
1115#define IWL_MIN_RELOAD_DURATION 1000 /* 1000 ms */
1116#define IWL_MAX_CONTINUE_RELOAD_CNT 4
1117
1118
a93e7973
WYG
1119enum iwl_reset {
1120 IWL_RF_RESET = 0,
1121 IWL_FW_RESET,
8a472da4
WYG
1122 IWL_MAX_FORCE_RESET,
1123};
1124
1125struct iwl_force_reset {
1126 int reset_request_count;
1127 int reset_success_count;
1128 int reset_reject_count;
1129 unsigned long reset_duration;
1130 unsigned long last_force_reset_jiffies;
a93e7973
WYG
1131};
1132
a0ee74cf
WYG
1133/* extend beacon time format bit shifting */
1134/*
1135 * for _3945 devices
1136 * bits 31:24 - extended
1137 * bits 23:0 - interval
1138 */
1139#define IWL3945_EXT_BEACON_TIME_POS 24
1140/*
1141 * for _agn devices
1142 * bits 31:22 - extended
1143 * bits 21:0 - interval
1144 */
1145#define IWLAGN_EXT_BEACON_TIME_POS 22
1146
7194207c
JB
1147/**
1148 * struct iwl_notification_wait - notification wait entry
1149 * @list: list head for global list
1150 * @fn: function called with the notification
1151 * @cmd: command ID
1152 *
1153 * This structure is not used directly, to wait for a
1154 * notification declare it on the stack, and call
1155 * iwlagn_init_notification_wait() with appropriate
1156 * parameters. Then do whatever will cause the ucode
1157 * to notify the driver, and to wait for that then
1158 * call iwlagn_wait_notification().
1159 *
1160 * Each notification is one-shot. If at some point we
1161 * need to support multi-shot notifications (which
1162 * can't be allocated on the stack) we need to modify
1163 * the code for them.
1164 */
1165struct iwl_notification_wait {
1166 struct list_head list;
1167
1168 void (*fn)(struct iwl_priv *priv, struct iwl_rx_packet *pkt);
1169
1170 u8 cmd;
1171 bool triggered;
1172};
1173
246ed355
JB
1174enum iwl_rxon_context_id {
1175 IWL_RXON_CTX_BSS,
ece9c4ee 1176 IWL_RXON_CTX_PAN,
246ed355
JB
1177
1178 NUM_IWL_RXON_CTX
1179};
1180
1181struct iwl_rxon_context {
8bd413e6 1182 struct ieee80211_vif *vif;
e72f368b
JB
1183
1184 const u8 *ac_to_fifo;
1185 const u8 *ac_to_queue;
1186 u8 mcast_queue;
1187
763cc3bf
JB
1188 /*
1189 * We could use the vif to indicate active, but we
1190 * also need it to be active during disabling when
1191 * we already removed the vif for type setting.
1192 */
1193 bool always_active, is_active;
1194
2295c66b
JB
1195 bool ht_need_multiple_chains;
1196
246ed355 1197 enum iwl_rxon_context_id ctxid;
d0fe478c
JB
1198
1199 u32 interface_modes, exclusive_interface_modes;
1200 u8 unused_devtype, ap_devtype, ibss_devtype, station_devtype;
1201
246ed355
JB
1202 /*
1203 * We declare this const so it can only be
1204 * changed via explicit cast within the
1205 * routines that actually update the physical
1206 * hardware.
1207 */
1208 const struct iwl_rxon_cmd active;
1209 struct iwl_rxon_cmd staging;
1210
1211 struct iwl_rxon_time_cmd timing;
a194e324 1212
8dfdb9d5
JB
1213 struct iwl_qos_info qos_data;
1214
2995bafa 1215 u8 bcast_sta_id, ap_sta_id;
8f2d3d2a
JB
1216
1217 u8 rxon_cmd, rxon_assoc_cmd, rxon_timing_cmd;
8dfdb9d5 1218 u8 qos_cmd;
c10afb6e
JB
1219 u8 wep_key_cmd;
1220
1221 struct iwl_wep_key wep_keys[WEP_KEYS_MAX];
1222 u8 key_mapping_keys;
770e13bd
JB
1223
1224 __le32 station_flags;
7e6a5886
JB
1225
1226 struct {
1227 bool non_gf_sta_present;
1228 u8 protection;
1229 bool enabled, is_40mhz;
1230 u8 extension_chan_offset;
1231 } ht;
246ed355
JB
1232};
1233
266af4c7
JB
1234enum iwl_scan_type {
1235 IWL_SCAN_NORMAL,
1236 IWL_SCAN_RADIO_RESET,
1237 IWL_SCAN_OFFCH_TX,
1238};
1239
c79dd5b5 1240struct iwl_priv {
5d08cd1d
CH
1241
1242 /* ieee device used by generic ieee processing code */
1243 struct ieee80211_hw *hw;
1244 struct ieee80211_channel *ieee_channels;
1245 struct ieee80211_rate *ieee_rates;
82b9a121 1246 struct iwl_cfg *cfg;
5d08cd1d
CH
1247
1248 /* temporary frame storage list */
1249 struct list_head free_frames;
1250 int frames_count;
1251
8318d78a 1252 enum ieee80211_band band;
2f301227 1253 int alloc_rxb_page;
5d08cd1d 1254
c79dd5b5 1255 void (*rx_handlers[REPLY_MAX])(struct iwl_priv *priv,
a55360e4 1256 struct iwl_rx_mem_buffer *rxb);
5d08cd1d 1257
8318d78a 1258 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
5d08cd1d 1259
5d08cd1d 1260 /* spectrum measurement report caching */
2aa6ab86 1261 struct iwl_spectrum_notification measure_report;
5d08cd1d 1262 u8 measurement_status;
81963d68 1263
5d08cd1d
CH
1264 /* ucode beacon time */
1265 u32 ucode_beacon_time;
a13d276f 1266 int missed_beacon_threshold;
5d08cd1d 1267
a85d7cca
JB
1268 /* track IBSS manager (last beacon) status */
1269 u32 ibss_manager;
1270
410f2bb3
SG
1271 /* jiffies when last recovery from statistics was performed */
1272 unsigned long rx_statistics_jiffies;
3e4fb5fa 1273
a93e7973 1274 /* force reset */
8a472da4 1275 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET];
a93e7973 1276
491bc292
WYG
1277 /* firmware reload counter and timestamp */
1278 unsigned long reload_jiffies;
1279 int reload_count;
1280
5a2a780c 1281 /* we allocate array of iwl_channel_info for NIC's valid channels.
5d08cd1d 1282 * Access via channel # using indirect index array */
bf85ea4f 1283 struct iwl_channel_info *channel_info; /* channel info array */
5d08cd1d
CH
1284 u8 channel_count; /* # of channels */
1285
5d08cd1d
CH
1286 /* thermal calibration */
1287 s32 temperature; /* degrees Kelvin */
1288 s32 last_temperature;
1289
7c616cba 1290 /* init calibration results */
6e21f2c1 1291 struct iwl_calib_result calib_results[IWL_CALIB_MAX];
7c616cba 1292
5d08cd1d 1293 /* Scan related variables */
5d08cd1d 1294 unsigned long scan_start;
5d08cd1d 1295 unsigned long scan_start_tsf;
811ecc99 1296 void *scan_cmd;
00700ee0 1297 enum ieee80211_band scan_band;
1ecf9fc1 1298 struct cfg80211_scan_request *scan_request;
f84b29ec 1299 struct ieee80211_vif *scan_vif;
266af4c7 1300 enum iwl_scan_type scan_type;
76eff18b
TW
1301 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1302 u8 mgmt_tx_ant;
5d08cd1d
CH
1303
1304 /* spinlock */
1305 spinlock_t lock; /* protect general shared data */
1306 spinlock_t hcmd_lock; /* protect hcmd */
a8b50a0a 1307 spinlock_t reg_lock; /* protect hw register access */
5d08cd1d 1308 struct mutex mutex;
d2dfe6df 1309 struct mutex sync_cmd_mutex; /* enable serialization of sync commands */
5d08cd1d
CH
1310
1311 /* basic pci-network driver stuff */
1312 struct pci_dev *pci_dev;
1313
1314 /* pci hardware address support */
1315 void __iomem *hw_base;
b661c819
TW
1316 u32 hw_rev;
1317 u32 hw_wa_rev;
1318 u8 rev_id;
5d08cd1d 1319
246ed355
JB
1320 /* microcode/device supports multiple contexts */
1321 u8 valid_contexts;
1322
13bb9483
JB
1323 /* command queue number */
1324 u8 cmd_queue;
1325
c10afb6e
JB
1326 /* max number of station keys */
1327 u8 sta_key_max_num;
1328
c6fa17ed
WYG
1329 /* EEPROM MAC addresses */
1330 struct mac_address addresses[2];
1331
5d08cd1d 1332 /* uCode images, save to reload in case of failure */
b08dfd04 1333 int fw_index; /* firmware we're trying to load */
c02b3acd
CR
1334 u32 ucode_ver; /* version of ucode, copy of
1335 iwl_ucode.ver */
5d08cd1d
CH
1336 struct fw_desc ucode_code; /* runtime inst */
1337 struct fw_desc ucode_data; /* runtime data original */
1338 struct fw_desc ucode_data_backup; /* runtime data save/restore */
1339 struct fw_desc ucode_init; /* initialization inst */
1340 struct fw_desc ucode_init_data; /* initialization data */
1341 struct fw_desc ucode_boot; /* bootstrap inst */
dbb983b7
RR
1342 enum ucode_type ucode_type;
1343 u8 ucode_write_complete; /* the image write is complete */
b08dfd04 1344 char firmware_name[25];
5d08cd1d 1345
246ed355 1346 struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX];
5d08cd1d 1347
0924e519
WYG
1348 struct iwl_switch_rxon switch_rxon;
1349
5d08cd1d 1350 /* 1st responses from initialize and runtime uCode images.
5a2a780c 1351 * _agn's initialize alive response contains some calibration data. */
885ba202
TW
1352 struct iwl_init_alive_resp card_alive_init;
1353 struct iwl_alive_resp card_alive;
5d08cd1d 1354
5d08cd1d 1355 u16 active_rate;
5d08cd1d 1356
5d08cd1d 1357 u8 start_calib;
f0832f13
EG
1358 struct iwl_sensitivity_data sensitivity_data;
1359 struct iwl_chain_noise_data chain_noise_data;
c8312fac 1360 bool enhance_sensitivity_table;
5d08cd1d 1361 __le16 sensitivity_tbl[HD_TABLE_SIZE];
c8312fac 1362 __le16 enhance_sensitivity_tbl[ENHANCE_HD_TABLE_ENTRIES];
5d08cd1d 1363
fad95bf5 1364 struct iwl_ht_config current_ht_config;
5d08cd1d 1365
5d08cd1d 1366 /* Rate scaling data */
5d08cd1d
CH
1367 u8 retry_rate;
1368
1369 wait_queue_head_t wait_command_queue;
1370
1371 int activity_timer_active;
1372
1373 /* Rx and Tx DMA processing queues */
a55360e4 1374 struct iwl_rx_queue rxq;
88804e2b 1375 struct iwl_tx_queue *txq;
5d08cd1d 1376 unsigned long txq_ctx_active_msk;
4ddbb7d0
TW
1377 struct iwl_dma_ptr kw; /* keep warm address */
1378 struct iwl_dma_ptr scd_bc_tbls;
1379
5d08cd1d
CH
1380 u32 scd_base_addr; /* scheduler sram base address */
1381
1382 unsigned long status;
5d08cd1d 1383
19758bef 1384 /* counts mgmt, ctl, and data packets */
22fdf3c9
WYG
1385 struct traffic_stats tx_stats;
1386 struct traffic_stats rx_stats;
19758bef 1387
a83b9141
WYG
1388 /* counts interrupts */
1389 struct isr_statistics isr_stats;
1390
5da4b55f 1391 struct iwl_power_mgr power_data;
3ad3b92a 1392 struct iwl_tt_mgmt thermal_throttle;
5d08cd1d 1393
5d08cd1d 1394 /* context information */
59c02b41 1395 u8 bssid[ETH_ALEN]; /* used only on 3945 but filled by core */
5d08cd1d 1396
9c5ac091
RC
1397 /* station table variables */
1398
1399 /* Note: if lock and sta_lock are needed, lock must be acquired first */
5d08cd1d
CH
1400 spinlock_t sta_lock;
1401 int num_stations;
6def9761 1402 struct iwl_station_entry stations[IWL_STATION_COUNT];
80fb47a1 1403 unsigned long ucode_key_table;
5d08cd1d 1404
e4e72fb4
JB
1405 /* queue refcounts */
1406#define IWL_MAX_HW_QUEUES 32
1407 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
1408 /* for each AC */
1409 atomic_t queue_stop_count[4];
1410
5d08cd1d 1411 /* Indication if ieee80211_ops->open has been called */
69dc5d9d 1412 u8 is_open;
5d08cd1d
CH
1413
1414 u8 mac80211_registered;
5d08cd1d 1415
af6b8ee3 1416 /* eeprom -- this is in the card's little endian byte order */
073d3f5f 1417 u8 *eeprom;
0848e297 1418 int nvm_device_type;
073d3f5f 1419 struct iwl_eeprom_calib_info *calib_info;
5d08cd1d 1420
05c914fe 1421 enum nl80211_iftype iw_mode;
5d08cd1d 1422
5d08cd1d 1423 /* Last Rx'd beacon timestamp */
3109ece1 1424 u64 timestamp;
5d08cd1d 1425
ee525d13
JB
1426 union {
1427#if defined(CONFIG_IWL3945) || defined(CONFIG_IWL3945_MODULE)
1428 struct {
1429 void *shared_virt;
1430 dma_addr_t shared_phys;
1431
1432 struct delayed_work thermal_periodic;
1433 struct delayed_work rfkill_poll;
1434
1435 struct iwl3945_notif_statistics statistics;
d73e4923 1436#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK
1437 struct iwl3945_notif_statistics accum_statistics;
1438 struct iwl3945_notif_statistics delta_statistics;
1439 struct iwl3945_notif_statistics max_delta;
1440#endif
ee525d13
JB
1441
1442 u32 sta_supp_rates;
e99f168c
JB
1443 int last_rx_rssi; /* From Rx packet statistics */
1444
1445 /* Rx'd packet timing information */
1446 u32 last_beacon_time;
1447 u64 last_tsf;
67d613ae
JB
1448
1449 /*
1450 * each calibration channel group in the
1451 * EEPROM has a derived clip setting for
1452 * each rate.
1453 */
1454 const struct iwl3945_clip_group clip_groups[5];
1455
ee525d13 1456 } _3945;
a4c8b2a6
JB
1457#endif
1458#if defined(CONFIG_IWLAGN) || defined(CONFIG_IWLAGN_MODULE)
1459 struct {
1460 /* INT ICT Table */
1461 __le32 *ict_tbl;
1462 void *ict_tbl_vir;
1463 dma_addr_t ict_tbl_dma;
1464 dma_addr_t aligned_ict_tbl_dma;
1465 int ict_index;
1466 u32 inta;
1467 bool use_ict;
d5a0ffa3
WYG
1468 /*
1469 * reporting the number of tids has AGG on. 0 means
1470 * no AGGREGATION
1471 */
1472 u8 agg_tids_count;
05d57520
JB
1473
1474 struct iwl_rx_phy_res last_phy_res;
1475 bool last_phy_res_valid;
a15707d8
RC
1476
1477 struct completion firmware_loading_complete;
a2064b7a 1478
b2e640d4
JB
1479 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1480 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
f3aebeee 1481
6a822d06
WYG
1482 /*
1483 * chain noise reset and gain commands are the
1484 * two extra calibration commands follows the standard
1485 * phy calibration commands
1486 */
1487 u8 phy_calib_chain_noise_reset_cmd;
1488 u8 phy_calib_chain_noise_gain_cmd;
1489
f3aebeee 1490 struct iwl_notif_statistics statistics;
7980fba5 1491 struct iwl_bt_notif_statistics statistics_bt;
91835ba4
WYG
1492 /* counts reply_tx error */
1493 struct reply_tx_error_statistics reply_tx_stats;
814665fe 1494 struct reply_agg_tx_error_statistics reply_agg_tx_stats;
f3aebeee
WYG
1495#ifdef CONFIG_IWLWIFI_DEBUGFS
1496 struct iwl_notif_statistics accum_statistics;
1497 struct iwl_notif_statistics delta_statistics;
1498 struct iwl_notif_statistics max_delta;
7980fba5
WYG
1499 struct iwl_bt_notif_statistics accum_statistics_bt;
1500 struct iwl_bt_notif_statistics delta_statistics_bt;
1501 struct iwl_bt_notif_statistics max_delta_bt;
f3aebeee 1502#endif
7194207c
JB
1503
1504 /* notification wait support */
1505 struct list_head notif_waits;
1506 spinlock_t notif_wait_lock;
1507 wait_queue_head_t notif_waitq;
9b9190d9
JB
1508
1509 /* remain-on-channel offload support */
1510 struct ieee80211_channel *hw_roc_channel;
1511 struct delayed_work hw_roc_work;
1512 enum nl80211_channel_type hw_roc_chantype;
1513 int hw_roc_duration;
266af4c7
JB
1514
1515 struct sk_buff *offchan_tx_skb;
1516 int offchan_tx_timeout;
1517 struct ieee80211_channel *offchan_tx_chan;
a4c8b2a6 1518 } _agn;
ee525d13
JB
1519#endif
1520 };
1521
22bf59a0 1522 /* bt coex */
f21dd005 1523 u8 bt_enable_flag;
da5dbb97 1524 u8 bt_status;
66e863a5 1525 u8 bt_traffic_load, last_bt_traffic_load;
f37837c9 1526 bool bt_ch_announce;
bee008b7
WYG
1527 bool bt_full_concurrent;
1528 bool bt_ant_couple_ok;
fbba9410
WYG
1529 __le32 kill_ack_mask;
1530 __le32 kill_cts_mask;
1531 __le16 bt_valid;
22bf59a0
WYG
1532 u16 bt_on_thresh;
1533 u16 bt_duration;
1534 u16 dynamic_frag_thresh;
bee008b7 1535 u8 bt_ci_compliance;
9e4afc21
JB
1536 struct work_struct bt_traffic_change_work;
1537
5425e490 1538 struct iwl_hw_params hw_params;
4ddbb7d0 1539
40cefda9 1540 u32 inta_mask;
5d08cd1d 1541
5d08cd1d
CH
1542 struct workqueue_struct *workqueue;
1543
5d08cd1d 1544 struct work_struct restart;
5d08cd1d
CH
1545 struct work_struct scan_completed;
1546 struct work_struct rx_replenish;
5d08cd1d 1547 struct work_struct abort_scan;
12e934dc 1548
5d08cd1d 1549 struct work_struct beacon_update;
76d04815 1550 struct iwl_rxon_context *beacon_ctx;
12e934dc 1551 struct sk_buff *beacon_skb;
76d04815 1552
a28027cd
WYG
1553 struct work_struct tt_work;
1554 struct work_struct ct_enter;
1555 struct work_struct ct_exit;
88be0264 1556 struct work_struct start_internal_scan;
65550636 1557 struct work_struct tx_flush;
bee008b7 1558 struct work_struct bt_full_concurrency;
fbba9410 1559 struct work_struct bt_runtime_config;
5d08cd1d
CH
1560
1561 struct tasklet_struct irq_tasklet;
1562
1563 struct delayed_work init_alive_start;
1564 struct delayed_work alive_start;
5d08cd1d 1565 struct delayed_work scan_check;
4a8a4322 1566
630fe9b6
TW
1567 /* TX Power */
1568 s8 tx_power_user_lmt;
dc1b0973 1569 s8 tx_power_device_lmt;
ae16fc3c 1570 s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
a25a66ac 1571 s8 tx_power_next;
5d08cd1d 1572
5d08cd1d 1573
d08853a3 1574#ifdef CONFIG_IWLWIFI_DEBUG
5d08cd1d 1575 /* debugging info */
3d816c77
RC
1576 u32 debug_level; /* per device debugging will override global
1577 iwl_debug_level if set */
d73e4923 1578#endif /* CONFIG_IWLWIFI_DEBUG */
712b6cf5
TW
1579#ifdef CONFIG_IWLWIFI_DEBUGFS
1580 /* debugfs */
20594eb0
WYG
1581 u16 tx_traffic_idx;
1582 u16 rx_traffic_idx;
1583 u8 *tx_traffic;
1584 u8 *rx_traffic;
4c84a8f1
JB
1585 struct dentry *debugfs_dir;
1586 u32 dbgfs_sram_offset, dbgfs_sram_len;
d73e4923 1587 bool disable_ht40;
712b6cf5 1588#endif /* CONFIG_IWLWIFI_DEBUGFS */
5d08cd1d
CH
1589
1590 struct work_struct txpower_work;
445c2dff
TW
1591 u32 disable_sens_cal;
1592 u32 disable_chain_noise_cal;
203566f3 1593 u32 disable_tx_power_cal;
16e727e8 1594 struct work_struct run_time_calib_work;
5d08cd1d 1595 struct timer_list statistics_periodic;
a9e1cb6a 1596 struct timer_list ucode_trace;
22de94de 1597 struct timer_list watchdog;
086ed117 1598 bool hw_ready;
a9e1cb6a
WYG
1599
1600 struct iwl_event_log event_log;
5ed540ae
WYG
1601
1602 struct led_classdev led;
1603 unsigned long blink_on, blink_off;
1604 bool led_registered;
c79dd5b5 1605}; /*iwl_priv */
5d08cd1d 1606
36470749
RR
1607static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1608{
1609 set_bit(txq_id, &priv->txq_ctx_active_msk);
1610}
1611
1612static inline void iwl_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1613{
1614 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1615}
1616
994d31f7 1617#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77
RC
1618/*
1619 * iwl_get_debug_level: Return active debug level for device
1620 *
1621 * Using sysfs it is possible to set per device debug level. This debug
1622 * level will be used if set, otherwise the global debug level which can be
1623 * set via module parameter is used.
1624 */
1625static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1626{
1627 if (priv->debug_level)
1628 return priv->debug_level;
1629 else
1630 return iwl_debug_level;
1631}
a332f8d6 1632#else
3d816c77
RC
1633static inline u32 iwl_get_debug_level(struct iwl_priv *priv)
1634{
1635 return iwl_debug_level;
1636}
a332f8d6
TW
1637#endif
1638
1639
a332f8d6
TW
1640static inline struct ieee80211_hdr *iwl_tx_queue_get_hdr(struct iwl_priv *priv,
1641 int txq_id, int idx)
1642{
ff0d91c3 1643 if (priv->txq[txq_id].txb[idx].skb)
a332f8d6 1644 return (struct ieee80211_hdr *)priv->txq[txq_id].
ff0d91c3 1645 txb[idx].skb->data;
a332f8d6
TW
1646 return NULL;
1647}
a332f8d6 1648
246ed355
JB
1649static inline struct iwl_rxon_context *
1650iwl_rxon_ctx_from_vif(struct ieee80211_vif *vif)
1651{
1652 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1653
1654 return vif_priv->ctx;
1655}
1656
1657#define for_each_context(priv, ctx) \
1658 for (ctx = &priv->contexts[IWL_RXON_CTX_BSS]; \
1659 ctx < &priv->contexts[NUM_IWL_RXON_CTX]; ctx++) \
1660 if (priv->valid_contexts & BIT(ctx->ctxid))
1661
1662static inline int iwl_is_associated(struct iwl_priv *priv,
1663 enum iwl_rxon_context_id ctxid)
1664{
1665 return (priv->contexts[ctxid].active.filter_flags &
1666 RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1667}
1668
1669static inline int iwl_is_any_associated(struct iwl_priv *priv)
1670{
1671 return iwl_is_associated(priv, IWL_RXON_CTX_BSS);
1672}
a332f8d6 1673
246ed355 1674static inline int iwl_is_associated_ctx(struct iwl_rxon_context *ctx)
5d08cd1d 1675{
246ed355 1676 return (ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
5d08cd1d
CH
1677}
1678
bf85ea4f 1679static inline int is_channel_valid(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1680{
1681 if (ch_info == NULL)
1682 return 0;
1683 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1684}
1685
bf85ea4f 1686static inline int is_channel_radar(const struct iwl_channel_info *ch_info)
5d08cd1d
CH
1687{
1688 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1689}
1690
bf85ea4f 1691static inline u8 is_channel_a_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1692{
8318d78a 1693 return ch_info->band == IEEE80211_BAND_5GHZ;
5d08cd1d
CH
1694}
1695
bf85ea4f 1696static inline u8 is_channel_bg_band(const struct iwl_channel_info *ch_info)
5d08cd1d 1697{
8318d78a 1698 return ch_info->band == IEEE80211_BAND_2GHZ;
5d08cd1d
CH
1699}
1700
bf85ea4f 1701static inline int is_channel_passive(const struct iwl_channel_info *ch)
5d08cd1d
CH
1702{
1703 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1704}
1705
bf85ea4f 1706static inline int is_channel_ibss(const struct iwl_channel_info *ch)
5d08cd1d
CH
1707{
1708 return ((ch->flags & EEPROM_CHANNEL_IBSS)) ? 1 : 0;
1709}
1710
64a76b50
ZY
1711static inline void __iwl_free_pages(struct iwl_priv *priv, struct page *page)
1712{
1713 __free_pages(page, priv->hw_params.rx_page_order);
1714 priv->alloc_rxb_page--;
1715}
1716
1717static inline void iwl_free_pages(struct iwl_priv *priv, unsigned long page)
1718{
1719 free_pages(page, priv->hw_params.rx_page_order);
1720 priv->alloc_rxb_page--;
1721}
be1f3ab6 1722#endif /* __iwl_dev_h__ */
This page took 1.408594 seconds and 4 git commands to generate.