]> Git Repo - linux.git/blame - drivers/pci/pci.h
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'afs-fixes-20220802' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowe...
[linux.git] / drivers / pci / pci.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
557848c3
ZY		 2#ifndef DRIVERS_PCI_H
3#define DRIVERS_PCI_H
4
2209e06f
AG		 5#include <linux/pci.h>
6
f8bf2aeb
JS		 7/* Number of possible devfns: 0.0 to 1f.7 inclusive */
8#define MAX_NR_DEVFNS 256
9
fff905f3
WY		 10#define PCI_FIND_CAP_TTL 48
11
8531e283
LW		 12#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
13
343e51ae 14extern const unsigned char pcie_link_speed[];
11eb0e0e 15extern bool pci_early_dump;
343e51ae 16
7a1562d4 17bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
af65d1ad 18bool pcie_cap_has_rtctl(const struct pci_dev *dev);
7a1562d4 19
1da177e4
LT		 20/* Functions internal to the PCI core code */
21
f39d5b72
BH		 22int pci_create_sysfs_dev_files(struct pci_dev *pdev);
23void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
f39d5b72 24void pci_cleanup_rom(struct pci_dev *dev);
506140f9
KW		 25#ifdef CONFIG_DMI
26extern const struct attribute_group pci_dev_smbios_attr_group;
27#endif
f7195824 28
3b519e4e
MW		 29enum pci_mmap_api {
30 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
31 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
32};
f39d5b72
BH		 33int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
34 enum pci_mmap_api mmap_api);
f7195824 35
e20afa06
AN		 36bool pci_reset_supported(struct pci_dev *dev);
37void pci_init_reset_methods(struct pci_dev *dev);
381634ca 38int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
c4eed62a 39int pci_bus_error_reset(struct pci_dev *dev);
ce5ccdef 40
f0ab0017
BH		 41struct pci_cap_saved_data {
42 u16 cap_nr;
43 bool cap_extended;
44 unsigned int size;
45 u32 data[];
46};
47
48struct pci_cap_saved_state {
49 struct hlist_node next;
50 struct pci_cap_saved_data cap;
51};
52
53void pci_allocate_cap_save_buffers(struct pci_dev *dev);
54void pci_free_cap_save_buffers(struct pci_dev *dev);
55int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
56int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
57 u16 cap, unsigned int size);
58struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
59struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
60 u16 cap);
61
638c133e
BH		 62#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
63#define PCI_PM_D3HOT_WAIT 10 /* msec */
64#define PCI_PM_D3COLD_WAIT 100 /* msec */
c776dd50 65
f39d5b72 66void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
b51033e0 67void pci_refresh_power_state(struct pci_dev *dev);
adfac8f6 68int pci_power_up(struct pci_dev *dev);
f39d5b72
BH		 69void pci_disable_enabled_device(struct pci_dev *dev);
70int pci_finish_runtime_suspend(struct pci_dev *dev);
600a5b4f 71void pcie_clear_device_status(struct pci_dev *dev);
dcb0453d 72void pcie_clear_root_pme_status(struct pci_dev *dev);
669696eb
KS		 73bool pci_check_pme_status(struct pci_dev *dev);
74void pci_pme_wakeup_bus(struct pci_bus *bus);
f39d5b72 75int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
0ce3fcaf 76void pci_pme_restore(struct pci_dev *dev);
0c7376ad
RW		 77bool pci_dev_need_resume(struct pci_dev *dev);
78void pci_dev_adjust_pme(struct pci_dev *dev);
2cef548a 79void pci_dev_complete_resume(struct pci_dev *pci_dev);
f39d5b72
BH		 80void pci_config_pm_runtime_get(struct pci_dev *dev);
81void pci_config_pm_runtime_put(struct pci_dev *dev);
82void pci_pm_init(struct pci_dev *dev);
938174e5 83void pci_ea_init(struct pci_dev *dev);
cbc40d5c
BH		 84void pci_msi_init(struct pci_dev *dev);
85void pci_msix_init(struct pci_dev *dev);
c6a63307 86bool pci_bridge_d3_possible(struct pci_dev *dev);
1ed276a7 87void pci_bridge_d3_update(struct pci_dev *dev);
ad9001f2 88void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
e1b0d0bb 89void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
aa8c6c93 90
b6e335ae
RW		 91static inline void pci_wakeup_event(struct pci_dev *dev)
92{
93 /* Wait 100 ms before the system can be put into a sleep state. */
94 pm_wakeup_event(&dev->dev, 100);
95}
96
326c1cda 97static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
aa8c6c93
RW		 98{
99 return !!(pci_dev->subordinate);
100}
0f64474b 101
9d26d3a8
MW		 102static inline bool pci_power_manageable(struct pci_dev *pci_dev)
103{
104 /*
105 * Currently we allow normal PCI devices and PCI bridges transition
106 * into D3 if their bridge_d3 is set.
107 */
108 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
109}
110
984998e3
MW		 111static inline bool pcie_downstream_port(const struct pci_dev *dev)
112{
113 int type = pci_pcie_type(dev);
114
115 return type == PCI_EXP_TYPE_ROOT_PORT ||
116 type == PCI_EXP_TYPE_DOWNSTREAM ||
117 type == PCI_EXP_TYPE_PCIE_BRIDGE;
118}
119
e947e7b1 120void pci_vpd_init(struct pci_dev *dev);
64379079 121void pci_vpd_release(struct pci_dev *dev);
d93f8399 122extern const struct attribute_group pci_dev_vpd_attr_group;
94e61088 123
440589dd
KS		 124/* PCI Virtual Channel */
125int pci_save_vc_state(struct pci_dev *dev);
126void pci_restore_vc_state(struct pci_dev *dev);
127void pci_allocate_vc_save_buffers(struct pci_dev *dev);
128
1da177e4
LT		 129/* PCI /proc functions */
130#ifdef CONFIG_PROC_FS
f39d5b72
BH		 131int pci_proc_attach_device(struct pci_dev *dev);
132int pci_proc_detach_device(struct pci_dev *dev);
133int pci_proc_detach_bus(struct pci_bus *bus);
1da177e4
LT		 134#else
135static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
136static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
1da177e4
LT		 137static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
138#endif
139
140/* Functions for PCI Hotplug drivers to use */
a8e4b9c1 141int pci_hp_add_bridge(struct pci_dev *dev);
1da177e4 142
f19aeb1f 143#ifdef HAVE_PCI_LEGACY
f39d5b72
BH		 144void pci_create_legacy_files(struct pci_bus *bus);
145void pci_remove_legacy_files(struct pci_bus *bus);
f19aeb1f
BH		 146#else
147static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
148static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
149#endif
1da177e4
LT		 150
151/* Lock for read/write access to pci device and bus lists */
d71374da 152extern struct rw_semaphore pci_bus_sem;
c4eed62a 153extern struct mutex pci_slot_mutex;
1da177e4 154
a2e27787
JK		 155extern raw_spinlock_t pci_lock;
156
3789af9a 157extern unsigned int pci_pm_d3hot_delay;
88187dfa 158
4b47b0ee 159#ifdef CONFIG_PCI_MSI
309e57df 160void pci_no_msi(void);
4b47b0ee 161#else
309e57df 162static inline void pci_no_msi(void) { }
4b47b0ee 163#endif
8fed4b65 164
b55438fd 165void pci_realloc_get_opt(char *);
f483d392 166
ffadcc2f
KCA		 167static inline int pci_no_d1d2(struct pci_dev *dev)
168{
169 unsigned int parent_dstates = 0;
4b47b0ee 170
ffadcc2f
KCA		 171 if (dev->bus->self)
172 parent_dstates = dev->bus->self->no_d1d2;
173 return (dev->no_d1d2 || parent_dstates);
174
175}
5136b2da 176extern const struct attribute_group *pci_dev_groups[];
56039e65 177extern const struct attribute_group *pcibus_groups[];
69f2dc24 178extern const struct device_type pci_dev_type;
0f49ba55 179extern const struct attribute_group *pci_bus_groups[];
705b1aaa 180
003d3b2c 181extern unsigned long pci_hotplug_io_size;
d7b8a217
NJ		 182extern unsigned long pci_hotplug_mmio_size;
183extern unsigned long pci_hotplug_mmio_pref_size;
003d3b2c 184extern unsigned long pci_hotplug_bus_size;
1da177e4
LT		 185
186/**
187 * pci_match_one_device - Tell if a PCI device structure has a matching
0aa0f5d1 188 * PCI device id structure
1da177e4
LT		 189 * @id: single PCI device id structure to match
190 * @dev: the PCI device structure to match against
367b09fe 191 *
1da177e4
LT		 192 * Returns the matching pci_device_id structure or %NULL if there is no match.
193 */
194static inline const struct pci_device_id *
195pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
196{
197 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
198 (id->device == PCI_ANY_ID || id->device == dev->device) &&
199 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
200 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
201 !((id->class ^ dev->class) & id->class_mask))
202 return id;
203 return NULL;
204}
205
f46753c5
AC		 206/* PCI slot sysfs helper code */
207#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
208
209extern struct kset *pci_slots_kset;
210
211struct pci_slot_attribute {
212 struct attribute attr;
213 ssize_t (*show)(struct pci_slot *, char *);
214 ssize_t (*store)(struct pci_slot *, const char *, size_t);
215};
216#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
217
0b400c7e
YZ		 218enum pci_bar_type {
219 pci_bar_unknown, /* Standard PCI BAR probe */
0aa0f5d1 220 pci_bar_io, /* An I/O port BAR */
0b400c7e
YZ		 221 pci_bar_mem32, /* A 32-bit memory BAR */
222 pci_bar_mem64, /* A 64-bit memory BAR */
223};
224
975e1ac1
KS		 225struct device *pci_get_host_bridge_device(struct pci_dev *dev);
226void pci_put_host_bridge_device(struct device *dev);
227
62ce94a7 228int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
efdc87da
YL		 229bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
230 int crs_timeout);
aa667c64
JP		 231bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
232 int crs_timeout);
233int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
234
f39d5b72
BH		 235int pci_setup_device(struct pci_dev *dev);
236int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
237 struct resource *res, unsigned int reg);
f39d5b72 238void pci_configure_ari(struct pci_dev *dev);
10874f5a 239void __pci_bus_size_bridges(struct pci_bus *bus,
d66ecb72 240 struct list_head *realloc_head);
10874f5a
BH		 241void __pci_bus_assign_resources(const struct pci_bus *bus,
242 struct list_head *realloc_head,
243 struct list_head *fail_head);
0f7e7aee 244bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
939de1d6 245
2069ecfb 246void pci_reassigndev_resource_alignment(struct pci_dev *dev);
f39d5b72 247void pci_disable_bridge_window(struct pci_dev *dev);
ecd29c1a
KS		 248struct pci_bus *pci_bus_get(struct pci_bus *bus);
249void pci_bus_put(struct pci_bus *bus);
32a9a682 250
757bfaa2
YY		 251/* PCIe link information from Link Capabilities 2 */
252#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
34191749
GP		 253 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
254 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
757bfaa2
YY		 255 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
256 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
257 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
258 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
259 PCI_SPEED_UNKNOWN)
6cf57be0 260
b852f63a
TG		 261/* PCIe speed to Mb/s reduced by encoding overhead */
262#define PCIE_SPEED2MBS_ENC(speed) \
34191749
GP		 263 ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
264 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
9cb3985a 265 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
b852f63a
TG		 266 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
267 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
268 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
269 0)
270
e56faff5 271const char *pci_speed_string(enum pci_bus_speed speed);
6cf57be0 272enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
c70b65fb 273enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
b852f63a
TG		 274u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
275 enum pcie_link_width *width);
2d1ce5ec 276void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
0fa635ae 277void pcie_report_downtraining(struct pci_dev *dev);
5da78d95 278void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
6cf57be0 279
d1b054da
YZ		 280/* Single Root I/O Virtualization */
281struct pci_sriov {
0aa0f5d1
BH		 282 int pos; /* Capability position */
283 int nres; /* Number of resources */
284 u32 cap; /* SR-IOV Capabilities */
285 u16 ctrl; /* SR-IOV Control */
286 u16 total_VFs; /* Total VFs associated with the PF */
287 u16 initial_VFs; /* Initial VFs associated with the PF */
288 u16 num_VFs; /* Number of VFs available */
289 u16 offset; /* First VF Routing ID offset */
290 u16 stride; /* Following VF stride */
291 u16 vf_device; /* VF device ID */
292 u32 pgsz; /* Page size for BAR alignment */
293 u8 link; /* Function Dependency Link */
294 u8 max_VF_buses; /* Max buses consumed by VFs */
295 u16 driver_max_VFs; /* Max num VFs driver supports */
296 struct pci_dev *dev; /* Lowest numbered PF */
297 struct pci_dev *self; /* This PF */
cf0921be
KA		 298 u32 class; /* VF device */
299 u8 hdr_type; /* VF header type */
300 u16 subsystem_vendor; /* VF subsystem vendor */
301 u16 subsystem_device; /* VF subsystem device */
0aa0f5d1
BH		 302 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
303 bool drivers_autoprobe; /* Auto probing of VFs by driver */
d1b054da
YZ		 304};
305
a6bd101b
KB		 306/**
307 * pci_dev_set_io_state - Set the new error state if possible.
308 *
347269c1
KW		 309 * @dev: PCI device to set new error_state
310 * @new: the state we want dev to be in
a6bd101b
KB		 311 *
312 * Must be called with device_lock held.
313 *
314 * Returns true if state has been changed to the requested state.
315 */
316static inline bool pci_dev_set_io_state(struct pci_dev *dev,
317 pci_channel_state_t new)
318{
319 bool changed = false;
320
321 device_lock_assert(&dev->dev);
322 switch (new) {
323 case pci_channel_io_perm_failure:
324 switch (dev->error_state) {
325 case pci_channel_io_frozen:
326 case pci_channel_io_normal:
327 case pci_channel_io_perm_failure:
328 changed = true;
329 break;
330 }
331 break;
332 case pci_channel_io_frozen:
333 switch (dev->error_state) {
334 case pci_channel_io_frozen:
335 case pci_channel_io_normal:
336 changed = true;
337 break;
338 }
339 break;
340 case pci_channel_io_normal:
341 switch (dev->error_state) {
342 case pci_channel_io_frozen:
343 case pci_channel_io_normal:
344 changed = true;
345 break;
346 }
347 break;
348 }
349 if (changed)
350 dev->error_state = new;
351 return changed;
352}
89ee9f76
KB		 353
354static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
355{
a6bd101b
KB		 356 device_lock(&dev->dev);
357 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
358 device_unlock(&dev->dev);
359
89ee9f76
KB		 360 return 0;
361}
362
363static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
364{
a6bd101b 365 return dev->error_state == pci_channel_io_perm_failure;
89ee9f76
KB		 366}
367
a6bd101b
KB		 368/* pci_dev priv_flags */
369#define PCI_DEV_ADDED 0
a97396c6
LW		 370#define PCI_DPC_RECOVERED 1
371#define PCI_DPC_RECOVERING 2
a6bd101b 372
44bda4b7
HV		 373static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
374{
375 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
376}
377
378static inline bool pci_dev_is_added(const struct pci_dev *dev)
379{
380 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
381}
382
1e451160
KB		 383#ifdef CONFIG_PCIEAER
384#include <linux/aer.h>
385
386#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
387
388struct aer_err_info {
389 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
390 int error_dev_num;
391
392 unsigned int id:16;
393
394 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
395 unsigned int __pad1:5;
396 unsigned int multi_error_valid:1;
397
398 unsigned int first_error:5;
399 unsigned int __pad2:2;
400 unsigned int tlp_header_valid:1;
401
402 unsigned int status; /* COR/UNCOR Error Status */
403 unsigned int mask; /* COR/UNCOR Error Mask */
404 struct aer_header_log_regs tlp; /* TLP Header */
405};
406
407int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
408void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
409#endif /* CONFIG_PCIEAER */
410
90655631
SK		 411#ifdef CONFIG_PCIEPORTBUS
412/* Cached RCEC Endpoint Association */
413struct rcec_ea {
414 u8 nextbusn;
415 u8 lastbusn;
416 u32 bitmap;
417};
418#endif
419
4f802170
KB		 420#ifdef CONFIG_PCIE_DPC
421void pci_save_dpc_state(struct pci_dev *dev);
422void pci_restore_dpc_state(struct pci_dev *dev);
27005618 423void pci_dpc_init(struct pci_dev *pdev);
aea47413
KS		 424void dpc_process_error(struct pci_dev *pdev);
425pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
a97396c6 426bool pci_dpc_recovered(struct pci_dev *pdev);
4f802170
KB		 427#else
428static inline void pci_save_dpc_state(struct pci_dev *dev) {}
429static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
27005618 430static inline void pci_dpc_init(struct pci_dev *pdev) {}
a97396c6 431static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
4f802170
KB		 432#endif
433
90655631
SK		 434#ifdef CONFIG_PCIEPORTBUS
435void pci_rcec_init(struct pci_dev *dev);
436void pci_rcec_exit(struct pci_dev *dev);
507b460f 437void pcie_link_rcec(struct pci_dev *rcec);
af113553
SK		 438void pcie_walk_rcec(struct pci_dev *rcec,
439 int (*cb)(struct pci_dev *, void *),
440 void *userdata);
90655631
SK		 441#else
442static inline void pci_rcec_init(struct pci_dev *dev) {}
443static inline void pci_rcec_exit(struct pci_dev *dev) {}
507b460f 444static inline void pcie_link_rcec(struct pci_dev *rcec) {}
af113553
SK		 445static inline void pcie_walk_rcec(struct pci_dev *rcec,
446 int (*cb)(struct pci_dev *, void *),
447 void *userdata) {}
90655631
SK		 448#endif
449
1900ca13 450#ifdef CONFIG_PCI_ATS
b92b512a
KS		 451/* Address Translation Service */
452void pci_ats_init(struct pci_dev *dev);
f39d5b72 453void pci_restore_ats_state(struct pci_dev *dev);
1900ca13 454#else
b92b512a
KS		 455static inline void pci_ats_init(struct pci_dev *d) { }
456static inline void pci_restore_ats_state(struct pci_dev *dev) { }
1900ca13
HX		 457#endif /* CONFIG_PCI_ATS */
458
c065190b
KS		 459#ifdef CONFIG_PCI_PRI
460void pci_pri_init(struct pci_dev *dev);
fef2dd8b 461void pci_restore_pri_state(struct pci_dev *pdev);
c065190b
KS		 462#else
463static inline void pci_pri_init(struct pci_dev *dev) { }
fef2dd8b 464static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
c065190b
KS		 465#endif
466
751035b8
KS		 467#ifdef CONFIG_PCI_PASID
468void pci_pasid_init(struct pci_dev *dev);
fef2dd8b 469void pci_restore_pasid_state(struct pci_dev *pdev);
751035b8
KS		 470#else
471static inline void pci_pasid_init(struct pci_dev *dev) { }
fef2dd8b 472static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
751035b8
KS		 473#endif
474
d1b054da 475#ifdef CONFIG_PCI_IOV
f39d5b72
BH		 476int pci_iov_init(struct pci_dev *dev);
477void pci_iov_release(struct pci_dev *dev);
38972375 478void pci_iov_remove(struct pci_dev *dev);
6ffa2489 479void pci_iov_update_resource(struct pci_dev *dev, int resno);
f39d5b72
BH		 480resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
481void pci_restore_iov_state(struct pci_dev *dev);
482int pci_iov_bus_range(struct pci_bus *bus);
c3d5c2d9
LR		 483extern const struct attribute_group sriov_pf_dev_attr_group;
484extern const struct attribute_group sriov_vf_dev_attr_group;
d1b054da
YZ		 485#else
486static inline int pci_iov_init(struct pci_dev *dev)
487{
488 return -ENODEV;
489}
490static inline void pci_iov_release(struct pci_dev *dev)
491
38972375
JK		 492{
493}
494static inline void pci_iov_remove(struct pci_dev *dev)
d1b054da
YZ		 495{
496}
8c5cdb6a
YZ		 497static inline void pci_restore_iov_state(struct pci_dev *dev)
498{
499}
a28724b0
YZ		 500static inline int pci_iov_bus_range(struct pci_bus *bus)
501{
502 return 0;
503}
302b4215 504
d1b054da
YZ		 505#endif /* CONFIG_PCI_IOV */
506
39850ed5
DB		 507#ifdef CONFIG_PCIE_PTM
508void pci_save_ptm_state(struct pci_dev *dev);
509void pci_restore_ptm_state(struct pci_dev *dev);
a697f072 510void pci_disable_ptm(struct pci_dev *dev);
39850ed5
DB		 511#else
512static inline void pci_save_ptm_state(struct pci_dev *dev) { }
513static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
a697f072 514static inline void pci_disable_ptm(struct pci_dev *dev) { }
39850ed5
DB		 515#endif
516
f39d5b72 517unsigned long pci_cardbus_resource_alignment(struct resource *);
0a2daa1c 518
0e52247a 519static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
f39d5b72 520 struct resource *res)
6faf17f6
CW		 521{
522#ifdef CONFIG_PCI_IOV
523 int resno = res - dev->resource;
524
525 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
526 return pci_sriov_resource_alignment(dev, resno);
527#endif
0aa0f5d1 528 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
0a2daa1c 529 return pci_cardbus_resource_alignment(res);
6faf17f6
CW		 530 return resource_alignment(res);
531}
532
52fbf5bd 533void pci_acs_init(struct pci_dev *dev);
bd2e9567
BH		 534#ifdef CONFIG_PCI_QUIRKS
535int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
536int pci_dev_specific_enable_acs(struct pci_dev *dev);
73c47dde 537int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
bd2e9567
BH		 538#else
539static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
540 u16 acs_flags)
541{
542 return -ENOTTY;
543}
544static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
545{
546 return -ENOTTY;
547}
73c47dde
LG		 548static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
549{
550 return -ENOTTY;
551}
bd2e9567 552#endif
ae21ee65 553
2e28bc84 554/* PCI error reporting and recovery */
e8e5ff2a 555pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
8f1bbfbc
SK		 556 pci_channel_state_t state,
557 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
2e28bc84 558
9f5a70f1 559bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
7d8e7d19
BH		 560#ifdef CONFIG_PCIEASPM
561void pcie_aspm_init_link_state(struct pci_dev *pdev);
562void pcie_aspm_exit_link_state(struct pci_dev *pdev);
7d8e7d19
BH		 563void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
564#else
565static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
566static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
7d8e7d19
BH		 567static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
568#endif
569
72bde9ce
KS		 570#ifdef CONFIG_PCIE_ECRC
571void pcie_set_ecrc_checking(struct pci_dev *dev);
572void pcie_ecrc_get_policy(char *str);
573#else
574static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
575static inline void pcie_ecrc_get_policy(char *str) { }
576#endif
577
9bb04a0c
JY		 578#ifdef CONFIG_PCIE_PTM
579void pci_ptm_init(struct pci_dev *dev);
580#else
581static inline void pci_ptm_init(struct pci_dev *dev) { }
582#endif
583
b9c3b266
DC		 584struct pci_dev_reset_methods {
585 u16 vendor;
586 u16 device;
9bdc81ce 587 int (*reset)(struct pci_dev *dev, bool probe);
b9c3b266
DC		 588};
589
e20afa06 590struct pci_reset_fn_method {
9bdc81ce 591 int (*reset_fn)(struct pci_dev *pdev, bool probe);
e20afa06 592 char *name;
b9c3b266
DC		 593};
594
93177a74 595#ifdef CONFIG_PCI_QUIRKS
9bdc81ce 596int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
93177a74 597#else
9bdc81ce 598static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
93177a74
RW		 599{
600 return -ENOTTY;
601}
602#endif
b9c3b266 603
169de969
DL		 604#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
605int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
606 struct resource *res);
16f7ae59
AB		 607#else
608static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
609 u16 segment, struct resource *res)
610{
611 return -ENODEV;
612}
169de969
DL		 613#endif
614
276b738d
CK		 615int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
616int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
617static inline u64 pci_rebar_size_to_bytes(int size)
618{
619 return 1ULL << (size + 20);
620}
621
9e2aee80
RH		 622struct device_node;
623
624#ifdef CONFIG_OF
625int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
626int of_get_pci_domain_nr(struct device_node *node);
627int of_pci_get_max_link_speed(struct device_node *node);
35662423
PR		 628u32 of_pci_get_slot_power_limit(struct device_node *node,
629 u8 *slot_power_limit_value,
630 u8 *slot_power_limit_scale);
621f7e35
KS		 631void pci_set_of_node(struct pci_dev *dev);
632void pci_release_of_node(struct pci_dev *dev);
633void pci_set_bus_of_node(struct pci_bus *bus);
634void pci_release_bus_of_node(struct pci_bus *bus);
9e2aee80 635
669cbc70
RH		 636int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
637
9e2aee80
RH		 638#else
639static inline int
640of_pci_parse_bus_range(struct device_node *node, struct resource *res)
641{
642 return -EINVAL;
643}
644
645static inline int
646of_get_pci_domain_nr(struct device_node *node)
647{
648 return -1;
649}
650
651static inline int
652of_pci_get_max_link_speed(struct device_node *node)
653{
654 return -EINVAL;
655}
621f7e35 656
35662423
PR		 657static inline u32
658of_pci_get_slot_power_limit(struct device_node *node,
659 u8 *slot_power_limit_value,
660 u8 *slot_power_limit_scale)
661{
662 if (slot_power_limit_value)
663 *slot_power_limit_value = 0;
664 if (slot_power_limit_scale)
665 *slot_power_limit_scale = 0;
666 return 0;
667}
668
621f7e35
KS		 669static inline void pci_set_of_node(struct pci_dev *dev) { }
670static inline void pci_release_of_node(struct pci_dev *dev) { }
671static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
672static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
669cbc70
RH		 673
674static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
675{
676 return 0;
677}
678
9e2aee80
RH		 679#endif /* CONFIG_OF */
680
60ed982a
RJ		 681#ifdef CONFIG_PCIEAER
682void pci_no_aer(void);
683void pci_aer_init(struct pci_dev *dev);
db89ccbe 684void pci_aer_exit(struct pci_dev *dev);
81aa5206 685extern const struct attribute_group aer_stats_attr_group;
7ab92e89 686void pci_aer_clear_fatal_status(struct pci_dev *dev);
894020fd 687int pci_aer_clear_status(struct pci_dev *dev);
20e15e67 688int pci_aer_raw_clear_status(struct pci_dev *dev);
60ed982a
RJ		 689#else
690static inline void pci_no_aer(void) { }
31f996ef 691static inline void pci_aer_init(struct pci_dev *d) { }
db89ccbe 692static inline void pci_aer_exit(struct pci_dev *d) { }
7ab92e89 693static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
894020fd 694static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
20e15e67 695static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
60ed982a
RJ		 696#endif
697
8c3aac6e 698#ifdef CONFIG_ACPI
4a2dbedd 699int pci_acpi_program_hp_params(struct pci_dev *dev);
506140f9 700extern const struct attribute_group pci_dev_acpi_attr_group;
3a15955d 701void pci_set_acpi_fwnode(struct pci_dev *dev);
9bdc81ce 702int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
d97c5d4c
RW		 703bool acpi_pci_power_manageable(struct pci_dev *dev);
704bool acpi_pci_bridge_d3(struct pci_dev *dev);
705int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
706pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
707void acpi_pci_refresh_power_state(struct pci_dev *dev);
708int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
709bool acpi_pci_need_resume(struct pci_dev *dev);
710pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
8c3aac6e 711#else
9bdc81ce 712static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
6937b7dd
SD		 713{
714 return -ENOTTY;
715}
3a15955d 716static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {}
4a2dbedd 717static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
8c3aac6e
KW		 718{
719 return -ENODEV;
720}
d97c5d4c
RW		 721static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
722{
723 return false;
724}
725static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
726{
727 return false;
728}
729static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
730{
731 return -ENODEV;
732}
733static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
734{
735 return PCI_UNKNOWN;
736}
737static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) {}
738static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
739{
740 return -ENODEV;
741}
742static inline bool acpi_pci_need_resume(struct pci_dev *dev)
743{
744 return false;
745}
746static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
747{
748 return PCI_POWER_ERROR;
749}
8c3aac6e
KW		 750#endif
751
72ea91af
HK		 752#ifdef CONFIG_PCIEASPM
753extern const struct attribute_group aspm_ctrl_attr_group;
754#endif
755
d88f521d
AN		 756extern const struct attribute_group pci_dev_reset_method_attr_group;
757
d5b0d883
RW		 758#ifdef CONFIG_X86_INTEL_MID
759bool pci_use_mid_pm(void);
760int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
761pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
762#else
763static inline bool pci_use_mid_pm(void)
764{
765 return false;
766}
767static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
768{
769 return -ENODEV;
770}
771static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
772{
773 return PCI_UNKNOWN;
774}
775#endif
776
557848c3 777#endif /* DRIVERS_PCI_H */
Empty description
This page took 1.530549 seconds and 4 git commands to generate.